1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung's ExynosAutov920 SoC device tree source 4 * 5 * Copyright (c) 2023 Samsung Electronics Co., Ltd. 6 * 7 */ 8 9#include <dt-bindings/clock/samsung,exynosautov920.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/soc/samsung,exynos-usi.h> 12 13/ { 14 compatible = "samsung,exynosautov920"; 15 #address-cells = <2>; 16 #size-cells = <1>; 17 18 interrupt-parent = <&gic>; 19 20 aliases { 21 pinctrl0 = &pinctrl_alive; 22 pinctrl1 = &pinctrl_aud; 23 pinctrl2 = &pinctrl_hsi0; 24 pinctrl3 = &pinctrl_hsi1; 25 pinctrl4 = &pinctrl_hsi2; 26 pinctrl5 = &pinctrl_hsi2ufs; 27 pinctrl6 = &pinctrl_peric0; 28 pinctrl7 = &pinctrl_peric1; 29 }; 30 31 arm-pmu { 32 compatible = "arm,cortex-a78-pmu"; 33 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 34 }; 35 36 xtcxo: clock { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-output-names = "oscclk"; 40 }; 41 42 cpus: cpus { 43 #address-cells = <2>; 44 #size-cells = <0>; 45 46 cpu-map { 47 cluster0 { 48 core0 { 49 cpu = <&cpu0>; 50 }; 51 core1 { 52 cpu = <&cpu1>; 53 }; 54 core2 { 55 cpu = <&cpu2>; 56 }; 57 core3 { 58 cpu = <&cpu3>; 59 }; 60 }; 61 62 cluster1 { 63 core0 { 64 cpu = <&cpu4>; 65 }; 66 core1 { 67 cpu = <&cpu5>; 68 }; 69 core2 { 70 cpu = <&cpu6>; 71 }; 72 core3 { 73 cpu = <&cpu7>; 74 }; 75 }; 76 77 cluster2 { 78 core0 { 79 cpu = <&cpu8>; 80 }; 81 core1 { 82 cpu = <&cpu9>; 83 }; 84 }; 85 }; 86 87 cpu0: cpu@0 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a78ae"; 90 reg = <0x0 0x0>; 91 enable-method = "psci"; 92 i-cache-size = <0x10000>; 93 i-cache-line-size = <64>; 94 i-cache-sets = <256>; 95 d-cache-size = <0x10000>; 96 d-cache-line-size = <64>; 97 d-cache-sets = <256>; 98 next-level-cache = <&l2_cache_cl0>; 99 }; 100 101 cpu1: cpu@100 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a78ae"; 104 reg = <0x0 0x100>; 105 enable-method = "psci"; 106 i-cache-size = <0x10000>; 107 i-cache-line-size = <64>; 108 i-cache-sets = <256>; 109 d-cache-size = <0x10000>; 110 d-cache-line-size = <64>; 111 d-cache-sets = <256>; 112 next-level-cache = <&l2_cache_cl0>; 113 }; 114 115 cpu2: cpu@200 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a78ae"; 118 reg = <0x0 0x200>; 119 enable-method = "psci"; 120 i-cache-size = <0x10000>; 121 i-cache-line-size = <64>; 122 i-cache-sets = <256>; 123 d-cache-size = <0x10000>; 124 d-cache-line-size = <64>; 125 d-cache-sets = <256>; 126 next-level-cache = <&l2_cache_cl0>; 127 }; 128 129 cpu3: cpu@300 { 130 device_type = "cpu"; 131 compatible = "arm,cortex-a78ae"; 132 reg = <0x0 0x300>; 133 enable-method = "psci"; 134 i-cache-size = <0x10000>; 135 i-cache-line-size = <64>; 136 i-cache-sets = <256>; 137 d-cache-size = <0x10000>; 138 d-cache-line-size = <64>; 139 d-cache-sets = <256>; 140 next-level-cache = <&l2_cache_cl0>; 141 }; 142 143 cpu4: cpu@10000 { 144 device_type = "cpu"; 145 compatible = "arm,cortex-a78ae"; 146 reg = <0x0 0x10000>; 147 enable-method = "psci"; 148 i-cache-size = <0x10000>; 149 i-cache-line-size = <64>; 150 i-cache-sets = <256>; 151 d-cache-size = <0x10000>; 152 d-cache-line-size = <64>; 153 d-cache-sets = <256>; 154 next-level-cache = <&l2_cache_cl1>; 155 }; 156 157 cpu5: cpu@10100 { 158 device_type = "cpu"; 159 compatible = "arm,cortex-a78ae"; 160 reg = <0x0 0x10100>; 161 enable-method = "psci"; 162 i-cache-size = <0x10000>; 163 i-cache-line-size = <64>; 164 i-cache-sets = <256>; 165 d-cache-size = <0x10000>; 166 d-cache-line-size = <64>; 167 d-cache-sets = <256>; 168 next-level-cache = <&l2_cache_cl1>; 169 }; 170 171 cpu6: cpu@10200 { 172 device_type = "cpu"; 173 compatible = "arm,cortex-a78ae"; 174 reg = <0x0 0x10200>; 175 enable-method = "psci"; 176 i-cache-size = <0x10000>; 177 i-cache-line-size = <64>; 178 i-cache-sets = <256>; 179 d-cache-size = <0x10000>; 180 d-cache-line-size = <64>; 181 d-cache-sets = <256>; 182 next-level-cache = <&l2_cache_cl1>; 183 }; 184 185 cpu7: cpu@10300 { 186 device_type = "cpu"; 187 compatible = "arm,cortex-a78ae"; 188 reg = <0x0 0x10300>; 189 enable-method = "psci"; 190 i-cache-size = <0x10000>; 191 i-cache-line-size = <64>; 192 i-cache-sets = <256>; 193 d-cache-size = <0x10000>; 194 d-cache-line-size = <64>; 195 d-cache-sets = <256>; 196 next-level-cache = <&l2_cache_cl1>; 197 }; 198 199 cpu8: cpu@20000 { 200 device_type = "cpu"; 201 compatible = "arm,cortex-a78ae"; 202 reg = <0x0 0x20000>; 203 enable-method = "psci"; 204 i-cache-size = <0x10000>; 205 i-cache-line-size = <64>; 206 i-cache-sets = <256>; 207 d-cache-size = <0x10000>; 208 d-cache-line-size = <64>; 209 d-cache-sets = <256>; 210 next-level-cache = <&l2_cache_cl2>; 211 }; 212 213 cpu9: cpu@20100 { 214 device_type = "cpu"; 215 compatible = "arm,cortex-a78ae"; 216 reg = <0x0 0x20100>; 217 enable-method = "psci"; 218 i-cache-size = <0x10000>; 219 i-cache-line-size = <64>; 220 i-cache-sets = <256>; 221 d-cache-size = <0x10000>; 222 d-cache-line-size = <64>; 223 d-cache-sets = <256>; 224 next-level-cache = <&l2_cache_cl2>; 225 }; 226 227 l2_cache_cl0: l2-cache0 { 228 compatible = "cache"; 229 cache-level = <2>; 230 cache-unified; 231 cache-size = <0x40000>; 232 cache-line-size = <64>; 233 cache-sets = <512>; 234 next-level-cache = <&l3_cache_cl0>; 235 }; 236 237 l2_cache_cl1: l2-cache1 { 238 compatible = "cache"; 239 cache-level = <2>; 240 cache-unified; 241 cache-size = <0x40000>; 242 cache-line-size = <64>; 243 cache-sets = <512>; 244 next-level-cache = <&l3_cache_cl1>; 245 }; 246 247 l2_cache_cl2: l2-cache2 { 248 compatible = "cache"; 249 cache-level = <2>; 250 cache-unified; 251 cache-size = <0x40000>; 252 cache-line-size = <64>; 253 cache-sets = <512>; 254 next-level-cache = <&l3_cache_cl2>; 255 }; 256 257 l3_cache_cl0: l3-cache0 { 258 compatible = "cache"; 259 cache-level = <3>; 260 cache-unified; 261 cache-size = <0x200000>;/* 2MB L3 cache for cpu cluster-0 */ 262 cache-line-size = <64>; 263 cache-sets = <2048>; 264 }; 265 266 l3_cache_cl1: l3-cache1 { 267 compatible = "cache"; 268 cache-level = <3>; 269 cache-unified; 270 cache-size = <0x200000>;/* 2MB L3 cache for cpu cluster-1 */ 271 cache-line-size = <64>; 272 cache-sets = <2048>; 273 }; 274 275 l3_cache_cl2: l3-cache2 { 276 compatible = "cache"; 277 cache-level = <3>; 278 cache-unified; 279 cache-size = <0x100000>;/* 1MB L3 cache for cpu cluster-2 */ 280 cache-line-size = <64>; 281 cache-sets = <1365>; 282 }; 283 }; 284 285 psci { 286 compatible = "arm,psci-1.0"; 287 method = "smc"; 288 }; 289 290 soc: soc@0 { 291 compatible = "simple-bus"; 292 #address-cells = <1>; 293 #size-cells = <1>; 294 ranges = <0x0 0x0 0x0 0x20000000>; 295 296 chipid@10000000 { 297 compatible = "samsung,exynosautov920-chipid", 298 "samsung,exynos850-chipid"; 299 reg = <0x10000000 0x24>; 300 }; 301 302 cmu_misc: clock-controller@10020000 { 303 compatible = "samsung,exynosautov920-cmu-misc"; 304 reg = <0x10020000 0x8000>; 305 #clock-cells = <1>; 306 307 clocks = <&xtcxo>, 308 <&cmu_top DOUT_CLKCMU_MISC_NOC>; 309 clock-names = "oscclk", 310 "noc"; 311 }; 312 313 watchdog_cl0: watchdog@10060000 { 314 compatible = "samsung,exynosautov920-wdt"; 315 reg = <0x10060000 0x100>; 316 interrupts = <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>; 317 clocks = <&xtcxo>, <&xtcxo>; 318 clock-names = "watchdog", "watchdog_src"; 319 samsung,syscon-phandle = <&pmu_system_controller>; 320 samsung,cluster-index = <0>; 321 }; 322 323 watchdog_cl1: watchdog@10070000 { 324 compatible = "samsung,exynosautov920-wdt"; 325 reg = <0x10070000 0x100>; 326 interrupts = <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&xtcxo>, <&xtcxo>; 328 clock-names = "watchdog", "watchdog_src"; 329 samsung,syscon-phandle = <&pmu_system_controller>; 330 samsung,cluster-index = <1>; 331 }; 332 333 gic: interrupt-controller@10400000 { 334 compatible = "arm,gic-v3"; 335 #interrupt-cells = <3>; 336 #address-cells = <0>; 337 interrupt-controller; 338 reg = <0x10400000 0x10000>, 339 <0x10460000 0x140000>; 340 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 341 }; 342 343 spdma0: dma-controller@10180000 { 344 compatible = "arm,pl330", "arm,primecell"; 345 reg = <0x10180000 0x1000>; 346 interrupts = <GIC_SPI 918 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>; 348 clock-names = "apb_pclk"; 349 #dma-cells = <1>; 350 }; 351 352 spdma1: dma-controller@10190000 { 353 compatible = "arm,pl330", "arm,primecell"; 354 reg = <0x10190000 0x1000>; 355 interrupts = <GIC_SPI 917 IRQ_TYPE_LEVEL_HIGH>; 356 clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>; 357 clock-names = "apb_pclk"; 358 #dma-cells = <1>; 359 }; 360 361 pdma0: dma-controller@101a0000 { 362 compatible = "arm,pl330", "arm,primecell"; 363 reg = <0x101a0000 0x1000>; 364 interrupts = <GIC_SPI 916 IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>; 366 clock-names = "apb_pclk"; 367 #dma-cells = <1>; 368 }; 369 370 pdma1: dma-controller@101b0000 { 371 compatible = "arm,pl330", "arm,primecell"; 372 reg = <0x101b0000 0x1000>; 373 interrupts = <GIC_SPI 915 IRQ_TYPE_LEVEL_HIGH>; 374 clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>; 375 clock-names = "apb_pclk"; 376 #dma-cells = <1>; 377 }; 378 379 pdma2: dma-controller@101c0000 { 380 compatible = "arm,pl330", "arm,primecell"; 381 reg = <0x101c0000 0x1000>; 382 interrupts = <GIC_SPI 914 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>; 384 clock-names = "apb_pclk"; 385 #dma-cells = <1>; 386 }; 387 388 pdma3: dma-controller@101d0000 { 389 compatible = "arm,pl330", "arm,primecell"; 390 reg = <0x101d0000 0x1000>; 391 interrupts = <GIC_SPI 913 IRQ_TYPE_LEVEL_HIGH>; 392 clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>; 393 clock-names = "apb_pclk"; 394 #dma-cells = <1>; 395 }; 396 397 pdma4: dma-controller@101e0000 { 398 compatible = "arm,pl330", "arm,primecell"; 399 reg = <0x101e0000 0x1000>; 400 interrupts = <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>; 401 clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>; 402 clock-names = "apb_pclk"; 403 #dma-cells = <1>; 404 }; 405 406 cmu_peric0: clock-controller@10800000 { 407 compatible = "samsung,exynosautov920-cmu-peric0"; 408 reg = <0x10800000 0x8000>; 409 #clock-cells = <1>; 410 411 clocks = <&xtcxo>, 412 <&cmu_top DOUT_CLKCMU_PERIC0_NOC>, 413 <&cmu_top DOUT_CLKCMU_PERIC0_IP>; 414 clock-names = "oscclk", 415 "noc", 416 "ip"; 417 }; 418 419 syscon_peric0: syscon@10820000 { 420 compatible = "samsung,exynosautov920-peric0-sysreg", 421 "syscon"; 422 reg = <0x10820000 0x2000>; 423 }; 424 425 pinctrl_peric0: pinctrl@10830000 { 426 compatible = "samsung,exynosautov920-pinctrl"; 427 reg = <0x10830000 0x10000>; 428 interrupts = <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>; 429 }; 430 431 usi_0: usi@108800c0 { 432 compatible = "samsung,exynosautov920-usi", 433 "samsung,exynos850-usi"; 434 reg = <0x108800c0 0x20>; 435 samsung,sysreg = <&syscon_peric0 0x1000>; 436 samsung,mode = <USI_MODE_UART>; 437 #address-cells = <1>; 438 #size-cells = <1>; 439 ranges; 440 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 441 <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>; 442 clock-names = "pclk", "ipclk"; 443 status = "disabled"; 444 445 serial_0: serial@10880000 { 446 compatible = "samsung,exynosautov920-uart", 447 "samsung,exynos850-uart"; 448 reg = <0x10880000 0xc0>; 449 interrupts = <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>; 450 pinctrl-names = "default"; 451 pinctrl-0 = <&uart0_bus>; 452 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 453 <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>; 454 clock-names = "uart", "clk_uart_baud0"; 455 samsung,uart-fifosize = <256>; 456 status = "disabled"; 457 }; 458 }; 459 460 usi_1: usi@108a00c0 { 461 compatible = "samsung,exynosautov920-usi", 462 "samsung,exynos850-usi"; 463 reg = <0x108a00c0 0x20>; 464 samsung,sysreg = <&syscon_peric0 0x1008>; 465 samsung,mode = <USI_V2_UART>; 466 #address-cells = <1>; 467 #size-cells = <1>; 468 ranges; 469 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 470 <&cmu_peric0 CLK_DOUT_PERIC0_USI01_USI>; 471 clock-names = "pclk", "ipclk"; 472 status = "disabled"; 473 474 serial_1: serial@108a0000 { 475 compatible = "samsung,exynosautov920-uart", 476 "samsung,exynos850-uart"; 477 reg = <0x108a0000 0xc0>; 478 interrupts = <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>; 479 pinctrl-names = "default"; 480 pinctrl-0 = <&uart1_bus>; 481 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 482 <&cmu_peric0 CLK_DOUT_PERIC0_USI01_USI>; 483 clock-names = "uart", "clk_uart_baud0"; 484 samsung,uart-fifosize = <256>; 485 status = "disabled"; 486 }; 487 }; 488 489 usi_2: usi@108c00c0 { 490 compatible = "samsung,exynosautov920-usi", 491 "samsung,exynos850-usi"; 492 reg = <0x108c00c0 0x20>; 493 samsung,sysreg = <&syscon_peric0 0x1010>; 494 samsung,mode = <USI_V2_UART>; 495 #address-cells = <1>; 496 #size-cells = <1>; 497 ranges; 498 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 499 <&cmu_peric0 CLK_DOUT_PERIC0_USI02_USI>; 500 clock-names = "pclk", "ipclk"; 501 status = "disabled"; 502 503 serial_2: serial@108c0000 { 504 compatible = "samsung,exynosautov920-uart", 505 "samsung,exynos850-uart"; 506 reg = <0x108c0000 0xc0>; 507 interrupts = <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>; 508 pinctrl-names = "default"; 509 pinctrl-0 = <&uart2_bus>; 510 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 511 <&cmu_peric0 CLK_DOUT_PERIC0_USI02_USI>; 512 clock-names = "uart", "clk_uart_baud0"; 513 samsung,uart-fifosize = <64>; 514 status = "disabled"; 515 }; 516 }; 517 518 usi_3: usi@108e00c0 { 519 compatible = "samsung,exynosautov920-usi", 520 "samsung,exynos850-usi"; 521 reg = <0x108e00c0 0x20>; 522 samsung,sysreg = <&syscon_peric0 0x1018>; 523 samsung,mode = <USI_V2_UART>; 524 #address-cells = <1>; 525 #size-cells = <1>; 526 ranges; 527 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 528 <&cmu_peric0 CLK_DOUT_PERIC0_USI03_USI>; 529 clock-names = "pclk", "ipclk"; 530 status = "disabled"; 531 532 serial_3: serial@108e0000 { 533 compatible = "samsung,exynosautov920-uart", 534 "samsung,exynos850-uart"; 535 reg = <0x108e0000 0xc0>; 536 interrupts = <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>; 537 pinctrl-names = "default"; 538 pinctrl-0 = <&uart3_bus>; 539 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 540 <&cmu_peric0 CLK_DOUT_PERIC0_USI03_USI>; 541 clock-names = "uart", "clk_uart_baud0"; 542 samsung,uart-fifosize = <64>; 543 status = "disabled"; 544 }; 545 }; 546 547 usi_4: usi@109000c0 { 548 compatible = "samsung,exynosautov920-usi", 549 "samsung,exynos850-usi"; 550 reg = <0x109000c0 0x20>; 551 samsung,sysreg = <&syscon_peric0 0x1020>; 552 samsung,mode = <USI_V2_UART>; 553 #address-cells = <1>; 554 #size-cells = <1>; 555 ranges; 556 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 557 <&cmu_peric0 CLK_DOUT_PERIC0_USI04_USI>; 558 clock-names = "pclk", "ipclk"; 559 status = "disabled"; 560 561 serial_4: serial@10900000 { 562 compatible = "samsung,exynosautov920-uart", 563 "samsung,exynos850-uart"; 564 reg = <0x10900000 0xc0>; 565 interrupts = <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>; 566 pinctrl-names = "default"; 567 pinctrl-0 = <&uart4_bus>; 568 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 569 <&cmu_peric0 CLK_DOUT_PERIC0_USI04_USI>; 570 clock-names = "uart", "clk_uart_baud0"; 571 samsung,uart-fifosize = <64>; 572 status = "disabled"; 573 }; 574 }; 575 576 usi_5: usi@109200c0 { 577 compatible = "samsung,exynosautov920-usi", 578 "samsung,exynos850-usi"; 579 reg = <0x109200c0 0x20>; 580 samsung,sysreg = <&syscon_peric0 0x1028>; 581 samsung,mode = <USI_V2_UART>; 582 #address-cells = <1>; 583 #size-cells = <1>; 584 ranges; 585 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 586 <&cmu_peric0 CLK_DOUT_PERIC0_USI05_USI>; 587 clock-names = "pclk", "ipclk"; 588 status = "disabled"; 589 590 serial_5: serial@10920000 { 591 compatible = "samsung,exynosautov920-uart", 592 "samsung,exynos850-uart"; 593 reg = <0x10920000 0xc0>; 594 interrupts = <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>; 595 pinctrl-names = "default"; 596 pinctrl-0 = <&uart5_bus>; 597 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 598 <&cmu_peric0 CLK_DOUT_PERIC0_USI05_USI>; 599 clock-names = "uart", "clk_uart_baud0"; 600 samsung,uart-fifosize = <64>; 601 status = "disabled"; 602 }; 603 }; 604 605 usi_6: usi@109400c0 { 606 compatible = "samsung,exynosautov920-usi", 607 "samsung,exynos850-usi"; 608 reg = <0x109400c0 0x20>; 609 samsung,sysreg = <&syscon_peric0 0x1030>; 610 samsung,mode = <USI_V2_UART>; 611 #address-cells = <1>; 612 #size-cells = <1>; 613 ranges; 614 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 615 <&cmu_peric0 CLK_DOUT_PERIC0_USI06_USI>; 616 clock-names = "pclk", "ipclk"; 617 status = "disabled"; 618 619 serial_6: serial@10940000 { 620 compatible = "samsung,exynosautov920-uart", 621 "samsung,exynos850-uart"; 622 reg = <0x10940000 0xc0>; 623 interrupts = <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>; 624 pinctrl-names = "default"; 625 pinctrl-0 = <&uart6_bus>; 626 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 627 <&cmu_peric0 CLK_DOUT_PERIC0_USI06_USI>; 628 clock-names = "uart", "clk_uart_baud0"; 629 samsung,uart-fifosize = <64>; 630 status = "disabled"; 631 }; 632 }; 633 634 usi_7: usi@109600c0 { 635 compatible = "samsung,exynosautov920-usi", 636 "samsung,exynos850-usi"; 637 reg = <0x109600c0 0x20>; 638 samsung,sysreg = <&syscon_peric0 0x1038>; 639 samsung,mode = <USI_V2_UART>; 640 #address-cells = <1>; 641 #size-cells = <1>; 642 ranges; 643 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 644 <&cmu_peric0 CLK_DOUT_PERIC0_USI07_USI>; 645 clock-names = "pclk", "ipclk"; 646 status = "disabled"; 647 648 serial_7: serial@10960000 { 649 compatible = "samsung,exynosautov920-uart", 650 "samsung,exynos850-uart"; 651 reg = <0x10960000 0xc0>; 652 interrupts = <GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH>; 653 pinctrl-names = "default"; 654 pinctrl-0 = <&uart7_bus>; 655 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 656 <&cmu_peric0 CLK_DOUT_PERIC0_USI07_USI>; 657 clock-names = "uart", "clk_uart_baud0"; 658 samsung,uart-fifosize = <64>; 659 status = "disabled"; 660 }; 661 }; 662 663 usi_8: usi@109800c0 { 664 compatible = "samsung,exynosautov920-usi", 665 "samsung,exynos850-usi"; 666 reg = <0x109800c0 0x20>; 667 samsung,sysreg = <&syscon_peric0 0x1040>; 668 samsung,mode = <USI_V2_UART>; 669 #address-cells = <1>; 670 #size-cells = <1>; 671 ranges; 672 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 673 <&cmu_peric0 CLK_DOUT_PERIC0_USI08_USI>; 674 clock-names = "pclk", "ipclk"; 675 status = "disabled"; 676 677 serial_8: serial@10980000 { 678 compatible = "samsung,exynosautov920-uart", 679 "samsung,exynos850-uart"; 680 reg = <0x10980000 0xc0>; 681 interrupts = <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>; 682 pinctrl-names = "default"; 683 pinctrl-0 = <&uart8_bus>; 684 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, 685 <&cmu_peric0 CLK_DOUT_PERIC0_USI08_USI>; 686 clock-names = "uart", "clk_uart_baud0"; 687 samsung,uart-fifosize = <64>; 688 status = "disabled"; 689 }; 690 }; 691 692 pwm: pwm@109b0000 { 693 compatible = "samsung,exynosautov920-pwm", 694 "samsung,exynos4210-pwm"; 695 reg = <0x109b0000 0x100>; 696 samsung,pwm-outputs = <0>, <1>, <2>, <3>; 697 #pwm-cells = <3>; 698 clocks = <&xtcxo>; 699 clock-names = "timers"; 700 status = "disabled"; 701 }; 702 703 cmu_peric1: clock-controller@10c00000 { 704 compatible = "samsung,exynosautov920-cmu-peric1"; 705 reg = <0x10c00000 0x8000>; 706 #clock-cells = <1>; 707 708 clocks = <&xtcxo>, 709 <&cmu_top DOUT_CLKCMU_PERIC1_NOC>, 710 <&cmu_top DOUT_CLKCMU_PERIC1_IP>; 711 clock-names = "oscclk", 712 "noc", 713 "ip"; 714 }; 715 716 syscon_peric1: syscon@10c20000 { 717 compatible = "samsung,exynosautov920-peric1-sysreg", 718 "syscon"; 719 reg = <0x10c20000 0x2000>; 720 }; 721 722 pinctrl_peric1: pinctrl@10c30000 { 723 compatible = "samsung,exynosautov920-pinctrl"; 724 reg = <0x10c30000 0x10000>; 725 interrupts = <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>; 726 }; 727 728 usi_9: usi@10c800c0 { 729 compatible = "samsung,exynosautov920-usi", 730 "samsung,exynos850-usi"; 731 reg = <0x10c800c0 0x20>; 732 samsung,sysreg = <&syscon_peric1 0x1000>; 733 samsung,mode = <USI_V2_UART>; 734 #address-cells = <1>; 735 #size-cells = <1>; 736 ranges; 737 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 738 <&cmu_peric1 CLK_DOUT_PERIC1_USI09_USI>; 739 clock-names = "pclk", "ipclk"; 740 status = "disabled"; 741 742 serial_9: serial@10c8000 { 743 compatible = "samsung,exynosautov920-uart", 744 "samsung,exynos850-uart"; 745 reg = <0x10c80000 0xc0>; 746 interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>; 747 pinctrl-names = "default"; 748 pinctrl-0 = <&uart9_bus>; 749 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 750 <&cmu_peric1 CLK_DOUT_PERIC1_USI09_USI>; 751 clock-names = "uart", "clk_uart_baud0"; 752 samsung,uart-fifosize = <256>; 753 status = "disabled"; 754 }; 755 }; 756 757 usi_10: usi@10ca00c0 { 758 compatible = "samsung,exynosautov920-usi", 759 "samsung,exynos850-usi"; 760 reg = <0x10ca00c0 0x20>; 761 samsung,sysreg = <&syscon_peric1 0x1008>; 762 samsung,mode = <USI_V2_UART>; 763 #address-cells = <1>; 764 #size-cells = <1>; 765 ranges; 766 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 767 <&cmu_peric1 CLK_DOUT_PERIC1_USI10_USI>; 768 clock-names = "pclk", "ipclk"; 769 status = "disabled"; 770 771 serial_10: serial@10ca0000 { 772 compatible = "samsung,exynosautov920-uart", 773 "samsung,exynos850-uart"; 774 reg = <0x10ca0000 0xc0>; 775 interrupts = <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>; 776 pinctrl-names = "default"; 777 pinctrl-0 = <&uart10_bus>; 778 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 779 <&cmu_peric1 CLK_DOUT_PERIC1_USI10_USI>; 780 clock-names = "uart", "clk_uart_baud0"; 781 samsung,uart-fifosize = <64>; 782 status = "disabled"; 783 }; 784 }; 785 786 usi_11: usi@10cc00c0 { 787 compatible = "samsung,exynosautov920-usi", 788 "samsung,exynos850-usi"; 789 reg = <0x10cc00c0 0x20>; 790 samsung,sysreg = <&syscon_peric1 0x1010>; 791 samsung,mode = <USI_V2_UART>; 792 #address-cells = <1>; 793 #size-cells = <1>; 794 ranges; 795 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 796 <&cmu_peric1 CLK_DOUT_PERIC1_USI11_USI>; 797 clock-names = "pclk", "ipclk"; 798 status = "disabled"; 799 800 serial_11: serial@10cc0000 { 801 compatible = "samsung,exynosautov920-uart", 802 "samsung,exynos850-uart"; 803 reg = <0x10cc0000 0xc0>; 804 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>; 805 pinctrl-names = "default"; 806 pinctrl-0 = <&uart11_bus>; 807 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 808 <&cmu_peric1 CLK_DOUT_PERIC1_USI11_USI>; 809 clock-names = "uart", "clk_uart_baud0"; 810 samsung,uart-fifosize = <64>; 811 status = "disabled"; 812 }; 813 }; 814 815 usi_12: usi@10ce00c0 { 816 compatible = "samsung,exynosautov920-usi", 817 "samsung,exynos850-usi"; 818 reg = <0x10ce00c0 0x20>; 819 samsung,sysreg = <&syscon_peric1 0x1018>; 820 samsung,mode = <USI_V2_UART>; 821 #address-cells = <1>; 822 #size-cells = <1>; 823 ranges; 824 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 825 <&cmu_peric1 CLK_DOUT_PERIC1_USI12_USI>; 826 clock-names = "pclk", "ipclk"; 827 status = "disabled"; 828 829 serial_12: serial@10ce0000 { 830 compatible = "samsung,exynosautov920-uart", 831 "samsung,exynos850-uart"; 832 reg = <0x10ce0000 0xc0>; 833 interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>; 834 pinctrl-names = "default"; 835 pinctrl-0 = <&uart12_bus>; 836 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 837 <&cmu_peric1 CLK_DOUT_PERIC1_USI12_USI>; 838 clock-names = "uart", "clk_uart_baud0"; 839 samsung,uart-fifosize = <64>; 840 status = "disabled"; 841 }; 842 }; 843 844 usi_13: usi@10d000c0 { 845 compatible = "samsung,exynosautov920-usi", 846 "samsung,exynos850-usi"; 847 reg = <0x10d000c0 0x20>; 848 samsung,sysreg = <&syscon_peric1 0x1020>; 849 samsung,mode = <USI_V2_UART>; 850 #address-cells = <1>; 851 #size-cells = <1>; 852 ranges; 853 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 854 <&cmu_peric1 CLK_DOUT_PERIC1_USI13_USI>; 855 clock-names = "pclk", "ipclk"; 856 status = "disabled"; 857 858 serial_13: serial@10d00000 { 859 compatible = "samsung,exynosautov920-uart", 860 "samsung,exynos850-uart"; 861 reg = <0x10d00000 0xc0>; 862 interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>; 863 pinctrl-names = "default"; 864 pinctrl-0 = <&uart13_bus>; 865 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 866 <&cmu_peric1 CLK_DOUT_PERIC1_USI13_USI>; 867 clock-names = "uart", "clk_uart_baud0"; 868 samsung,uart-fifosize = <64>; 869 status = "disabled"; 870 }; 871 }; 872 873 usi_14: usi@10d200c0 { 874 compatible = "samsung,exynosautov920-usi", 875 "samsung,exynos850-usi"; 876 reg = <0x10d200c0 0x20>; 877 samsung,sysreg = <&syscon_peric1 0x1028>; 878 samsung,mode = <USI_V2_UART>; 879 #address-cells = <1>; 880 #size-cells = <1>; 881 ranges; 882 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 883 <&cmu_peric1 CLK_DOUT_PERIC1_USI14_USI>; 884 clock-names = "pclk", "ipclk"; 885 status = "disabled"; 886 887 serial_14: serial@10d20000 { 888 compatible = "samsung,exynosautov920-uart", 889 "samsung,exynos850-uart"; 890 reg = <0x10d20000 0xc0>; 891 interrupts = <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>; 892 pinctrl-names = "default"; 893 pinctrl-0 = <&uart14_bus>; 894 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 895 <&cmu_peric1 CLK_DOUT_PERIC1_USI14_USI>; 896 clock-names = "uart", "clk_uart_baud0"; 897 samsung,uart-fifosize = <64>; 898 status = "disabled"; 899 }; 900 }; 901 902 usi_15: usi@10d400c0 { 903 compatible = "samsung,exynosautov920-usi", 904 "samsung,exynos850-usi"; 905 reg = <0x10d400c0 0x20>; 906 samsung,sysreg = <&syscon_peric1 0x1030>; 907 samsung,mode = <USI_V2_UART>; 908 #address-cells = <1>; 909 #size-cells = <1>; 910 ranges; 911 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 912 <&cmu_peric1 CLK_DOUT_PERIC1_USI15_USI>; 913 clock-names = "pclk", "ipclk"; 914 status = "disabled"; 915 916 serial_15: serial@10d40000 { 917 compatible = "samsung,exynosautov920-uart", 918 "samsung,exynos850-uart"; 919 reg = <0x10d40000 0xc0>; 920 interrupts = <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>; 921 pinctrl-names = "default"; 922 pinctrl-0 = <&uart15_bus>; 923 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 924 <&cmu_peric1 CLK_DOUT_PERIC1_USI15_USI>; 925 clock-names = "uart", "clk_uart_baud0"; 926 samsung,uart-fifosize = <64>; 927 status = "disabled"; 928 }; 929 }; 930 931 usi_16: usi@10d600c0 { 932 compatible = "samsung,exynosautov920-usi", 933 "samsung,exynos850-usi"; 934 reg = <0x10d600c0 0x20>; 935 samsung,sysreg = <&syscon_peric1 0x1038>; 936 samsung,mode = <USI_V2_UART>; 937 #address-cells = <1>; 938 #size-cells = <1>; 939 ranges; 940 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 941 <&cmu_peric1 CLK_DOUT_PERIC1_USI16_USI>; 942 clock-names = "pclk", "ipclk"; 943 status = "disabled"; 944 945 serial_16: serial@10d60000 { 946 compatible = "samsung,exynosautov920-uart", 947 "samsung,exynos850-uart"; 948 reg = <0x10d60000 0xc0>; 949 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>; 950 pinctrl-names = "default"; 951 pinctrl-0 = <&uart16_bus>; 952 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 953 <&cmu_peric1 CLK_DOUT_PERIC1_USI16_USI>; 954 clock-names = "uart", "clk_uart_baud0"; 955 samsung,uart-fifosize = <64>; 956 status = "disabled"; 957 }; 958 }; 959 960 usi_17: usi@10d800c0 { 961 compatible = "samsung,exynosautov920-usi", 962 "samsung,exynos850-usi"; 963 reg = <0x10d800c0 0x20>; 964 samsung,sysreg = <&syscon_peric1 0x1040>; 965 samsung,mode = <USI_V2_UART>; 966 #address-cells = <1>; 967 #size-cells = <1>; 968 ranges; 969 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 970 <&cmu_peric1 CLK_DOUT_PERIC1_USI17_USI>; 971 clock-names = "pclk", "ipclk"; 972 status = "disabled"; 973 974 serial_17: serial@10d80000 { 975 compatible = "samsung,exynosautov920-uart", 976 "samsung,exynos850-uart"; 977 reg = <0x10d80000 0xc0>; 978 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 979 pinctrl-names = "default"; 980 pinctrl-0 = <&uart17_bus>; 981 clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, 982 <&cmu_peric1 CLK_DOUT_PERIC1_USI17_USI>; 983 clock-names = "uart", "clk_uart_baud0"; 984 samsung,uart-fifosize = <64>; 985 status = "disabled"; 986 }; 987 }; 988 989 cmu_top: clock-controller@11000000 { 990 compatible = "samsung,exynosautov920-cmu-top"; 991 reg = <0x11000000 0x8000>; 992 #clock-cells = <1>; 993 994 clocks = <&xtcxo>; 995 clock-names = "oscclk"; 996 }; 997 998 pinctrl_alive: pinctrl@11850000 { 999 compatible = "samsung,exynosautov920-pinctrl"; 1000 reg = <0x11850000 0x10000>; 1001 1002 wakeup-interrupt-controller { 1003 compatible = "samsung,exynosautov920-wakeup-eint"; 1004 }; 1005 }; 1006 1007 pmu_system_controller: system-controller@11860000 { 1008 compatible = "samsung,exynosautov920-pmu", 1009 "samsung,exynos7-pmu","syscon"; 1010 reg = <0x11860000 0x10000>; 1011 }; 1012 1013 cmu_hsi0: clock-controller@16000000 { 1014 compatible = "samsung,exynosautov920-cmu-hsi0"; 1015 reg = <0x16000000 0x8000>; 1016 #clock-cells = <1>; 1017 1018 clocks = <&xtcxo>, 1019 <&cmu_top DOUT_CLKCMU_HSI0_NOC>; 1020 clock-names = "oscclk", 1021 "noc"; 1022 }; 1023 1024 pinctrl_hsi0: pinctrl@16040000 { 1025 compatible = "samsung,exynosautov920-pinctrl"; 1026 reg = <0x16040000 0x10000>; 1027 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>; 1028 }; 1029 1030 cmu_hsi1: clock-controller@16400000 { 1031 compatible = "samsung,exynosautov920-cmu-hsi1"; 1032 reg = <0x16400000 0x8000>; 1033 #clock-cells = <1>; 1034 1035 clocks = <&xtcxo>, 1036 <&cmu_top DOUT_CLKCMU_HSI1_NOC>, 1037 <&cmu_top DOUT_CLKCMU_HSI1_USBDRD>, 1038 <&cmu_top DOUT_CLKCMU_HSI1_MMC_CARD>; 1039 clock-names = "oscclk", 1040 "noc", 1041 "usbdrd", 1042 "mmc_card"; 1043 }; 1044 1045 pinctrl_hsi1: pinctrl@16450000 { 1046 compatible = "samsung,exynosautov920-pinctrl"; 1047 reg = <0x16450000 0x10000>; 1048 interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>; 1049 }; 1050 1051 pinctrl_hsi2: pinctrl@16c10000 { 1052 compatible = "samsung,exynosautov920-pinctrl"; 1053 reg = <0x16c10000 0x10000>; 1054 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1055 }; 1056 1057 pinctrl_hsi2ufs: pinctrl@16d20000 { 1058 compatible = "samsung,exynosautov920-pinctrl"; 1059 reg = <0x16d20000 0x10000>; 1060 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1061 }; 1062 1063 ufs_0_phy: phy@16e04000 { 1064 compatible = "samsung,exynosautov920-ufs-phy"; 1065 reg = <0x16e04000 0x4000>; 1066 reg-names = "phy-pma"; 1067 clocks = <&xtcxo>; 1068 clock-names = "ref_clk"; 1069 samsung,pmu-syscon = <&pmu_system_controller>; 1070 #phy-cells = <0>; 1071 status = "disabled"; 1072 }; 1073 1074 pinctrl_aud: pinctrl@1a460000 { 1075 compatible = "samsung,exynosautov920-pinctrl"; 1076 reg = <0x1a460000 0x10000>; 1077 }; 1078 1079 cmu_cpucl0: clock-controller@1ec00000 { 1080 compatible = "samsung,exynosautov920-cmu-cpucl0"; 1081 reg = <0x1ec00000 0x8000>; 1082 #clock-cells = <1>; 1083 1084 clocks = <&xtcxo>, 1085 <&cmu_top DOUT_CLKCMU_CPUCL0_SWITCH>, 1086 <&cmu_top DOUT_CLKCMU_CPUCL0_CLUSTER>, 1087 <&cmu_top DOUT_CLKCMU_CPUCL0_DBG>; 1088 clock-names = "oscclk", 1089 "switch", 1090 "cluster", 1091 "dbg"; 1092 }; 1093 1094 cmu_cpucl1: clock-controller@1ed00000 { 1095 compatible = "samsung,exynosautov920-cmu-cpucl1"; 1096 reg = <0x1ed00000 0x8000>; 1097 #clock-cells = <1>; 1098 1099 clocks = <&xtcxo>, 1100 <&cmu_top DOUT_CLKCMU_CPUCL1_SWITCH>, 1101 <&cmu_top DOUT_CLKCMU_CPUCL1_CLUSTER>; 1102 clock-names = "oscclk", 1103 "switch", 1104 "cluster"; 1105 }; 1106 1107 cmu_cpucl2: clock-controller@1ee00000 { 1108 compatible = "samsung,exynosautov920-cmu-cpucl2"; 1109 reg = <0x1ee00000 0x8000>; 1110 #clock-cells = <1>; 1111 1112 clocks = <&xtcxo>, 1113 <&cmu_top DOUT_CLKCMU_CPUCL2_SWITCH>, 1114 <&cmu_top DOUT_CLKCMU_CPUCL2_CLUSTER>; 1115 clock-names = "oscclk", 1116 "switch", 1117 "cluster"; 1118 }; 1119 }; 1120 1121 timer { 1122 compatible = "arm,armv8-timer"; 1123 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 1124 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 1125 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 1126 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 1127 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 1128 }; 1129}; 1130 1131#include "exynosautov920-pinctrl.dtsi" 1132