xref: /linux/arch/arm64/boot/dts/exynos/exynos7885.dtsi (revision 06d07429858317ded2db7986113a9e0129cd599b) 
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung Exynos7885 SoC device tree source
4 *
5 * Copyright (c) 2021 Samsung Electronics Co., Ltd.
6 * Copyright (c) 2021 Dávid Virág
7 */
8
9#include <dt-bindings/clock/exynos7885.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11
12/ {
13	compatible = "samsung,exynos7885";
14	#address-cells = <2>;
15	#size-cells = <1>;
16
17	interrupt-parent = <&gic>;
18
19	aliases {
20		pinctrl0 = &pinctrl_alive;
21		pinctrl1 = &pinctrl_dispaud;
22		pinctrl2 = &pinctrl_fsys;
23		pinctrl3 = &pinctrl_top;
24	};
25
26	arm-a53-pmu {
27		compatible = "arm,cortex-a53-pmu";
28		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
29			     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
30			     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
31			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
32			     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
33			     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
34		interrupt-affinity = <&cpu0>,
35				     <&cpu1>,
36				     <&cpu2>,
37				     <&cpu3>,
38				     <&cpu4>,
39				     <&cpu5>;
40	};
41
42	arm-a73-pmu {
43		compatible = "arm,cortex-a73-pmu";
44		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
45			     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
46		interrupt-affinity = <&cpu6>,
47				     <&cpu7>;
48	};
49
50	cpus {
51		#address-cells = <1>;
52		#size-cells = <0>;
53
54		cpu-map {
55			cluster0 {
56				core0 {
57					cpu = <&cpu0>;
58				};
59				core1 {
60					cpu = <&cpu1>;
61				};
62				core2 {
63					cpu = <&cpu2>;
64				};
65				core3 {
66					cpu = <&cpu3>;
67				};
68				core4 {
69					cpu = <&cpu4>;
70				};
71				core5 {
72					cpu = <&cpu5>;
73				};
74			};
75
76			cluster1 {
77				core0 {
78					cpu = <&cpu6>;
79				};
80				core1 {
81					cpu = <&cpu7>;
82				};
83			};
84		};
85
86		cpu0: cpu@100 {
87			device_type = "cpu";
88			compatible = "arm,cortex-a53";
89			reg = <0x100>;
90			enable-method = "psci";
91		};
92
93		cpu1: cpu@101 {
94			device_type = "cpu";
95			compatible = "arm,cortex-a53";
96			reg = <0x101>;
97			enable-method = "psci";
98		};
99
100		cpu2: cpu@102 {
101			device_type = "cpu";
102			compatible = "arm,cortex-a53";
103			reg = <0x102>;
104			enable-method = "psci";
105		};
106
107		cpu3: cpu@103 {
108			device_type = "cpu";
109			compatible = "arm,cortex-a53";
110			reg = <0x103>;
111			enable-method = "psci";
112		};
113
114		cpu4: cpu@200 {
115			device_type = "cpu";
116			compatible = "arm,cortex-a53";
117			reg = <0x200>;
118			enable-method = "psci";
119		};
120
121		cpu5: cpu@201 {
122			device_type = "cpu";
123			compatible = "arm,cortex-a53";
124			reg = <0x201>;
125			enable-method = "psci";
126		};
127
128		cpu6: cpu@0 {
129			device_type = "cpu";
130			compatible = "arm,cortex-a73";
131			reg = <0x0>;
132			enable-method = "psci";
133		};
134
135		cpu7: cpu@1 {
136			device_type = "cpu";
137			compatible = "arm,cortex-a73";
138			reg = <0x1>;
139			enable-method = "psci";
140		};
141	};
142
143	psci {
144		compatible = "arm,psci";
145		method = "smc";
146		cpu_suspend = <0xc4000001>;
147		cpu_off = <0x84000002>;
148		cpu_on = <0xc4000003>;
149	};
150
151	timer {
152		compatible = "arm,armv8-timer";
153		/* Hypervisor Virtual Timer interrupt is not wired to GIC */
154		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
155			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
156			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
157			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
158	};
159
160	fixed-rate-clocks {
161		oscclk: osc-clock {
162			compatible = "fixed-clock";
163			#clock-cells = <0>;
164			clock-output-names = "oscclk";
165		};
166	};
167
168	soc: soc@0 {
169		compatible = "simple-bus";
170		#address-cells = <1>;
171		#size-cells = <1>;
172		ranges = <0x0 0x0 0x0 0x20000000>;
173
174		chipid@10000000 {
175			compatible = "samsung,exynos7885-chipid",
176				     "samsung,exynos850-chipid";
177			reg = <0x10000000 0x24>;
178		};
179
180		gic: interrupt-controller@12301000 {
181			compatible = "arm,gic-400";
182			#interrupt-cells = <3>;
183			#address-cells = <0>;
184			interrupt-controller;
185			reg = <0x12301000 0x1000>,
186			      <0x12302000 0x2000>,
187			      <0x12304000 0x2000>,
188			      <0x12306000 0x2000>;
189			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
190						 IRQ_TYPE_LEVEL_HIGH)>;
191		};
192
193		cmu_peri: clock-controller@10010000 {
194			compatible = "samsung,exynos7885-cmu-peri";
195			reg = <0x10010000 0x8000>;
196			#clock-cells = <1>;
197
198			clocks = <&oscclk>,
199				 <&cmu_top CLK_DOUT_PERI_BUS>,
200				 <&cmu_top CLK_DOUT_PERI_SPI0>,
201				 <&cmu_top CLK_DOUT_PERI_SPI1>,
202				 <&cmu_top CLK_DOUT_PERI_UART0>,
203				 <&cmu_top CLK_DOUT_PERI_UART1>,
204				 <&cmu_top CLK_DOUT_PERI_UART2>,
205				 <&cmu_top CLK_DOUT_PERI_USI0>,
206				 <&cmu_top CLK_DOUT_PERI_USI1>,
207				 <&cmu_top CLK_DOUT_PERI_USI2>;
208			clock-names = "oscclk",
209				      "dout_peri_bus",
210				      "dout_peri_spi0",
211				      "dout_peri_spi1",
212				      "dout_peri_uart0",
213				      "dout_peri_uart1",
214				      "dout_peri_uart2",
215				      "dout_peri_usi0",
216				      "dout_peri_usi1",
217				      "dout_peri_usi2";
218		};
219
220		cmu_core: clock-controller@12000000 {
221			compatible = "samsung,exynos7885-cmu-core";
222			reg = <0x12000000 0x8000>;
223			#clock-cells = <1>;
224
225			clocks = <&oscclk>,
226				 <&cmu_top CLK_DOUT_CORE_BUS>,
227				 <&cmu_top CLK_DOUT_CORE_CCI>,
228				 <&cmu_top CLK_DOUT_CORE_G3D>;
229			clock-names = "oscclk",
230				      "dout_core_bus",
231				      "dout_core_cci",
232				      "dout_core_g3d";
233		};
234
235		cmu_top: clock-controller@12060000 {
236			compatible = "samsung,exynos7885-cmu-top";
237			reg = <0x12060000 0x8000>;
238			#clock-cells = <1>;
239
240			clocks = <&oscclk>;
241			clock-names = "oscclk";
242		};
243
244		cmu_fsys: clock-controller@13400000 {
245			compatible = "samsung,exynos7885-cmu-fsys";
246			reg = <0x13400000 0x8000>;
247			#clock-cells = <1>;
248
249			clocks = <&oscclk>,
250				 <&cmu_top CLK_DOUT_FSYS_BUS>,
251				 <&cmu_top CLK_DOUT_FSYS_MMC_CARD>,
252				 <&cmu_top CLK_DOUT_FSYS_MMC_EMBD>,
253				 <&cmu_top CLK_DOUT_FSYS_MMC_SDIO>,
254				 <&cmu_top CLK_DOUT_FSYS_USB30DRD>;
255			clock-names = "oscclk",
256				      "dout_fsys_bus",
257				      "dout_fsys_mmc_card",
258				      "dout_fsys_mmc_embd",
259				      "dout_fsys_mmc_sdio",
260				      "dout_fsys_usb30drd";
261		};
262
263		pinctrl_alive: pinctrl@11cb0000 {
264			compatible = "samsung,exynos7885-pinctrl";
265			reg = <0x11cb0000 0x1000>;
266
267			wakeup-interrupt-controller {
268				compatible = "samsung,exynos7885-wakeup-eint",
269					     "samsung,exynos7-wakeup-eint";
270				interrupt-parent = <&gic>;
271				interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
272			};
273		};
274
275		pinctrl_fsys: pinctrl@13430000 {
276			compatible = "samsung,exynos7885-pinctrl";
277			reg = <0x13430000 0x1000>;
278			interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
279		};
280
281		pinctrl_top: pinctrl@139b0000 {
282			compatible = "samsung,exynos7885-pinctrl";
283			reg = <0x139b0000 0x1000>;
284			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
285		};
286
287		pinctrl_dispaud: pinctrl@148f0000 {
288			compatible = "samsung,exynos7885-pinctrl";
289			reg = <0x148f0000 0x1000>;
290			interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
291		};
292
293		pmu_system_controller: system-controller@11c80000 {
294			compatible = "samsung,exynos7885-pmu",
295				     "samsung,exynos7-pmu", "syscon";
296			reg = <0x11c80000 0x10000>;
297		};
298
299		mmc_0: mmc@13500000 {
300			compatible = "samsung,exynos7885-dw-mshc-smu",
301				     "samsung,exynos7-dw-mshc-smu";
302			reg = <0x13500000 0x2000>;
303			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
304			#address-cells = <1>;
305			#size-cells = <0>;
306			clocks = <&cmu_fsys CLK_GOUT_MMC_EMBD_ACLK>,
307				 <&cmu_fsys CLK_GOUT_MMC_EMBD_SDCLKIN>;
308			clock-names = "biu", "ciu";
309			fifo-depth = <0x40>;
310			status = "disabled";
311		};
312
313		serial_0: serial@13800000 {
314			compatible = "samsung,exynos7885-uart",
315				     "samsung,exynos5433-uart";
316			reg = <0x13800000 0x100>;
317			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
318			pinctrl-names = "default";
319			pinctrl-0 = <&uart0_bus>;
320			clocks = <&cmu_peri CLK_GOUT_UART0_PCLK>,
321				 <&cmu_peri CLK_GOUT_UART0_EXT_UCLK>;
322			clock-names = "uart", "clk_uart_baud0";
323			samsung,uart-fifosize = <64>;
324			status = "disabled";
325		};
326
327		serial_1: serial@13810000 {
328			compatible = "samsung,exynos7885-uart",
329				     "samsung,exynos5433-uart";
330			reg = <0x13810000 0x100>;
331			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
332			pinctrl-names = "default";
333			pinctrl-0 = <&uart1_bus>;
334			clocks = <&cmu_peri CLK_GOUT_UART1_PCLK>,
335				 <&cmu_peri CLK_GOUT_UART1_EXT_UCLK>;
336			clock-names = "uart", "clk_uart_baud0";
337			samsung,uart-fifosize = <256>;
338			status = "disabled";
339		};
340
341		serial_2: serial@13820000 {
342			compatible = "samsung,exynos7885-uart",
343				     "samsung,exynos5433-uart";
344			reg = <0x13820000 0x100>;
345			interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>;
346			pinctrl-names = "default";
347			pinctrl-0 = <&uart2_bus>;
348			clocks = <&cmu_peri CLK_GOUT_UART2_PCLK>,
349				 <&cmu_peri CLK_GOUT_UART2_EXT_UCLK>;
350			clock-names = "uart", "clk_uart_baud0";
351			samsung,uart-fifosize = <256>;
352			status = "disabled";
353		};
354
355		i2c_0: i2c@13830000 {
356			compatible = "samsung,exynos7885-i2c",
357				     "samsung,s3c2440-i2c";
358			reg = <0x13830000 0x100>;
359			interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
360			#address-cells = <1>;
361			#size-cells = <0>;
362			pinctrl-names = "default";
363			pinctrl-0 = <&i2c0_bus>;
364			clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>;
365			clock-names = "i2c";
366			status = "disabled";
367		};
368
369		i2c_1: i2c@13840000 {
370			compatible = "samsung,exynos7885-i2c",
371				     "samsung,s3c2440-i2c";
372			reg = <0x13840000 0x100>;
373			interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
374			#address-cells = <1>;
375			#size-cells = <0>;
376			pinctrl-names = "default";
377			pinctrl-0 = <&i2c1_bus>;
378			clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>;
379			clock-names = "i2c";
380			status = "disabled";
381		};
382
383		i2c_2: i2c@13850000 {
384			compatible = "samsung,exynos7885-i2c",
385				     "samsung,s3c2440-i2c";
386			reg = <0x13850000 0x100>;
387			interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
388			#address-cells = <1>;
389			#size-cells = <0>;
390			pinctrl-names = "default";
391			pinctrl-0 = <&i2c2_bus>;
392			clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>;
393			clock-names = "i2c";
394			status = "disabled";
395		};
396
397		i2c_3: i2c@13860000 {
398			compatible = "samsung,exynos7885-i2c",
399				     "samsung,s3c2440-i2c";
400			reg = <0x13860000 0x100>;
401			interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
402			#address-cells = <1>;
403			#size-cells = <0>;
404			pinctrl-names = "default";
405			pinctrl-0 = <&i2c3_bus>;
406			clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>;
407			clock-names = "i2c";
408			status = "disabled";
409		};
410
411		i2c_4: i2c@13870000 {
412			compatible = "samsung,exynos7885-i2c",
413				     "samsung,s3c2440-i2c";
414			reg = <0x13870000 0x100>;
415			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
416			#address-cells = <1>;
417			#size-cells = <0>;
418			pinctrl-names = "default";
419			pinctrl-0 = <&i2c4_bus>;
420			clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>;
421			clock-names = "i2c";
422			status = "disabled";
423		};
424
425		i2c_5: i2c@13880000 {
426			compatible = "samsung,exynos7885-i2c",
427				     "samsung,s3c2440-i2c";
428			reg = <0x13880000 0x100>;
429			interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
430			#address-cells = <1>;
431			#size-cells = <0>;
432			pinctrl-names = "default";
433			pinctrl-0 = <&i2c5_bus>;
434			clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>;
435			clock-names = "i2c";
436			status = "disabled";
437		};
438
439		i2c_6: i2c@13890000 {
440			compatible = "samsung,exynos7885-i2c",
441				     "samsung,s3c2440-i2c";
442			reg = <0x13890000 0x100>;
443			interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
444			#address-cells = <1>;
445			#size-cells = <0>;
446			pinctrl-names = "default";
447			pinctrl-0 = <&i2c6_bus>;
448			clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>;
449			clock-names = "i2c";
450			status = "disabled";
451		};
452
453		i2c_7: i2c@11cd0000 {
454			compatible = "samsung,exynos7885-i2c",
455				     "samsung,s3c2440-i2c";
456			reg = <0x11cd0000 0x100>;
457			interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
458			#address-cells = <1>;
459			#size-cells = <0>;
460			pinctrl-names = "default";
461			pinctrl-0 = <&i2c7_bus>;
462			clocks = <&cmu_peri CLK_GOUT_I2C7_PCLK>;
463			clock-names = "i2c";
464			status = "disabled";
465		};
466	};
467};
468
469#include "exynos7885-pinctrl.dtsi"
470#include "arm/samsung/exynos-syscon-restart.dtsi"
471