1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 3#include <dt-bindings/interrupt-controller/irq.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/en7523-clk.h> 6#include <dt-bindings/reset/airoha,en7581-reset.h> 7 8/ { 9 interrupt-parent = <&gic>; 10 #address-cells = <2>; 11 #size-cells = <2>; 12 13 reserved-memory { 14 #address-cells = <2>; 15 #size-cells = <2>; 16 ranges; 17 18 npu-binary@84000000 { 19 no-map; 20 reg = <0x0 0x84000000 0x0 0xa00000>; 21 }; 22 23 npu-flag@84b0000 { 24 no-map; 25 reg = <0x0 0x84b00000 0x0 0x100000>; 26 }; 27 28 npu-pkt@85000000 { 29 no-map; 30 reg = <0x0 0x85000000 0x0 0x1a00000>; 31 }; 32 33 npu-phyaddr@86b00000 { 34 no-map; 35 reg = <0x0 0x86b00000 0x0 0x100000>; 36 }; 37 38 npu-rxdesc@86d00000 { 39 no-map; 40 reg = <0x0 0x86d00000 0x0 0x100000>; 41 }; 42 }; 43 44 psci { 45 compatible = "arm,psci-1.0"; 46 method = "smc"; 47 }; 48 49 cpus { 50 #address-cells = <1>; 51 #size-cells = <0>; 52 53 cpu-map { 54 cluster0 { 55 core0 { 56 cpu = <&cpu0>; 57 }; 58 59 core1 { 60 cpu = <&cpu1>; 61 }; 62 63 core2 { 64 cpu = <&cpu2>; 65 }; 66 67 core3 { 68 cpu = <&cpu3>; 69 }; 70 }; 71 }; 72 73 cpu0: cpu@0 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a53"; 76 reg = <0x0>; 77 enable-method = "psci"; 78 clock-frequency = <80000000>; 79 next-level-cache = <&l2>; 80 }; 81 82 cpu1: cpu@1 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a53"; 85 reg = <0x1>; 86 enable-method = "psci"; 87 clock-frequency = <80000000>; 88 next-level-cache = <&l2>; 89 }; 90 91 cpu2: cpu@2 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a53"; 94 reg = <0x2>; 95 enable-method = "psci"; 96 clock-frequency = <80000000>; 97 next-level-cache = <&l2>; 98 }; 99 100 cpu3: cpu@3 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a53"; 103 reg = <0x3>; 104 enable-method = "psci"; 105 clock-frequency = <80000000>; 106 next-level-cache = <&l2>; 107 }; 108 109 l2: l2-cache { 110 compatible = "cache"; 111 cache-size = <0x80000>; 112 cache-line-size = <64>; 113 cache-level = <2>; 114 cache-unified; 115 }; 116 }; 117 118 timer { 119 compatible = "arm,armv8-timer"; 120 interrupt-parent = <&gic>; 121 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 122 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 123 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 124 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 125 }; 126 127 clk20m: clock-20000000 { 128 compatible = "fixed-clock"; 129 #clock-cells = <0>; 130 clock-frequency = <20000000>; 131 }; 132 133 soc { 134 compatible = "simple-bus"; 135 #address-cells = <2>; 136 #size-cells = <2>; 137 ranges; 138 139 gic: interrupt-controller@9000000 { 140 compatible = "arm,gic-v3"; 141 interrupt-controller; 142 #interrupt-cells = <3>; 143 #address-cells = <1>; 144 #size-cells = <1>; 145 reg = <0x0 0x09000000 0x0 0x20000>, 146 <0x0 0x09080000 0x0 0x80000>, 147 <0x0 0x09400000 0x0 0x2000>, 148 <0x0 0x09500000 0x0 0x2000>, 149 <0x0 0x09600000 0x0 0x20000>; 150 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 151 }; 152 153 spi@1fa10000 { 154 compatible = "airoha,en7581-snand"; 155 reg = <0x0 0x1fa10000 0x0 0x140>, 156 <0x0 0x1fa11000 0x0 0x160>; 157 158 clocks = <&scuclk EN7523_CLK_SPI>; 159 clock-names = "spi"; 160 161 #address-cells = <1>; 162 #size-cells = <0>; 163 164 status = "disabled"; 165 166 spi_nand: nand@0 { 167 compatible = "spi-nand"; 168 reg = <0>; 169 170 spi-max-frequency = <50000000>; 171 spi-tx-bus-width = <1>; 172 spi-rx-bus-width = <2>; 173 }; 174 }; 175 176 scuclk: clock-controller@1fb00000 { 177 compatible = "airoha,en7581-scu"; 178 reg = <0x0 0x1fb00000 0x0 0x970>; 179 #clock-cells = <1>; 180 #reset-cells = <1>; 181 }; 182 183 pbus_csr: syscon@1fbe3400 { 184 compatible = "airoha,en7581-pbus-csr", "syscon"; 185 reg = <0x0 0x1fbe3400 0x0 0xff>; 186 }; 187 188 pciephy: phy@1fa5a000 { 189 compatible = "airoha,en7581-pcie-phy"; 190 reg = <0x0 0x1fa5a000 0x0 0xfff>, 191 <0x0 0x1fa5b000 0x0 0xfff>, 192 <0x0 0x1fa5c000 0x0 0xfff>, 193 <0x0 0x1fc10044 0x0 0x4>, 194 <0x0 0x1fc30044 0x0 0x4>, 195 <0x0 0x1fc15030 0x0 0x104>; 196 reg-names = "csr-2l", "pma0", "pma1", 197 "p0-xr-dtime", "p1-xr-dtime", 198 "rx-aeq"; 199 #phy-cells = <0>; 200 }; 201 202 pcie0: pcie@1fc00000 { 203 compatible = "airoha,en7581-pcie"; 204 device_type = "pci"; 205 linux,pci-domain = <0>; 206 #address-cells = <3>; 207 #size-cells = <2>; 208 209 reg = <0x0 0x1fc00000 0x0 0x1670>; 210 reg-names = "pcie-mac"; 211 212 clocks = <&scuclk EN7523_CLK_PCIE>; 213 clock-names = "sys-ck"; 214 215 phys = <&pciephy>; 216 phy-names = "pcie-phy"; 217 218 ranges = <0x02000000 0 0x20000000 0x0 0x20000000 0 0x4000000>; 219 220 resets = <&scuclk EN7581_PCIE0_RST>, 221 <&scuclk EN7581_PCIE1_RST>, 222 <&scuclk EN7581_PCIE2_RST>; 223 reset-names = "phy-lane0", "phy-lane1", "phy-lane2"; 224 225 mediatek,pbus-csr = <&pbus_csr 0x0 0x4>; 226 227 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 228 bus-range = <0x00 0xff>; 229 #interrupt-cells = <1>; 230 interrupt-map-mask = <0 0 0 7>; 231 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 232 <0 0 0 2 &pcie_intc0 1>, 233 <0 0 0 3 &pcie_intc0 2>, 234 <0 0 0 4 &pcie_intc0 3>; 235 236 status = "disabled"; 237 238 pcie_intc0: interrupt-controller { 239 interrupt-controller; 240 #address-cells = <0>; 241 #interrupt-cells = <1>; 242 }; 243 }; 244 245 pcie1: pcie@1fc20000 { 246 compatible = "airoha,en7581-pcie"; 247 device_type = "pci"; 248 linux,pci-domain = <1>; 249 #address-cells = <3>; 250 #size-cells = <2>; 251 252 reg = <0x0 0x1fc20000 0x0 0x1670>; 253 reg-names = "pcie-mac"; 254 255 clocks = <&scuclk EN7523_CLK_PCIE>; 256 clock-names = "sys-ck"; 257 258 phys = <&pciephy>; 259 phy-names = "pcie-phy"; 260 261 ranges = <0x02000000 0 0x24000000 0x0 0x24000000 0 0x4000000>; 262 263 resets = <&scuclk EN7581_PCIE0_RST>, 264 <&scuclk EN7581_PCIE1_RST>, 265 <&scuclk EN7581_PCIE2_RST>; 266 reset-names = "phy-lane0", "phy-lane1", "phy-lane2"; 267 268 mediatek,pbus-csr = <&pbus_csr 0x8 0xc>; 269 270 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 271 bus-range = <0x00 0xff>; 272 #interrupt-cells = <1>; 273 interrupt-map-mask = <0 0 0 7>; 274 interrupt-map = <0 0 0 1 &pcie_intc1 0>, 275 <0 0 0 2 &pcie_intc1 1>, 276 <0 0 0 3 &pcie_intc1 2>, 277 <0 0 0 4 &pcie_intc1 3>; 278 279 status = "disabled"; 280 281 pcie_intc1: interrupt-controller { 282 interrupt-controller; 283 #address-cells = <0>; 284 #interrupt-cells = <1>; 285 }; 286 }; 287 288 uart1: serial@1fbf0000 { 289 compatible = "ns16550"; 290 reg = <0x0 0x1fbf0000 0x0 0x30>; 291 reg-io-width = <4>; 292 reg-shift = <2>; 293 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 294 clock-frequency = <1843200>; 295 }; 296 297 rng@1faa1000 { 298 compatible = "airoha,en7581-trng"; 299 reg = <0x0 0x1faa1000 0x0 0xc04>; 300 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 301 }; 302 303 system-controller@1fbf0200 { 304 compatible = "airoha,en7581-gpio-sysctl", "syscon", 305 "simple-mfd"; 306 reg = <0x0 0x1fbf0200 0x0 0xc0>; 307 308 en7581_pinctrl: pinctrl { 309 compatible = "airoha,en7581-pinctrl"; 310 311 interrupt-parent = <&gic>; 312 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 313 314 gpio-controller; 315 #gpio-cells = <2>; 316 317 interrupt-controller; 318 #interrupt-cells = <2>; 319 }; 320 }; 321 322 i2c0: i2c@1fbf8000 { 323 compatible = "mediatek,mt7621-i2c"; 324 reg = <0x0 0x1fbf8000 0x0 0x100>; 325 326 resets = <&scuclk EN7581_I2C2_RST>; 327 328 clocks = <&clk20m>; 329 clock-frequency = <100000>; 330 #address-cells = <1>; 331 #size-cells = <0>; 332 333 status = "disabled"; 334 }; 335 336 i2c1: i2c@1fbf8100 { 337 compatible = "mediatek,mt7621-i2c"; 338 reg = <0x0 0x1fbf8100 0x0 0x100>; 339 340 resets = <&scuclk EN7581_I2C_MASTER_RST>; 341 342 clocks = <&clk20m>; 343 clock-frequency = <100000>; 344 #address-cells = <1>; 345 #size-cells = <0>; 346 347 status = "disabled"; 348 }; 349 }; 350}; 351