1 // SPDX-License-Identifier: GPL-2.0-only
2 /****************************************************************************
3
4 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
5 All rights reserved
6 www.echoaudio.com
7
8 This file is part of Echo Digital Audio's generic driver library.
9 *************************************************************************
10
11 Translation from C++ and adaptation for use in ALSA-Driver
12 were made by Giuliano Pochini <pochini@shiny.it>
13
14 ****************************************************************************/
15
16
17
18 /* These functions are common for all "3G" cards */
19
20
check_asic_status(struct echoaudio * chip)21 static int check_asic_status(struct echoaudio *chip)
22 {
23 u32 box_status;
24
25 if (wait_handshake(chip))
26 return -EIO;
27
28 chip->comm_page->ext_box_status = cpu_to_le32(E3G_ASIC_NOT_LOADED);
29 chip->asic_loaded = false;
30 clear_handshake(chip);
31 send_vector(chip, DSP_VC_TEST_ASIC);
32
33 if (wait_handshake(chip)) {
34 chip->dsp_code = NULL;
35 return -EIO;
36 }
37
38 box_status = le32_to_cpu(chip->comm_page->ext_box_status);
39 dev_dbg(chip->card->dev, "box_status=%x\n", box_status);
40 if (box_status == E3G_ASIC_NOT_LOADED)
41 return -ENODEV;
42
43 chip->asic_loaded = true;
44 return box_status & E3G_BOX_TYPE_MASK;
45 }
46
47
48
get_frq_reg(struct echoaudio * chip)49 static inline u32 get_frq_reg(struct echoaudio *chip)
50 {
51 return le32_to_cpu(chip->comm_page->e3g_frq_register);
52 }
53
54
55
56 /* Most configuration of 3G cards is accomplished by writing the control
57 register. write_control_reg sends the new control register value to the DSP. */
write_control_reg(struct echoaudio * chip,u32 ctl,u32 frq,char force)58 static int write_control_reg(struct echoaudio *chip, u32 ctl, u32 frq,
59 char force)
60 {
61 __le32 ctl_reg, frq_reg;
62
63 if (wait_handshake(chip))
64 return -EIO;
65
66 dev_dbg(chip->card->dev,
67 "WriteControlReg: Setting 0x%x, 0x%x\n", ctl, frq);
68
69 ctl_reg = cpu_to_le32(ctl);
70 frq_reg = cpu_to_le32(frq);
71
72 if (ctl_reg != chip->comm_page->control_register ||
73 frq_reg != chip->comm_page->e3g_frq_register || force) {
74 chip->comm_page->e3g_frq_register = frq_reg;
75 chip->comm_page->control_register = ctl_reg;
76 clear_handshake(chip);
77 return send_vector(chip, DSP_VC_WRITE_CONTROL_REG);
78 }
79
80 dev_dbg(chip->card->dev, "WriteControlReg: not written, no change\n");
81 return 0;
82 }
83
84
85
86 /* Set the digital mode - currently for Gina24, Layla24, Mona, 3G */
set_digital_mode(struct echoaudio * chip,u8 mode)87 static int set_digital_mode(struct echoaudio *chip, u8 mode)
88 {
89 u8 previous_mode;
90 int err, i, o;
91
92 /* All audio channels must be closed before changing the digital mode */
93 if (snd_BUG_ON(chip->pipe_alloc_mask))
94 return -EAGAIN;
95
96 if (snd_BUG_ON(!(chip->digital_modes & (1 << mode))))
97 return -EINVAL;
98
99 previous_mode = chip->digital_mode;
100 err = dsp_set_digital_mode(chip, mode);
101
102 /* If we successfully changed the digital mode from or to ADAT,
103 * then make sure all output, input and monitor levels are
104 * updated by the DSP comm object. */
105 if (err >= 0 && previous_mode != mode &&
106 (previous_mode == DIGITAL_MODE_ADAT || mode == DIGITAL_MODE_ADAT)) {
107 guard(spinlock_irq)(&chip->lock);
108 for (o = 0; o < num_busses_out(chip); o++)
109 for (i = 0; i < num_busses_in(chip); i++)
110 set_monitor_gain(chip, o, i,
111 chip->monitor_gain[o][i]);
112
113 #ifdef ECHOCARD_HAS_INPUT_GAIN
114 for (i = 0; i < num_busses_in(chip); i++)
115 set_input_gain(chip, i, chip->input_gain[i]);
116 update_input_line_level(chip);
117 #endif
118
119 for (o = 0; o < num_busses_out(chip); o++)
120 set_output_gain(chip, o, chip->output_gain[o]);
121 update_output_line_level(chip);
122 }
123
124 return err;
125 }
126
127
128
set_spdif_bits(struct echoaudio * chip,u32 control_reg,u32 rate)129 static u32 set_spdif_bits(struct echoaudio *chip, u32 control_reg, u32 rate)
130 {
131 control_reg &= E3G_SPDIF_FORMAT_CLEAR_MASK;
132
133 switch (rate) {
134 case 32000 :
135 control_reg |= E3G_SPDIF_SAMPLE_RATE0 | E3G_SPDIF_SAMPLE_RATE1;
136 break;
137 case 44100 :
138 if (chip->professional_spdif)
139 control_reg |= E3G_SPDIF_SAMPLE_RATE0;
140 break;
141 case 48000 :
142 control_reg |= E3G_SPDIF_SAMPLE_RATE1;
143 break;
144 }
145
146 if (chip->professional_spdif)
147 control_reg |= E3G_SPDIF_PRO_MODE;
148
149 if (chip->non_audio_spdif)
150 control_reg |= E3G_SPDIF_NOT_AUDIO;
151
152 control_reg |= E3G_SPDIF_24_BIT | E3G_SPDIF_TWO_CHANNEL |
153 E3G_SPDIF_COPY_PERMIT;
154
155 return control_reg;
156 }
157
158
159
160 /* Set the S/PDIF output format */
set_professional_spdif(struct echoaudio * chip,char prof)161 static int set_professional_spdif(struct echoaudio *chip, char prof)
162 {
163 u32 control_reg;
164
165 control_reg = le32_to_cpu(chip->comm_page->control_register);
166 chip->professional_spdif = prof;
167 control_reg = set_spdif_bits(chip, control_reg, chip->sample_rate);
168 return write_control_reg(chip, control_reg, get_frq_reg(chip), 0);
169 }
170
171
172
173 /* detect_input_clocks() returns a bitmask consisting of all the input clocks
174 currently connected to the hardware; this changes as the user connects and
175 disconnects clock inputs. You should use this information to determine which
176 clocks the user is allowed to select. */
detect_input_clocks(const struct echoaudio * chip)177 static u32 detect_input_clocks(const struct echoaudio *chip)
178 {
179 u32 clocks_from_dsp, clock_bits;
180
181 /* Map the DSP clock detect bits to the generic driver clock
182 * detect bits */
183 clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
184
185 clock_bits = ECHO_CLOCK_BIT_INTERNAL;
186
187 if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_WORD)
188 clock_bits |= ECHO_CLOCK_BIT_WORD;
189
190 switch(chip->digital_mode) {
191 case DIGITAL_MODE_SPDIF_RCA:
192 case DIGITAL_MODE_SPDIF_OPTICAL:
193 if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_SPDIF)
194 clock_bits |= ECHO_CLOCK_BIT_SPDIF;
195 break;
196 case DIGITAL_MODE_ADAT:
197 if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_ADAT)
198 clock_bits |= ECHO_CLOCK_BIT_ADAT;
199 break;
200 }
201
202 return clock_bits;
203 }
204
205
206
load_asic(struct echoaudio * chip)207 static int load_asic(struct echoaudio *chip)
208 {
209 int box_type, err;
210
211 if (chip->asic_loaded)
212 return 0;
213
214 /* Give the DSP a few milliseconds to settle down */
215 mdelay(2);
216
217 err = load_asic_generic(chip, DSP_FNC_LOAD_3G_ASIC, FW_3G_ASIC);
218 if (err < 0)
219 return err;
220
221 chip->asic_code = FW_3G_ASIC;
222
223 /* Now give the new ASIC some time to set up */
224 msleep(1000);
225 /* See if it worked */
226 box_type = check_asic_status(chip);
227
228 /* Set up the control register if the load succeeded -
229 * 48 kHz, internal clock, S/PDIF RCA mode */
230 if (box_type >= 0) {
231 err = write_control_reg(chip, E3G_48KHZ,
232 E3G_FREQ_REG_DEFAULT, true);
233 if (err < 0)
234 return err;
235 }
236
237 return box_type;
238 }
239
240
241
set_sample_rate(struct echoaudio * chip,u32 rate)242 static int set_sample_rate(struct echoaudio *chip, u32 rate)
243 {
244 u32 control_reg, clock, base_rate, frq_reg;
245
246 /* Only set the clock for internal mode. */
247 if (chip->input_clock != ECHO_CLOCK_INTERNAL) {
248 dev_warn(chip->card->dev,
249 "Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n");
250 /* Save the rate anyhow */
251 chip->comm_page->sample_rate = cpu_to_le32(rate);
252 chip->sample_rate = rate;
253 set_input_clock(chip, chip->input_clock);
254 return 0;
255 }
256
257 if (snd_BUG_ON(rate >= 50000 &&
258 chip->digital_mode == DIGITAL_MODE_ADAT))
259 return -EINVAL;
260
261 control_reg = le32_to_cpu(chip->comm_page->control_register);
262 control_reg &= E3G_CLOCK_CLEAR_MASK;
263
264 switch (rate) {
265 case 96000:
266 clock = E3G_96KHZ;
267 break;
268 case 88200:
269 clock = E3G_88KHZ;
270 break;
271 case 48000:
272 clock = E3G_48KHZ;
273 break;
274 case 44100:
275 clock = E3G_44KHZ;
276 break;
277 case 32000:
278 clock = E3G_32KHZ;
279 break;
280 default:
281 clock = E3G_CONTINUOUS_CLOCK;
282 if (rate > 50000)
283 clock |= E3G_DOUBLE_SPEED_MODE;
284 break;
285 }
286
287 control_reg |= clock;
288 control_reg = set_spdif_bits(chip, control_reg, rate);
289
290 base_rate = rate;
291 if (base_rate > 50000)
292 base_rate /= 2;
293 if (base_rate < 32000)
294 base_rate = 32000;
295
296 frq_reg = E3G_MAGIC_NUMBER / base_rate - 2;
297 if (frq_reg > E3G_FREQ_REG_MAX)
298 frq_reg = E3G_FREQ_REG_MAX;
299
300 chip->comm_page->sample_rate = cpu_to_le32(rate); /* ignored by the DSP */
301 chip->sample_rate = rate;
302 dev_dbg(chip->card->dev,
303 "SetSampleRate: %d clock %x\n", rate, control_reg);
304
305 /* Tell the DSP about it - DSP reads both control reg & freq reg */
306 return write_control_reg(chip, control_reg, frq_reg, 0);
307 }
308
309
310
311 /* Set the sample clock source to internal, S/PDIF, ADAT */
set_input_clock(struct echoaudio * chip,u16 clock)312 static int set_input_clock(struct echoaudio *chip, u16 clock)
313 {
314 u32 control_reg, clocks_from_dsp;
315
316
317 /* Mask off the clock select bits */
318 control_reg = le32_to_cpu(chip->comm_page->control_register) &
319 E3G_CLOCK_CLEAR_MASK;
320 clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
321
322 switch (clock) {
323 case ECHO_CLOCK_INTERNAL:
324 chip->input_clock = ECHO_CLOCK_INTERNAL;
325 return set_sample_rate(chip, chip->sample_rate);
326 case ECHO_CLOCK_SPDIF:
327 if (chip->digital_mode == DIGITAL_MODE_ADAT)
328 return -EAGAIN;
329 control_reg |= E3G_SPDIF_CLOCK;
330 if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_SPDIF96)
331 control_reg |= E3G_DOUBLE_SPEED_MODE;
332 else
333 control_reg &= ~E3G_DOUBLE_SPEED_MODE;
334 break;
335 case ECHO_CLOCK_ADAT:
336 if (chip->digital_mode != DIGITAL_MODE_ADAT)
337 return -EAGAIN;
338 control_reg |= E3G_ADAT_CLOCK;
339 control_reg &= ~E3G_DOUBLE_SPEED_MODE;
340 break;
341 case ECHO_CLOCK_WORD:
342 control_reg |= E3G_WORD_CLOCK;
343 if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_WORD96)
344 control_reg |= E3G_DOUBLE_SPEED_MODE;
345 else
346 control_reg &= ~E3G_DOUBLE_SPEED_MODE;
347 break;
348 default:
349 dev_err(chip->card->dev,
350 "Input clock 0x%x not supported for Echo3G\n", clock);
351 return -EINVAL;
352 }
353
354 chip->input_clock = clock;
355 return write_control_reg(chip, control_reg, get_frq_reg(chip), 1);
356 }
357
358
359
dsp_set_digital_mode(struct echoaudio * chip,u8 mode)360 static int dsp_set_digital_mode(struct echoaudio *chip, u8 mode)
361 {
362 u32 control_reg;
363 int err, incompatible_clock;
364
365 /* Set clock to "internal" if it's not compatible with the new mode */
366 incompatible_clock = false;
367 switch (mode) {
368 case DIGITAL_MODE_SPDIF_OPTICAL:
369 case DIGITAL_MODE_SPDIF_RCA:
370 if (chip->input_clock == ECHO_CLOCK_ADAT)
371 incompatible_clock = true;
372 break;
373 case DIGITAL_MODE_ADAT:
374 if (chip->input_clock == ECHO_CLOCK_SPDIF)
375 incompatible_clock = true;
376 break;
377 default:
378 dev_err(chip->card->dev,
379 "Digital mode not supported: %d\n", mode);
380 return -EINVAL;
381 }
382
383 guard(spinlock_irq)(&chip->lock);
384
385 if (incompatible_clock) {
386 chip->sample_rate = 48000;
387 set_input_clock(chip, ECHO_CLOCK_INTERNAL);
388 }
389
390 /* Clear the current digital mode */
391 control_reg = le32_to_cpu(chip->comm_page->control_register);
392 control_reg &= E3G_DIGITAL_MODE_CLEAR_MASK;
393
394 /* Tweak the control reg */
395 switch (mode) {
396 case DIGITAL_MODE_SPDIF_OPTICAL:
397 control_reg |= E3G_SPDIF_OPTICAL_MODE;
398 break;
399 case DIGITAL_MODE_SPDIF_RCA:
400 /* E3G_SPDIF_OPTICAL_MODE bit cleared */
401 break;
402 case DIGITAL_MODE_ADAT:
403 control_reg |= E3G_ADAT_MODE;
404 control_reg &= ~E3G_DOUBLE_SPEED_MODE; /* @@ useless */
405 break;
406 }
407
408 err = write_control_reg(chip, control_reg, get_frq_reg(chip), 1);
409 if (err < 0)
410 return err;
411 chip->digital_mode = mode;
412
413 dev_dbg(chip->card->dev, "set_digital_mode(%d)\n", chip->digital_mode);
414 return incompatible_clock;
415 }
416