1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Imagination E5010 JPEG Encoder driver. 4 * 5 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ 6 * 7 * Author: David Huang <d-huang@ti.com> 8 * Author: Devarsh Thakkar <devarsht@ti.com> 9 */ 10 11 #ifndef _E5010_JPEG_ENC_HW_H 12 #define _E5010_JPEG_ENC_HW_H 13 14 #include "e5010-core-regs.h" 15 #include "e5010-mmu-regs.h" 16 17 int e5010_hw_enable_output_address_error_irq(void __iomem *core_offset, u32 enable); 18 int e5010_hw_enable_picture_done_irq(void __iomem *core_offset, u32 enable); 19 int e5010_hw_enable_auto_clock_gating(void __iomem *core_offset, u32 enable); 20 int e5010_hw_enable_manual_clock_gating(void __iomem *core_offset, u32 enable); 21 int e5010_hw_enable_crc_check(void __iomem *core_offset, u32 enable); 22 int e5010_hw_set_input_source_to_memory(void __iomem *core_offset, u32 set); 23 int e5010_hw_set_input_luma_addr(void __iomem *core_offset, u32 val); 24 int e5010_hw_set_input_chroma_addr(void __iomem *core_offset, u32 val); 25 int e5010_hw_set_output_base_addr(void __iomem *core_offset, u32 val); 26 int e5010_hw_get_output_size(void __iomem *core_offset); 27 int e5010_hw_set_horizontal_size(void __iomem *core_offset, u32 val); 28 int e5010_hw_set_vertical_size(void __iomem *core_offset, u32 val); 29 int e5010_hw_set_luma_stride(void __iomem *core_offset, u32 bytesperline); 30 int e5010_hw_set_chroma_stride(void __iomem *core_offset, u32 bytesperline); 31 int e5010_hw_set_input_subsampling(void __iomem *core_offset, u32 val); 32 int e5010_hw_set_chroma_order(void __iomem *core_offset, u32 val); 33 int e5010_hw_set_qpvalue(void __iomem *core_offset, u32 offset, u32 value); 34 void e5010_reset(struct device *dev, void __iomem *core_offset, void __iomem *mmu_offset); 35 void e5010_hw_set_output_max_size(void __iomem *core_offset, u32 val); 36 void e5010_hw_clear_picture_done(void __iomem *core_offset, u32 clear); 37 void e5010_hw_encode_start(void __iomem *core_offset, u32 start); 38 void e5010_hw_clear_output_error(void __iomem *core_offset, u32 clear); 39 void e5010_hw_bypass_mmu(void __iomem *mmu_base, u32 enable); 40 bool e5010_hw_pic_done_irq(void __iomem *core_base); 41 bool e5010_hw_output_address_irq(void __iomem *core_base); 42 #endif 43