1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Xilinx Zynq MPSoC Firmware layer 4 * 5 * Copyright (C) 2014-2018 Xilinx, Inc. 6 * 7 */ 8 9 #ifndef _DT_BINDINGS_CLK_ZYNQMP_H 10 #define _DT_BINDINGS_CLK_ZYNQMP_H 11 12 /* 13 * These bindings are deprecated, because they do not match the actual 14 * concept of bindings but rather contain pure firmware values. 15 * Instead include the header in the DTS source directory. 16 */ 17 #warning "These bindings are deprecated. Instead use the header in the DTS source directory." 18 19 #define IOPLL 0 20 #define RPLL 1 21 #define APLL 2 22 #define DPLL 3 23 #define VPLL 4 24 #define IOPLL_TO_FPD 5 25 #define RPLL_TO_FPD 6 26 #define APLL_TO_LPD 7 27 #define DPLL_TO_LPD 8 28 #define VPLL_TO_LPD 9 29 #define ACPU 10 30 #define ACPU_HALF 11 31 #define DBF_FPD 12 32 #define DBF_LPD 13 33 #define DBG_TRACE 14 34 #define DBG_TSTMP 15 35 #define DP_VIDEO_REF 16 36 #define DP_AUDIO_REF 17 37 #define DP_STC_REF 18 38 #define GDMA_REF 19 39 #define DPDMA_REF 20 40 #define DDR_REF 21 41 #define SATA_REF 22 42 #define PCIE_REF 23 43 #define GPU_REF 24 44 #define GPU_PP0_REF 25 45 #define GPU_PP1_REF 26 46 #define TOPSW_MAIN 27 47 #define TOPSW_LSBUS 28 48 #define GTGREF0_REF 29 49 #define LPD_SWITCH 30 50 #define LPD_LSBUS 31 51 #define USB0_BUS_REF 32 52 #define USB1_BUS_REF 33 53 #define USB3_DUAL_REF 34 54 #define USB0 35 55 #define USB1 36 56 #define CPU_R5 37 57 #define CPU_R5_CORE 38 58 #define CSU_SPB 39 59 #define CSU_PLL 40 60 #define PCAP 41 61 #define IOU_SWITCH 42 62 #define GEM_TSU_REF 43 63 #define GEM_TSU 44 64 #define GEM0_TX 45 65 #define GEM1_TX 46 66 #define GEM2_TX 47 67 #define GEM3_TX 48 68 #define GEM0_RX 49 69 #define GEM1_RX 50 70 #define GEM2_RX 51 71 #define GEM3_RX 52 72 #define QSPI_REF 53 73 #define SDIO0_REF 54 74 #define SDIO1_REF 55 75 #define UART0_REF 56 76 #define UART1_REF 57 77 #define SPI0_REF 58 78 #define SPI1_REF 59 79 #define NAND_REF 60 80 #define I2C0_REF 61 81 #define I2C1_REF 62 82 #define CAN0_REF 63 83 #define CAN1_REF 64 84 #define CAN0 65 85 #define CAN1 66 86 #define DLL_REF 67 87 #define ADMA_REF 68 88 #define TIMESTAMP_REF 69 89 #define AMS_REF 70 90 #define PL0_REF 71 91 #define PL1_REF 72 92 #define PL2_REF 73 93 #define PL3_REF 74 94 #define WDT 75 95 #define IOPLL_INT 76 96 #define IOPLL_PRE_SRC 77 97 #define IOPLL_HALF 78 98 #define IOPLL_INT_MUX 79 99 #define IOPLL_POST_SRC 80 100 #define RPLL_INT 81 101 #define RPLL_PRE_SRC 82 102 #define RPLL_HALF 83 103 #define RPLL_INT_MUX 84 104 #define RPLL_POST_SRC 85 105 #define APLL_INT 86 106 #define APLL_PRE_SRC 87 107 #define APLL_HALF 88 108 #define APLL_INT_MUX 89 109 #define APLL_POST_SRC 90 110 #define DPLL_INT 91 111 #define DPLL_PRE_SRC 92 112 #define DPLL_HALF 93 113 #define DPLL_INT_MUX 94 114 #define DPLL_POST_SRC 95 115 #define VPLL_INT 96 116 #define VPLL_PRE_SRC 97 117 #define VPLL_HALF 98 118 #define VPLL_INT_MUX 99 119 #define VPLL_POST_SRC 100 120 #define CAN0_MIO 101 121 #define CAN1_MIO 102 122 #define ACPU_FULL 103 123 #define GEM0_REF 104 124 #define GEM1_REF 105 125 #define GEM2_REF 106 126 #define GEM3_REF 107 127 #define GEM0_REF_UNG 108 128 #define GEM1_REF_UNG 109 129 #define GEM2_REF_UNG 110 130 #define GEM3_REF_UNG 111 131 #define LPD_WDT 112 132 133 #endif 134