xref: /linux/drivers/gpu/drm/msm/registers/display/dsi_phy_28nm_8960.xml (revision db5d28c0bfe566908719bec8e25443aabecbb802) 
1<?xml version="1.0" encoding="UTF-8"?>
2<database xmlns="http://nouveau.freedesktop.org/"
3xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
5<import file="freedreno_copyright.xml"/>
6
7<domain name="DSI_28nm_8960_PHY" width="32">
8
9	<array offset="0x00000" name="LN" length="4" stride="0x40">
10		<reg32 offset="0x00" name="CFG_0"/>
11		<reg32 offset="0x04" name="CFG_1"/>
12		<reg32 offset="0x08" name="CFG_2"/>
13		<reg32 offset="0x0c" name="TEST_DATAPATH"/>
14		<reg32 offset="0x14" name="TEST_STR_0"/>
15		<reg32 offset="0x18" name="TEST_STR_1"/>
16	</array>
17
18	<reg32 offset="0x00100" name="LNCK_CFG_0"/>
19	<reg32 offset="0x00104" name="LNCK_CFG_1"/>
20	<reg32 offset="0x00108" name="LNCK_CFG_2"/>
21
22	<reg32 offset="0x0010c" name="LNCK_TEST_DATAPATH"/>
23	<reg32 offset="0x00114" name="LNCK_TEST_STR0"/>
24	<reg32 offset="0x00118" name="LNCK_TEST_STR1"/>
25
26	<reg32 offset="0x00140" name="TIMING_CTRL_0">
27		<bitfield name="CLK_ZERO" low="0" high="7" type="uint"/>
28	</reg32>
29	<reg32 offset="0x00144" name="TIMING_CTRL_1">
30		<bitfield name="CLK_TRAIL" low="0" high="7" type="uint"/>
31	</reg32>
32	<reg32 offset="0x00148" name="TIMING_CTRL_2">
33		<bitfield name="CLK_PREPARE" low="0" high="7" type="uint"/>
34	</reg32>
35
36	<reg32 offset="0x0014c" name="TIMING_CTRL_3"/>
37
38	<reg32 offset="0x00150" name="TIMING_CTRL_4">
39		<bitfield name="HS_EXIT" low="0" high="7" type="uint"/>
40	</reg32>
41	<reg32 offset="0x00154" name="TIMING_CTRL_5">
42		<bitfield name="HS_ZERO" low="0" high="7" type="uint"/>
43	</reg32>
44	<reg32 offset="0x00158" name="TIMING_CTRL_6">
45		<bitfield name="HS_PREPARE" low="0" high="7" type="uint"/>
46	</reg32>
47	<reg32 offset="0x0015c" name="TIMING_CTRL_7">
48		<bitfield name="HS_TRAIL" low="0" high="7" type="uint"/>
49	</reg32>
50	<reg32 offset="0x00160" name="TIMING_CTRL_8">
51		<bitfield name="HS_RQST" low="0" high="7" type="uint"/>
52	</reg32>
53	<reg32 offset="0x00164" name="TIMING_CTRL_9">
54		<bitfield name="TA_GO" low="0" high="2" type="uint"/>
55		<bitfield name="TA_SURE" low="4" high="6" type="uint"/>
56	</reg32>
57	<reg32 offset="0x00168" name="TIMING_CTRL_10">
58		<bitfield name="TA_GET" low="0" high="2" type="uint"/>
59	</reg32>
60	<reg32 offset="0x0016c" name="TIMING_CTRL_11">
61		<bitfield name="TRIG3_CMD" low="0" high="7" type="uint"/>
62	</reg32>
63
64	<reg32 offset="0x00170" name="CTRL_0"/>
65	<reg32 offset="0x00174" name="CTRL_1"/>
66	<reg32 offset="0x00178" name="CTRL_2"/>
67	<reg32 offset="0x0017c" name="CTRL_3"/>
68
69	<reg32 offset="0x00180" name="STRENGTH_0"/>
70	<reg32 offset="0x00184" name="STRENGTH_1"/>
71	<reg32 offset="0x00188" name="STRENGTH_2"/>
72
73	<reg32 offset="0x0018c" name="BIST_CTRL_0"/>
74	<reg32 offset="0x00190" name="BIST_CTRL_1"/>
75	<reg32 offset="0x00194" name="BIST_CTRL_2"/>
76	<reg32 offset="0x00198" name="BIST_CTRL_3"/>
77	<reg32 offset="0x0019c" name="BIST_CTRL_4"/>
78
79	<reg32 offset="0x001b0" name="LDO_CTRL"/>
80</domain>
81
82<domain name="DSI_28nm_8960_PHY_MISC" width="32">
83	<reg32 offset="0x00000" name="REGULATOR_CTRL_0"/>
84	<reg32 offset="0x00004" name="REGULATOR_CTRL_1"/>
85	<reg32 offset="0x00008" name="REGULATOR_CTRL_2"/>
86	<reg32 offset="0x0000c" name="REGULATOR_CTRL_3"/>
87	<reg32 offset="0x00010" name="REGULATOR_CTRL_4"/>
88	<reg32 offset="0x00014" name="REGULATOR_CTRL_5"/>
89	<reg32 offset="0x00018" name="REGULATOR_CAL_PWR_CFG"/>
90	<reg32 offset="0x00028" name="CAL_HW_TRIGGER"/>
91	<reg32 offset="0x0002c" name="CAL_SW_CFG_0"/>
92	<reg32 offset="0x00030" name="CAL_SW_CFG_1"/>
93	<reg32 offset="0x00034" name="CAL_SW_CFG_2"/>
94	<reg32 offset="0x00038" name="CAL_HW_CFG_0"/>
95	<reg32 offset="0x0003c" name="CAL_HW_CFG_1"/>
96	<reg32 offset="0x00040" name="CAL_HW_CFG_2"/>
97	<reg32 offset="0x00044" name="CAL_HW_CFG_3"/>
98	<reg32 offset="0x00048" name="CAL_HW_CFG_4"/>
99	<reg32 offset="0x00050" name="CAL_STATUS">
100		<bitfield name="CAL_BUSY" pos="4" type="boolean"/>
101	</reg32>
102</domain>
103
104<domain name="DSI_28nm_8960_PHY_PLL" width="32">
105	<reg32 offset="0x00000" name="CTRL_0">
106		<bitfield name="ENABLE" pos="0" type="boolean"/>
107	</reg32>
108	<reg32 offset="0x00004" name="CTRL_1"/>
109	<reg32 offset="0x00008" name="CTRL_2"/>
110	<reg32 offset="0x0000c" name="CTRL_3"/>
111	<reg32 offset="0x00010" name="CTRL_4"/>
112	<reg32 offset="0x00014" name="CTRL_5"/>
113	<reg32 offset="0x00018" name="CTRL_6"/>
114	<reg32 offset="0x0001c" name="CTRL_7"/>
115	<reg32 offset="0x00020" name="CTRL_8"/>
116	<reg32 offset="0x00024" name="CTRL_9"/>
117	<reg32 offset="0x00028" name="CTRL_10"/>
118	<reg32 offset="0x0002c" name="CTRL_11"/>
119	<reg32 offset="0x00030" name="CTRL_12"/>
120	<reg32 offset="0x00034" name="CTRL_13"/>
121	<reg32 offset="0x00038" name="CTRL_14"/>
122	<reg32 offset="0x0003c" name="CTRL_15"/>
123	<reg32 offset="0x00040" name="CTRL_16"/>
124	<reg32 offset="0x00044" name="CTRL_17"/>
125	<reg32 offset="0x00048" name="CTRL_18"/>
126	<reg32 offset="0x0004c" name="CTRL_19"/>
127	<reg32 offset="0x00050" name="CTRL_20"/>
128
129	<reg32 offset="0x00080" name="RDY">
130		<bitfield name="PLL_RDY" pos="0" type="boolean"/>
131	</reg32>
132</domain>
133
134</database>
135