1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /*
3 * Renesas UFS host controller driver
4 *
5 * Copyright (C) 2022 Renesas Electronics Corporation
6 */
7
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/err.h>
12 #include <linux/firmware.h>
13 #include <linux/iopoll.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/nvmem-consumer.h>
17 #include <linux/of.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/sys_soc.h>
21 #include <ufs/ufshcd.h>
22
23 #include "ufshcd-pltfrm.h"
24
25 #define EFUSE_CALIB_SIZE 8
26
27 struct ufs_renesas_priv {
28 const struct firmware *fw;
29 void (*pre_init)(struct ufs_hba *hba);
30 bool initialized; /* The hardware needs initialization once */
31 u8 calib[EFUSE_CALIB_SIZE];
32 };
33
34 #define UFS_RENESAS_FIRMWARE_NAME "r8a779f0_ufs.bin"
35 MODULE_FIRMWARE(UFS_RENESAS_FIRMWARE_NAME);
36
ufs_renesas_dbg_register_dump(struct ufs_hba * hba)37 static void ufs_renesas_dbg_register_dump(struct ufs_hba *hba)
38 {
39 ufshcd_dump_regs(hba, 0xc0, 0x40, "regs: 0xc0 + ");
40 }
41
ufs_renesas_poll(struct ufs_hba * hba,u32 reg,u32 expected,u32 mask)42 static void ufs_renesas_poll(struct ufs_hba *hba, u32 reg, u32 expected, u32 mask)
43 {
44 int ret;
45 u32 val;
46
47 ret = readl_poll_timeout_atomic(hba->mmio_base + reg,
48 val, (val & mask) == expected,
49 10, 1000);
50 if (ret)
51 dev_err(hba->dev, "%s: poll failed %d (%08x, %08x, %08x)\n",
52 __func__, ret, val, mask, expected);
53 }
54
ufs_renesas_read(struct ufs_hba * hba,u32 reg)55 static u32 ufs_renesas_read(struct ufs_hba *hba, u32 reg)
56 {
57 return ufshcd_readl(hba, reg);
58 }
59
ufs_renesas_write(struct ufs_hba * hba,u32 reg,u32 value)60 static void ufs_renesas_write(struct ufs_hba *hba, u32 reg, u32 value)
61 {
62 ufshcd_writel(hba, value, reg);
63 }
64
ufs_renesas_write_d0_d4(struct ufs_hba * hba,u32 data_d0,u32 data_d4)65 static void ufs_renesas_write_d0_d4(struct ufs_hba *hba, u32 data_d0, u32 data_d4)
66 {
67 ufs_renesas_write(hba, 0xd0, data_d0);
68 ufs_renesas_write(hba, 0xd4, data_d4);
69 }
70
ufs_renesas_write_800_80c_poll(struct ufs_hba * hba,u32 addr,u32 data_800)71 static void ufs_renesas_write_800_80c_poll(struct ufs_hba *hba, u32 addr,
72 u32 data_800)
73 {
74 ufs_renesas_write_d0_d4(hba, 0x0000080c, 0x00000100);
75 ufs_renesas_write_d0_d4(hba, 0x00000800, (data_800 << 16) | BIT(8) | addr);
76 ufs_renesas_write(hba, 0xd0, 0x0000080c);
77 ufs_renesas_poll(hba, 0xd4, BIT(8), BIT(8));
78 }
79
ufs_renesas_write_804_80c_poll(struct ufs_hba * hba,u32 addr,u32 data_804)80 static void ufs_renesas_write_804_80c_poll(struct ufs_hba *hba, u32 addr, u32 data_804)
81 {
82 ufs_renesas_write_d0_d4(hba, 0x0000080c, 0x00000100);
83 ufs_renesas_write_d0_d4(hba, 0x00000804, (data_804 << 16) | BIT(8) | addr);
84 ufs_renesas_write(hba, 0xd0, 0x0000080c);
85 ufs_renesas_poll(hba, 0xd4, BIT(8), BIT(8));
86 }
87
ufs_renesas_write_828_82c_poll(struct ufs_hba * hba,u32 data_828)88 static void ufs_renesas_write_828_82c_poll(struct ufs_hba *hba, u32 data_828)
89 {
90 ufs_renesas_write_d0_d4(hba, 0x0000082c, 0x0f000000);
91 ufs_renesas_write_d0_d4(hba, 0x00000828, data_828);
92 ufs_renesas_write(hba, 0xd0, 0x0000082c);
93 ufs_renesas_poll(hba, 0xd4, data_828, data_828);
94 }
95
ufs_renesas_write_phy(struct ufs_hba * hba,u32 addr16,u32 data16)96 static void ufs_renesas_write_phy(struct ufs_hba *hba, u32 addr16, u32 data16)
97 {
98 ufs_renesas_write(hba, 0xf0, 1);
99 ufs_renesas_write_800_80c_poll(hba, 0x16, addr16 & 0xff);
100 ufs_renesas_write_800_80c_poll(hba, 0x17, (addr16 >> 8) & 0xff);
101 ufs_renesas_write_800_80c_poll(hba, 0x18, data16 & 0xff);
102 ufs_renesas_write_800_80c_poll(hba, 0x19, (data16 >> 8) & 0xff);
103 ufs_renesas_write_800_80c_poll(hba, 0x1c, 0x01);
104 ufs_renesas_write_828_82c_poll(hba, 0x0f000000);
105 ufs_renesas_write(hba, 0xf0, 0);
106 }
107
ufs_renesas_set_phy(struct ufs_hba * hba,u32 addr16,u32 data16)108 static void ufs_renesas_set_phy(struct ufs_hba *hba, u32 addr16, u32 data16)
109 {
110 u32 low, high;
111
112 ufs_renesas_write(hba, 0xf0, 1);
113 ufs_renesas_write_800_80c_poll(hba, 0x16, addr16 & 0xff);
114 ufs_renesas_write_800_80c_poll(hba, 0x17, (addr16 >> 8) & 0xff);
115 ufs_renesas_write_800_80c_poll(hba, 0x1c, 0x01);
116 ufs_renesas_write_828_82c_poll(hba, 0x0f000000);
117 ufs_renesas_write_804_80c_poll(hba, 0x1a, 0);
118 ufs_renesas_write(hba, 0xd0, 0x00000808);
119 low = ufs_renesas_read(hba, 0xd4) & 0xff;
120 ufs_renesas_write_804_80c_poll(hba, 0x1b, 0);
121 ufs_renesas_write(hba, 0xd0, 0x00000808);
122 high = ufs_renesas_read(hba, 0xd4) & 0xff;
123 ufs_renesas_write_828_82c_poll(hba, 0x0f000000);
124 ufs_renesas_write(hba, 0xf0, 0);
125
126 data16 |= (high << 8) | low;
127 ufs_renesas_write_phy(hba, addr16, data16);
128 }
129
ufs_renesas_reset_indirect_write(struct ufs_hba * hba,int gpio,u32 addr,u32 data)130 static void ufs_renesas_reset_indirect_write(struct ufs_hba *hba, int gpio,
131 u32 addr, u32 data)
132 {
133 ufs_renesas_write(hba, 0xf0, gpio);
134 ufs_renesas_write_800_80c_poll(hba, addr, data);
135 }
136
ufs_renesas_reset_indirect_update(struct ufs_hba * hba)137 static void ufs_renesas_reset_indirect_update(struct ufs_hba *hba)
138 {
139 ufs_renesas_write_d0_d4(hba, 0x0000082c, 0x0f000000);
140 ufs_renesas_write_d0_d4(hba, 0x00000828, 0x0f000000);
141 ufs_renesas_write(hba, 0xd0, 0x0000082c);
142 ufs_renesas_poll(hba, 0xd4, BIT(27) | BIT(26) | BIT(24), BIT(27) | BIT(26) | BIT(24));
143 ufs_renesas_write(hba, 0xf0, 0);
144 }
145
ufs_renesas_indirect_write(struct ufs_hba * hba,u32 gpio,u32 addr,u32 data_800)146 static void ufs_renesas_indirect_write(struct ufs_hba *hba, u32 gpio, u32 addr,
147 u32 data_800)
148 {
149 ufs_renesas_write(hba, 0xf0, gpio);
150 ufs_renesas_write_800_80c_poll(hba, addr, data_800);
151 ufs_renesas_write_828_82c_poll(hba, 0x0f000000);
152 ufs_renesas_write(hba, 0xf0, 0);
153 }
154
ufs_renesas_indirect_poll(struct ufs_hba * hba,u32 gpio,u32 addr,u32 expected,u32 mask)155 static void ufs_renesas_indirect_poll(struct ufs_hba *hba, u32 gpio, u32 addr,
156 u32 expected, u32 mask)
157 {
158 ufs_renesas_write(hba, 0xf0, gpio);
159 ufs_renesas_write_800_80c_poll(hba, addr, 0);
160 ufs_renesas_write(hba, 0xd0, 0x00000808);
161 ufs_renesas_poll(hba, 0xd4, expected, mask);
162 ufs_renesas_write(hba, 0xf0, 0);
163 }
164
ufs_renesas_init_step1_to_3(struct ufs_hba * hba,bool init108)165 static void ufs_renesas_init_step1_to_3(struct ufs_hba *hba, bool init108)
166 {
167 ufs_renesas_write(hba, 0xc0, 0x49425308);
168 ufs_renesas_write_d0_d4(hba, 0x00000104, 0x00000002);
169 if (init108)
170 ufs_renesas_write_d0_d4(hba, 0x00000108, 0x00000002);
171 udelay(1);
172 ufs_renesas_write_d0_d4(hba, 0x00000828, 0x00000200);
173 udelay(1);
174 ufs_renesas_write_d0_d4(hba, 0x00000828, 0x00000000);
175 ufs_renesas_write_d0_d4(hba, 0x00000104, 0x00000001);
176 if (init108)
177 ufs_renesas_write_d0_d4(hba, 0x00000108, 0x00000001);
178 ufs_renesas_write_d0_d4(hba, 0x00000940, 0x00000001);
179 udelay(1);
180 ufs_renesas_write_d0_d4(hba, 0x00000940, 0x00000000);
181
182 ufs_renesas_write(hba, 0xc0, 0x49425308);
183 ufs_renesas_write(hba, 0xc0, 0x41584901);
184 }
185
ufs_renesas_init_step4_to_6(struct ufs_hba * hba)186 static void ufs_renesas_init_step4_to_6(struct ufs_hba *hba)
187 {
188 ufs_renesas_write_d0_d4(hba, 0x0000080c, 0x00000100);
189 ufs_renesas_write_d0_d4(hba, 0x00000804, 0x00000000);
190 ufs_renesas_write(hba, 0xd0, 0x0000080c);
191 ufs_renesas_poll(hba, 0xd4, BIT(8), BIT(8));
192
193 ufs_renesas_write(hba, REG_CONTROLLER_ENABLE, 0x00000001);
194
195 ufs_renesas_write(hba, 0xd0, 0x00000804);
196 ufs_renesas_poll(hba, 0xd4, BIT(8) | BIT(6) | BIT(0), BIT(8) | BIT(6) | BIT(0));
197 }
198
ufs_renesas_init_disable_timer(struct ufs_hba * hba)199 static u32 ufs_renesas_init_disable_timer(struct ufs_hba *hba)
200 {
201 u32 timer_val;
202
203 ufs_renesas_write(hba, 0xd0, 0x00000d00);
204 timer_val = ufs_renesas_read(hba, 0xd4) & 0x0000ffff;
205 ufs_renesas_write(hba, 0xd4, 0x00000000);
206 ufs_renesas_write_d0_d4(hba, 0x0000082c, 0x0f000000);
207 ufs_renesas_write_d0_d4(hba, 0x00000828, 0x08000000);
208 ufs_renesas_write(hba, 0xd0, 0x0000082c);
209 ufs_renesas_poll(hba, 0xd4, BIT(27), BIT(27));
210 ufs_renesas_write(hba, 0xd0, 0x00000d2c);
211 ufs_renesas_poll(hba, 0xd4, BIT(0), BIT(0));
212
213 return timer_val;
214 }
215
ufs_renesas_init_enable_timer(struct ufs_hba * hba,u32 timer_val)216 static void ufs_renesas_init_enable_timer(struct ufs_hba *hba, u32 timer_val)
217 {
218 ufs_renesas_write(hba, 0xf0, 0);
219 ufs_renesas_write(hba, 0xd0, 0x00000d00);
220 ufs_renesas_write(hba, 0xd4, timer_val);
221 }
222
ufs_renesas_write_phy_10ad_10af(struct ufs_hba * hba,u32 data_10ad,u32 data_10af)223 static void ufs_renesas_write_phy_10ad_10af(struct ufs_hba *hba,
224 u32 data_10ad, u32 data_10af)
225 {
226 ufs_renesas_write_phy(hba, 0x10ae, 0x0001);
227 ufs_renesas_write_phy(hba, 0x10ad, data_10ad);
228 ufs_renesas_write_phy(hba, 0x10af, data_10af);
229 ufs_renesas_write_phy(hba, 0x10b6, 0x0001);
230 ufs_renesas_write_phy(hba, 0x10ae, 0x0000);
231 }
232
ufs_renesas_init_compensation_and_slicers(struct ufs_hba * hba)233 static void ufs_renesas_init_compensation_and_slicers(struct ufs_hba *hba)
234 {
235 ufs_renesas_write_phy_10ad_10af(hba, 0x0000, 0x0001);
236 ufs_renesas_write_phy_10ad_10af(hba, 0x0000, 0x0002);
237 ufs_renesas_write_phy_10ad_10af(hba, 0x0080, 0x0000);
238 ufs_renesas_write_phy_10ad_10af(hba, 0x0080, 0x001a);
239 }
240
ufs_renesas_r8a779f0_es10_pre_init(struct ufs_hba * hba)241 static void ufs_renesas_r8a779f0_es10_pre_init(struct ufs_hba *hba)
242 {
243 u32 timer_val;
244
245 /* This setting is for SERIES B */
246 ufs_renesas_init_step1_to_3(hba, false);
247
248 ufs_renesas_init_step4_to_6(hba);
249
250 timer_val = ufs_renesas_init_disable_timer(hba);
251
252 /* phy setup */
253 ufs_renesas_indirect_write(hba, 1, 0x01, 0x001f);
254 ufs_renesas_indirect_write(hba, 7, 0x5d, 0x0014);
255 ufs_renesas_indirect_write(hba, 7, 0x5e, 0x0014);
256 ufs_renesas_indirect_write(hba, 7, 0x0d, 0x0003);
257 ufs_renesas_indirect_write(hba, 7, 0x0e, 0x0007);
258 ufs_renesas_indirect_write(hba, 7, 0x5f, 0x0003);
259 ufs_renesas_indirect_write(hba, 7, 0x60, 0x0003);
260 ufs_renesas_indirect_write(hba, 7, 0x5b, 0x00a6);
261 ufs_renesas_indirect_write(hba, 7, 0x5c, 0x0003);
262
263 ufs_renesas_indirect_poll(hba, 7, 0x3c, 0, BIT(7));
264 ufs_renesas_indirect_poll(hba, 7, 0x4c, 0, BIT(4));
265
266 ufs_renesas_indirect_write(hba, 1, 0x32, 0x0080);
267 ufs_renesas_indirect_write(hba, 1, 0x1f, 0x0001);
268 ufs_renesas_indirect_write(hba, 0, 0x2c, 0x0001);
269 ufs_renesas_indirect_write(hba, 0, 0x32, 0x0087);
270
271 ufs_renesas_indirect_write(hba, 1, 0x4d, 0x0061);
272 ufs_renesas_indirect_write(hba, 4, 0x9b, 0x0009);
273 ufs_renesas_indirect_write(hba, 4, 0xa6, 0x0005);
274 ufs_renesas_indirect_write(hba, 4, 0xa5, 0x0058);
275 ufs_renesas_indirect_write(hba, 1, 0x39, 0x0027);
276 ufs_renesas_indirect_write(hba, 1, 0x47, 0x004c);
277
278 ufs_renesas_indirect_write(hba, 7, 0x0d, 0x0002);
279 ufs_renesas_indirect_write(hba, 7, 0x0e, 0x0007);
280
281 ufs_renesas_write_phy(hba, 0x0028, 0x0061);
282 ufs_renesas_write_phy(hba, 0x4014, 0x0061);
283 ufs_renesas_set_phy(hba, 0x401c, BIT(2));
284 ufs_renesas_write_phy(hba, 0x4000, 0x0000);
285 ufs_renesas_write_phy(hba, 0x4001, 0x0000);
286
287 ufs_renesas_init_compensation_and_slicers(hba);
288
289 ufs_renesas_indirect_write(hba, 7, 0x70, 0x0016);
290 ufs_renesas_indirect_write(hba, 7, 0x71, 0x0016);
291 ufs_renesas_indirect_write(hba, 7, 0x72, 0x0014);
292 ufs_renesas_indirect_write(hba, 7, 0x73, 0x0014);
293 ufs_renesas_indirect_write(hba, 7, 0x74, 0x0000);
294 ufs_renesas_indirect_write(hba, 7, 0x75, 0x0000);
295 ufs_renesas_indirect_write(hba, 7, 0x76, 0x0010);
296 ufs_renesas_indirect_write(hba, 7, 0x77, 0x0010);
297 ufs_renesas_indirect_write(hba, 7, 0x78, 0x00ff);
298 ufs_renesas_indirect_write(hba, 7, 0x79, 0x0000);
299
300 ufs_renesas_indirect_write(hba, 7, 0x19, 0x0007);
301 ufs_renesas_indirect_write(hba, 7, 0x1a, 0x0007);
302 ufs_renesas_indirect_write(hba, 7, 0x24, 0x000c);
303 ufs_renesas_indirect_write(hba, 7, 0x25, 0x000c);
304 ufs_renesas_indirect_write(hba, 7, 0x62, 0x0000);
305 ufs_renesas_indirect_write(hba, 7, 0x63, 0x0000);
306 ufs_renesas_indirect_write(hba, 7, 0x5d, 0x0014);
307 ufs_renesas_indirect_write(hba, 7, 0x5e, 0x0017);
308 ufs_renesas_indirect_write(hba, 7, 0x5d, 0x0004);
309 ufs_renesas_indirect_write(hba, 7, 0x5e, 0x0017);
310 ufs_renesas_indirect_poll(hba, 7, 0x55, 0, BIT(6));
311 ufs_renesas_indirect_poll(hba, 7, 0x41, 0, BIT(7));
312 /* end of phy setup */
313
314 ufs_renesas_init_enable_timer(hba, timer_val);
315 }
316
ufs_renesas_r8a779f0_init_step3_add(struct ufs_hba * hba,bool assert)317 static void ufs_renesas_r8a779f0_init_step3_add(struct ufs_hba *hba, bool assert)
318 {
319 u32 val_2x = 0, val_3x = 0, val_4x = 0;
320
321 if (assert) {
322 val_2x = 0x0001;
323 val_3x = 0x0003;
324 val_4x = 0x0001;
325 }
326
327 ufs_renesas_reset_indirect_write(hba, 7, 0x20, val_2x);
328 ufs_renesas_reset_indirect_write(hba, 7, 0x4a, val_4x);
329 ufs_renesas_reset_indirect_write(hba, 7, 0x35, val_3x);
330 ufs_renesas_reset_indirect_update(hba);
331 ufs_renesas_reset_indirect_write(hba, 7, 0x21, val_2x);
332 ufs_renesas_reset_indirect_write(hba, 7, 0x4b, val_4x);
333 ufs_renesas_reset_indirect_write(hba, 7, 0x36, val_3x);
334 ufs_renesas_reset_indirect_update(hba);
335 }
336
ufs_renesas_r8a779f0_pre_init(struct ufs_hba * hba)337 static void ufs_renesas_r8a779f0_pre_init(struct ufs_hba *hba)
338 {
339 struct ufs_renesas_priv *priv = ufshcd_get_variant(hba);
340 u32 timer_val;
341 u32 data;
342 int i;
343
344 /* This setting is for SERIES B */
345 ufs_renesas_init_step1_to_3(hba, true);
346
347 ufs_renesas_r8a779f0_init_step3_add(hba, true);
348 ufs_renesas_reset_indirect_write(hba, 7, 0x5f, 0x0063);
349 ufs_renesas_reset_indirect_update(hba);
350 ufs_renesas_reset_indirect_write(hba, 7, 0x60, 0x0003);
351 ufs_renesas_reset_indirect_update(hba);
352 ufs_renesas_reset_indirect_write(hba, 7, 0x5b, 0x00a6);
353 ufs_renesas_reset_indirect_update(hba);
354 ufs_renesas_reset_indirect_write(hba, 7, 0x5c, 0x0003);
355 ufs_renesas_reset_indirect_update(hba);
356 ufs_renesas_r8a779f0_init_step3_add(hba, false);
357
358 ufs_renesas_init_step4_to_6(hba);
359
360 timer_val = ufs_renesas_init_disable_timer(hba);
361
362 ufs_renesas_indirect_write(hba, 1, 0x01, 0x001f);
363 ufs_renesas_indirect_write(hba, 7, 0x5d, 0x0014);
364 ufs_renesas_indirect_write(hba, 7, 0x5e, 0x0014);
365 ufs_renesas_indirect_write(hba, 7, 0x0d, 0x0007);
366 ufs_renesas_indirect_write(hba, 7, 0x0e, 0x0007);
367
368 ufs_renesas_indirect_poll(hba, 7, 0x3c, 0, BIT(7));
369 ufs_renesas_indirect_poll(hba, 7, 0x4c, 0, BIT(4));
370
371 ufs_renesas_indirect_write(hba, 1, 0x32, 0x0080);
372 ufs_renesas_indirect_write(hba, 1, 0x1f, 0x0001);
373 ufs_renesas_indirect_write(hba, 1, 0x2c, 0x0001);
374 ufs_renesas_indirect_write(hba, 1, 0x32, 0x0087);
375
376 ufs_renesas_indirect_write(hba, 1, 0x4d, priv->calib[2]);
377 ufs_renesas_indirect_write(hba, 1, 0x4e, priv->calib[3]);
378 ufs_renesas_indirect_write(hba, 1, 0x0d, 0x0006);
379 ufs_renesas_indirect_write(hba, 1, 0x0e, 0x0007);
380 ufs_renesas_write_phy(hba, 0x0028, priv->calib[3]);
381 ufs_renesas_write_phy(hba, 0x4014, priv->calib[3]);
382
383 ufs_renesas_set_phy(hba, 0x401c, BIT(2));
384
385 ufs_renesas_write_phy(hba, 0x4000, priv->calib[6]);
386 ufs_renesas_write_phy(hba, 0x4001, priv->calib[7]);
387
388 ufs_renesas_indirect_write(hba, 1, 0x14, 0x0001);
389
390 ufs_renesas_init_compensation_and_slicers(hba);
391
392 ufs_renesas_indirect_write(hba, 7, 0x79, 0x0000);
393 ufs_renesas_indirect_write(hba, 7, 0x24, 0x000c);
394 ufs_renesas_indirect_write(hba, 7, 0x25, 0x000c);
395 ufs_renesas_indirect_write(hba, 7, 0x62, 0x00c0);
396 ufs_renesas_indirect_write(hba, 7, 0x63, 0x0001);
397
398 for (i = 0; i < priv->fw->size / 2; i++) {
399 data = (priv->fw->data[i * 2 + 1] << 8) | priv->fw->data[i * 2];
400 ufs_renesas_write_phy(hba, 0xc000 + i, data);
401 }
402
403 ufs_renesas_indirect_write(hba, 7, 0x0d, 0x0002);
404 ufs_renesas_indirect_write(hba, 7, 0x0e, 0x0007);
405
406 ufs_renesas_indirect_write(hba, 7, 0x5d, 0x0014);
407 ufs_renesas_indirect_write(hba, 7, 0x5e, 0x0017);
408 ufs_renesas_indirect_write(hba, 7, 0x5d, 0x0004);
409 ufs_renesas_indirect_write(hba, 7, 0x5e, 0x0017);
410 ufs_renesas_indirect_poll(hba, 7, 0x55, 0, BIT(6));
411 ufs_renesas_indirect_poll(hba, 7, 0x41, 0, BIT(7));
412
413 ufs_renesas_init_enable_timer(hba, timer_val);
414 }
415
ufs_renesas_hce_enable_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)416 static int ufs_renesas_hce_enable_notify(struct ufs_hba *hba,
417 enum ufs_notify_change_status status)
418 {
419 struct ufs_renesas_priv *priv = ufshcd_get_variant(hba);
420
421 if (priv->initialized)
422 return 0;
423
424 if (status == PRE_CHANGE)
425 priv->pre_init(hba);
426
427 priv->initialized = true;
428
429 return 0;
430 }
431
ufs_renesas_setup_clocks(struct ufs_hba * hba,bool on,enum ufs_notify_change_status status)432 static int ufs_renesas_setup_clocks(struct ufs_hba *hba, bool on,
433 enum ufs_notify_change_status status)
434 {
435 if (on && status == PRE_CHANGE)
436 pm_runtime_get_sync(hba->dev);
437 else if (!on && status == POST_CHANGE)
438 pm_runtime_put(hba->dev);
439
440 return 0;
441 }
442
443 static const struct soc_device_attribute ufs_fallback[] = {
444 { .soc_id = "r8a779f0", .revision = "ES1.[01]" },
445 { /* Sentinel */ }
446 };
447
ufs_renesas_init(struct ufs_hba * hba)448 static int ufs_renesas_init(struct ufs_hba *hba)
449 {
450 const struct soc_device_attribute *attr;
451 struct nvmem_cell *cell = NULL;
452 struct device *dev = hba->dev;
453 struct ufs_renesas_priv *priv;
454 u8 *data = NULL;
455 size_t len;
456 int ret;
457
458 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
459 if (!priv)
460 return -ENOMEM;
461 ufshcd_set_variant(hba, priv);
462
463 hba->quirks |= UFSHCD_QUIRK_HIBERN_FASTAUTO;
464
465 attr = soc_device_match(ufs_fallback);
466 if (attr)
467 goto fallback;
468
469 ret = request_firmware(&priv->fw, UFS_RENESAS_FIRMWARE_NAME, dev);
470 if (ret) {
471 dev_warn(dev, "Failed to load firmware\n");
472 goto fallback;
473 }
474
475 cell = nvmem_cell_get(dev, "calibration");
476 if (IS_ERR(cell)) {
477 dev_warn(dev, "No calibration data specified\n");
478 goto fallback;
479 }
480
481 data = nvmem_cell_read(cell, &len);
482 if (IS_ERR(data)) {
483 dev_warn(dev, "Failed to read calibration data: %pe\n", data);
484 goto fallback;
485 }
486
487 if (len != EFUSE_CALIB_SIZE) {
488 dev_warn(dev, "Invalid calibration data size %zu\n", len);
489 goto fallback;
490 }
491
492 memcpy(priv->calib, data, EFUSE_CALIB_SIZE);
493 priv->pre_init = ufs_renesas_r8a779f0_pre_init;
494 goto out;
495
496 fallback:
497 dev_info(dev, "Using ES1.0 init code\n");
498 priv->pre_init = ufs_renesas_r8a779f0_es10_pre_init;
499
500 out:
501 kfree(data);
502 if (!IS_ERR_OR_NULL(cell))
503 nvmem_cell_put(cell);
504
505 return 0;
506 }
507
ufs_renesas_exit(struct ufs_hba * hba)508 static void ufs_renesas_exit(struct ufs_hba *hba)
509 {
510 struct ufs_renesas_priv *priv = ufshcd_get_variant(hba);
511
512 release_firmware(priv->fw);
513 }
514
ufs_renesas_set_dma_mask(struct ufs_hba * hba)515 static int ufs_renesas_set_dma_mask(struct ufs_hba *hba)
516 {
517 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
518 }
519
520 static const struct ufs_hba_variant_ops ufs_renesas_vops = {
521 .name = "renesas",
522 .init = ufs_renesas_init,
523 .exit = ufs_renesas_exit,
524 .set_dma_mask = ufs_renesas_set_dma_mask,
525 .setup_clocks = ufs_renesas_setup_clocks,
526 .hce_enable_notify = ufs_renesas_hce_enable_notify,
527 .dbg_register_dump = ufs_renesas_dbg_register_dump,
528 };
529
530 static const struct of_device_id __maybe_unused ufs_renesas_of_match[] = {
531 { .compatible = "renesas,r8a779f0-ufs" },
532 { /* sentinel */ }
533 };
534 MODULE_DEVICE_TABLE(of, ufs_renesas_of_match);
535
ufs_renesas_probe(struct platform_device * pdev)536 static int ufs_renesas_probe(struct platform_device *pdev)
537 {
538 return ufshcd_pltfrm_init(pdev, &ufs_renesas_vops);
539 }
540
ufs_renesas_remove(struct platform_device * pdev)541 static void ufs_renesas_remove(struct platform_device *pdev)
542 {
543 ufshcd_pltfrm_remove(pdev);
544 }
545
546 static struct platform_driver ufs_renesas_platform = {
547 .probe = ufs_renesas_probe,
548 .remove = ufs_renesas_remove,
549 .driver = {
550 .name = "ufshcd-renesas",
551 .of_match_table = of_match_ptr(ufs_renesas_of_match),
552 },
553 };
554 module_platform_driver(ufs_renesas_platform);
555
556 MODULE_AUTHOR("Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>");
557 MODULE_DESCRIPTION("Renesas UFS host controller driver");
558 MODULE_LICENSE("Dual MIT/GPL");
559