1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // Copyright (C) 2020 NVIDIA CORPORATION.
4
5 #include <linux/clk.h>
6 #include <linux/completion.h>
7 #include <linux/delay.h>
8 #include <linux/dmaengine.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/dmapool.h>
11 #include <linux/err.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/iopoll.h>
15 #include <linux/kernel.h>
16 #include <linux/kthread.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/of.h>
21 #include <linux/reset.h>
22 #include <linux/spi/spi.h>
23 #include <linux/acpi.h>
24 #include <linux/property.h>
25 #include <linux/sizes.h>
26
27 #define QSPI_COMMAND1 0x000
28 #define QSPI_BIT_LENGTH(x) (((x) & 0x1f) << 0)
29 #define QSPI_PACKED BIT(5)
30 #define QSPI_INTERFACE_WIDTH_MASK (0x03 << 7)
31 #define QSPI_INTERFACE_WIDTH(x) (((x) & 0x03) << 7)
32 #define QSPI_INTERFACE_WIDTH_SINGLE QSPI_INTERFACE_WIDTH(0)
33 #define QSPI_INTERFACE_WIDTH_DUAL QSPI_INTERFACE_WIDTH(1)
34 #define QSPI_INTERFACE_WIDTH_QUAD QSPI_INTERFACE_WIDTH(2)
35 #define QSPI_SDR_DDR_SEL BIT(9)
36 #define QSPI_TX_EN BIT(11)
37 #define QSPI_RX_EN BIT(12)
38 #define QSPI_CS_SW_VAL BIT(20)
39 #define QSPI_CS_SW_HW BIT(21)
40
41 #define QSPI_CS_POL_INACTIVE(n) (1 << (22 + (n)))
42 #define QSPI_CS_POL_INACTIVE_MASK (0xF << 22)
43 #define QSPI_CS_SEL_0 (0 << 26)
44 #define QSPI_CS_SEL_1 (1 << 26)
45 #define QSPI_CS_SEL_2 (2 << 26)
46 #define QSPI_CS_SEL_3 (3 << 26)
47 #define QSPI_CS_SEL_MASK (3 << 26)
48 #define QSPI_CS_SEL(x) (((x) & 0x3) << 26)
49
50 #define QSPI_CONTROL_MODE_0 (0 << 28)
51 #define QSPI_CONTROL_MODE_3 (3 << 28)
52 #define QSPI_CONTROL_MODE_MASK (3 << 28)
53 #define QSPI_M_S BIT(30)
54 #define QSPI_PIO BIT(31)
55
56 #define QSPI_COMMAND2 0x004
57 #define QSPI_TX_TAP_DELAY(x) (((x) & 0x3f) << 10)
58 #define QSPI_RX_TAP_DELAY(x) (((x) & 0xff) << 0)
59
60 #define QSPI_CS_TIMING1 0x008
61 #define QSPI_SETUP_HOLD(setup, hold) (((setup) << 4) | (hold))
62
63 #define QSPI_CS_TIMING2 0x00c
64 #define CYCLES_BETWEEN_PACKETS_0(x) (((x) & 0x1f) << 0)
65 #define CS_ACTIVE_BETWEEN_PACKETS_0 BIT(5)
66
67 #define QSPI_TRANS_STATUS 0x010
68 #define QSPI_BLK_CNT(val) (((val) >> 0) & 0xffff)
69 #define QSPI_RDY BIT(30)
70
71 #define QSPI_FIFO_STATUS 0x014
72 #define QSPI_RX_FIFO_EMPTY BIT(0)
73 #define QSPI_RX_FIFO_FULL BIT(1)
74 #define QSPI_TX_FIFO_EMPTY BIT(2)
75 #define QSPI_TX_FIFO_FULL BIT(3)
76 #define QSPI_RX_FIFO_UNF BIT(4)
77 #define QSPI_RX_FIFO_OVF BIT(5)
78 #define QSPI_TX_FIFO_UNF BIT(6)
79 #define QSPI_TX_FIFO_OVF BIT(7)
80 #define QSPI_ERR BIT(8)
81 #define QSPI_TX_FIFO_FLUSH BIT(14)
82 #define QSPI_RX_FIFO_FLUSH BIT(15)
83 #define QSPI_TX_FIFO_EMPTY_COUNT(val) (((val) >> 16) & 0x7f)
84 #define QSPI_RX_FIFO_FULL_COUNT(val) (((val) >> 23) & 0x7f)
85
86 #define QSPI_FIFO_ERROR (QSPI_RX_FIFO_UNF | \
87 QSPI_RX_FIFO_OVF | \
88 QSPI_TX_FIFO_UNF | \
89 QSPI_TX_FIFO_OVF)
90 #define QSPI_FIFO_EMPTY (QSPI_RX_FIFO_EMPTY | \
91 QSPI_TX_FIFO_EMPTY)
92
93 #define QSPI_TX_DATA 0x018
94 #define QSPI_RX_DATA 0x01c
95
96 #define QSPI_DMA_CTL 0x020
97 #define QSPI_TX_TRIG(n) (((n) & 0x3) << 15)
98 #define QSPI_TX_TRIG_1 QSPI_TX_TRIG(0)
99 #define QSPI_TX_TRIG_4 QSPI_TX_TRIG(1)
100 #define QSPI_TX_TRIG_8 QSPI_TX_TRIG(2)
101 #define QSPI_TX_TRIG_16 QSPI_TX_TRIG(3)
102
103 #define QSPI_RX_TRIG(n) (((n) & 0x3) << 19)
104 #define QSPI_RX_TRIG_1 QSPI_RX_TRIG(0)
105 #define QSPI_RX_TRIG_4 QSPI_RX_TRIG(1)
106 #define QSPI_RX_TRIG_8 QSPI_RX_TRIG(2)
107 #define QSPI_RX_TRIG_16 QSPI_RX_TRIG(3)
108
109 #define QSPI_DMA_EN BIT(31)
110
111 #define QSPI_DMA_BLK 0x024
112 #define QSPI_DMA_BLK_SET(x) (((x) & 0xffff) << 0)
113
114 #define QSPI_DMA_MEM_ADDRESS 0x028
115 #define QSPI_DMA_HI_ADDRESS 0x02c
116
117 #define QSPI_TX_FIFO 0x108
118 #define QSPI_RX_FIFO 0x188
119
120 #define QSPI_FIFO_DEPTH 64
121
122 #define QSPI_INTR_MASK 0x18c
123 #define QSPI_INTR_RX_FIFO_UNF_MASK BIT(25)
124 #define QSPI_INTR_RX_FIFO_OVF_MASK BIT(26)
125 #define QSPI_INTR_TX_FIFO_UNF_MASK BIT(27)
126 #define QSPI_INTR_TX_FIFO_OVF_MASK BIT(28)
127 #define QSPI_INTR_RDY_MASK BIT(29)
128 #define QSPI_INTR_RX_TX_FIFO_ERR (QSPI_INTR_RX_FIFO_UNF_MASK | \
129 QSPI_INTR_RX_FIFO_OVF_MASK | \
130 QSPI_INTR_TX_FIFO_UNF_MASK | \
131 QSPI_INTR_TX_FIFO_OVF_MASK)
132
133 #define QSPI_MISC_REG 0x194
134 #define QSPI_NUM_DUMMY_CYCLE(x) (((x) & 0xff) << 0)
135 #define QSPI_DUMMY_CYCLES_MAX 0xff
136
137 #define QSPI_CMB_SEQ_CMD 0x19c
138 #define QSPI_COMMAND_VALUE_SET(X) (((x) & 0xFF) << 0)
139
140 #define QSPI_CMB_SEQ_CMD_CFG 0x1a0
141 #define QSPI_COMMAND_X1_X2_X4(x) ((((x) >> 1) & 0x3) << 13)
142 #define QSPI_COMMAND_X1_X2_X4_MASK (0x03 << 13)
143 #define QSPI_COMMAND_SDR_DDR BIT(12)
144 #define QSPI_COMMAND_SIZE_SET(x) (((x) & 0xFF) << 0)
145
146 #define QSPI_GLOBAL_CONFIG 0X1a4
147 #define QSPI_CMB_SEQ_EN BIT(0)
148 #define QSPI_TPM_WAIT_POLL_EN BIT(1)
149
150 #define QSPI_CMB_SEQ_ADDR 0x1a8
151 #define QSPI_ADDRESS_VALUE_SET(X) (((x) & 0xFFFF) << 0)
152
153 #define QSPI_CMB_SEQ_ADDR_CFG 0x1ac
154 #define QSPI_ADDRESS_X1_X2_X4(x) ((((x) >> 1) & 0x3) << 13)
155 #define QSPI_ADDRESS_X1_X2_X4_MASK (0x03 << 13)
156 #define QSPI_ADDRESS_SDR_DDR BIT(12)
157 #define QSPI_ADDRESS_SIZE_SET(x) (((x) & 0xFF) << 0)
158
159 #define DATA_DIR_TX BIT(0)
160 #define DATA_DIR_RX BIT(1)
161
162 #define QSPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
163 #define DEFAULT_QSPI_DMA_BUF_LEN SZ_64K
164
165 enum tegra_qspi_transfer_type {
166 CMD_TRANSFER = 0,
167 ADDR_TRANSFER = 1,
168 DUMMY_TRANSFER = 2,
169 DATA_TRANSFER = 3
170 };
171
172 struct tegra_qspi_soc_data {
173 bool cmb_xfer_capable;
174 bool supports_tpm;
175 bool has_ext_dma;
176 unsigned int cs_count;
177 };
178
179 struct tegra_qspi_client_data {
180 int tx_clk_tap_delay;
181 int rx_clk_tap_delay;
182 };
183
184 struct tegra_qspi {
185 struct device *dev;
186 struct spi_controller *host;
187 /* lock to protect data accessed by irq */
188 spinlock_t lock;
189
190 struct clk *clk;
191 void __iomem *base;
192 phys_addr_t phys;
193 unsigned int irq;
194
195 u32 cur_speed;
196 unsigned int cur_pos;
197 unsigned int words_per_32bit;
198 unsigned int bytes_per_word;
199 unsigned int curr_dma_words;
200 unsigned int cur_direction;
201
202 unsigned int cur_rx_pos;
203 unsigned int cur_tx_pos;
204
205 unsigned int dma_buf_size;
206 unsigned int max_buf_size;
207 bool is_curr_dma_xfer;
208
209 struct completion rx_dma_complete;
210 struct completion tx_dma_complete;
211
212 u32 tx_status;
213 u32 rx_status;
214 u32 status_reg;
215 bool is_packed;
216 bool use_dma;
217
218 u32 command1_reg;
219 u32 dma_control_reg;
220 u32 def_command1_reg;
221 u32 def_command2_reg;
222 u32 spi_cs_timing1;
223 u32 spi_cs_timing2;
224 u8 dummy_cycles;
225
226 struct completion xfer_completion;
227 struct spi_transfer *curr_xfer;
228
229 struct dma_chan *rx_dma_chan;
230 u32 *rx_dma_buf;
231 dma_addr_t rx_dma_phys;
232 struct dma_async_tx_descriptor *rx_dma_desc;
233
234 struct dma_chan *tx_dma_chan;
235 u32 *tx_dma_buf;
236 dma_addr_t tx_dma_phys;
237 struct dma_async_tx_descriptor *tx_dma_desc;
238 const struct tegra_qspi_soc_data *soc_data;
239 };
240
tegra_qspi_readl(struct tegra_qspi * tqspi,unsigned long offset)241 static inline u32 tegra_qspi_readl(struct tegra_qspi *tqspi, unsigned long offset)
242 {
243 return readl(tqspi->base + offset);
244 }
245
tegra_qspi_writel(struct tegra_qspi * tqspi,u32 value,unsigned long offset)246 static inline void tegra_qspi_writel(struct tegra_qspi *tqspi, u32 value, unsigned long offset)
247 {
248 writel(value, tqspi->base + offset);
249
250 /* read back register to make sure that register writes completed */
251 if (offset != QSPI_TX_FIFO)
252 readl(tqspi->base + QSPI_COMMAND1);
253 }
254
tegra_qspi_mask_clear_irq(struct tegra_qspi * tqspi)255 static void tegra_qspi_mask_clear_irq(struct tegra_qspi *tqspi)
256 {
257 u32 value;
258
259 /* write 1 to clear status register */
260 value = tegra_qspi_readl(tqspi, QSPI_TRANS_STATUS);
261 tegra_qspi_writel(tqspi, value, QSPI_TRANS_STATUS);
262
263 value = tegra_qspi_readl(tqspi, QSPI_INTR_MASK);
264 if (!(value & QSPI_INTR_RDY_MASK)) {
265 value |= (QSPI_INTR_RDY_MASK | QSPI_INTR_RX_TX_FIFO_ERR);
266 tegra_qspi_writel(tqspi, value, QSPI_INTR_MASK);
267 }
268
269 /* clear fifo status error if any */
270 value = tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS);
271 if (value & QSPI_ERR)
272 tegra_qspi_writel(tqspi, QSPI_ERR | QSPI_FIFO_ERROR, QSPI_FIFO_STATUS);
273 }
274
275 static unsigned int
tegra_qspi_calculate_curr_xfer_param(struct tegra_qspi * tqspi,struct spi_transfer * t)276 tegra_qspi_calculate_curr_xfer_param(struct tegra_qspi *tqspi, struct spi_transfer *t)
277 {
278 unsigned int max_word, max_len, total_fifo_words;
279 unsigned int remain_len = t->len - tqspi->cur_pos;
280 unsigned int bits_per_word = t->bits_per_word;
281
282 tqspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8);
283
284 /*
285 * Tegra QSPI controller supports packed or unpacked mode transfers.
286 * Packed mode is used for data transfers using 8, 16, or 32 bits per
287 * word with a minimum transfer of 1 word and for all other transfers
288 * unpacked mode will be used.
289 */
290
291 if ((bits_per_word == 8 || bits_per_word == 16 ||
292 bits_per_word == 32) && t->len > 3) {
293 tqspi->is_packed = true;
294 tqspi->words_per_32bit = 32 / bits_per_word;
295 } else {
296 tqspi->is_packed = false;
297 tqspi->words_per_32bit = 1;
298 }
299
300 if (tqspi->is_packed) {
301 max_len = min(remain_len, tqspi->max_buf_size);
302 tqspi->curr_dma_words = max_len / tqspi->bytes_per_word;
303 total_fifo_words = (max_len + 3) / 4;
304 } else {
305 max_word = (remain_len - 1) / tqspi->bytes_per_word + 1;
306 max_word = min(max_word, tqspi->max_buf_size / 4);
307 tqspi->curr_dma_words = max_word;
308 total_fifo_words = max_word;
309 }
310
311 return total_fifo_words;
312 }
313
314 static unsigned int
tegra_qspi_fill_tx_fifo_from_client_txbuf(struct tegra_qspi * tqspi,struct spi_transfer * t)315 tegra_qspi_fill_tx_fifo_from_client_txbuf(struct tegra_qspi *tqspi, struct spi_transfer *t)
316 {
317 unsigned int written_words, fifo_words_left, count;
318 unsigned int len, tx_empty_count, max_n_32bit, i;
319 u8 *tx_buf = (u8 *)t->tx_buf + tqspi->cur_tx_pos;
320 u32 fifo_status;
321
322 fifo_status = tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS);
323 tx_empty_count = QSPI_TX_FIFO_EMPTY_COUNT(fifo_status);
324
325 if (tqspi->is_packed) {
326 fifo_words_left = tx_empty_count * tqspi->words_per_32bit;
327 written_words = min(fifo_words_left, tqspi->curr_dma_words);
328 len = written_words * tqspi->bytes_per_word;
329 max_n_32bit = DIV_ROUND_UP(len, 4);
330 for (count = 0; count < max_n_32bit; count++) {
331 u32 x = 0;
332
333 for (i = 0; (i < 4) && len; i++, len--)
334 x |= (u32)(*tx_buf++) << (i * 8);
335 tegra_qspi_writel(tqspi, x, QSPI_TX_FIFO);
336 }
337
338 tqspi->cur_tx_pos += written_words * tqspi->bytes_per_word;
339 } else {
340 unsigned int write_bytes;
341 u8 bytes_per_word = tqspi->bytes_per_word;
342
343 max_n_32bit = min(tqspi->curr_dma_words, tx_empty_count);
344 written_words = max_n_32bit;
345 len = written_words * tqspi->bytes_per_word;
346 if (len > t->len - tqspi->cur_pos)
347 len = t->len - tqspi->cur_pos;
348 write_bytes = len;
349 for (count = 0; count < max_n_32bit; count++) {
350 u32 x = 0;
351
352 for (i = 0; len && (i < min(4, bytes_per_word)); i++, len--)
353 x |= (u32)(*tx_buf++) << (i * 8);
354 tegra_qspi_writel(tqspi, x, QSPI_TX_FIFO);
355 }
356
357 tqspi->cur_tx_pos += write_bytes;
358 }
359
360 return written_words;
361 }
362
363 static unsigned int
tegra_qspi_read_rx_fifo_to_client_rxbuf(struct tegra_qspi * tqspi,struct spi_transfer * t)364 tegra_qspi_read_rx_fifo_to_client_rxbuf(struct tegra_qspi *tqspi, struct spi_transfer *t)
365 {
366 u8 *rx_buf = (u8 *)t->rx_buf + tqspi->cur_rx_pos;
367 unsigned int len, rx_full_count, count, i;
368 unsigned int read_words = 0;
369 u32 fifo_status, x;
370
371 fifo_status = tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS);
372 rx_full_count = QSPI_RX_FIFO_FULL_COUNT(fifo_status);
373 if (tqspi->is_packed) {
374 len = tqspi->curr_dma_words * tqspi->bytes_per_word;
375 for (count = 0; count < rx_full_count; count++) {
376 x = tegra_qspi_readl(tqspi, QSPI_RX_FIFO);
377
378 for (i = 0; len && (i < 4); i++, len--)
379 *rx_buf++ = (x >> i * 8) & 0xff;
380 }
381
382 read_words += tqspi->curr_dma_words;
383 tqspi->cur_rx_pos += tqspi->curr_dma_words * tqspi->bytes_per_word;
384 } else {
385 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
386 u8 bytes_per_word = tqspi->bytes_per_word;
387 unsigned int read_bytes;
388
389 len = rx_full_count * bytes_per_word;
390 if (len > t->len - tqspi->cur_pos)
391 len = t->len - tqspi->cur_pos;
392 read_bytes = len;
393 for (count = 0; count < rx_full_count; count++) {
394 x = tegra_qspi_readl(tqspi, QSPI_RX_FIFO) & rx_mask;
395
396 for (i = 0; len && (i < bytes_per_word); i++, len--)
397 *rx_buf++ = (x >> (i * 8)) & 0xff;
398 }
399
400 read_words += rx_full_count;
401 tqspi->cur_rx_pos += read_bytes;
402 }
403
404 return read_words;
405 }
406
407 static void
tegra_qspi_copy_client_txbuf_to_qspi_txbuf(struct tegra_qspi * tqspi,struct spi_transfer * t)408 tegra_qspi_copy_client_txbuf_to_qspi_txbuf(struct tegra_qspi *tqspi, struct spi_transfer *t)
409 {
410 /*
411 * In packed mode, each word in FIFO may contain multiple packets
412 * based on bits per word. So all bytes in each FIFO word are valid.
413 *
414 * In unpacked mode, each word in FIFO contains single packet and
415 * based on bits per word any remaining bits in FIFO word will be
416 * ignored by the hardware and are invalid bits.
417 */
418 if (tqspi->is_packed) {
419 tqspi->cur_tx_pos += tqspi->curr_dma_words * tqspi->bytes_per_word;
420 } else {
421 u8 *tx_buf = (u8 *)t->tx_buf + tqspi->cur_tx_pos;
422 unsigned int i, count, consume, write_bytes;
423
424 /*
425 * Fill tx_dma_buf to contain single packet in each word based
426 * on bits per word from SPI core tx_buf.
427 */
428 consume = tqspi->curr_dma_words * tqspi->bytes_per_word;
429 if (consume > t->len - tqspi->cur_pos)
430 consume = t->len - tqspi->cur_pos;
431 write_bytes = consume;
432 for (count = 0; count < tqspi->curr_dma_words; count++) {
433 u32 x = 0;
434
435 for (i = 0; consume && (i < tqspi->bytes_per_word); i++, consume--)
436 x |= (u32)(*tx_buf++) << (i * 8);
437 tqspi->tx_dma_buf[count] = x;
438 }
439
440 tqspi->cur_tx_pos += write_bytes;
441 }
442 }
443
444 static void
tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf(struct tegra_qspi * tqspi,struct spi_transfer * t)445 tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf(struct tegra_qspi *tqspi, struct spi_transfer *t)
446 {
447 if (tqspi->is_packed) {
448 tqspi->cur_rx_pos += tqspi->curr_dma_words * tqspi->bytes_per_word;
449 } else {
450 unsigned char *rx_buf = t->rx_buf + tqspi->cur_rx_pos;
451 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
452 unsigned int i, count, consume, read_bytes;
453
454 /*
455 * Each FIFO word contains single data packet.
456 * Skip invalid bits in each FIFO word based on bits per word
457 * and align bytes while filling in SPI core rx_buf.
458 */
459 consume = tqspi->curr_dma_words * tqspi->bytes_per_word;
460 if (consume > t->len - tqspi->cur_pos)
461 consume = t->len - tqspi->cur_pos;
462 read_bytes = consume;
463 for (count = 0; count < tqspi->curr_dma_words; count++) {
464 u32 x = tqspi->rx_dma_buf[count] & rx_mask;
465
466 for (i = 0; consume && (i < tqspi->bytes_per_word); i++, consume--)
467 *rx_buf++ = (x >> (i * 8)) & 0xff;
468 }
469
470 tqspi->cur_rx_pos += read_bytes;
471 }
472 }
473
tegra_qspi_dma_complete(void * args)474 static void tegra_qspi_dma_complete(void *args)
475 {
476 struct completion *dma_complete = args;
477
478 complete(dma_complete);
479 }
480
tegra_qspi_start_tx_dma(struct tegra_qspi * tqspi,struct spi_transfer * t,int len)481 static int tegra_qspi_start_tx_dma(struct tegra_qspi *tqspi, struct spi_transfer *t, int len)
482 {
483 dma_addr_t tx_dma_phys;
484
485 reinit_completion(&tqspi->tx_dma_complete);
486
487 if (tqspi->is_packed)
488 tx_dma_phys = t->tx_dma;
489 else
490 tx_dma_phys = tqspi->tx_dma_phys;
491
492 tqspi->tx_dma_desc = dmaengine_prep_slave_single(tqspi->tx_dma_chan, tx_dma_phys,
493 len, DMA_MEM_TO_DEV,
494 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
495
496 if (!tqspi->tx_dma_desc) {
497 dev_err(tqspi->dev, "Unable to get TX descriptor\n");
498 return -EIO;
499 }
500
501 tqspi->tx_dma_desc->callback = tegra_qspi_dma_complete;
502 tqspi->tx_dma_desc->callback_param = &tqspi->tx_dma_complete;
503 dmaengine_submit(tqspi->tx_dma_desc);
504 dma_async_issue_pending(tqspi->tx_dma_chan);
505
506 return 0;
507 }
508
tegra_qspi_start_rx_dma(struct tegra_qspi * tqspi,struct spi_transfer * t,int len)509 static int tegra_qspi_start_rx_dma(struct tegra_qspi *tqspi, struct spi_transfer *t, int len)
510 {
511 dma_addr_t rx_dma_phys;
512
513 reinit_completion(&tqspi->rx_dma_complete);
514
515 if (tqspi->is_packed)
516 rx_dma_phys = t->rx_dma;
517 else
518 rx_dma_phys = tqspi->rx_dma_phys;
519
520 tqspi->rx_dma_desc = dmaengine_prep_slave_single(tqspi->rx_dma_chan, rx_dma_phys,
521 len, DMA_DEV_TO_MEM,
522 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
523
524 if (!tqspi->rx_dma_desc) {
525 dev_err(tqspi->dev, "Unable to get RX descriptor\n");
526 return -EIO;
527 }
528
529 tqspi->rx_dma_desc->callback = tegra_qspi_dma_complete;
530 tqspi->rx_dma_desc->callback_param = &tqspi->rx_dma_complete;
531 dmaengine_submit(tqspi->rx_dma_desc);
532 dma_async_issue_pending(tqspi->rx_dma_chan);
533
534 return 0;
535 }
536
tegra_qspi_flush_fifos(struct tegra_qspi * tqspi,bool atomic)537 static int tegra_qspi_flush_fifos(struct tegra_qspi *tqspi, bool atomic)
538 {
539 void __iomem *addr = tqspi->base + QSPI_FIFO_STATUS;
540 u32 val;
541
542 val = tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS);
543 if ((val & QSPI_FIFO_EMPTY) == QSPI_FIFO_EMPTY)
544 return 0;
545
546 val |= QSPI_RX_FIFO_FLUSH | QSPI_TX_FIFO_FLUSH;
547 tegra_qspi_writel(tqspi, val, QSPI_FIFO_STATUS);
548
549 if (!atomic)
550 return readl_relaxed_poll_timeout(addr, val,
551 (val & QSPI_FIFO_EMPTY) == QSPI_FIFO_EMPTY,
552 1000, 1000000);
553
554 return readl_relaxed_poll_timeout_atomic(addr, val,
555 (val & QSPI_FIFO_EMPTY) == QSPI_FIFO_EMPTY,
556 1000, 1000000);
557 }
558
tegra_qspi_unmask_irq(struct tegra_qspi * tqspi)559 static void tegra_qspi_unmask_irq(struct tegra_qspi *tqspi)
560 {
561 u32 intr_mask;
562
563 intr_mask = tegra_qspi_readl(tqspi, QSPI_INTR_MASK);
564 intr_mask &= ~(QSPI_INTR_RDY_MASK | QSPI_INTR_RX_TX_FIFO_ERR);
565 tegra_qspi_writel(tqspi, intr_mask, QSPI_INTR_MASK);
566 }
567
tegra_qspi_dma_map_xfer(struct tegra_qspi * tqspi,struct spi_transfer * t)568 static int tegra_qspi_dma_map_xfer(struct tegra_qspi *tqspi, struct spi_transfer *t)
569 {
570 u8 *tx_buf = (u8 *)t->tx_buf + tqspi->cur_tx_pos;
571 u8 *rx_buf = (u8 *)t->rx_buf + tqspi->cur_rx_pos;
572 unsigned int len;
573
574 len = DIV_ROUND_UP(tqspi->curr_dma_words * tqspi->bytes_per_word, 4) * 4;
575
576 if (t->tx_buf) {
577 t->tx_dma = dma_map_single(tqspi->dev, (void *)tx_buf, len, DMA_TO_DEVICE);
578 if (dma_mapping_error(tqspi->dev, t->tx_dma))
579 return -ENOMEM;
580 }
581
582 if (t->rx_buf) {
583 t->rx_dma = dma_map_single(tqspi->dev, (void *)rx_buf, len, DMA_FROM_DEVICE);
584 if (dma_mapping_error(tqspi->dev, t->rx_dma)) {
585 dma_unmap_single(tqspi->dev, t->tx_dma, len, DMA_TO_DEVICE);
586 return -ENOMEM;
587 }
588 }
589
590 return 0;
591 }
592
tegra_qspi_dma_unmap_xfer(struct tegra_qspi * tqspi,struct spi_transfer * t)593 static void tegra_qspi_dma_unmap_xfer(struct tegra_qspi *tqspi, struct spi_transfer *t)
594 {
595 unsigned int len;
596
597 len = DIV_ROUND_UP(tqspi->curr_dma_words * tqspi->bytes_per_word, 4) * 4;
598
599 if (t->tx_buf)
600 dma_unmap_single(tqspi->dev, t->tx_dma, len, DMA_TO_DEVICE);
601 if (t->rx_buf)
602 dma_unmap_single(tqspi->dev, t->rx_dma, len, DMA_FROM_DEVICE);
603 }
604
tegra_qspi_start_dma_based_transfer(struct tegra_qspi * tqspi,struct spi_transfer * t)605 static int tegra_qspi_start_dma_based_transfer(struct tegra_qspi *tqspi, struct spi_transfer *t)
606 {
607 struct dma_slave_config dma_sconfig = { 0 };
608 dma_addr_t rx_dma_phys, tx_dma_phys;
609 unsigned int len;
610 u8 dma_burst;
611 int ret = 0;
612 u32 val;
613
614 if (tqspi->is_packed) {
615 ret = tegra_qspi_dma_map_xfer(tqspi, t);
616 if (ret < 0)
617 return ret;
618 }
619
620 val = QSPI_DMA_BLK_SET(tqspi->curr_dma_words - 1);
621 tegra_qspi_writel(tqspi, val, QSPI_DMA_BLK);
622
623 tegra_qspi_unmask_irq(tqspi);
624
625 if (tqspi->is_packed)
626 len = DIV_ROUND_UP(tqspi->curr_dma_words * tqspi->bytes_per_word, 4) * 4;
627 else
628 len = tqspi->curr_dma_words * 4;
629
630 /* set attention level based on length of transfer */
631 if (tqspi->soc_data->has_ext_dma) {
632 val = 0;
633 if (len & 0xf) {
634 val |= QSPI_TX_TRIG_1 | QSPI_RX_TRIG_1;
635 dma_burst = 1;
636 } else if (((len) >> 4) & 0x1) {
637 val |= QSPI_TX_TRIG_4 | QSPI_RX_TRIG_4;
638 dma_burst = 4;
639 } else {
640 val |= QSPI_TX_TRIG_8 | QSPI_RX_TRIG_8;
641 dma_burst = 8;
642 }
643
644 tegra_qspi_writel(tqspi, val, QSPI_DMA_CTL);
645 }
646
647 tqspi->dma_control_reg = val;
648
649 dma_sconfig.device_fc = true;
650
651 if (tqspi->cur_direction & DATA_DIR_TX) {
652 if (tqspi->tx_dma_chan) {
653 dma_sconfig.dst_addr = tqspi->phys + QSPI_TX_FIFO;
654 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
655 dma_sconfig.dst_maxburst = dma_burst;
656 ret = dmaengine_slave_config(tqspi->tx_dma_chan, &dma_sconfig);
657 if (ret < 0) {
658 dev_err(tqspi->dev, "failed DMA slave config: %d\n", ret);
659 return ret;
660 }
661
662 tegra_qspi_copy_client_txbuf_to_qspi_txbuf(tqspi, t);
663 ret = tegra_qspi_start_tx_dma(tqspi, t, len);
664 if (ret < 0) {
665 dev_err(tqspi->dev, "failed to starting TX DMA: %d\n", ret);
666 return ret;
667 }
668 } else {
669 if (tqspi->is_packed)
670 tx_dma_phys = t->tx_dma;
671 else
672 tx_dma_phys = tqspi->tx_dma_phys;
673 tegra_qspi_copy_client_txbuf_to_qspi_txbuf(tqspi, t);
674 tegra_qspi_writel(tqspi, lower_32_bits(tx_dma_phys),
675 QSPI_DMA_MEM_ADDRESS);
676 tegra_qspi_writel(tqspi, (upper_32_bits(tx_dma_phys) & 0xff),
677 QSPI_DMA_HI_ADDRESS);
678 }
679 }
680
681 if (tqspi->cur_direction & DATA_DIR_RX) {
682 if (tqspi->rx_dma_chan) {
683 dma_sconfig.src_addr = tqspi->phys + QSPI_RX_FIFO;
684 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
685 dma_sconfig.src_maxburst = dma_burst;
686 ret = dmaengine_slave_config(tqspi->rx_dma_chan, &dma_sconfig);
687 if (ret < 0) {
688 dev_err(tqspi->dev, "failed DMA slave config: %d\n", ret);
689 return ret;
690 }
691
692 ret = tegra_qspi_start_rx_dma(tqspi, t, len);
693 if (ret < 0) {
694 dev_err(tqspi->dev, "failed to start RX DMA: %d\n", ret);
695 if (tqspi->cur_direction & DATA_DIR_TX)
696 dmaengine_terminate_all(tqspi->tx_dma_chan);
697 return ret;
698 }
699 } else {
700 if (tqspi->is_packed)
701 rx_dma_phys = t->rx_dma;
702 else
703 rx_dma_phys = tqspi->rx_dma_phys;
704
705 tegra_qspi_writel(tqspi, lower_32_bits(rx_dma_phys),
706 QSPI_DMA_MEM_ADDRESS);
707 tegra_qspi_writel(tqspi, (upper_32_bits(rx_dma_phys) & 0xff),
708 QSPI_DMA_HI_ADDRESS);
709 }
710 }
711
712 tegra_qspi_writel(tqspi, tqspi->command1_reg, QSPI_COMMAND1);
713
714 tqspi->is_curr_dma_xfer = true;
715 tqspi->dma_control_reg = val;
716 val |= QSPI_DMA_EN;
717 tegra_qspi_writel(tqspi, val, QSPI_DMA_CTL);
718
719 return ret;
720 }
721
tegra_qspi_start_cpu_based_transfer(struct tegra_qspi * qspi,struct spi_transfer * t)722 static int tegra_qspi_start_cpu_based_transfer(struct tegra_qspi *qspi, struct spi_transfer *t)
723 {
724 u32 val;
725 unsigned int cur_words;
726
727 if (qspi->cur_direction & DATA_DIR_TX)
728 cur_words = tegra_qspi_fill_tx_fifo_from_client_txbuf(qspi, t);
729 else
730 cur_words = qspi->curr_dma_words;
731
732 val = QSPI_DMA_BLK_SET(cur_words - 1);
733 tegra_qspi_writel(qspi, val, QSPI_DMA_BLK);
734
735 tegra_qspi_unmask_irq(qspi);
736
737 qspi->is_curr_dma_xfer = false;
738 val = qspi->command1_reg;
739 val |= QSPI_PIO;
740 tegra_qspi_writel(qspi, val, QSPI_COMMAND1);
741
742 return 0;
743 }
744
tegra_qspi_deinit_dma(struct tegra_qspi * tqspi)745 static void tegra_qspi_deinit_dma(struct tegra_qspi *tqspi)
746 {
747 if (tqspi->tx_dma_buf) {
748 dma_free_coherent(tqspi->dev, tqspi->dma_buf_size,
749 tqspi->tx_dma_buf, tqspi->tx_dma_phys);
750 tqspi->tx_dma_buf = NULL;
751 }
752
753 if (tqspi->tx_dma_chan) {
754 dma_release_channel(tqspi->tx_dma_chan);
755 tqspi->tx_dma_chan = NULL;
756 }
757
758 if (tqspi->rx_dma_buf) {
759 dma_free_coherent(tqspi->dev, tqspi->dma_buf_size,
760 tqspi->rx_dma_buf, tqspi->rx_dma_phys);
761 tqspi->rx_dma_buf = NULL;
762 }
763
764 if (tqspi->rx_dma_chan) {
765 dma_release_channel(tqspi->rx_dma_chan);
766 tqspi->rx_dma_chan = NULL;
767 }
768 }
769
tegra_qspi_init_dma(struct tegra_qspi * tqspi)770 static int tegra_qspi_init_dma(struct tegra_qspi *tqspi)
771 {
772 struct dma_chan *dma_chan;
773 dma_addr_t dma_phys;
774 u32 *dma_buf;
775 int err;
776
777 if (tqspi->soc_data->has_ext_dma) {
778 dma_chan = dma_request_chan(tqspi->dev, "rx");
779 if (IS_ERR(dma_chan)) {
780 err = PTR_ERR(dma_chan);
781 goto err_out;
782 }
783
784 tqspi->rx_dma_chan = dma_chan;
785
786 dma_chan = dma_request_chan(tqspi->dev, "tx");
787 if (IS_ERR(dma_chan)) {
788 err = PTR_ERR(dma_chan);
789 goto err_out;
790 }
791
792 tqspi->tx_dma_chan = dma_chan;
793 } else {
794 if (!device_iommu_mapped(tqspi->dev)) {
795 dev_warn(tqspi->dev,
796 "IOMMU not enabled in device-tree, falling back to PIO mode\n");
797 return 0;
798 }
799 }
800
801 dma_buf = dma_alloc_coherent(tqspi->dev, tqspi->dma_buf_size, &dma_phys, GFP_KERNEL);
802 if (!dma_buf) {
803 err = -ENOMEM;
804 goto err_out;
805 }
806
807 tqspi->rx_dma_buf = dma_buf;
808 tqspi->rx_dma_phys = dma_phys;
809
810 dma_buf = dma_alloc_coherent(tqspi->dev, tqspi->dma_buf_size, &dma_phys, GFP_KERNEL);
811 if (!dma_buf) {
812 err = -ENOMEM;
813 goto err_out;
814 }
815
816 tqspi->tx_dma_buf = dma_buf;
817 tqspi->tx_dma_phys = dma_phys;
818 tqspi->use_dma = true;
819
820 return 0;
821
822 err_out:
823 tegra_qspi_deinit_dma(tqspi);
824
825 if (err != -EPROBE_DEFER) {
826 dev_err(tqspi->dev, "cannot use DMA: %d\n", err);
827 dev_err(tqspi->dev, "falling back to PIO\n");
828 return 0;
829 }
830
831 return err;
832 }
833
tegra_qspi_setup_transfer_one(struct spi_device * spi,struct spi_transfer * t,bool is_first_of_msg)834 static u32 tegra_qspi_setup_transfer_one(struct spi_device *spi, struct spi_transfer *t,
835 bool is_first_of_msg)
836 {
837 struct tegra_qspi *tqspi = spi_controller_get_devdata(spi->controller);
838 struct tegra_qspi_client_data *cdata = spi->controller_data;
839 u32 command1, command2, speed = t->speed_hz;
840 u8 bits_per_word = t->bits_per_word;
841 u32 tx_tap = 0, rx_tap = 0;
842 int req_mode;
843
844 if (!has_acpi_companion(tqspi->dev) && speed != tqspi->cur_speed) {
845 clk_set_rate(tqspi->clk, speed);
846 tqspi->cur_speed = speed;
847 }
848
849 tqspi->cur_pos = 0;
850 tqspi->cur_rx_pos = 0;
851 tqspi->cur_tx_pos = 0;
852 tqspi->curr_xfer = t;
853
854 if (is_first_of_msg) {
855 tegra_qspi_mask_clear_irq(tqspi);
856
857 command1 = tqspi->def_command1_reg;
858 command1 |= QSPI_CS_SEL(spi_get_chipselect(spi, 0));
859 command1 |= QSPI_BIT_LENGTH(bits_per_word - 1);
860
861 command1 &= ~QSPI_CONTROL_MODE_MASK;
862 req_mode = spi->mode & 0x3;
863 if (req_mode == SPI_MODE_3)
864 command1 |= QSPI_CONTROL_MODE_3;
865 else
866 command1 |= QSPI_CONTROL_MODE_0;
867
868 if (spi->mode & SPI_CS_HIGH)
869 command1 |= QSPI_CS_SW_VAL;
870 else
871 command1 &= ~QSPI_CS_SW_VAL;
872 tegra_qspi_writel(tqspi, command1, QSPI_COMMAND1);
873
874 if (cdata && cdata->tx_clk_tap_delay)
875 tx_tap = cdata->tx_clk_tap_delay;
876
877 if (cdata && cdata->rx_clk_tap_delay)
878 rx_tap = cdata->rx_clk_tap_delay;
879
880 command2 = QSPI_TX_TAP_DELAY(tx_tap) | QSPI_RX_TAP_DELAY(rx_tap);
881 if (command2 != tqspi->def_command2_reg)
882 tegra_qspi_writel(tqspi, command2, QSPI_COMMAND2);
883
884 } else {
885 command1 = tqspi->command1_reg;
886 command1 &= ~QSPI_BIT_LENGTH(~0);
887 command1 |= QSPI_BIT_LENGTH(bits_per_word - 1);
888 }
889
890 command1 &= ~QSPI_SDR_DDR_SEL;
891
892 return command1;
893 }
894
tegra_qspi_start_transfer_one(struct spi_device * spi,struct spi_transfer * t,u32 command1)895 static int tegra_qspi_start_transfer_one(struct spi_device *spi,
896 struct spi_transfer *t, u32 command1)
897 {
898 struct tegra_qspi *tqspi = spi_controller_get_devdata(spi->controller);
899 unsigned int total_fifo_words;
900 u8 bus_width = 0;
901 int ret;
902
903 total_fifo_words = tegra_qspi_calculate_curr_xfer_param(tqspi, t);
904
905 command1 &= ~QSPI_PACKED;
906 if (tqspi->is_packed)
907 command1 |= QSPI_PACKED;
908 tegra_qspi_writel(tqspi, command1, QSPI_COMMAND1);
909
910 tqspi->cur_direction = 0;
911
912 command1 &= ~(QSPI_TX_EN | QSPI_RX_EN);
913 if (t->rx_buf) {
914 command1 |= QSPI_RX_EN;
915 tqspi->cur_direction |= DATA_DIR_RX;
916 bus_width = t->rx_nbits;
917 }
918
919 if (t->tx_buf) {
920 command1 |= QSPI_TX_EN;
921 tqspi->cur_direction |= DATA_DIR_TX;
922 bus_width = t->tx_nbits;
923 }
924
925 command1 &= ~QSPI_INTERFACE_WIDTH_MASK;
926
927 if (bus_width == SPI_NBITS_QUAD)
928 command1 |= QSPI_INTERFACE_WIDTH_QUAD;
929 else if (bus_width == SPI_NBITS_DUAL)
930 command1 |= QSPI_INTERFACE_WIDTH_DUAL;
931 else
932 command1 |= QSPI_INTERFACE_WIDTH_SINGLE;
933
934 tqspi->command1_reg = command1;
935
936 tegra_qspi_writel(tqspi, QSPI_NUM_DUMMY_CYCLE(tqspi->dummy_cycles), QSPI_MISC_REG);
937
938 ret = tegra_qspi_flush_fifos(tqspi, false);
939 if (ret < 0)
940 return ret;
941
942 if (tqspi->use_dma && total_fifo_words > QSPI_FIFO_DEPTH)
943 ret = tegra_qspi_start_dma_based_transfer(tqspi, t);
944 else
945 ret = tegra_qspi_start_cpu_based_transfer(tqspi, t);
946
947 return ret;
948 }
949
tegra_qspi_parse_cdata_dt(struct spi_device * spi)950 static struct tegra_qspi_client_data *tegra_qspi_parse_cdata_dt(struct spi_device *spi)
951 {
952 struct tegra_qspi_client_data *cdata;
953 struct tegra_qspi *tqspi = spi_controller_get_devdata(spi->controller);
954
955 cdata = devm_kzalloc(tqspi->dev, sizeof(*cdata), GFP_KERNEL);
956 if (!cdata)
957 return NULL;
958
959 device_property_read_u32(&spi->dev, "nvidia,tx-clk-tap-delay",
960 &cdata->tx_clk_tap_delay);
961 device_property_read_u32(&spi->dev, "nvidia,rx-clk-tap-delay",
962 &cdata->rx_clk_tap_delay);
963
964 return cdata;
965 }
966
tegra_qspi_setup(struct spi_device * spi)967 static int tegra_qspi_setup(struct spi_device *spi)
968 {
969 struct tegra_qspi *tqspi = spi_controller_get_devdata(spi->controller);
970 struct tegra_qspi_client_data *cdata = spi->controller_data;
971 unsigned long flags;
972 u32 val;
973 int ret;
974
975 ret = pm_runtime_resume_and_get(tqspi->dev);
976 if (ret < 0) {
977 dev_err(tqspi->dev, "failed to get runtime PM: %d\n", ret);
978 return ret;
979 }
980
981 if (!cdata) {
982 cdata = tegra_qspi_parse_cdata_dt(spi);
983 spi->controller_data = cdata;
984 }
985 spin_lock_irqsave(&tqspi->lock, flags);
986
987 /* keep default cs state to inactive */
988 val = tqspi->def_command1_reg;
989 val |= QSPI_CS_SEL(spi_get_chipselect(spi, 0));
990 if (spi->mode & SPI_CS_HIGH)
991 val &= ~QSPI_CS_POL_INACTIVE(spi_get_chipselect(spi, 0));
992 else
993 val |= QSPI_CS_POL_INACTIVE(spi_get_chipselect(spi, 0));
994
995 tqspi->def_command1_reg = val;
996 tegra_qspi_writel(tqspi, tqspi->def_command1_reg, QSPI_COMMAND1);
997
998 spin_unlock_irqrestore(&tqspi->lock, flags);
999
1000 pm_runtime_put(tqspi->dev);
1001
1002 return 0;
1003 }
1004
tegra_qspi_dump_regs(struct tegra_qspi * tqspi)1005 static void tegra_qspi_dump_regs(struct tegra_qspi *tqspi)
1006 {
1007 dev_dbg(tqspi->dev, "============ QSPI REGISTER DUMP ============\n");
1008 dev_dbg(tqspi->dev, "Command1: 0x%08x | Command2: 0x%08x\n",
1009 tegra_qspi_readl(tqspi, QSPI_COMMAND1),
1010 tegra_qspi_readl(tqspi, QSPI_COMMAND2));
1011 dev_dbg(tqspi->dev, "DMA_CTL: 0x%08x | DMA_BLK: 0x%08x\n",
1012 tegra_qspi_readl(tqspi, QSPI_DMA_CTL),
1013 tegra_qspi_readl(tqspi, QSPI_DMA_BLK));
1014 dev_dbg(tqspi->dev, "INTR_MASK: 0x%08x | MISC: 0x%08x\n",
1015 tegra_qspi_readl(tqspi, QSPI_INTR_MASK),
1016 tegra_qspi_readl(tqspi, QSPI_MISC_REG));
1017 dev_dbg(tqspi->dev, "TRANS_STAT: 0x%08x | FIFO_STATUS: 0x%08x\n",
1018 tegra_qspi_readl(tqspi, QSPI_TRANS_STATUS),
1019 tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS));
1020 }
1021
tegra_qspi_handle_error(struct tegra_qspi * tqspi)1022 static void tegra_qspi_handle_error(struct tegra_qspi *tqspi)
1023 {
1024 dev_err(tqspi->dev, "error in transfer, fifo status 0x%08x\n", tqspi->status_reg);
1025 tegra_qspi_dump_regs(tqspi);
1026 tegra_qspi_flush_fifos(tqspi, true);
1027 if (device_reset(tqspi->dev) < 0)
1028 dev_warn_once(tqspi->dev, "device reset failed\n");
1029 }
1030
tegra_qspi_transfer_end(struct spi_device * spi)1031 static void tegra_qspi_transfer_end(struct spi_device *spi)
1032 {
1033 struct tegra_qspi *tqspi = spi_controller_get_devdata(spi->controller);
1034 int cs_val = (spi->mode & SPI_CS_HIGH) ? 0 : 1;
1035
1036 if (cs_val)
1037 tqspi->command1_reg |= QSPI_CS_SW_VAL;
1038 else
1039 tqspi->command1_reg &= ~QSPI_CS_SW_VAL;
1040 tegra_qspi_writel(tqspi, tqspi->command1_reg, QSPI_COMMAND1);
1041 tegra_qspi_writel(tqspi, tqspi->def_command1_reg, QSPI_COMMAND1);
1042 }
1043
tegra_qspi_cmd_config(bool is_ddr,u8 bus_width,u8 len)1044 static u32 tegra_qspi_cmd_config(bool is_ddr, u8 bus_width, u8 len)
1045 {
1046 u32 cmd_config = 0;
1047
1048 /* Extract Command configuration and value */
1049 if (is_ddr)
1050 cmd_config |= QSPI_COMMAND_SDR_DDR;
1051 else
1052 cmd_config &= ~QSPI_COMMAND_SDR_DDR;
1053
1054 cmd_config |= QSPI_COMMAND_X1_X2_X4(bus_width);
1055 cmd_config |= QSPI_COMMAND_SIZE_SET((len * 8) - 1);
1056
1057 return cmd_config;
1058 }
1059
tegra_qspi_addr_config(bool is_ddr,u8 bus_width,u8 len)1060 static u32 tegra_qspi_addr_config(bool is_ddr, u8 bus_width, u8 len)
1061 {
1062 u32 addr_config = 0;
1063
1064 if (is_ddr)
1065 addr_config |= QSPI_ADDRESS_SDR_DDR;
1066 else
1067 addr_config &= ~QSPI_ADDRESS_SDR_DDR;
1068
1069 addr_config |= QSPI_ADDRESS_X1_X2_X4(bus_width);
1070 addr_config |= QSPI_ADDRESS_SIZE_SET((len * 8) - 1);
1071
1072 return addr_config;
1073 }
1074
tegra_qspi_combined_seq_xfer(struct tegra_qspi * tqspi,struct spi_message * msg)1075 static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi,
1076 struct spi_message *msg)
1077 {
1078 bool is_first_msg = true;
1079 struct spi_transfer *xfer;
1080 struct spi_device *spi = msg->spi;
1081 u8 transfer_phase = 0;
1082 u32 cmd1 = 0, dma_ctl = 0;
1083 int ret = 0;
1084 u32 address_value = 0;
1085 u32 cmd_config = 0, addr_config = 0;
1086 u8 cmd_value = 0, val = 0;
1087
1088 /* Enable Combined sequence mode */
1089 val = tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG);
1090 if (spi->mode & SPI_TPM_HW_FLOW) {
1091 if (tqspi->soc_data->supports_tpm)
1092 val |= QSPI_TPM_WAIT_POLL_EN;
1093 else
1094 return -EIO;
1095 }
1096 val |= QSPI_CMB_SEQ_EN;
1097 tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG);
1098 /* Process individual transfer list */
1099 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1100 switch (transfer_phase) {
1101 case CMD_TRANSFER:
1102 /* X1 SDR mode */
1103 cmd_config = tegra_qspi_cmd_config(false, xfer->tx_nbits,
1104 xfer->len);
1105 cmd_value = *((const u8 *)(xfer->tx_buf));
1106 break;
1107 case ADDR_TRANSFER:
1108 /* X1 SDR mode */
1109 addr_config = tegra_qspi_addr_config(false, xfer->tx_nbits,
1110 xfer->len);
1111 address_value = *((const u32 *)(xfer->tx_buf));
1112 break;
1113 case DUMMY_TRANSFER:
1114 if (xfer->dummy_data) {
1115 tqspi->dummy_cycles = xfer->len * 8 / xfer->tx_nbits;
1116 break;
1117 }
1118 transfer_phase++;
1119 fallthrough;
1120 case DATA_TRANSFER:
1121 /* Program Command, Address value in register */
1122 tegra_qspi_writel(tqspi, cmd_value, QSPI_CMB_SEQ_CMD);
1123 tegra_qspi_writel(tqspi, address_value,
1124 QSPI_CMB_SEQ_ADDR);
1125 /* Program Command and Address config in register */
1126 tegra_qspi_writel(tqspi, cmd_config,
1127 QSPI_CMB_SEQ_CMD_CFG);
1128 tegra_qspi_writel(tqspi, addr_config,
1129 QSPI_CMB_SEQ_ADDR_CFG);
1130
1131 reinit_completion(&tqspi->xfer_completion);
1132 cmd1 = tegra_qspi_setup_transfer_one(spi, xfer,
1133 is_first_msg);
1134 ret = tegra_qspi_start_transfer_one(spi, xfer,
1135 cmd1);
1136
1137 if (ret < 0) {
1138 dev_err(tqspi->dev, "Failed to start transfer-one: %d\n",
1139 ret);
1140 return ret;
1141 }
1142
1143 is_first_msg = false;
1144 ret = wait_for_completion_timeout
1145 (&tqspi->xfer_completion,
1146 QSPI_DMA_TIMEOUT);
1147
1148 if (WARN_ON_ONCE(ret == 0)) {
1149 dev_err_ratelimited(tqspi->dev,
1150 "QSPI Transfer failed with timeout\n");
1151 if (tqspi->is_curr_dma_xfer) {
1152 if ((tqspi->cur_direction & DATA_DIR_TX) &&
1153 tqspi->tx_dma_chan)
1154 dmaengine_terminate_all(tqspi->tx_dma_chan);
1155 if ((tqspi->cur_direction & DATA_DIR_RX) &&
1156 tqspi->rx_dma_chan)
1157 dmaengine_terminate_all(tqspi->rx_dma_chan);
1158 }
1159
1160 /* Abort transfer by resetting pio/dma bit */
1161 if (!tqspi->is_curr_dma_xfer) {
1162 cmd1 = tegra_qspi_readl
1163 (tqspi,
1164 QSPI_COMMAND1);
1165 cmd1 &= ~QSPI_PIO;
1166 tegra_qspi_writel
1167 (tqspi, cmd1,
1168 QSPI_COMMAND1);
1169 } else {
1170 dma_ctl = tegra_qspi_readl
1171 (tqspi,
1172 QSPI_DMA_CTL);
1173 dma_ctl &= ~QSPI_DMA_EN;
1174 tegra_qspi_writel(tqspi, dma_ctl,
1175 QSPI_DMA_CTL);
1176 }
1177
1178 /* Reset controller if timeout happens */
1179 if (device_reset(tqspi->dev) < 0)
1180 dev_warn_once(tqspi->dev,
1181 "device reset failed\n");
1182 ret = -EIO;
1183 goto exit;
1184 }
1185
1186 if (tqspi->tx_status || tqspi->rx_status) {
1187 dev_err(tqspi->dev, "QSPI Transfer failed\n");
1188 tqspi->tx_status = 0;
1189 tqspi->rx_status = 0;
1190 ret = -EIO;
1191 goto exit;
1192 }
1193 break;
1194 default:
1195 ret = -EINVAL;
1196 goto exit;
1197 }
1198 msg->actual_length += xfer->len;
1199 if (!xfer->cs_change && transfer_phase == DATA_TRANSFER) {
1200 tegra_qspi_transfer_end(spi);
1201 spi_transfer_delay_exec(xfer);
1202 }
1203 transfer_phase++;
1204 }
1205 ret = 0;
1206
1207 exit:
1208 msg->status = ret;
1209
1210 return ret;
1211 }
1212
tegra_qspi_non_combined_seq_xfer(struct tegra_qspi * tqspi,struct spi_message * msg)1213 static int tegra_qspi_non_combined_seq_xfer(struct tegra_qspi *tqspi,
1214 struct spi_message *msg)
1215 {
1216 struct spi_device *spi = msg->spi;
1217 struct spi_transfer *transfer;
1218 bool is_first_msg = true;
1219 int ret = 0, val = 0;
1220
1221 msg->status = 0;
1222 msg->actual_length = 0;
1223 tqspi->tx_status = 0;
1224 tqspi->rx_status = 0;
1225
1226 /* Disable Combined sequence mode */
1227 val = tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG);
1228 val &= ~QSPI_CMB_SEQ_EN;
1229 if (tqspi->soc_data->supports_tpm)
1230 val &= ~QSPI_TPM_WAIT_POLL_EN;
1231 tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG);
1232 list_for_each_entry(transfer, &msg->transfers, transfer_list) {
1233 struct spi_transfer *xfer = transfer;
1234 u8 dummy_bytes = 0;
1235 u32 cmd1;
1236
1237 tqspi->dummy_cycles = 0;
1238 /*
1239 * Tegra QSPI hardware supports dummy bytes transfer after actual transfer
1240 * bytes based on programmed dummy clock cycles in the QSPI_MISC register.
1241 * So, check if the next transfer is dummy data transfer and program dummy
1242 * clock cycles along with the current transfer and skip next transfer.
1243 */
1244 if (!list_is_last(&xfer->transfer_list, &msg->transfers)) {
1245 struct spi_transfer *next_xfer;
1246
1247 next_xfer = list_next_entry(xfer, transfer_list);
1248 if (next_xfer->dummy_data) {
1249 u32 dummy_cycles = next_xfer->len * 8 / next_xfer->tx_nbits;
1250
1251 if (dummy_cycles <= QSPI_DUMMY_CYCLES_MAX) {
1252 tqspi->dummy_cycles = dummy_cycles;
1253 dummy_bytes = next_xfer->len;
1254 transfer = next_xfer;
1255 }
1256 }
1257 }
1258
1259 reinit_completion(&tqspi->xfer_completion);
1260
1261 cmd1 = tegra_qspi_setup_transfer_one(spi, xfer, is_first_msg);
1262
1263 ret = tegra_qspi_start_transfer_one(spi, xfer, cmd1);
1264 if (ret < 0) {
1265 dev_err(tqspi->dev, "failed to start transfer: %d\n", ret);
1266 goto complete_xfer;
1267 }
1268
1269 ret = wait_for_completion_timeout(&tqspi->xfer_completion,
1270 QSPI_DMA_TIMEOUT);
1271 if (WARN_ON(ret == 0)) {
1272 dev_err(tqspi->dev, "transfer timeout\n");
1273 if (tqspi->is_curr_dma_xfer) {
1274 if ((tqspi->cur_direction & DATA_DIR_TX) && tqspi->tx_dma_chan)
1275 dmaengine_terminate_all(tqspi->tx_dma_chan);
1276 if ((tqspi->cur_direction & DATA_DIR_RX) && tqspi->rx_dma_chan)
1277 dmaengine_terminate_all(tqspi->rx_dma_chan);
1278 }
1279 tegra_qspi_handle_error(tqspi);
1280 ret = -EIO;
1281 goto complete_xfer;
1282 }
1283
1284 if (tqspi->tx_status || tqspi->rx_status) {
1285 tegra_qspi_handle_error(tqspi);
1286 ret = -EIO;
1287 goto complete_xfer;
1288 }
1289
1290 msg->actual_length += xfer->len + dummy_bytes;
1291
1292 complete_xfer:
1293 if (ret < 0) {
1294 tegra_qspi_transfer_end(spi);
1295 spi_transfer_delay_exec(xfer);
1296 goto exit;
1297 }
1298
1299 if (list_is_last(&xfer->transfer_list, &msg->transfers)) {
1300 /* de-activate CS after last transfer only when cs_change is not set */
1301 if (!xfer->cs_change) {
1302 tegra_qspi_transfer_end(spi);
1303 spi_transfer_delay_exec(xfer);
1304 }
1305 } else if (xfer->cs_change) {
1306 /* de-activated CS between the transfers only when cs_change is set */
1307 tegra_qspi_transfer_end(spi);
1308 spi_transfer_delay_exec(xfer);
1309 }
1310 }
1311
1312 ret = 0;
1313 exit:
1314 msg->status = ret;
1315
1316 return ret;
1317 }
1318
tegra_qspi_validate_cmb_seq(struct tegra_qspi * tqspi,struct spi_message * msg)1319 static bool tegra_qspi_validate_cmb_seq(struct tegra_qspi *tqspi,
1320 struct spi_message *msg)
1321 {
1322 int transfer_count = 0;
1323 struct spi_transfer *xfer;
1324
1325 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1326 transfer_count++;
1327 }
1328 if (!tqspi->soc_data->cmb_xfer_capable)
1329 return false;
1330 if (transfer_count > 4 || transfer_count < 3)
1331 return false;
1332 xfer = list_first_entry(&msg->transfers, typeof(*xfer),
1333 transfer_list);
1334 if (xfer->len > 2)
1335 return false;
1336 xfer = list_next_entry(xfer, transfer_list);
1337 if (xfer->len > 4 || xfer->len < 3)
1338 return false;
1339 xfer = list_next_entry(xfer, transfer_list);
1340 if (transfer_count == 4) {
1341 if (xfer->dummy_data != 1)
1342 return false;
1343 if ((xfer->len * 8 / xfer->tx_nbits) > QSPI_DUMMY_CYCLES_MAX)
1344 return false;
1345 xfer = list_next_entry(xfer, transfer_list);
1346 }
1347 if (!tqspi->soc_data->has_ext_dma && xfer->len > (QSPI_FIFO_DEPTH << 2))
1348 return false;
1349
1350 return true;
1351 }
1352
tegra_qspi_transfer_one_message(struct spi_controller * host,struct spi_message * msg)1353 static int tegra_qspi_transfer_one_message(struct spi_controller *host,
1354 struct spi_message *msg)
1355 {
1356 struct tegra_qspi *tqspi = spi_controller_get_devdata(host);
1357 int ret;
1358
1359 if (tegra_qspi_validate_cmb_seq(tqspi, msg))
1360 ret = tegra_qspi_combined_seq_xfer(tqspi, msg);
1361 else
1362 ret = tegra_qspi_non_combined_seq_xfer(tqspi, msg);
1363
1364 spi_finalize_current_message(host);
1365
1366 return ret;
1367 }
1368
handle_cpu_based_xfer(struct tegra_qspi * tqspi)1369 static irqreturn_t handle_cpu_based_xfer(struct tegra_qspi *tqspi)
1370 {
1371 struct spi_transfer *t = tqspi->curr_xfer;
1372 unsigned long flags;
1373
1374 spin_lock_irqsave(&tqspi->lock, flags);
1375
1376 if (tqspi->tx_status || tqspi->rx_status) {
1377 tegra_qspi_handle_error(tqspi);
1378 complete(&tqspi->xfer_completion);
1379 goto exit;
1380 }
1381
1382 if (tqspi->cur_direction & DATA_DIR_RX)
1383 tegra_qspi_read_rx_fifo_to_client_rxbuf(tqspi, t);
1384
1385 if (tqspi->cur_direction & DATA_DIR_TX)
1386 tqspi->cur_pos = tqspi->cur_tx_pos;
1387 else
1388 tqspi->cur_pos = tqspi->cur_rx_pos;
1389
1390 if (tqspi->cur_pos == t->len) {
1391 complete(&tqspi->xfer_completion);
1392 goto exit;
1393 }
1394
1395 tegra_qspi_calculate_curr_xfer_param(tqspi, t);
1396 tegra_qspi_start_cpu_based_transfer(tqspi, t);
1397 exit:
1398 spin_unlock_irqrestore(&tqspi->lock, flags);
1399 return IRQ_HANDLED;
1400 }
1401
handle_dma_based_xfer(struct tegra_qspi * tqspi)1402 static irqreturn_t handle_dma_based_xfer(struct tegra_qspi *tqspi)
1403 {
1404 struct spi_transfer *t = tqspi->curr_xfer;
1405 unsigned int total_fifo_words;
1406 unsigned long flags;
1407 long wait_status;
1408 int num_errors = 0;
1409
1410 if (tqspi->cur_direction & DATA_DIR_TX) {
1411 if (tqspi->tx_status) {
1412 if (tqspi->tx_dma_chan)
1413 dmaengine_terminate_all(tqspi->tx_dma_chan);
1414 num_errors++;
1415 } else if (tqspi->tx_dma_chan) {
1416 wait_status = wait_for_completion_interruptible_timeout(
1417 &tqspi->tx_dma_complete, QSPI_DMA_TIMEOUT);
1418 if (wait_status <= 0) {
1419 dmaengine_terminate_all(tqspi->tx_dma_chan);
1420 dev_err(tqspi->dev, "failed TX DMA transfer\n");
1421 num_errors++;
1422 }
1423 }
1424 }
1425
1426 if (tqspi->cur_direction & DATA_DIR_RX) {
1427 if (tqspi->rx_status) {
1428 if (tqspi->rx_dma_chan)
1429 dmaengine_terminate_all(tqspi->rx_dma_chan);
1430 num_errors++;
1431 } else if (tqspi->rx_dma_chan) {
1432 wait_status = wait_for_completion_interruptible_timeout(
1433 &tqspi->rx_dma_complete, QSPI_DMA_TIMEOUT);
1434 if (wait_status <= 0) {
1435 dmaengine_terminate_all(tqspi->rx_dma_chan);
1436 dev_err(tqspi->dev, "failed RX DMA transfer\n");
1437 num_errors++;
1438 }
1439 }
1440 }
1441
1442 spin_lock_irqsave(&tqspi->lock, flags);
1443
1444 if (num_errors) {
1445 tegra_qspi_dma_unmap_xfer(tqspi, t);
1446 tegra_qspi_handle_error(tqspi);
1447 complete(&tqspi->xfer_completion);
1448 goto exit;
1449 }
1450
1451 if (tqspi->cur_direction & DATA_DIR_RX)
1452 tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf(tqspi, t);
1453
1454 if (tqspi->cur_direction & DATA_DIR_TX)
1455 tqspi->cur_pos = tqspi->cur_tx_pos;
1456 else
1457 tqspi->cur_pos = tqspi->cur_rx_pos;
1458
1459 if (tqspi->cur_pos == t->len) {
1460 tegra_qspi_dma_unmap_xfer(tqspi, t);
1461 complete(&tqspi->xfer_completion);
1462 goto exit;
1463 }
1464
1465 tegra_qspi_dma_unmap_xfer(tqspi, t);
1466
1467 /* continue transfer in current message */
1468 total_fifo_words = tegra_qspi_calculate_curr_xfer_param(tqspi, t);
1469 if (total_fifo_words > QSPI_FIFO_DEPTH)
1470 num_errors = tegra_qspi_start_dma_based_transfer(tqspi, t);
1471 else
1472 num_errors = tegra_qspi_start_cpu_based_transfer(tqspi, t);
1473
1474 exit:
1475 spin_unlock_irqrestore(&tqspi->lock, flags);
1476 return IRQ_HANDLED;
1477 }
1478
tegra_qspi_isr_thread(int irq,void * context_data)1479 static irqreturn_t tegra_qspi_isr_thread(int irq, void *context_data)
1480 {
1481 struct tegra_qspi *tqspi = context_data;
1482
1483 tqspi->status_reg = tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS);
1484
1485 if (tqspi->cur_direction & DATA_DIR_TX)
1486 tqspi->tx_status = tqspi->status_reg & (QSPI_TX_FIFO_UNF | QSPI_TX_FIFO_OVF);
1487
1488 if (tqspi->cur_direction & DATA_DIR_RX)
1489 tqspi->rx_status = tqspi->status_reg & (QSPI_RX_FIFO_OVF | QSPI_RX_FIFO_UNF);
1490
1491 tegra_qspi_mask_clear_irq(tqspi);
1492
1493 if (!tqspi->is_curr_dma_xfer)
1494 return handle_cpu_based_xfer(tqspi);
1495
1496 return handle_dma_based_xfer(tqspi);
1497 }
1498
1499 static struct tegra_qspi_soc_data tegra210_qspi_soc_data = {
1500 .has_ext_dma = true,
1501 .cmb_xfer_capable = false,
1502 .supports_tpm = false,
1503 .cs_count = 1,
1504 };
1505
1506 static struct tegra_qspi_soc_data tegra186_qspi_soc_data = {
1507 .has_ext_dma = true,
1508 .cmb_xfer_capable = true,
1509 .supports_tpm = false,
1510 .cs_count = 1,
1511 };
1512
1513 static struct tegra_qspi_soc_data tegra234_qspi_soc_data = {
1514 .has_ext_dma = false,
1515 .cmb_xfer_capable = true,
1516 .supports_tpm = true,
1517 .cs_count = 1,
1518 };
1519
1520 static struct tegra_qspi_soc_data tegra241_qspi_soc_data = {
1521 .has_ext_dma = true,
1522 .cmb_xfer_capable = true,
1523 .supports_tpm = true,
1524 .cs_count = 4,
1525 };
1526
1527 static const struct of_device_id tegra_qspi_of_match[] = {
1528 {
1529 .compatible = "nvidia,tegra210-qspi",
1530 .data = &tegra210_qspi_soc_data,
1531 }, {
1532 .compatible = "nvidia,tegra186-qspi",
1533 .data = &tegra186_qspi_soc_data,
1534 }, {
1535 .compatible = "nvidia,tegra194-qspi",
1536 .data = &tegra186_qspi_soc_data,
1537 }, {
1538 .compatible = "nvidia,tegra234-qspi",
1539 .data = &tegra234_qspi_soc_data,
1540 }, {
1541 .compatible = "nvidia,tegra241-qspi",
1542 .data = &tegra241_qspi_soc_data,
1543 },
1544 {}
1545 };
1546
1547 MODULE_DEVICE_TABLE(of, tegra_qspi_of_match);
1548
1549 #ifdef CONFIG_ACPI
1550 static const struct acpi_device_id tegra_qspi_acpi_match[] = {
1551 {
1552 .id = "NVDA1213",
1553 .driver_data = (kernel_ulong_t)&tegra210_qspi_soc_data,
1554 }, {
1555 .id = "NVDA1313",
1556 .driver_data = (kernel_ulong_t)&tegra186_qspi_soc_data,
1557 }, {
1558 .id = "NVDA1413",
1559 .driver_data = (kernel_ulong_t)&tegra234_qspi_soc_data,
1560 }, {
1561 .id = "NVDA1513",
1562 .driver_data = (kernel_ulong_t)&tegra241_qspi_soc_data,
1563 },
1564 {}
1565 };
1566
1567 MODULE_DEVICE_TABLE(acpi, tegra_qspi_acpi_match);
1568 #endif
1569
tegra_qspi_probe(struct platform_device * pdev)1570 static int tegra_qspi_probe(struct platform_device *pdev)
1571 {
1572 struct spi_controller *host;
1573 struct tegra_qspi *tqspi;
1574 struct resource *r;
1575 int ret, qspi_irq;
1576 int bus_num;
1577
1578 host = devm_spi_alloc_host(&pdev->dev, sizeof(*tqspi));
1579 if (!host)
1580 return -ENOMEM;
1581
1582 platform_set_drvdata(pdev, host);
1583 tqspi = spi_controller_get_devdata(host);
1584
1585 host->mode_bits = SPI_MODE_0 | SPI_MODE_3 | SPI_CS_HIGH |
1586 SPI_TX_DUAL | SPI_RX_DUAL | SPI_TX_QUAD | SPI_RX_QUAD;
1587 host->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | SPI_BPW_MASK(8);
1588 host->flags = SPI_CONTROLLER_HALF_DUPLEX;
1589 host->setup = tegra_qspi_setup;
1590 host->transfer_one_message = tegra_qspi_transfer_one_message;
1591 host->num_chipselect = 1;
1592 host->auto_runtime_pm = true;
1593
1594 bus_num = of_alias_get_id(pdev->dev.of_node, "spi");
1595 if (bus_num >= 0)
1596 host->bus_num = bus_num;
1597
1598 tqspi->host = host;
1599 tqspi->dev = &pdev->dev;
1600 spin_lock_init(&tqspi->lock);
1601
1602 tqspi->soc_data = device_get_match_data(&pdev->dev);
1603 host->num_chipselect = tqspi->soc_data->cs_count;
1604 tqspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &r);
1605 if (IS_ERR(tqspi->base))
1606 return PTR_ERR(tqspi->base);
1607
1608 tqspi->phys = r->start;
1609 qspi_irq = platform_get_irq(pdev, 0);
1610 if (qspi_irq < 0)
1611 return qspi_irq;
1612 tqspi->irq = qspi_irq;
1613
1614 if (!has_acpi_companion(tqspi->dev)) {
1615 tqspi->clk = devm_clk_get(&pdev->dev, "qspi");
1616 if (IS_ERR(tqspi->clk)) {
1617 ret = PTR_ERR(tqspi->clk);
1618 dev_err(&pdev->dev, "failed to get clock: %d\n", ret);
1619 return ret;
1620 }
1621
1622 }
1623
1624 tqspi->max_buf_size = QSPI_FIFO_DEPTH << 2;
1625 tqspi->dma_buf_size = DEFAULT_QSPI_DMA_BUF_LEN;
1626
1627 ret = tegra_qspi_init_dma(tqspi);
1628 if (ret < 0)
1629 return ret;
1630
1631 if (tqspi->use_dma)
1632 tqspi->max_buf_size = tqspi->dma_buf_size;
1633
1634 init_completion(&tqspi->tx_dma_complete);
1635 init_completion(&tqspi->rx_dma_complete);
1636 init_completion(&tqspi->xfer_completion);
1637
1638 pm_runtime_enable(&pdev->dev);
1639 ret = pm_runtime_resume_and_get(&pdev->dev);
1640 if (ret < 0) {
1641 dev_err(&pdev->dev, "failed to get runtime PM: %d\n", ret);
1642 goto exit_pm_disable;
1643 }
1644
1645 if (device_reset(tqspi->dev) < 0)
1646 dev_warn_once(tqspi->dev, "device reset failed\n");
1647
1648 tqspi->def_command1_reg = QSPI_M_S | QSPI_CS_SW_HW | QSPI_CS_SW_VAL;
1649 tegra_qspi_writel(tqspi, tqspi->def_command1_reg, QSPI_COMMAND1);
1650 tqspi->spi_cs_timing1 = tegra_qspi_readl(tqspi, QSPI_CS_TIMING1);
1651 tqspi->spi_cs_timing2 = tegra_qspi_readl(tqspi, QSPI_CS_TIMING2);
1652 tqspi->def_command2_reg = tegra_qspi_readl(tqspi, QSPI_COMMAND2);
1653
1654 pm_runtime_put(&pdev->dev);
1655
1656 ret = request_threaded_irq(tqspi->irq, NULL,
1657 tegra_qspi_isr_thread, IRQF_ONESHOT,
1658 dev_name(&pdev->dev), tqspi);
1659 if (ret < 0) {
1660 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", tqspi->irq, ret);
1661 goto exit_pm_disable;
1662 }
1663
1664 host->dev.of_node = pdev->dev.of_node;
1665 ret = spi_register_controller(host);
1666 if (ret < 0) {
1667 dev_err(&pdev->dev, "failed to register host: %d\n", ret);
1668 goto exit_free_irq;
1669 }
1670
1671 return 0;
1672
1673 exit_free_irq:
1674 free_irq(qspi_irq, tqspi);
1675 exit_pm_disable:
1676 pm_runtime_force_suspend(&pdev->dev);
1677 tegra_qspi_deinit_dma(tqspi);
1678 return ret;
1679 }
1680
tegra_qspi_remove(struct platform_device * pdev)1681 static void tegra_qspi_remove(struct platform_device *pdev)
1682 {
1683 struct spi_controller *host = platform_get_drvdata(pdev);
1684 struct tegra_qspi *tqspi = spi_controller_get_devdata(host);
1685
1686 spi_unregister_controller(host);
1687 free_irq(tqspi->irq, tqspi);
1688 pm_runtime_force_suspend(&pdev->dev);
1689 tegra_qspi_deinit_dma(tqspi);
1690 }
1691
tegra_qspi_suspend(struct device * dev)1692 static int __maybe_unused tegra_qspi_suspend(struct device *dev)
1693 {
1694 struct spi_controller *host = dev_get_drvdata(dev);
1695
1696 return spi_controller_suspend(host);
1697 }
1698
tegra_qspi_resume(struct device * dev)1699 static int __maybe_unused tegra_qspi_resume(struct device *dev)
1700 {
1701 struct spi_controller *host = dev_get_drvdata(dev);
1702 struct tegra_qspi *tqspi = spi_controller_get_devdata(host);
1703 int ret;
1704
1705 ret = pm_runtime_resume_and_get(dev);
1706 if (ret < 0) {
1707 dev_err(dev, "failed to get runtime PM: %d\n", ret);
1708 return ret;
1709 }
1710
1711 tegra_qspi_writel(tqspi, tqspi->command1_reg, QSPI_COMMAND1);
1712 tegra_qspi_writel(tqspi, tqspi->def_command2_reg, QSPI_COMMAND2);
1713 pm_runtime_put(dev);
1714
1715 return spi_controller_resume(host);
1716 }
1717
tegra_qspi_runtime_suspend(struct device * dev)1718 static int __maybe_unused tegra_qspi_runtime_suspend(struct device *dev)
1719 {
1720 struct spi_controller *host = dev_get_drvdata(dev);
1721 struct tegra_qspi *tqspi = spi_controller_get_devdata(host);
1722
1723 /* Runtime pm disabled with ACPI */
1724 if (has_acpi_companion(tqspi->dev))
1725 return 0;
1726 /* flush all write which are in PPSB queue by reading back */
1727 tegra_qspi_readl(tqspi, QSPI_COMMAND1);
1728
1729 clk_disable_unprepare(tqspi->clk);
1730
1731 return 0;
1732 }
1733
tegra_qspi_runtime_resume(struct device * dev)1734 static int __maybe_unused tegra_qspi_runtime_resume(struct device *dev)
1735 {
1736 struct spi_controller *host = dev_get_drvdata(dev);
1737 struct tegra_qspi *tqspi = spi_controller_get_devdata(host);
1738 int ret;
1739
1740 /* Runtime pm disabled with ACPI */
1741 if (has_acpi_companion(tqspi->dev))
1742 return 0;
1743 ret = clk_prepare_enable(tqspi->clk);
1744 if (ret < 0)
1745 dev_err(tqspi->dev, "failed to enable clock: %d\n", ret);
1746
1747 return ret;
1748 }
1749
1750 static const struct dev_pm_ops tegra_qspi_pm_ops = {
1751 SET_RUNTIME_PM_OPS(tegra_qspi_runtime_suspend, tegra_qspi_runtime_resume, NULL)
1752 SET_SYSTEM_SLEEP_PM_OPS(tegra_qspi_suspend, tegra_qspi_resume)
1753 };
1754
1755 static struct platform_driver tegra_qspi_driver = {
1756 .driver = {
1757 .name = "tegra-qspi",
1758 .pm = &tegra_qspi_pm_ops,
1759 .of_match_table = tegra_qspi_of_match,
1760 .acpi_match_table = ACPI_PTR(tegra_qspi_acpi_match),
1761 },
1762 .probe = tegra_qspi_probe,
1763 .remove = tegra_qspi_remove,
1764 };
1765 module_platform_driver(tegra_qspi_driver);
1766
1767 MODULE_ALIAS("platform:qspi-tegra");
1768 MODULE_DESCRIPTION("NVIDIA Tegra QSPI Controller Driver");
1769 MODULE_AUTHOR("Sowjanya Komatineni <skomatineni@nvidia.com>");
1770 MODULE_LICENSE("GPL v2");
1771