1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Renesas RZ/V2H Renesas Serial Peripheral Interface (RSPI) 4 * 5 * Copyright (C) 2025 Renesas Electronics Corporation 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bitops.h> 10 #include <linux/bits.h> 11 #include <linux/clk.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/limits.h> 15 #include <linux/log2.h> 16 #include <linux/math.h> 17 #include <linux/of.h> 18 #include <linux/platform_device.h> 19 #include <linux/property.h> 20 #include <linux/reset.h> 21 #include <linux/spi/spi.h> 22 #include <linux/wait.h> 23 24 /* Registers */ 25 #define RSPI_SPDR 0x00 26 #define RSPI_SPCR 0x08 27 #define RSPI_SPPCR 0x0e 28 #define RSPI_SSLP 0x10 29 #define RSPI_SPBR 0x11 30 #define RSPI_SPSCR 0x13 31 #define RSPI_SPCMD 0x14 32 #define RSPI_SPDCR2 0x44 33 #define RSPI_SPSR 0x52 34 #define RSPI_SPSRC 0x6a 35 #define RSPI_SPFCR 0x6c 36 37 /* Register SPCR */ 38 #define RSPI_SPCR_BPEN BIT(31) 39 #define RSPI_SPCR_MSTR BIT(30) 40 #define RSPI_SPCR_SPRIE BIT(17) 41 #define RSPI_SPCR_SCKASE BIT(12) 42 #define RSPI_SPCR_SPE BIT(0) 43 44 /* Register SPPCR */ 45 #define RSPI_SPPCR_SPLP2 BIT(1) 46 47 /* Register SPBR */ 48 #define RSPI_SPBR_SPR_MIN 0 49 #define RSPI_SPBR_SPR_PCLK_MIN 1 50 #define RSPI_SPBR_SPR_MAX 255 51 52 /* Register SPCMD */ 53 #define RSPI_SPCMD_SSLA GENMASK(25, 24) 54 #define RSPI_SPCMD_SPB GENMASK(20, 16) 55 #define RSPI_SPCMD_LSBF BIT(12) 56 #define RSPI_SPCMD_SSLKP BIT(7) 57 #define RSPI_SPCMD_BRDV GENMASK(3, 2) 58 #define RSPI_SPCMD_CPOL BIT(1) 59 #define RSPI_SPCMD_CPHA BIT(0) 60 61 #define RSPI_SPCMD_BRDV_MIN 0 62 #define RSPI_SPCMD_BRDV_MAX 3 63 64 /* Register SPDCR2 */ 65 #define RSPI_SPDCR2_TTRG GENMASK(11, 8) 66 #define RSPI_SPDCR2_RTRG GENMASK(3, 0) 67 68 /* Register SPSR */ 69 #define RSPI_SPSR_SPRF BIT(15) 70 71 /* Register RSPI_SPSRC */ 72 #define RSPI_SPSRC_CLEAR 0xfd80 73 74 #define RSPI_RESET_NUM 2 75 76 struct rzv2h_rspi_best_clock { 77 struct clk *clk; 78 unsigned long clk_rate; 79 unsigned long error; 80 u32 actual_hz; 81 u8 brdv; 82 u8 spr; 83 }; 84 85 struct rzv2h_rspi_info { 86 void (*find_tclk_rate)(struct clk *clk, u32 hz, u8 spr_min, u8 spr_max, 87 struct rzv2h_rspi_best_clock *best_clk); 88 void (*find_pclk_rate)(struct clk *clk, u32 hz, u8 spr_low, u8 spr_high, 89 struct rzv2h_rspi_best_clock *best_clk); 90 const char *tclk_name; 91 unsigned int fifo_size; 92 unsigned int num_clks; 93 }; 94 95 struct rzv2h_rspi_priv { 96 struct reset_control_bulk_data resets[RSPI_RESET_NUM]; 97 struct spi_controller *controller; 98 const struct rzv2h_rspi_info *info; 99 void __iomem *base; 100 struct clk *tclk; 101 struct clk *pclk; 102 wait_queue_head_t wait; 103 unsigned int bytes_per_word; 104 u32 last_speed_hz; 105 u32 freq; 106 u16 status; 107 u8 spr; 108 u8 brdv; 109 bool use_pclk; 110 }; 111 112 #define RZV2H_RSPI_TX(func, type) \ 113 static inline void rzv2h_rspi_tx_##type(struct rzv2h_rspi_priv *rspi, \ 114 const void *txbuf, \ 115 unsigned int index) { \ 116 type buf = 0; \ 117 \ 118 if (txbuf) \ 119 buf = ((type *)txbuf)[index]; \ 120 \ 121 func(buf, rspi->base + RSPI_SPDR); \ 122 } 123 124 #define RZV2H_RSPI_RX(func, type) \ 125 static inline void rzv2h_rspi_rx_##type(struct rzv2h_rspi_priv *rspi, \ 126 void *rxbuf, \ 127 unsigned int index) { \ 128 type buf = func(rspi->base + RSPI_SPDR); \ 129 \ 130 if (rxbuf) \ 131 ((type *)rxbuf)[index] = buf; \ 132 } 133 134 RZV2H_RSPI_TX(writel, u32) 135 RZV2H_RSPI_TX(writew, u16) 136 RZV2H_RSPI_TX(writeb, u8) 137 RZV2H_RSPI_RX(readl, u32) 138 RZV2H_RSPI_RX(readw, u16) 139 RZV2H_RSPI_RX(readl, u8) 140 141 static void rzv2h_rspi_reg_rmw(const struct rzv2h_rspi_priv *rspi, 142 int reg_offs, u32 bit_mask, u32 value) 143 { 144 u32 tmp; 145 146 value <<= __ffs(bit_mask); 147 tmp = (readl(rspi->base + reg_offs) & ~bit_mask) | value; 148 writel(tmp, rspi->base + reg_offs); 149 } 150 151 static inline void rzv2h_rspi_spe_disable(const struct rzv2h_rspi_priv *rspi) 152 { 153 rzv2h_rspi_reg_rmw(rspi, RSPI_SPCR, RSPI_SPCR_SPE, 0); 154 } 155 156 static inline void rzv2h_rspi_spe_enable(const struct rzv2h_rspi_priv *rspi) 157 { 158 rzv2h_rspi_reg_rmw(rspi, RSPI_SPCR, RSPI_SPCR_SPE, 1); 159 } 160 161 static inline void rzv2h_rspi_clear_fifos(const struct rzv2h_rspi_priv *rspi) 162 { 163 writeb(1, rspi->base + RSPI_SPFCR); 164 } 165 166 static inline void rzv2h_rspi_clear_all_irqs(struct rzv2h_rspi_priv *rspi) 167 { 168 writew(RSPI_SPSRC_CLEAR, rspi->base + RSPI_SPSRC); 169 rspi->status = 0; 170 } 171 172 static irqreturn_t rzv2h_rx_irq_handler(int irq, void *data) 173 { 174 struct rzv2h_rspi_priv *rspi = data; 175 176 rspi->status = readw(rspi->base + RSPI_SPSR); 177 wake_up(&rspi->wait); 178 179 return IRQ_HANDLED; 180 } 181 182 static inline int rzv2h_rspi_wait_for_interrupt(struct rzv2h_rspi_priv *rspi, 183 u32 wait_mask) 184 { 185 return wait_event_timeout(rspi->wait, (rspi->status & wait_mask), 186 HZ) == 0 ? -ETIMEDOUT : 0; 187 } 188 189 static void rzv2h_rspi_send(struct rzv2h_rspi_priv *rspi, const void *txbuf, 190 unsigned int index) 191 { 192 switch (rspi->bytes_per_word) { 193 case 4: 194 rzv2h_rspi_tx_u32(rspi, txbuf, index); 195 break; 196 case 2: 197 rzv2h_rspi_tx_u16(rspi, txbuf, index); 198 break; 199 default: 200 rzv2h_rspi_tx_u8(rspi, txbuf, index); 201 } 202 } 203 204 static int rzv2h_rspi_receive(struct rzv2h_rspi_priv *rspi, void *rxbuf, 205 unsigned int index) 206 { 207 int ret; 208 209 ret = rzv2h_rspi_wait_for_interrupt(rspi, RSPI_SPSR_SPRF); 210 if (ret) 211 return ret; 212 213 switch (rspi->bytes_per_word) { 214 case 4: 215 rzv2h_rspi_rx_u32(rspi, rxbuf, index); 216 break; 217 case 2: 218 rzv2h_rspi_rx_u16(rspi, rxbuf, index); 219 break; 220 default: 221 rzv2h_rspi_rx_u8(rspi, rxbuf, index); 222 } 223 224 return 0; 225 } 226 227 static int rzv2h_rspi_transfer_one(struct spi_controller *controller, 228 struct spi_device *spi, 229 struct spi_transfer *transfer) 230 { 231 struct rzv2h_rspi_priv *rspi = spi_controller_get_devdata(controller); 232 unsigned int words_to_transfer, i; 233 int ret = 0; 234 235 transfer->effective_speed_hz = rspi->freq; 236 words_to_transfer = transfer->len / rspi->bytes_per_word; 237 238 for (i = 0; i < words_to_transfer; i++) { 239 rzv2h_rspi_clear_all_irqs(rspi); 240 241 rzv2h_rspi_send(rspi, transfer->tx_buf, i); 242 243 ret = rzv2h_rspi_receive(rspi, transfer->rx_buf, i); 244 if (ret) 245 break; 246 } 247 248 rzv2h_rspi_clear_all_irqs(rspi); 249 250 if (ret) 251 transfer->error = SPI_TRANS_FAIL_IO; 252 253 spi_finalize_current_transfer(controller); 254 255 return ret; 256 } 257 258 static inline u32 rzv2h_rspi_calc_bitrate(unsigned long tclk_rate, u8 spr, 259 u8 brdv) 260 { 261 return DIV_ROUND_UP(tclk_rate, (2 * (spr + 1) * (1 << brdv))); 262 } 263 264 static void rzv2h_rspi_find_rate_variable(struct clk *clk, u32 hz, 265 u8 spr_min, u8 spr_max, 266 struct rzv2h_rspi_best_clock *best) 267 { 268 long clk_rate, clk_min_rate, clk_max_rate; 269 int min_rate_spr, max_rate_spr; 270 unsigned long error; 271 u32 actual_hz; 272 u8 brdv; 273 int spr; 274 275 /* 276 * On T2H / N2H, the source for the SPI clock is PCLKSPIn, which is a 277 * 1/32, 1/30, 1/25 or 1/24 divider of PLL4, which is 2400MHz, 278 * resulting in either 75MHz, 80MHz, 96MHz or 100MHz. 279 */ 280 clk_min_rate = clk_round_rate(clk, 0); 281 if (clk_min_rate < 0) 282 return; 283 284 clk_max_rate = clk_round_rate(clk, ULONG_MAX); 285 if (clk_max_rate < 0) 286 return; 287 288 /* 289 * From the manual: 290 * Bit rate = f(PCLKSPIn) / (2 * (n + 1) * 2^N) 291 * 292 * If we adapt it to the current context, we get the following: 293 * hz = rate / ((spr + 1) * (1 << (brdv + 1))) 294 * 295 * This can be written in multiple forms depending on what we want to 296 * determine. 297 * 298 * To find the rate, having hz, spr and brdv: 299 * rate = hz * (spr + 1) * (1 << (brdv + 1) 300 * 301 * To find the spr, having rate, hz, and spr: 302 * spr = rate / (hz * (1 << (brdv + 1)) - 1 303 */ 304 305 for (brdv = RSPI_SPCMD_BRDV_MIN; brdv <= RSPI_SPCMD_BRDV_MAX; brdv++) { 306 /* Calculate the divisor needed to find the SPR from a rate. */ 307 u32 rate_div = hz * (1 << (brdv + 1)); 308 309 /* 310 * If the SPR for the minimum rate is greater than the maximum 311 * allowed value skip this BRDV. The divisor increases with each 312 * BRDV iteration, so the following BRDV might result in a 313 * minimum SPR that is in the valid range. 314 */ 315 min_rate_spr = DIV_ROUND_CLOSEST(clk_min_rate, rate_div) - 1; 316 if (min_rate_spr > spr_max) 317 continue; 318 319 /* 320 * If the SPR for the maximum rate is less than the minimum 321 * allowed value, exit. The divisor only increases with each 322 * BRDV iteration, so the following BRDV cannot result in a 323 * maximum SPR that is in the valid range. 324 */ 325 max_rate_spr = DIV_ROUND_CLOSEST(clk_max_rate, rate_div) - 1; 326 if (max_rate_spr < spr_min) 327 break; 328 329 if (min_rate_spr < spr_min) 330 min_rate_spr = spr_min; 331 332 if (max_rate_spr > spr_max) 333 max_rate_spr = spr_max; 334 335 for (spr = min_rate_spr; spr <= max_rate_spr; spr++) { 336 clk_rate = (spr + 1) * rate_div; 337 338 clk_rate = clk_round_rate(clk, clk_rate); 339 if (clk_rate <= 0) 340 continue; 341 342 actual_hz = rzv2h_rspi_calc_bitrate(clk_rate, spr, brdv); 343 error = abs((long)hz - (long)actual_hz); 344 345 if (error >= best->error) 346 continue; 347 348 *best = (struct rzv2h_rspi_best_clock) { 349 .clk = clk, 350 .clk_rate = clk_rate, 351 .error = error, 352 .actual_hz = actual_hz, 353 .brdv = brdv, 354 .spr = spr, 355 }; 356 357 if (!error) 358 return; 359 } 360 } 361 } 362 363 static void rzv2h_rspi_find_rate_fixed(struct clk *clk, u32 hz, 364 u8 spr_min, u8 spr_max, 365 struct rzv2h_rspi_best_clock *best) 366 { 367 unsigned long clk_rate; 368 unsigned long error; 369 u32 actual_hz; 370 int spr; 371 u8 brdv; 372 373 /* 374 * From the manual: 375 * Bit rate = f(RSPI_n_TCLK)/(2*(n+1)*2^(N)) 376 * 377 * Where: 378 * * RSPI_n_TCLK is fixed to 200MHz on V2H 379 * * n = SPR - is RSPI_SPBR.SPR (from 0 to 255) 380 * * N = BRDV - is RSPI_SPCMD.BRDV (from 0 to 3) 381 */ 382 clk_rate = clk_get_rate(clk); 383 for (brdv = RSPI_SPCMD_BRDV_MIN; brdv <= RSPI_SPCMD_BRDV_MAX; brdv++) { 384 spr = DIV_ROUND_UP(clk_rate, hz * (1 << (brdv + 1))); 385 spr--; 386 if (spr >= spr_min && spr <= spr_max) 387 goto clock_found; 388 } 389 390 return; 391 392 clock_found: 393 actual_hz = rzv2h_rspi_calc_bitrate(clk_rate, spr, brdv); 394 error = abs((long)hz - (long)actual_hz); 395 396 if (error >= best->error) 397 return; 398 399 *best = (struct rzv2h_rspi_best_clock) { 400 .clk = clk, 401 .clk_rate = clk_rate, 402 .error = error, 403 .actual_hz = actual_hz, 404 .brdv = brdv, 405 .spr = spr, 406 }; 407 } 408 409 static u32 rzv2h_rspi_setup_clock(struct rzv2h_rspi_priv *rspi, u32 hz) 410 { 411 struct rzv2h_rspi_best_clock best_clock = { 412 .error = ULONG_MAX, 413 }; 414 int ret; 415 416 rspi->info->find_tclk_rate(rspi->tclk, hz, RSPI_SPBR_SPR_MIN, 417 RSPI_SPBR_SPR_MAX, &best_clock); 418 419 /* 420 * T2H and N2H can also use PCLK as a source, which is 125MHz, but not 421 * when both SPR and BRDV are 0. 422 */ 423 if (best_clock.error && rspi->info->find_pclk_rate) 424 rspi->info->find_pclk_rate(rspi->pclk, hz, RSPI_SPBR_SPR_PCLK_MIN, 425 RSPI_SPBR_SPR_MAX, &best_clock); 426 427 if (!best_clock.clk_rate) 428 return -EINVAL; 429 430 ret = clk_set_rate(best_clock.clk, best_clock.clk_rate); 431 if (ret) 432 return 0; 433 434 rspi->use_pclk = best_clock.clk == rspi->pclk; 435 rspi->spr = best_clock.spr; 436 rspi->brdv = best_clock.brdv; 437 438 return best_clock.actual_hz; 439 } 440 441 static int rzv2h_rspi_prepare_message(struct spi_controller *ctlr, 442 struct spi_message *message) 443 { 444 struct rzv2h_rspi_priv *rspi = spi_controller_get_devdata(ctlr); 445 const struct spi_device *spi = message->spi; 446 struct spi_transfer *xfer; 447 u32 speed_hz = U32_MAX; 448 u8 bits_per_word; 449 u32 conf32; 450 u16 conf16; 451 u8 conf8; 452 453 /* Make sure SPCR.SPE is 0 before amending the configuration */ 454 rzv2h_rspi_spe_disable(rspi); 455 456 list_for_each_entry(xfer, &message->transfers, transfer_list) { 457 if (!xfer->speed_hz) 458 continue; 459 460 speed_hz = min(xfer->speed_hz, speed_hz); 461 bits_per_word = xfer->bits_per_word; 462 } 463 464 if (speed_hz == U32_MAX) 465 return -EINVAL; 466 467 rspi->bytes_per_word = roundup_pow_of_two(BITS_TO_BYTES(bits_per_word)); 468 469 if (speed_hz != rspi->last_speed_hz) { 470 rspi->freq = rzv2h_rspi_setup_clock(rspi, speed_hz); 471 if (!rspi->freq) 472 return -EINVAL; 473 474 rspi->last_speed_hz = speed_hz; 475 } 476 477 writeb(rspi->spr, rspi->base + RSPI_SPBR); 478 479 /* Configure the device to work in "host" mode */ 480 conf32 = RSPI_SPCR_MSTR; 481 482 /* Auto-stop function */ 483 conf32 |= RSPI_SPCR_SCKASE; 484 485 /* SPI receive buffer full interrupt enable */ 486 conf32 |= RSPI_SPCR_SPRIE; 487 488 /* Bypass synchronization circuit */ 489 conf32 |= FIELD_PREP(RSPI_SPCR_BPEN, rspi->use_pclk); 490 491 writel(conf32, rspi->base + RSPI_SPCR); 492 493 /* Use SPCMD0 only */ 494 writeb(0x0, rspi->base + RSPI_SPSCR); 495 496 /* Setup loopback */ 497 conf8 = FIELD_PREP(RSPI_SPPCR_SPLP2, !!(spi->mode & SPI_LOOP)); 498 writeb(conf8, rspi->base + RSPI_SPPCR); 499 500 /* Setup mode */ 501 conf32 = FIELD_PREP(RSPI_SPCMD_CPOL, !!(spi->mode & SPI_CPOL)); 502 conf32 |= FIELD_PREP(RSPI_SPCMD_CPHA, !!(spi->mode & SPI_CPHA)); 503 conf32 |= FIELD_PREP(RSPI_SPCMD_LSBF, !!(spi->mode & SPI_LSB_FIRST)); 504 conf32 |= FIELD_PREP(RSPI_SPCMD_SPB, bits_per_word - 1); 505 conf32 |= FIELD_PREP(RSPI_SPCMD_BRDV, rspi->brdv); 506 conf32 |= FIELD_PREP(RSPI_SPCMD_SSLKP, 1); 507 conf32 |= FIELD_PREP(RSPI_SPCMD_SSLA, spi_get_chipselect(spi, 0)); 508 writel(conf32, rspi->base + RSPI_SPCMD); 509 if (spi->mode & SPI_CS_HIGH) 510 writeb(BIT(spi_get_chipselect(spi, 0)), rspi->base + RSPI_SSLP); 511 else 512 writeb(0, rspi->base + RSPI_SSLP); 513 514 /* Setup FIFO thresholds */ 515 conf16 = FIELD_PREP(RSPI_SPDCR2_TTRG, rspi->info->fifo_size - 1); 516 conf16 |= FIELD_PREP(RSPI_SPDCR2_RTRG, 0); 517 writew(conf16, rspi->base + RSPI_SPDCR2); 518 519 rzv2h_rspi_clear_fifos(rspi); 520 521 rzv2h_rspi_spe_enable(rspi); 522 523 return 0; 524 } 525 526 static int rzv2h_rspi_unprepare_message(struct spi_controller *ctlr, 527 struct spi_message *message) 528 { 529 struct rzv2h_rspi_priv *rspi = spi_controller_get_devdata(ctlr); 530 531 rzv2h_rspi_spe_disable(rspi); 532 533 return 0; 534 } 535 536 static int rzv2h_rspi_probe(struct platform_device *pdev) 537 { 538 struct spi_controller *controller; 539 struct device *dev = &pdev->dev; 540 struct rzv2h_rspi_priv *rspi; 541 struct clk_bulk_data *clks; 542 int irq_rx, ret, i; 543 long tclk_rate; 544 545 controller = devm_spi_alloc_host(dev, sizeof(*rspi)); 546 if (!controller) 547 return -ENOMEM; 548 549 rspi = spi_controller_get_devdata(controller); 550 platform_set_drvdata(pdev, rspi); 551 552 rspi->controller = controller; 553 554 rspi->info = device_get_match_data(dev); 555 556 rspi->base = devm_platform_ioremap_resource(pdev, 0); 557 if (IS_ERR(rspi->base)) 558 return PTR_ERR(rspi->base); 559 560 ret = devm_clk_bulk_get_all_enabled(dev, &clks); 561 if (ret != rspi->info->num_clks) 562 return dev_err_probe(dev, ret >= 0 ? -EINVAL : ret, 563 "cannot get clocks\n"); 564 for (i = 0; i < rspi->info->num_clks; i++) { 565 if (!strcmp(clks[i].id, rspi->info->tclk_name)) { 566 rspi->tclk = clks[i].clk; 567 } else if (rspi->info->find_pclk_rate && 568 !strcmp(clks[i].id, "pclk")) { 569 rspi->pclk = clks[i].clk; 570 } 571 } 572 573 if (!rspi->tclk) 574 return dev_err_probe(dev, -EINVAL, "Failed to get tclk\n"); 575 576 rspi->resets[0].id = "presetn"; 577 rspi->resets[1].id = "tresetn"; 578 ret = devm_reset_control_bulk_get_optional_exclusive(dev, RSPI_RESET_NUM, 579 rspi->resets); 580 if (ret) 581 return dev_err_probe(dev, ret, "cannot get resets\n"); 582 583 irq_rx = platform_get_irq_byname(pdev, "rx"); 584 if (irq_rx < 0) 585 return dev_err_probe(dev, irq_rx, "cannot get IRQ 'rx'\n"); 586 587 ret = reset_control_bulk_deassert(RSPI_RESET_NUM, rspi->resets); 588 if (ret) 589 return dev_err_probe(dev, ret, "failed to deassert resets\n"); 590 591 init_waitqueue_head(&rspi->wait); 592 593 ret = devm_request_irq(dev, irq_rx, rzv2h_rx_irq_handler, 0, 594 dev_name(dev), rspi); 595 if (ret) { 596 dev_err(dev, "cannot request `rx` IRQ\n"); 597 goto quit_resets; 598 } 599 600 controller->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | 601 SPI_LSB_FIRST | SPI_LOOP; 602 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 603 controller->prepare_message = rzv2h_rspi_prepare_message; 604 controller->unprepare_message = rzv2h_rspi_unprepare_message; 605 controller->num_chipselect = 4; 606 controller->transfer_one = rzv2h_rspi_transfer_one; 607 608 tclk_rate = clk_round_rate(rspi->tclk, 0); 609 if (tclk_rate < 0) { 610 ret = tclk_rate; 611 goto quit_resets; 612 } 613 614 controller->min_speed_hz = rzv2h_rspi_calc_bitrate(tclk_rate, 615 RSPI_SPBR_SPR_MAX, 616 RSPI_SPCMD_BRDV_MAX); 617 618 tclk_rate = clk_round_rate(rspi->tclk, ULONG_MAX); 619 if (tclk_rate < 0) { 620 ret = tclk_rate; 621 goto quit_resets; 622 } 623 624 controller->max_speed_hz = rzv2h_rspi_calc_bitrate(tclk_rate, 625 RSPI_SPBR_SPR_MIN, 626 RSPI_SPCMD_BRDV_MIN); 627 628 device_set_node(&controller->dev, dev_fwnode(dev)); 629 630 ret = spi_register_controller(controller); 631 if (ret) { 632 dev_err(dev, "register controller failed\n"); 633 goto quit_resets; 634 } 635 636 return 0; 637 638 quit_resets: 639 reset_control_bulk_assert(RSPI_RESET_NUM, rspi->resets); 640 641 return ret; 642 } 643 644 static void rzv2h_rspi_remove(struct platform_device *pdev) 645 { 646 struct rzv2h_rspi_priv *rspi = platform_get_drvdata(pdev); 647 648 spi_unregister_controller(rspi->controller); 649 650 reset_control_bulk_assert(RSPI_RESET_NUM, rspi->resets); 651 } 652 653 static const struct rzv2h_rspi_info rzv2h_info = { 654 .find_tclk_rate = rzv2h_rspi_find_rate_fixed, 655 .tclk_name = "tclk", 656 .fifo_size = 16, 657 .num_clks = 3, 658 }; 659 660 static const struct rzv2h_rspi_info rzt2h_info = { 661 .find_tclk_rate = rzv2h_rspi_find_rate_variable, 662 .find_pclk_rate = rzv2h_rspi_find_rate_fixed, 663 .tclk_name = "pclkspi", 664 .fifo_size = 4, 665 .num_clks = 2, 666 }; 667 668 static const struct of_device_id rzv2h_rspi_match[] = { 669 { .compatible = "renesas,r9a09g057-rspi", &rzv2h_info }, 670 { .compatible = "renesas,r9a09g077-rspi", &rzt2h_info }, 671 { /* sentinel */ } 672 }; 673 MODULE_DEVICE_TABLE(of, rzv2h_rspi_match); 674 675 static struct platform_driver rzv2h_rspi_drv = { 676 .probe = rzv2h_rspi_probe, 677 .remove = rzv2h_rspi_remove, 678 .driver = { 679 .name = "rzv2h_rspi", 680 .of_match_table = rzv2h_rspi_match, 681 }, 682 }; 683 module_platform_driver(rzv2h_rspi_drv); 684 685 MODULE_LICENSE("GPL"); 686 MODULE_AUTHOR("Fabrizio Castro <fabrizio.castro.jz@renesas.com>"); 687 MODULE_DESCRIPTION("Renesas RZ/V2H(P) Serial Peripheral Interface Driver"); 688