1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Copyright (c) 2013-2014 Samsung Electronics Co., Ltd
4 // http://www.samsung.com
5 //
6 // Copyright (C) 2013 Google, Inc
7
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10 #include <linux/module.h>
11 #include <linux/i2c.h>
12 #include <linux/bcd.h>
13 #include <linux/regmap.h>
14 #include <linux/rtc.h>
15 #include <linux/platform_device.h>
16 #include <linux/mfd/samsung/core.h>
17 #include <linux/mfd/samsung/irq.h>
18 #include <linux/mfd/samsung/rtc.h>
19 #include <linux/mfd/samsung/s2mps14.h>
20
21 /*
22 * Maximum number of retries for checking changes in UDR field
23 * of S5M_RTC_UDR_CON register (to limit possible endless loop).
24 *
25 * After writing to RTC registers (setting time or alarm) read the UDR field
26 * in S5M_RTC_UDR_CON register. UDR is auto-cleared when data have
27 * been transferred.
28 */
29 #define UDR_READ_RETRY_CNT 5
30
31 enum {
32 RTC_SEC = 0,
33 RTC_MIN,
34 RTC_HOUR,
35 RTC_WEEKDAY,
36 RTC_DATE,
37 RTC_MONTH,
38 RTC_YEAR1,
39 RTC_YEAR2,
40 /* Make sure this is always the last enum name. */
41 RTC_MAX_NUM_TIME_REGS
42 };
43
44 /*
45 * Registers used by the driver which are different between chipsets.
46 *
47 * Operations like read time and write alarm/time require updating
48 * specific fields in UDR register. These fields usually are auto-cleared
49 * (with some exceptions).
50 *
51 * Table of operations per device:
52 *
53 * Device | Write time | Read time | Write alarm
54 * =================================================
55 * S5M8767 | UDR + TIME | | UDR
56 * S2MPS11/14 | WUDR | RUDR | WUDR + RUDR
57 * S2MPS13 | WUDR | RUDR | WUDR + AUDR
58 * S2MPS15 | WUDR | RUDR | AUDR
59 */
60 struct s5m_rtc_reg_config {
61 /* Number of registers used for setting time/alarm0/alarm1 */
62 unsigned int regs_count;
63 /* First register for time, seconds */
64 unsigned int time;
65 /* RTC control register */
66 unsigned int ctrl;
67 /* First register for alarm 0, seconds */
68 unsigned int alarm0;
69 /* First register for alarm 1, seconds */
70 unsigned int alarm1;
71 /*
72 * Register for update flag (UDR). Typically setting UDR field to 1
73 * will enable update of time or alarm register. Then it will be
74 * auto-cleared after successful update.
75 */
76 unsigned int udr_update;
77 /* Auto-cleared mask in UDR field for writing time and alarm */
78 unsigned int autoclear_udr_mask;
79 /*
80 * Masks in UDR field for time and alarm operations.
81 * The read time mask can be 0. Rest should not.
82 */
83 unsigned int read_time_udr_mask;
84 unsigned int write_time_udr_mask;
85 unsigned int write_alarm_udr_mask;
86 };
87
88 /* Register map for S5M8767 */
89 static const struct s5m_rtc_reg_config s5m_rtc_regs = {
90 .regs_count = 8,
91 .time = S5M_RTC_SEC,
92 .ctrl = S5M_ALARM1_CONF,
93 .alarm0 = S5M_ALARM0_SEC,
94 .alarm1 = S5M_ALARM1_SEC,
95 .udr_update = S5M_RTC_UDR_CON,
96 .autoclear_udr_mask = S5M_RTC_UDR_MASK,
97 .read_time_udr_mask = 0, /* Not needed */
98 .write_time_udr_mask = S5M_RTC_UDR_MASK | S5M_RTC_TIME_EN_MASK,
99 .write_alarm_udr_mask = S5M_RTC_UDR_MASK,
100 };
101
102 /* Register map for S2MPS13 */
103 static const struct s5m_rtc_reg_config s2mps13_rtc_regs = {
104 .regs_count = 7,
105 .time = S2MPS_RTC_SEC,
106 .ctrl = S2MPS_RTC_CTRL,
107 .alarm0 = S2MPS_ALARM0_SEC,
108 .alarm1 = S2MPS_ALARM1_SEC,
109 .udr_update = S2MPS_RTC_UDR_CON,
110 .autoclear_udr_mask = S2MPS_RTC_WUDR_MASK,
111 .read_time_udr_mask = S2MPS_RTC_RUDR_MASK,
112 .write_time_udr_mask = S2MPS_RTC_WUDR_MASK,
113 .write_alarm_udr_mask = S2MPS_RTC_WUDR_MASK | S2MPS13_RTC_AUDR_MASK,
114 };
115
116 /* Register map for S2MPS11/14 */
117 static const struct s5m_rtc_reg_config s2mps14_rtc_regs = {
118 .regs_count = 7,
119 .time = S2MPS_RTC_SEC,
120 .ctrl = S2MPS_RTC_CTRL,
121 .alarm0 = S2MPS_ALARM0_SEC,
122 .alarm1 = S2MPS_ALARM1_SEC,
123 .udr_update = S2MPS_RTC_UDR_CON,
124 .autoclear_udr_mask = S2MPS_RTC_WUDR_MASK,
125 .read_time_udr_mask = S2MPS_RTC_RUDR_MASK,
126 .write_time_udr_mask = S2MPS_RTC_WUDR_MASK,
127 .write_alarm_udr_mask = S2MPS_RTC_WUDR_MASK | S2MPS_RTC_RUDR_MASK,
128 };
129
130 /*
131 * Register map for S2MPS15 - in comparison to S2MPS14 the WUDR and AUDR bits
132 * are swapped.
133 */
134 static const struct s5m_rtc_reg_config s2mps15_rtc_regs = {
135 .regs_count = 7,
136 .time = S2MPS_RTC_SEC,
137 .ctrl = S2MPS_RTC_CTRL,
138 .alarm0 = S2MPS_ALARM0_SEC,
139 .alarm1 = S2MPS_ALARM1_SEC,
140 .udr_update = S2MPS_RTC_UDR_CON,
141 .autoclear_udr_mask = S2MPS_RTC_WUDR_MASK,
142 .read_time_udr_mask = S2MPS_RTC_RUDR_MASK,
143 .write_time_udr_mask = S2MPS15_RTC_WUDR_MASK,
144 .write_alarm_udr_mask = S2MPS15_RTC_AUDR_MASK,
145 };
146
147 struct s5m_rtc_info {
148 struct device *dev;
149 struct sec_pmic_dev *s5m87xx;
150 struct regmap *regmap;
151 struct rtc_device *rtc_dev;
152 int irq;
153 enum sec_device_type device_type;
154 int rtc_24hr_mode;
155 const struct s5m_rtc_reg_config *regs;
156 };
157
158 static const struct regmap_config s5m_rtc_regmap_config = {
159 .reg_bits = 8,
160 .val_bits = 8,
161
162 .max_register = S5M_RTC_REG_MAX,
163 };
164
165 static const struct regmap_config s2mps14_rtc_regmap_config = {
166 .reg_bits = 8,
167 .val_bits = 8,
168
169 .max_register = S2MPS_RTC_REG_MAX,
170 };
171
s5m8767_data_to_tm(u8 * data,struct rtc_time * tm,int rtc_24hr_mode)172 static void s5m8767_data_to_tm(u8 *data, struct rtc_time *tm,
173 int rtc_24hr_mode)
174 {
175 tm->tm_sec = data[RTC_SEC] & 0x7f;
176 tm->tm_min = data[RTC_MIN] & 0x7f;
177 if (rtc_24hr_mode) {
178 tm->tm_hour = data[RTC_HOUR] & 0x1f;
179 } else {
180 tm->tm_hour = data[RTC_HOUR] & 0x0f;
181 if (data[RTC_HOUR] & HOUR_PM_MASK)
182 tm->tm_hour += 12;
183 }
184
185 tm->tm_wday = ffs(data[RTC_WEEKDAY] & 0x7f);
186 tm->tm_mday = data[RTC_DATE] & 0x1f;
187 tm->tm_mon = (data[RTC_MONTH] & 0x0f) - 1;
188 tm->tm_year = (data[RTC_YEAR1] & 0x7f) + 100;
189 tm->tm_yday = 0;
190 tm->tm_isdst = 0;
191 }
192
s5m8767_tm_to_data(struct rtc_time * tm,u8 * data)193 static int s5m8767_tm_to_data(struct rtc_time *tm, u8 *data)
194 {
195 data[RTC_SEC] = tm->tm_sec;
196 data[RTC_MIN] = tm->tm_min;
197
198 if (tm->tm_hour >= 12)
199 data[RTC_HOUR] = tm->tm_hour | HOUR_PM_MASK;
200 else
201 data[RTC_HOUR] = tm->tm_hour & ~HOUR_PM_MASK;
202
203 data[RTC_WEEKDAY] = 1 << tm->tm_wday;
204 data[RTC_DATE] = tm->tm_mday;
205 data[RTC_MONTH] = tm->tm_mon + 1;
206 data[RTC_YEAR1] = tm->tm_year - 100;
207
208 return 0;
209 }
210
211 /*
212 * Read RTC_UDR_CON register and wait till UDR field is cleared.
213 * This indicates that time/alarm update ended.
214 */
s5m8767_wait_for_udr_update(struct s5m_rtc_info * info)215 static int s5m8767_wait_for_udr_update(struct s5m_rtc_info *info)
216 {
217 int ret, retry = UDR_READ_RETRY_CNT;
218 unsigned int data;
219
220 do {
221 ret = regmap_read(info->regmap, info->regs->udr_update, &data);
222 } while (--retry && (data & info->regs->autoclear_udr_mask) && !ret);
223
224 if (!retry)
225 dev_err(info->dev, "waiting for UDR update, reached max number of retries\n");
226
227 return ret;
228 }
229
s5m_check_peding_alarm_interrupt(struct s5m_rtc_info * info,struct rtc_wkalrm * alarm)230 static int s5m_check_peding_alarm_interrupt(struct s5m_rtc_info *info,
231 struct rtc_wkalrm *alarm)
232 {
233 int ret;
234 unsigned int val;
235
236 switch (info->device_type) {
237 case S5M8767X:
238 ret = regmap_read(info->regmap, S5M_RTC_STATUS, &val);
239 val &= S5M_ALARM0_STATUS;
240 break;
241 case S2MPS15X:
242 case S2MPS14X:
243 case S2MPS13X:
244 ret = regmap_read(info->s5m87xx->regmap_pmic, S2MPS14_REG_ST2,
245 &val);
246 val &= S2MPS_ALARM0_STATUS;
247 break;
248 default:
249 return -EINVAL;
250 }
251 if (ret < 0)
252 return ret;
253
254 if (val)
255 alarm->pending = 1;
256 else
257 alarm->pending = 0;
258
259 return 0;
260 }
261
s5m8767_rtc_set_time_reg(struct s5m_rtc_info * info)262 static int s5m8767_rtc_set_time_reg(struct s5m_rtc_info *info)
263 {
264 int ret;
265 unsigned int data;
266
267 ret = regmap_read(info->regmap, info->regs->udr_update, &data);
268 if (ret < 0) {
269 dev_err(info->dev, "failed to read update reg(%d)\n", ret);
270 return ret;
271 }
272
273 data |= info->regs->write_time_udr_mask;
274
275 ret = regmap_write(info->regmap, info->regs->udr_update, data);
276 if (ret < 0) {
277 dev_err(info->dev, "failed to write update reg(%d)\n", ret);
278 return ret;
279 }
280
281 ret = s5m8767_wait_for_udr_update(info);
282
283 return ret;
284 }
285
s5m8767_rtc_set_alarm_reg(struct s5m_rtc_info * info)286 static int s5m8767_rtc_set_alarm_reg(struct s5m_rtc_info *info)
287 {
288 int ret;
289 unsigned int data;
290
291 ret = regmap_read(info->regmap, info->regs->udr_update, &data);
292 if (ret < 0) {
293 dev_err(info->dev, "%s: fail to read update reg(%d)\n",
294 __func__, ret);
295 return ret;
296 }
297
298 data |= info->regs->write_alarm_udr_mask;
299 switch (info->device_type) {
300 case S5M8767X:
301 data &= ~S5M_RTC_TIME_EN_MASK;
302 break;
303 case S2MPS15X:
304 case S2MPS14X:
305 case S2MPS13X:
306 /* No exceptions needed */
307 break;
308 default:
309 return -EINVAL;
310 }
311
312 ret = regmap_write(info->regmap, info->regs->udr_update, data);
313 if (ret < 0) {
314 dev_err(info->dev, "%s: fail to write update reg(%d)\n",
315 __func__, ret);
316 return ret;
317 }
318
319 ret = s5m8767_wait_for_udr_update(info);
320
321 /* On S2MPS13 the AUDR is not auto-cleared */
322 if (info->device_type == S2MPS13X)
323 regmap_update_bits(info->regmap, info->regs->udr_update,
324 S2MPS13_RTC_AUDR_MASK, 0);
325
326 return ret;
327 }
328
s5m_rtc_read_time(struct device * dev,struct rtc_time * tm)329 static int s5m_rtc_read_time(struct device *dev, struct rtc_time *tm)
330 {
331 struct s5m_rtc_info *info = dev_get_drvdata(dev);
332 u8 data[RTC_MAX_NUM_TIME_REGS];
333 int ret;
334
335 if (info->regs->read_time_udr_mask) {
336 ret = regmap_update_bits(info->regmap,
337 info->regs->udr_update,
338 info->regs->read_time_udr_mask,
339 info->regs->read_time_udr_mask);
340 if (ret) {
341 dev_err(dev,
342 "Failed to prepare registers for time reading: %d\n",
343 ret);
344 return ret;
345 }
346 }
347 ret = regmap_bulk_read(info->regmap, info->regs->time, data,
348 info->regs->regs_count);
349 if (ret < 0)
350 return ret;
351
352 switch (info->device_type) {
353 case S5M8767X:
354 case S2MPS15X:
355 case S2MPS14X:
356 case S2MPS13X:
357 s5m8767_data_to_tm(data, tm, info->rtc_24hr_mode);
358 break;
359
360 default:
361 return -EINVAL;
362 }
363
364 dev_dbg(dev, "%s: %ptR(%d)\n", __func__, tm, tm->tm_wday);
365
366 return 0;
367 }
368
s5m_rtc_set_time(struct device * dev,struct rtc_time * tm)369 static int s5m_rtc_set_time(struct device *dev, struct rtc_time *tm)
370 {
371 struct s5m_rtc_info *info = dev_get_drvdata(dev);
372 u8 data[RTC_MAX_NUM_TIME_REGS];
373 int ret = 0;
374
375 switch (info->device_type) {
376 case S5M8767X:
377 case S2MPS15X:
378 case S2MPS14X:
379 case S2MPS13X:
380 ret = s5m8767_tm_to_data(tm, data);
381 break;
382 default:
383 return -EINVAL;
384 }
385
386 if (ret < 0)
387 return ret;
388
389 dev_dbg(dev, "%s: %ptR(%d)\n", __func__, tm, tm->tm_wday);
390
391 ret = regmap_raw_write(info->regmap, info->regs->time, data,
392 info->regs->regs_count);
393 if (ret < 0)
394 return ret;
395
396 ret = s5m8767_rtc_set_time_reg(info);
397
398 return ret;
399 }
400
s5m_rtc_read_alarm(struct device * dev,struct rtc_wkalrm * alrm)401 static int s5m_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
402 {
403 struct s5m_rtc_info *info = dev_get_drvdata(dev);
404 u8 data[RTC_MAX_NUM_TIME_REGS];
405 int ret, i;
406
407 ret = regmap_bulk_read(info->regmap, info->regs->alarm0, data,
408 info->regs->regs_count);
409 if (ret < 0)
410 return ret;
411
412 switch (info->device_type) {
413 case S5M8767X:
414 case S2MPS15X:
415 case S2MPS14X:
416 case S2MPS13X:
417 s5m8767_data_to_tm(data, &alrm->time, info->rtc_24hr_mode);
418 alrm->enabled = 0;
419 for (i = 0; i < info->regs->regs_count; i++) {
420 if (data[i] & ALARM_ENABLE_MASK) {
421 alrm->enabled = 1;
422 break;
423 }
424 }
425 break;
426
427 default:
428 return -EINVAL;
429 }
430
431 dev_dbg(dev, "%s: %ptR(%d)\n", __func__, &alrm->time, alrm->time.tm_wday);
432
433 return s5m_check_peding_alarm_interrupt(info, alrm);
434 }
435
s5m_rtc_stop_alarm(struct s5m_rtc_info * info)436 static int s5m_rtc_stop_alarm(struct s5m_rtc_info *info)
437 {
438 u8 data[RTC_MAX_NUM_TIME_REGS];
439 int ret, i;
440 struct rtc_time tm;
441
442 ret = regmap_bulk_read(info->regmap, info->regs->alarm0, data,
443 info->regs->regs_count);
444 if (ret < 0)
445 return ret;
446
447 s5m8767_data_to_tm(data, &tm, info->rtc_24hr_mode);
448 dev_dbg(info->dev, "%s: %ptR(%d)\n", __func__, &tm, tm.tm_wday);
449
450 switch (info->device_type) {
451 case S5M8767X:
452 case S2MPS15X:
453 case S2MPS14X:
454 case S2MPS13X:
455 for (i = 0; i < info->regs->regs_count; i++)
456 data[i] &= ~ALARM_ENABLE_MASK;
457
458 ret = regmap_raw_write(info->regmap, info->regs->alarm0, data,
459 info->regs->regs_count);
460 if (ret < 0)
461 return ret;
462
463 ret = s5m8767_rtc_set_alarm_reg(info);
464
465 break;
466
467 default:
468 return -EINVAL;
469 }
470
471 return ret;
472 }
473
s5m_rtc_start_alarm(struct s5m_rtc_info * info)474 static int s5m_rtc_start_alarm(struct s5m_rtc_info *info)
475 {
476 int ret;
477 u8 data[RTC_MAX_NUM_TIME_REGS];
478 struct rtc_time tm;
479
480 ret = regmap_bulk_read(info->regmap, info->regs->alarm0, data,
481 info->regs->regs_count);
482 if (ret < 0)
483 return ret;
484
485 s5m8767_data_to_tm(data, &tm, info->rtc_24hr_mode);
486 dev_dbg(info->dev, "%s: %ptR(%d)\n", __func__, &tm, tm.tm_wday);
487
488 switch (info->device_type) {
489 case S5M8767X:
490 case S2MPS15X:
491 case S2MPS14X:
492 case S2MPS13X:
493 data[RTC_SEC] |= ALARM_ENABLE_MASK;
494 data[RTC_MIN] |= ALARM_ENABLE_MASK;
495 data[RTC_HOUR] |= ALARM_ENABLE_MASK;
496 data[RTC_WEEKDAY] &= ~ALARM_ENABLE_MASK;
497 if (data[RTC_DATE] & 0x1f)
498 data[RTC_DATE] |= ALARM_ENABLE_MASK;
499 if (data[RTC_MONTH] & 0xf)
500 data[RTC_MONTH] |= ALARM_ENABLE_MASK;
501 if (data[RTC_YEAR1] & 0x7f)
502 data[RTC_YEAR1] |= ALARM_ENABLE_MASK;
503
504 ret = regmap_raw_write(info->regmap, info->regs->alarm0, data,
505 info->regs->regs_count);
506 if (ret < 0)
507 return ret;
508 ret = s5m8767_rtc_set_alarm_reg(info);
509
510 break;
511
512 default:
513 return -EINVAL;
514 }
515
516 return ret;
517 }
518
s5m_rtc_set_alarm(struct device * dev,struct rtc_wkalrm * alrm)519 static int s5m_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
520 {
521 struct s5m_rtc_info *info = dev_get_drvdata(dev);
522 u8 data[RTC_MAX_NUM_TIME_REGS];
523 int ret;
524
525 switch (info->device_type) {
526 case S5M8767X:
527 case S2MPS15X:
528 case S2MPS14X:
529 case S2MPS13X:
530 s5m8767_tm_to_data(&alrm->time, data);
531 break;
532
533 default:
534 return -EINVAL;
535 }
536
537 dev_dbg(dev, "%s: %ptR(%d)\n", __func__, &alrm->time, alrm->time.tm_wday);
538
539 ret = s5m_rtc_stop_alarm(info);
540 if (ret < 0)
541 return ret;
542
543 ret = regmap_raw_write(info->regmap, info->regs->alarm0, data,
544 info->regs->regs_count);
545 if (ret < 0)
546 return ret;
547
548 ret = s5m8767_rtc_set_alarm_reg(info);
549 if (ret < 0)
550 return ret;
551
552 if (alrm->enabled)
553 ret = s5m_rtc_start_alarm(info);
554
555 return ret;
556 }
557
s5m_rtc_alarm_irq_enable(struct device * dev,unsigned int enabled)558 static int s5m_rtc_alarm_irq_enable(struct device *dev,
559 unsigned int enabled)
560 {
561 struct s5m_rtc_info *info = dev_get_drvdata(dev);
562
563 if (enabled)
564 return s5m_rtc_start_alarm(info);
565 else
566 return s5m_rtc_stop_alarm(info);
567 }
568
s5m_rtc_alarm_irq(int irq,void * data)569 static irqreturn_t s5m_rtc_alarm_irq(int irq, void *data)
570 {
571 struct s5m_rtc_info *info = data;
572
573 rtc_update_irq(info->rtc_dev, 1, RTC_IRQF | RTC_AF);
574
575 return IRQ_HANDLED;
576 }
577
578 static const struct rtc_class_ops s5m_rtc_ops = {
579 .read_time = s5m_rtc_read_time,
580 .set_time = s5m_rtc_set_time,
581 .read_alarm = s5m_rtc_read_alarm,
582 .set_alarm = s5m_rtc_set_alarm,
583 .alarm_irq_enable = s5m_rtc_alarm_irq_enable,
584 };
585
s5m8767_rtc_init_reg(struct s5m_rtc_info * info)586 static int s5m8767_rtc_init_reg(struct s5m_rtc_info *info)
587 {
588 u8 data[2];
589 int ret;
590
591 switch (info->device_type) {
592 case S5M8767X:
593 /* UDR update time. Default of 7.32 ms is too long. */
594 ret = regmap_update_bits(info->regmap, S5M_RTC_UDR_CON,
595 S5M_RTC_UDR_T_MASK, S5M_RTC_UDR_T_450_US);
596 if (ret < 0)
597 dev_err(info->dev, "%s: fail to change UDR time: %d\n",
598 __func__, ret);
599
600 /* Set RTC control register : Binary mode, 24hour mode */
601 data[0] = (1 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
602 data[1] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
603
604 ret = regmap_raw_write(info->regmap, S5M_ALARM0_CONF, data, 2);
605 break;
606
607 case S2MPS15X:
608 case S2MPS14X:
609 case S2MPS13X:
610 data[0] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
611 ret = regmap_write(info->regmap, info->regs->ctrl, data[0]);
612 if (ret < 0)
613 break;
614
615 /*
616 * Should set WUDR & (RUDR or AUDR) bits to high after writing
617 * RTC_CTRL register like writing Alarm registers. We can't find
618 * the description from datasheet but vendor code does that
619 * really.
620 */
621 ret = s5m8767_rtc_set_alarm_reg(info);
622 break;
623
624 default:
625 return -EINVAL;
626 }
627
628 info->rtc_24hr_mode = 1;
629 if (ret < 0)
630 return dev_err_probe(info->dev, ret,
631 "%s: fail to write controlm reg\n",
632 __func__);
633
634 return ret;
635 }
636
s5m_rtc_probe(struct platform_device * pdev)637 static int s5m_rtc_probe(struct platform_device *pdev)
638 {
639 struct sec_pmic_dev *s5m87xx = dev_get_drvdata(pdev->dev.parent);
640 struct s5m_rtc_info *info;
641 struct i2c_client *i2c;
642 const struct regmap_config *regmap_cfg;
643 int ret, alarm_irq;
644
645 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
646 if (!info)
647 return -ENOMEM;
648
649 switch (platform_get_device_id(pdev)->driver_data) {
650 case S2MPS15X:
651 regmap_cfg = &s2mps14_rtc_regmap_config;
652 info->regs = &s2mps15_rtc_regs;
653 alarm_irq = S2MPS14_IRQ_RTCA0;
654 break;
655 case S2MPS14X:
656 regmap_cfg = &s2mps14_rtc_regmap_config;
657 info->regs = &s2mps14_rtc_regs;
658 alarm_irq = S2MPS14_IRQ_RTCA0;
659 break;
660 case S2MPS13X:
661 regmap_cfg = &s2mps14_rtc_regmap_config;
662 info->regs = &s2mps13_rtc_regs;
663 alarm_irq = S2MPS14_IRQ_RTCA0;
664 break;
665 case S5M8767X:
666 regmap_cfg = &s5m_rtc_regmap_config;
667 info->regs = &s5m_rtc_regs;
668 alarm_irq = S5M8767_IRQ_RTCA1;
669 break;
670 default:
671 return dev_err_probe(&pdev->dev, -ENODEV,
672 "Device type %lu is not supported by RTC driver\n",
673 platform_get_device_id(pdev)->driver_data);
674 }
675
676 i2c = devm_i2c_new_dummy_device(&pdev->dev, s5m87xx->i2c->adapter,
677 RTC_I2C_ADDR);
678 if (IS_ERR(i2c))
679 return dev_err_probe(&pdev->dev, PTR_ERR(i2c),
680 "Failed to allocate I2C for RTC\n");
681
682 info->regmap = devm_regmap_init_i2c(i2c, regmap_cfg);
683 if (IS_ERR(info->regmap))
684 return dev_err_probe(&pdev->dev, PTR_ERR(info->regmap),
685 "Failed to allocate RTC register map\n");
686
687 info->dev = &pdev->dev;
688 info->s5m87xx = s5m87xx;
689 info->device_type = platform_get_device_id(pdev)->driver_data;
690
691 if (s5m87xx->irq_data) {
692 info->irq = regmap_irq_get_virq(s5m87xx->irq_data, alarm_irq);
693 if (info->irq <= 0)
694 return dev_err_probe(&pdev->dev, -EINVAL,
695 "Failed to get virtual IRQ %d\n",
696 alarm_irq);
697 }
698
699 platform_set_drvdata(pdev, info);
700
701 ret = s5m8767_rtc_init_reg(info);
702 if (ret)
703 return ret;
704
705 info->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
706 if (IS_ERR(info->rtc_dev))
707 return PTR_ERR(info->rtc_dev);
708
709 info->rtc_dev->ops = &s5m_rtc_ops;
710
711 info->rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_2000;
712 info->rtc_dev->range_max = RTC_TIMESTAMP_END_2099;
713
714 if (!info->irq) {
715 clear_bit(RTC_FEATURE_ALARM, info->rtc_dev->features);
716 } else {
717 ret = devm_request_threaded_irq(&pdev->dev, info->irq, NULL,
718 s5m_rtc_alarm_irq, 0, "rtc-alarm0",
719 info);
720 if (ret < 0)
721 return dev_err_probe(&pdev->dev, ret,
722 "Failed to request alarm IRQ %d\n",
723 info->irq);
724 device_init_wakeup(&pdev->dev, true);
725 }
726
727 return devm_rtc_register_device(info->rtc_dev);
728 }
729
730 #ifdef CONFIG_PM_SLEEP
s5m_rtc_resume(struct device * dev)731 static int s5m_rtc_resume(struct device *dev)
732 {
733 struct s5m_rtc_info *info = dev_get_drvdata(dev);
734 int ret = 0;
735
736 if (info->irq && device_may_wakeup(dev))
737 ret = disable_irq_wake(info->irq);
738
739 return ret;
740 }
741
s5m_rtc_suspend(struct device * dev)742 static int s5m_rtc_suspend(struct device *dev)
743 {
744 struct s5m_rtc_info *info = dev_get_drvdata(dev);
745 int ret = 0;
746
747 if (info->irq && device_may_wakeup(dev))
748 ret = enable_irq_wake(info->irq);
749
750 return ret;
751 }
752 #endif /* CONFIG_PM_SLEEP */
753
754 static SIMPLE_DEV_PM_OPS(s5m_rtc_pm_ops, s5m_rtc_suspend, s5m_rtc_resume);
755
756 static const struct platform_device_id s5m_rtc_id[] = {
757 { "s5m-rtc", S5M8767X },
758 { "s2mps13-rtc", S2MPS13X },
759 { "s2mps14-rtc", S2MPS14X },
760 { "s2mps15-rtc", S2MPS15X },
761 { },
762 };
763 MODULE_DEVICE_TABLE(platform, s5m_rtc_id);
764
765 static struct platform_driver s5m_rtc_driver = {
766 .driver = {
767 .name = "s5m-rtc",
768 .pm = &s5m_rtc_pm_ops,
769 },
770 .probe = s5m_rtc_probe,
771 .id_table = s5m_rtc_id,
772 };
773
774 module_platform_driver(s5m_rtc_driver);
775
776 /* Module information */
777 MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>");
778 MODULE_DESCRIPTION("Samsung S5M/S2MPS14 RTC driver");
779 MODULE_LICENSE("GPL");
780