1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * pm8xxx RTC driver
4 *
5 * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
6 * Copyright (c) 2023, Linaro Limited
7 */
8 #include <linux/efi.h>
9 #include <linux/of.h>
10 #include <linux/module.h>
11 #include <linux/nvmem-consumer.h>
12 #include <linux/init.h>
13 #include <linux/rtc.h>
14 #include <linux/platform_device.h>
15 #include <linux/pm.h>
16 #include <linux/pm_wakeirq.h>
17 #include <linux/regmap.h>
18 #include <linux/slab.h>
19 #include <linux/spinlock.h>
20 #include <linux/unaligned.h>
21
22 #include <asm/byteorder.h>
23
24 /* RTC_CTRL register bit fields */
25 #define PM8xxx_RTC_ENABLE BIT(7)
26 #define PM8xxx_RTC_ALARM_CLEAR BIT(0)
27 #define PM8xxx_RTC_ALARM_ENABLE BIT(7)
28
29 #define NUM_8_BIT_RTC_REGS 0x4
30
31 /**
32 * struct pm8xxx_rtc_regs - describe RTC registers per PMIC versions
33 * @ctrl: address of control register
34 * @write: base address of write registers
35 * @read: base address of read registers
36 * @alarm_ctrl: address of alarm control register
37 * @alarm_ctrl2: address of alarm control2 register
38 * @alarm_rw: base address of alarm read-write registers
39 * @alarm_en: alarm enable mask
40 */
41 struct pm8xxx_rtc_regs {
42 unsigned int ctrl;
43 unsigned int write;
44 unsigned int read;
45 unsigned int alarm_ctrl;
46 unsigned int alarm_ctrl2;
47 unsigned int alarm_rw;
48 unsigned int alarm_en;
49 };
50
51 struct qcom_uefi_rtc_info {
52 __le32 offset_gps;
53 u8 reserved[8];
54 } __packed;
55
56 /**
57 * struct pm8xxx_rtc - RTC driver internal structure
58 * @rtc: RTC device
59 * @regmap: regmap used to access registers
60 * @allow_set_time: whether the time can be set
61 * @use_uefi: use UEFI variable as fallback for offset
62 * @alarm_irq: alarm irq number
63 * @regs: register description
64 * @dev: device structure
65 * @rtc_info: qcom uefi rtc-info structure
66 * @nvmem_cell: nvmem cell for offset
67 * @offset: offset from epoch in seconds
68 * @offset_dirty: offset needs to be stored on shutdown
69 */
70 struct pm8xxx_rtc {
71 struct rtc_device *rtc;
72 struct regmap *regmap;
73 bool allow_set_time;
74 bool use_uefi;
75 int alarm_irq;
76 const struct pm8xxx_rtc_regs *regs;
77 struct device *dev;
78 struct qcom_uefi_rtc_info rtc_info;
79 struct nvmem_cell *nvmem_cell;
80 u32 offset;
81 bool offset_dirty;
82 };
83
84 #ifdef CONFIG_EFI
85
86 MODULE_IMPORT_NS("EFIVAR");
87
88 #define QCOM_UEFI_NAME L"RTCInfo"
89 #define QCOM_UEFI_GUID EFI_GUID(0x882f8c2b, 0x9646, 0x435f, \
90 0x8d, 0xe5, 0xf2, 0x08, 0xff, 0x80, 0xc1, 0xbd)
91 #define QCOM_UEFI_ATTRS (EFI_VARIABLE_NON_VOLATILE | \
92 EFI_VARIABLE_BOOTSERVICE_ACCESS | \
93 EFI_VARIABLE_RUNTIME_ACCESS)
94
pm8xxx_rtc_read_uefi_offset(struct pm8xxx_rtc * rtc_dd)95 static int pm8xxx_rtc_read_uefi_offset(struct pm8xxx_rtc *rtc_dd)
96 {
97 struct qcom_uefi_rtc_info *rtc_info = &rtc_dd->rtc_info;
98 unsigned long size = sizeof(*rtc_info);
99 struct device *dev = rtc_dd->dev;
100 efi_status_t status;
101 u32 offset_gps;
102 int rc;
103
104 rc = efivar_lock();
105 if (rc)
106 return rc;
107
108 status = efivar_get_variable(QCOM_UEFI_NAME, &QCOM_UEFI_GUID, NULL,
109 &size, rtc_info);
110 efivar_unlock();
111
112 if (status != EFI_SUCCESS) {
113 dev_dbg(dev, "failed to read UEFI offset: %lu\n", status);
114 return efi_status_to_err(status);
115 }
116
117 if (size != sizeof(*rtc_info)) {
118 dev_dbg(dev, "unexpected UEFI structure size %lu\n", size);
119 return -EINVAL;
120 }
121
122 dev_dbg(dev, "uefi_rtc_info = %*ph\n", (int)size, rtc_info);
123
124 /* Convert from GPS to Unix time offset */
125 offset_gps = le32_to_cpu(rtc_info->offset_gps);
126 rtc_dd->offset = offset_gps + (u32)RTC_TIMESTAMP_EPOCH_GPS;
127
128 return 0;
129 }
130
pm8xxx_rtc_write_uefi_offset(struct pm8xxx_rtc * rtc_dd,u32 offset)131 static int pm8xxx_rtc_write_uefi_offset(struct pm8xxx_rtc *rtc_dd, u32 offset)
132 {
133 struct qcom_uefi_rtc_info *rtc_info = &rtc_dd->rtc_info;
134 unsigned long size = sizeof(*rtc_info);
135 struct device *dev = rtc_dd->dev;
136 efi_status_t status;
137 u32 offset_gps;
138
139 /* Convert from Unix to GPS time offset */
140 offset_gps = offset - (u32)RTC_TIMESTAMP_EPOCH_GPS;
141
142 rtc_info->offset_gps = cpu_to_le32(offset_gps);
143
144 dev_dbg(dev, "efi_rtc_info = %*ph\n", (int)size, rtc_info);
145
146 status = efivar_set_variable(QCOM_UEFI_NAME, &QCOM_UEFI_GUID,
147 QCOM_UEFI_ATTRS, size, rtc_info);
148 if (status != EFI_SUCCESS) {
149 dev_dbg(dev, "failed to write UEFI offset: %lx\n", status);
150 return efi_status_to_err(status);
151 }
152
153 return 0;
154 }
155
156 #else /* CONFIG_EFI */
157
pm8xxx_rtc_read_uefi_offset(struct pm8xxx_rtc * rtc_dd)158 static int pm8xxx_rtc_read_uefi_offset(struct pm8xxx_rtc *rtc_dd)
159 {
160 return -ENODEV;
161 }
162
pm8xxx_rtc_write_uefi_offset(struct pm8xxx_rtc * rtc_dd,u32 offset)163 static int pm8xxx_rtc_write_uefi_offset(struct pm8xxx_rtc *rtc_dd, u32 offset)
164 {
165 return -ENODEV;
166 }
167
168 #endif /* CONFIG_EFI */
169
pm8xxx_rtc_read_nvmem_offset(struct pm8xxx_rtc * rtc_dd)170 static int pm8xxx_rtc_read_nvmem_offset(struct pm8xxx_rtc *rtc_dd)
171 {
172 size_t len;
173 void *buf;
174 int rc;
175
176 buf = nvmem_cell_read(rtc_dd->nvmem_cell, &len);
177 if (IS_ERR(buf)) {
178 rc = PTR_ERR(buf);
179 dev_dbg(rtc_dd->dev, "failed to read nvmem offset: %d\n", rc);
180 return rc;
181 }
182
183 if (len != sizeof(u32)) {
184 dev_dbg(rtc_dd->dev, "unexpected nvmem cell size %zu\n", len);
185 kfree(buf);
186 return -EINVAL;
187 }
188
189 rtc_dd->offset = get_unaligned_le32(buf);
190
191 kfree(buf);
192
193 return 0;
194 }
195
pm8xxx_rtc_write_nvmem_offset(struct pm8xxx_rtc * rtc_dd,u32 offset)196 static int pm8xxx_rtc_write_nvmem_offset(struct pm8xxx_rtc *rtc_dd, u32 offset)
197 {
198 u8 buf[sizeof(u32)];
199 int rc;
200
201 put_unaligned_le32(offset, buf);
202
203 rc = nvmem_cell_write(rtc_dd->nvmem_cell, buf, sizeof(buf));
204 if (rc < 0) {
205 dev_dbg(rtc_dd->dev, "failed to write nvmem offset: %d\n", rc);
206 return rc;
207 }
208
209 return 0;
210 }
211
pm8xxx_rtc_read_raw(struct pm8xxx_rtc * rtc_dd,u32 * secs)212 static int pm8xxx_rtc_read_raw(struct pm8xxx_rtc *rtc_dd, u32 *secs)
213 {
214 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
215 u8 value[NUM_8_BIT_RTC_REGS];
216 unsigned int reg;
217 int rc;
218
219 rc = regmap_bulk_read(rtc_dd->regmap, regs->read, value, sizeof(value));
220 if (rc)
221 return rc;
222
223 /*
224 * Read the LSB again and check if there has been a carry over.
225 * If there has, redo the read operation.
226 */
227 rc = regmap_read(rtc_dd->regmap, regs->read, ®);
228 if (rc < 0)
229 return rc;
230
231 if (reg < value[0]) {
232 rc = regmap_bulk_read(rtc_dd->regmap, regs->read, value,
233 sizeof(value));
234 if (rc)
235 return rc;
236 }
237
238 *secs = get_unaligned_le32(value);
239
240 return 0;
241 }
242
pm8xxx_rtc_update_offset(struct pm8xxx_rtc * rtc_dd,u32 secs)243 static int pm8xxx_rtc_update_offset(struct pm8xxx_rtc *rtc_dd, u32 secs)
244 {
245 u32 raw_secs;
246 u32 offset;
247 int rc;
248
249 if (!rtc_dd->nvmem_cell && !rtc_dd->use_uefi)
250 return -ENODEV;
251
252 rc = pm8xxx_rtc_read_raw(rtc_dd, &raw_secs);
253 if (rc)
254 return rc;
255
256 offset = secs - raw_secs;
257
258 if (offset == rtc_dd->offset)
259 return 0;
260
261 /*
262 * Reduce flash wear by deferring updates due to clock drift until
263 * shutdown.
264 */
265 if (abs_diff(offset, rtc_dd->offset) < 30) {
266 rtc_dd->offset_dirty = true;
267 goto out;
268 }
269
270 if (rtc_dd->nvmem_cell)
271 rc = pm8xxx_rtc_write_nvmem_offset(rtc_dd, offset);
272 else
273 rc = pm8xxx_rtc_write_uefi_offset(rtc_dd, offset);
274
275 if (rc)
276 return rc;
277
278 rtc_dd->offset_dirty = false;
279 out:
280 rtc_dd->offset = offset;
281
282 return 0;
283 }
284
285 /*
286 * Steps to write the RTC registers.
287 * 1. Disable alarm if enabled.
288 * 2. Disable rtc if enabled.
289 * 3. Write 0x00 to LSB.
290 * 4. Write Byte[1], Byte[2], Byte[3] then Byte[0].
291 * 5. Enable rtc if disabled in step 2.
292 * 6. Enable alarm if disabled in step 1.
293 */
__pm8xxx_rtc_set_time(struct pm8xxx_rtc * rtc_dd,u32 secs)294 static int __pm8xxx_rtc_set_time(struct pm8xxx_rtc *rtc_dd, u32 secs)
295 {
296 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
297 u8 value[NUM_8_BIT_RTC_REGS];
298 bool alarm_enabled;
299 int rc;
300
301 put_unaligned_le32(secs, value);
302
303 rc = regmap_update_bits_check(rtc_dd->regmap, regs->alarm_ctrl,
304 regs->alarm_en, 0, &alarm_enabled);
305 if (rc)
306 return rc;
307
308 /* Disable RTC */
309 rc = regmap_update_bits(rtc_dd->regmap, regs->ctrl, PM8xxx_RTC_ENABLE, 0);
310 if (rc)
311 return rc;
312
313 /* Write 0 to Byte[0] */
314 rc = regmap_write(rtc_dd->regmap, regs->write, 0);
315 if (rc)
316 return rc;
317
318 /* Write Byte[1], Byte[2], Byte[3] */
319 rc = regmap_bulk_write(rtc_dd->regmap, regs->write + 1,
320 &value[1], sizeof(value) - 1);
321 if (rc)
322 return rc;
323
324 /* Write Byte[0] */
325 rc = regmap_write(rtc_dd->regmap, regs->write, value[0]);
326 if (rc)
327 return rc;
328
329 /* Enable RTC */
330 rc = regmap_update_bits(rtc_dd->regmap, regs->ctrl, PM8xxx_RTC_ENABLE,
331 PM8xxx_RTC_ENABLE);
332 if (rc)
333 return rc;
334
335 if (alarm_enabled) {
336 rc = regmap_update_bits(rtc_dd->regmap, regs->alarm_ctrl,
337 regs->alarm_en, regs->alarm_en);
338 if (rc)
339 return rc;
340 }
341
342 return 0;
343 }
344
pm8xxx_rtc_set_time(struct device * dev,struct rtc_time * tm)345 static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
346 {
347 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
348 u32 secs;
349 int rc;
350
351 secs = rtc_tm_to_time64(tm);
352
353 if (rtc_dd->allow_set_time)
354 rc = __pm8xxx_rtc_set_time(rtc_dd, secs);
355 else
356 rc = pm8xxx_rtc_update_offset(rtc_dd, secs);
357
358 if (rc)
359 return rc;
360
361 dev_dbg(dev, "set time: %ptRd %ptRt (%u + %u)\n", tm, tm,
362 secs - rtc_dd->offset, rtc_dd->offset);
363 return 0;
364 }
365
pm8xxx_rtc_read_time(struct device * dev,struct rtc_time * tm)366 static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
367 {
368 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
369 u32 secs;
370 int rc;
371
372 rc = pm8xxx_rtc_read_raw(rtc_dd, &secs);
373 if (rc)
374 return rc;
375
376 secs += rtc_dd->offset;
377 rtc_time64_to_tm(secs, tm);
378
379 dev_dbg(dev, "read time: %ptRd %ptRt (%u + %u)\n", tm, tm,
380 secs - rtc_dd->offset, rtc_dd->offset);
381 return 0;
382 }
383
pm8xxx_rtc_set_alarm(struct device * dev,struct rtc_wkalrm * alarm)384 static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
385 {
386 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
387 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
388 u8 value[NUM_8_BIT_RTC_REGS];
389 u32 secs;
390 int rc;
391
392 secs = rtc_tm_to_time64(&alarm->time);
393 secs -= rtc_dd->offset;
394 put_unaligned_le32(secs, value);
395
396 rc = regmap_update_bits(rtc_dd->regmap, regs->alarm_ctrl,
397 regs->alarm_en, 0);
398 if (rc)
399 return rc;
400
401 rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
402 sizeof(value));
403 if (rc)
404 return rc;
405
406 if (alarm->enabled) {
407 rc = regmap_update_bits(rtc_dd->regmap, regs->alarm_ctrl,
408 regs->alarm_en, regs->alarm_en);
409 if (rc)
410 return rc;
411 }
412
413 dev_dbg(dev, "set alarm: %ptRd %ptRt\n", &alarm->time, &alarm->time);
414
415 return 0;
416 }
417
pm8xxx_rtc_read_alarm(struct device * dev,struct rtc_wkalrm * alarm)418 static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
419 {
420 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
421 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
422 u8 value[NUM_8_BIT_RTC_REGS];
423 unsigned int ctrl_reg;
424 u32 secs;
425 int rc;
426
427 rc = regmap_bulk_read(rtc_dd->regmap, regs->alarm_rw, value,
428 sizeof(value));
429 if (rc)
430 return rc;
431
432 secs = get_unaligned_le32(value);
433 secs += rtc_dd->offset;
434 rtc_time64_to_tm(secs, &alarm->time);
435
436 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
437 if (rc)
438 return rc;
439
440 alarm->enabled = !!(ctrl_reg & PM8xxx_RTC_ALARM_ENABLE);
441
442 dev_dbg(dev, "read alarm: %ptRd %ptRt\n", &alarm->time, &alarm->time);
443
444 return 0;
445 }
446
pm8xxx_rtc_alarm_irq_enable(struct device * dev,unsigned int enable)447 static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
448 {
449 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
450 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
451 u8 value[NUM_8_BIT_RTC_REGS] = {0};
452 unsigned int val;
453 int rc;
454
455 if (enable)
456 val = regs->alarm_en;
457 else
458 val = 0;
459
460 rc = regmap_update_bits(rtc_dd->regmap, regs->alarm_ctrl,
461 regs->alarm_en, val);
462 if (rc)
463 return rc;
464
465 /* Clear alarm register */
466 if (!enable) {
467 rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
468 sizeof(value));
469 if (rc)
470 return rc;
471 }
472
473 return 0;
474 }
475
476 static const struct rtc_class_ops pm8xxx_rtc_ops = {
477 .read_time = pm8xxx_rtc_read_time,
478 .set_time = pm8xxx_rtc_set_time,
479 .set_alarm = pm8xxx_rtc_set_alarm,
480 .read_alarm = pm8xxx_rtc_read_alarm,
481 .alarm_irq_enable = pm8xxx_rtc_alarm_irq_enable,
482 };
483
pm8xxx_alarm_trigger(int irq,void * dev_id)484 static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id)
485 {
486 struct pm8xxx_rtc *rtc_dd = dev_id;
487 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
488 int rc;
489
490 rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC_AF);
491
492 /* Disable alarm */
493 rc = regmap_update_bits(rtc_dd->regmap, regs->alarm_ctrl,
494 regs->alarm_en, 0);
495 if (rc)
496 return IRQ_NONE;
497
498 /* Clear alarm status */
499 rc = regmap_update_bits(rtc_dd->regmap, regs->alarm_ctrl2,
500 PM8xxx_RTC_ALARM_CLEAR, 0);
501 if (rc)
502 return IRQ_NONE;
503
504 return IRQ_HANDLED;
505 }
506
pm8xxx_rtc_enable(struct pm8xxx_rtc * rtc_dd)507 static int pm8xxx_rtc_enable(struct pm8xxx_rtc *rtc_dd)
508 {
509 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
510
511 return regmap_update_bits(rtc_dd->regmap, regs->ctrl, PM8xxx_RTC_ENABLE,
512 PM8xxx_RTC_ENABLE);
513 }
514
515 static const struct pm8xxx_rtc_regs pm8921_regs = {
516 .ctrl = 0x11d,
517 .write = 0x11f,
518 .read = 0x123,
519 .alarm_rw = 0x127,
520 .alarm_ctrl = 0x11d,
521 .alarm_ctrl2 = 0x11e,
522 .alarm_en = BIT(1),
523 };
524
525 static const struct pm8xxx_rtc_regs pm8058_regs = {
526 .ctrl = 0x1e8,
527 .write = 0x1ea,
528 .read = 0x1ee,
529 .alarm_rw = 0x1f2,
530 .alarm_ctrl = 0x1e8,
531 .alarm_ctrl2 = 0x1e9,
532 .alarm_en = BIT(1),
533 };
534
535 static const struct pm8xxx_rtc_regs pm8941_regs = {
536 .ctrl = 0x6046,
537 .write = 0x6040,
538 .read = 0x6048,
539 .alarm_rw = 0x6140,
540 .alarm_ctrl = 0x6146,
541 .alarm_ctrl2 = 0x6148,
542 .alarm_en = BIT(7),
543 };
544
545 static const struct pm8xxx_rtc_regs pmk8350_regs = {
546 .ctrl = 0x6146,
547 .write = 0x6140,
548 .read = 0x6148,
549 .alarm_rw = 0x6240,
550 .alarm_ctrl = 0x6246,
551 .alarm_ctrl2 = 0x6248,
552 .alarm_en = BIT(7),
553 };
554
555 static const struct of_device_id pm8xxx_id_table[] = {
556 { .compatible = "qcom,pm8921-rtc", .data = &pm8921_regs },
557 { .compatible = "qcom,pm8058-rtc", .data = &pm8058_regs },
558 { .compatible = "qcom,pm8941-rtc", .data = &pm8941_regs },
559 { .compatible = "qcom,pmk8350-rtc", .data = &pmk8350_regs },
560 { },
561 };
562 MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
563
pm8xxx_rtc_probe_offset(struct pm8xxx_rtc * rtc_dd)564 static int pm8xxx_rtc_probe_offset(struct pm8xxx_rtc *rtc_dd)
565 {
566 int rc;
567
568 rtc_dd->nvmem_cell = devm_nvmem_cell_get(rtc_dd->dev, "offset");
569 if (IS_ERR(rtc_dd->nvmem_cell)) {
570 rc = PTR_ERR(rtc_dd->nvmem_cell);
571 if (rc != -ENOENT)
572 return rc;
573 rtc_dd->nvmem_cell = NULL;
574 } else {
575 return pm8xxx_rtc_read_nvmem_offset(rtc_dd);
576 }
577
578 /* Use UEFI storage as fallback if available */
579 rtc_dd->use_uefi = of_property_read_bool(rtc_dd->dev->of_node,
580 "qcom,uefi-rtc-info");
581 if (!rtc_dd->use_uefi)
582 return 0;
583
584 if (!efivar_is_available()) {
585 if (IS_ENABLED(CONFIG_EFI))
586 return -EPROBE_DEFER;
587
588 dev_warn(rtc_dd->dev, "efivars not available\n");
589 rtc_dd->use_uefi = false;
590 }
591
592 return pm8xxx_rtc_read_uefi_offset(rtc_dd);
593 }
594
pm8xxx_rtc_probe(struct platform_device * pdev)595 static int pm8xxx_rtc_probe(struct platform_device *pdev)
596 {
597 const struct of_device_id *match;
598 struct pm8xxx_rtc *rtc_dd;
599 int rc;
600
601 match = of_match_node(pm8xxx_id_table, pdev->dev.of_node);
602 if (!match)
603 return -ENXIO;
604
605 rtc_dd = devm_kzalloc(&pdev->dev, sizeof(*rtc_dd), GFP_KERNEL);
606 if (rtc_dd == NULL)
607 return -ENOMEM;
608
609 rtc_dd->regs = match->data;
610 rtc_dd->dev = &pdev->dev;
611
612 rtc_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL);
613 if (!rtc_dd->regmap)
614 return -ENXIO;
615
616 if (!of_property_read_bool(pdev->dev.of_node, "qcom,no-alarm")) {
617 rtc_dd->alarm_irq = platform_get_irq(pdev, 0);
618 if (rtc_dd->alarm_irq < 0)
619 return -ENXIO;
620 }
621
622 rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node,
623 "allow-set-time");
624 if (!rtc_dd->allow_set_time) {
625 rc = pm8xxx_rtc_probe_offset(rtc_dd);
626 if (rc)
627 return rc;
628 }
629
630 rc = pm8xxx_rtc_enable(rtc_dd);
631 if (rc)
632 return rc;
633
634 platform_set_drvdata(pdev, rtc_dd);
635
636 rtc_dd->rtc = devm_rtc_allocate_device(&pdev->dev);
637 if (IS_ERR(rtc_dd->rtc))
638 return PTR_ERR(rtc_dd->rtc);
639
640 rtc_dd->rtc->ops = &pm8xxx_rtc_ops;
641 rtc_dd->rtc->range_max = U32_MAX;
642
643 if (rtc_dd->alarm_irq) {
644 rc = devm_request_any_context_irq(&pdev->dev, rtc_dd->alarm_irq,
645 pm8xxx_alarm_trigger,
646 IRQF_TRIGGER_RISING,
647 "pm8xxx_rtc_alarm", rtc_dd);
648 if (rc < 0)
649 return rc;
650
651 rc = devm_pm_set_wake_irq(&pdev->dev, rtc_dd->alarm_irq);
652 if (rc)
653 return rc;
654
655 devm_device_init_wakeup(&pdev->dev);
656 } else {
657 clear_bit(RTC_FEATURE_ALARM, rtc_dd->rtc->features);
658 }
659
660 return devm_rtc_register_device(rtc_dd->rtc);
661 }
662
pm8xxx_shutdown(struct platform_device * pdev)663 static void pm8xxx_shutdown(struct platform_device *pdev)
664 {
665 struct pm8xxx_rtc *rtc_dd = platform_get_drvdata(pdev);
666
667 if (rtc_dd->offset_dirty) {
668 if (rtc_dd->nvmem_cell)
669 pm8xxx_rtc_write_nvmem_offset(rtc_dd, rtc_dd->offset);
670 else
671 pm8xxx_rtc_write_uefi_offset(rtc_dd, rtc_dd->offset);
672 }
673 }
674
675 static struct platform_driver pm8xxx_rtc_driver = {
676 .probe = pm8xxx_rtc_probe,
677 .shutdown = pm8xxx_shutdown,
678 .driver = {
679 .name = "rtc-pm8xxx",
680 .of_match_table = pm8xxx_id_table,
681 },
682 };
683
684 module_platform_driver(pm8xxx_rtc_driver);
685
686 MODULE_DESCRIPTION("PMIC8xxx RTC driver");
687 MODULE_LICENSE("GPL v2");
688 MODULE_AUTHOR("Anirudh Ghayal <aghayal@codeaurora.org>");
689 MODULE_AUTHOR("Johan Hovold <johan@kernel.org>");
690