1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2022 Microchip Technology Inc.
3 // pci1xxxx gpio driver
4
5 #include <linux/module.h>
6 #include <linux/spinlock.h>
7 #include <linux/gpio/driver.h>
8 #include <linux/bio.h>
9 #include <linux/mutex.h>
10 #include <linux/kthread.h>
11 #include <linux/interrupt.h>
12
13 #include "mchp_pci1xxxx_gp.h"
14
15 #define PCI1XXXX_NR_PINS 93
16 #define PERI_GEN_RESET 0
17 #define OUT_EN_OFFSET(x) ((((x) / 32) * 4) + 0x400)
18 #define INP_EN_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x10)
19 #define OUT_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x20)
20 #define INP_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x30)
21 #define PULLUP_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x40)
22 #define PULLDOWN_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x50)
23 #define OPENDRAIN_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x60)
24 #define WAKEMASK_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x70)
25 #define MODE_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x80)
26 #define INTR_LO_TO_HI_EDGE_CONFIG(x) ((((x) / 32) * 4) + 0x400 + 0x90)
27 #define INTR_HI_TO_LO_EDGE_CONFIG(x) ((((x) / 32) * 4) + 0x400 + 0xA0)
28 #define INTR_LEVEL_CONFIG_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0xB0)
29 #define INTR_LEVEL_MASK_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0xC0)
30 #define INTR_STAT_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0xD0)
31 #define DEBOUNCE_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0xE0)
32 #define PIO_GLOBAL_CONFIG_OFFSET (0x400 + 0xF0)
33 #define PIO_PCI_CTRL_REG_OFFSET (0x400 + 0xF4)
34 #define INTR_MASK_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x100)
35 #define INTR_STATUS_OFFSET(x) (((x) * 4) + 0x400 + 0xD0)
36
37 struct pci1xxxx_gpio {
38 struct auxiliary_device *aux_dev;
39 void __iomem *reg_base;
40 raw_spinlock_t wa_lock;
41 struct gpio_chip gpio;
42 spinlock_t lock;
43 int irq_base;
44 };
45
pci1xxxx_gpio_get_direction(struct gpio_chip * gpio,unsigned int nr)46 static int pci1xxxx_gpio_get_direction(struct gpio_chip *gpio, unsigned int nr)
47 {
48 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
49 u32 data;
50 int ret = -EINVAL;
51
52 data = readl(priv->reg_base + INP_EN_OFFSET(nr));
53 if (data & BIT(nr % 32)) {
54 ret = 1;
55 } else {
56 data = readl(priv->reg_base + OUT_EN_OFFSET(nr));
57 if (data & BIT(nr % 32))
58 ret = 0;
59 }
60
61 return ret;
62 }
63
pci1xxx_assign_bit(void __iomem * base_addr,unsigned int reg_offset,unsigned int bitpos,bool set)64 static inline void pci1xxx_assign_bit(void __iomem *base_addr, unsigned int reg_offset,
65 unsigned int bitpos, bool set)
66 {
67 u32 data;
68
69 data = readl(base_addr + reg_offset);
70 if (set)
71 data |= BIT(bitpos);
72 else
73 data &= ~BIT(bitpos);
74 writel(data, base_addr + reg_offset);
75 }
76
pci1xxxx_gpio_direction_input(struct gpio_chip * gpio,unsigned int nr)77 static int pci1xxxx_gpio_direction_input(struct gpio_chip *gpio, unsigned int nr)
78 {
79 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
80 unsigned long flags;
81
82 spin_lock_irqsave(&priv->lock, flags);
83 pci1xxx_assign_bit(priv->reg_base, INP_EN_OFFSET(nr), (nr % 32), true);
84 pci1xxx_assign_bit(priv->reg_base, OUT_EN_OFFSET(nr), (nr % 32), false);
85 spin_unlock_irqrestore(&priv->lock, flags);
86
87 return 0;
88 }
89
pci1xxxx_gpio_get(struct gpio_chip * gpio,unsigned int nr)90 static int pci1xxxx_gpio_get(struct gpio_chip *gpio, unsigned int nr)
91 {
92 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
93
94 return (readl(priv->reg_base + INP_OFFSET(nr)) >> (nr % 32)) & 1;
95 }
96
pci1xxxx_gpio_direction_output(struct gpio_chip * gpio,unsigned int nr,int val)97 static int pci1xxxx_gpio_direction_output(struct gpio_chip *gpio,
98 unsigned int nr, int val)
99 {
100 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
101 unsigned long flags;
102 u32 data;
103
104 spin_lock_irqsave(&priv->lock, flags);
105 pci1xxx_assign_bit(priv->reg_base, INP_EN_OFFSET(nr), (nr % 32), false);
106 pci1xxx_assign_bit(priv->reg_base, OUT_EN_OFFSET(nr), (nr % 32), true);
107 data = readl(priv->reg_base + OUT_OFFSET(nr));
108 if (val)
109 data |= (1 << (nr % 32));
110 else
111 data &= ~(1 << (nr % 32));
112 writel(data, priv->reg_base + OUT_OFFSET(nr));
113 spin_unlock_irqrestore(&priv->lock, flags);
114
115 return 0;
116 }
117
pci1xxxx_gpio_set(struct gpio_chip * gpio,unsigned int nr,int val)118 static void pci1xxxx_gpio_set(struct gpio_chip *gpio,
119 unsigned int nr, int val)
120 {
121 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
122 unsigned long flags;
123
124 spin_lock_irqsave(&priv->lock, flags);
125 pci1xxx_assign_bit(priv->reg_base, OUT_OFFSET(nr), (nr % 32), val);
126 spin_unlock_irqrestore(&priv->lock, flags);
127 }
128
pci1xxxx_gpio_set_config(struct gpio_chip * gpio,unsigned int offset,unsigned long config)129 static int pci1xxxx_gpio_set_config(struct gpio_chip *gpio, unsigned int offset,
130 unsigned long config)
131 {
132 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
133 unsigned long flags;
134 int ret = 0;
135
136 spin_lock_irqsave(&priv->lock, flags);
137 switch (pinconf_to_config_param(config)) {
138 case PIN_CONFIG_BIAS_PULL_UP:
139 pci1xxx_assign_bit(priv->reg_base, PULLUP_OFFSET(offset), (offset % 32), true);
140 break;
141 case PIN_CONFIG_BIAS_PULL_DOWN:
142 pci1xxx_assign_bit(priv->reg_base, PULLDOWN_OFFSET(offset), (offset % 32), true);
143 break;
144 case PIN_CONFIG_BIAS_DISABLE:
145 pci1xxx_assign_bit(priv->reg_base, PULLUP_OFFSET(offset), (offset % 32), false);
146 pci1xxx_assign_bit(priv->reg_base, PULLDOWN_OFFSET(offset), (offset % 32), false);
147 break;
148 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
149 pci1xxx_assign_bit(priv->reg_base, OPENDRAIN_OFFSET(offset), (offset % 32), true);
150 break;
151 case PIN_CONFIG_DRIVE_PUSH_PULL:
152 pci1xxx_assign_bit(priv->reg_base, OPENDRAIN_OFFSET(offset), (offset % 32), false);
153 break;
154 default:
155 ret = -ENOTSUPP;
156 break;
157 }
158 spin_unlock_irqrestore(&priv->lock, flags);
159
160 return ret;
161 }
162
pci1xxxx_gpio_irq_ack(struct irq_data * data)163 static void pci1xxxx_gpio_irq_ack(struct irq_data *data)
164 {
165 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
166 struct pci1xxxx_gpio *priv = gpiochip_get_data(chip);
167 unsigned int gpio = irqd_to_hwirq(data);
168 unsigned long flags;
169
170 spin_lock_irqsave(&priv->lock, flags);
171 writel(BIT(gpio % 32), priv->reg_base + INTR_STAT_OFFSET(gpio));
172 spin_unlock_irqrestore(&priv->lock, flags);
173 }
174
pci1xxxx_gpio_irq_set_mask(struct irq_data * data,bool set)175 static void pci1xxxx_gpio_irq_set_mask(struct irq_data *data, bool set)
176 {
177 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
178 struct pci1xxxx_gpio *priv = gpiochip_get_data(chip);
179 unsigned int gpio = irqd_to_hwirq(data);
180 unsigned long flags;
181
182 if (!set)
183 gpiochip_enable_irq(chip, gpio);
184 spin_lock_irqsave(&priv->lock, flags);
185 pci1xxx_assign_bit(priv->reg_base, INTR_MASK_OFFSET(gpio), (gpio % 32), set);
186 spin_unlock_irqrestore(&priv->lock, flags);
187 if (set)
188 gpiochip_disable_irq(chip, gpio);
189 }
190
pci1xxxx_gpio_irq_mask(struct irq_data * data)191 static void pci1xxxx_gpio_irq_mask(struct irq_data *data)
192 {
193 pci1xxxx_gpio_irq_set_mask(data, true);
194 }
195
pci1xxxx_gpio_irq_unmask(struct irq_data * data)196 static void pci1xxxx_gpio_irq_unmask(struct irq_data *data)
197 {
198 pci1xxxx_gpio_irq_set_mask(data, false);
199 }
200
pci1xxxx_gpio_set_type(struct irq_data * data,unsigned int trigger_type)201 static int pci1xxxx_gpio_set_type(struct irq_data *data, unsigned int trigger_type)
202 {
203 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
204 struct pci1xxxx_gpio *priv = gpiochip_get_data(chip);
205 unsigned int gpio = irqd_to_hwirq(data);
206 unsigned int bitpos = gpio % 32;
207
208 if (trigger_type & IRQ_TYPE_EDGE_FALLING) {
209 pci1xxx_assign_bit(priv->reg_base, INTR_HI_TO_LO_EDGE_CONFIG(gpio),
210 bitpos, false);
211 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio),
212 bitpos, false);
213 irq_set_handler_locked(data, handle_edge_irq);
214 } else {
215 pci1xxx_assign_bit(priv->reg_base, INTR_HI_TO_LO_EDGE_CONFIG(gpio),
216 bitpos, true);
217 }
218
219 if (trigger_type & IRQ_TYPE_EDGE_RISING) {
220 pci1xxx_assign_bit(priv->reg_base, INTR_LO_TO_HI_EDGE_CONFIG(gpio),
221 bitpos, false);
222 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos,
223 false);
224 irq_set_handler_locked(data, handle_edge_irq);
225 } else {
226 pci1xxx_assign_bit(priv->reg_base, INTR_LO_TO_HI_EDGE_CONFIG(gpio),
227 bitpos, true);
228 }
229
230 if (trigger_type & IRQ_TYPE_LEVEL_LOW) {
231 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_CONFIG_OFFSET(gpio),
232 bitpos, true);
233 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio),
234 bitpos, false);
235 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos,
236 true);
237 irq_set_handler_locked(data, handle_edge_irq);
238 }
239
240 if (trigger_type & IRQ_TYPE_LEVEL_HIGH) {
241 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_CONFIG_OFFSET(gpio),
242 bitpos, false);
243 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio),
244 bitpos, false);
245 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos,
246 true);
247 irq_set_handler_locked(data, handle_edge_irq);
248 }
249
250 if ((!(trigger_type & IRQ_TYPE_LEVEL_LOW)) && (!(trigger_type & IRQ_TYPE_LEVEL_HIGH)))
251 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio), bitpos, true);
252
253 return true;
254 }
255
pci1xxxx_gpio_irq_handler(int irq,void * dev_id)256 static irqreturn_t pci1xxxx_gpio_irq_handler(int irq, void *dev_id)
257 {
258 struct pci1xxxx_gpio *priv = dev_id;
259 struct gpio_chip *gc = &priv->gpio;
260 unsigned long int_status = 0;
261 unsigned long wa_flags;
262 unsigned long flags;
263 u8 pincount;
264 int bit;
265 u8 gpiobank;
266
267 spin_lock_irqsave(&priv->lock, flags);
268 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, 16, true);
269 spin_unlock_irqrestore(&priv->lock, flags);
270 for (gpiobank = 0; gpiobank < 3; gpiobank++) {
271 spin_lock_irqsave(&priv->lock, flags);
272 int_status = readl(priv->reg_base + INTR_STATUS_OFFSET(gpiobank));
273 spin_unlock_irqrestore(&priv->lock, flags);
274 if (gpiobank == 2)
275 pincount = 29;
276 else
277 pincount = 32;
278 for_each_set_bit(bit, &int_status, pincount) {
279 unsigned int irq;
280
281 spin_lock_irqsave(&priv->lock, flags);
282 writel(BIT(bit), priv->reg_base + INTR_STATUS_OFFSET(gpiobank));
283 spin_unlock_irqrestore(&priv->lock, flags);
284 irq = irq_find_mapping(gc->irq.domain, (bit + (gpiobank * 32)));
285 raw_spin_lock_irqsave(&priv->wa_lock, wa_flags);
286 generic_handle_irq(irq);
287 raw_spin_unlock_irqrestore(&priv->wa_lock, wa_flags);
288 }
289 }
290 spin_lock_irqsave(&priv->lock, flags);
291 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, 16, false);
292 spin_unlock_irqrestore(&priv->lock, flags);
293
294 return IRQ_HANDLED;
295 }
296
297 static const struct irq_chip pci1xxxx_gpio_irqchip = {
298 .name = "pci1xxxx_gpio",
299 .irq_ack = pci1xxxx_gpio_irq_ack,
300 .irq_mask = pci1xxxx_gpio_irq_mask,
301 .irq_unmask = pci1xxxx_gpio_irq_unmask,
302 .irq_set_type = pci1xxxx_gpio_set_type,
303 .flags = IRQCHIP_IMMUTABLE,
304 GPIOCHIP_IRQ_RESOURCE_HELPERS,
305 };
306
pci1xxxx_gpio_suspend(struct device * dev)307 static int pci1xxxx_gpio_suspend(struct device *dev)
308 {
309 struct pci1xxxx_gpio *priv = dev_get_drvdata(dev);
310 unsigned long flags;
311
312 spin_lock_irqsave(&priv->lock, flags);
313 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET,
314 16, true);
315 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET,
316 17, false);
317 pci1xxx_assign_bit(priv->reg_base, PERI_GEN_RESET, 16, true);
318 spin_unlock_irqrestore(&priv->lock, flags);
319
320 return 0;
321 }
322
pci1xxxx_gpio_resume(struct device * dev)323 static int pci1xxxx_gpio_resume(struct device *dev)
324 {
325 struct pci1xxxx_gpio *priv = dev_get_drvdata(dev);
326 unsigned long flags;
327
328 spin_lock_irqsave(&priv->lock, flags);
329 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET,
330 17, true);
331 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET,
332 16, false);
333 pci1xxx_assign_bit(priv->reg_base, PERI_GEN_RESET, 16, false);
334 spin_unlock_irqrestore(&priv->lock, flags);
335
336 return 0;
337 }
338
pci1xxxx_gpio_setup(struct pci1xxxx_gpio * priv,int irq)339 static int pci1xxxx_gpio_setup(struct pci1xxxx_gpio *priv, int irq)
340 {
341 struct gpio_chip *gchip = &priv->gpio;
342 struct gpio_irq_chip *girq;
343 int retval;
344
345 gchip->label = dev_name(&priv->aux_dev->dev);
346 gchip->parent = &priv->aux_dev->dev;
347 gchip->owner = THIS_MODULE;
348 gchip->direction_input = pci1xxxx_gpio_direction_input;
349 gchip->direction_output = pci1xxxx_gpio_direction_output;
350 gchip->get_direction = pci1xxxx_gpio_get_direction;
351 gchip->get = pci1xxxx_gpio_get;
352 gchip->set = pci1xxxx_gpio_set;
353 gchip->set_config = pci1xxxx_gpio_set_config;
354 gchip->dbg_show = NULL;
355 gchip->base = -1;
356 gchip->ngpio = PCI1XXXX_NR_PINS;
357 gchip->can_sleep = false;
358
359 retval = devm_request_threaded_irq(&priv->aux_dev->dev, irq,
360 NULL, pci1xxxx_gpio_irq_handler,
361 IRQF_ONESHOT, "PCI1xxxxGPIO", priv);
362
363 if (retval)
364 return retval;
365
366 girq = &priv->gpio.irq;
367 gpio_irq_chip_set_chip(girq, &pci1xxxx_gpio_irqchip);
368 girq->parent_handler = NULL;
369 girq->num_parents = 0;
370 girq->parents = NULL;
371 girq->default_type = IRQ_TYPE_NONE;
372 girq->handler = handle_bad_irq;
373
374 return 0;
375 }
376
pci1xxxx_gpio_probe(struct auxiliary_device * aux_dev,const struct auxiliary_device_id * id)377 static int pci1xxxx_gpio_probe(struct auxiliary_device *aux_dev,
378 const struct auxiliary_device_id *id)
379
380 {
381 struct auxiliary_device_wrapper *aux_dev_wrapper;
382 struct gp_aux_data_type *pdata;
383 struct pci1xxxx_gpio *priv;
384 int retval;
385
386 aux_dev_wrapper = (struct auxiliary_device_wrapper *)
387 container_of(aux_dev, struct auxiliary_device_wrapper, aux_dev);
388
389 pdata = &aux_dev_wrapper->gp_aux_data;
390
391 if (!pdata)
392 return -EINVAL;
393
394 priv = devm_kzalloc(&aux_dev->dev, sizeof(struct pci1xxxx_gpio), GFP_KERNEL);
395 if (!priv)
396 return -ENOMEM;
397
398 spin_lock_init(&priv->lock);
399 priv->aux_dev = aux_dev;
400
401 if (!devm_request_mem_region(&aux_dev->dev, pdata->region_start, 0x800, aux_dev->name))
402 return -EBUSY;
403
404 priv->reg_base = devm_ioremap(&aux_dev->dev, pdata->region_start, 0x800);
405 if (!priv->reg_base)
406 return -ENOMEM;
407
408 writel(0x0264, (priv->reg_base + 0x400 + 0xF0));
409
410 retval = pci1xxxx_gpio_setup(priv, pdata->irq_num);
411
412 if (retval < 0)
413 return retval;
414
415 dev_set_drvdata(&aux_dev->dev, priv);
416
417 return devm_gpiochip_add_data(&aux_dev->dev, &priv->gpio, priv);
418 }
419
420 static DEFINE_SIMPLE_DEV_PM_OPS(pci1xxxx_gpio_pm_ops, pci1xxxx_gpio_suspend, pci1xxxx_gpio_resume);
421
422 static const struct auxiliary_device_id pci1xxxx_gpio_auxiliary_id_table[] = {
423 {.name = "mchp_pci1xxxx_gp.gp_gpio"},
424 {}
425 };
426 MODULE_DEVICE_TABLE(auxiliary, pci1xxxx_gpio_auxiliary_id_table);
427
428 static struct auxiliary_driver pci1xxxx_gpio_driver = {
429 .driver = {
430 .name = "PCI1xxxxGPIO",
431 .pm = &pci1xxxx_gpio_pm_ops,
432 },
433 .probe = pci1xxxx_gpio_probe,
434 .id_table = pci1xxxx_gpio_auxiliary_id_table
435 };
436 module_auxiliary_driver(pci1xxxx_gpio_driver);
437
438 MODULE_DESCRIPTION("Microchip Technology Inc. PCI1xxxx GPIO controller");
439 MODULE_AUTHOR("Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>");
440 MODULE_LICENSE("GPL");
441