1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2022 Microchip Technology Inc.
3 // pci1xxxx gpio driver
4
5 #include <linux/module.h>
6 #include <linux/spinlock.h>
7 #include <linux/gpio/driver.h>
8 #include <linux/bio.h>
9 #include <linux/mutex.h>
10 #include <linux/pci.h>
11 #include <linux/kthread.h>
12 #include <linux/interrupt.h>
13
14 #include "mchp_pci1xxxx_gp.h"
15
16 #define PCI1XXXX_NR_PINS 93
17 #define PCI_DEV_REV_OFFSET 0x08
18 #define PERI_GEN_RESET 0
19 #define OUT_EN_OFFSET(x) ((((x) / 32) * 4) + 0x400)
20 #define INP_EN_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x10)
21 #define OUT_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x20)
22 #define INP_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x30)
23 #define PULLUP_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x40)
24 #define PULLDOWN_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x50)
25 #define OPENDRAIN_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x60)
26 #define WAKEMASK_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x70)
27 #define MODE_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x80)
28 #define INTR_LO_TO_HI_EDGE_CONFIG(x) ((((x) / 32) * 4) + 0x400 + 0x90)
29 #define INTR_HI_TO_LO_EDGE_CONFIG(x) ((((x) / 32) * 4) + 0x400 + 0xA0)
30 #define INTR_LEVEL_CONFIG_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0xB0)
31 #define INTR_LEVEL_MASK_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0xC0)
32 #define INTR_STAT_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0xD0)
33 #define DEBOUNCE_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0xE0)
34 #define PIO_GLOBAL_CONFIG_OFFSET (0x400 + 0xF0)
35 #define PIO_PCI_CTRL_REG_OFFSET (0x400 + 0xF4)
36 #define INTR_MASK_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x100)
37 #define INTR_STATUS_OFFSET(x) (((x) * 4) + 0x400 + 0xD0)
38
39 struct pci1xxxx_gpio {
40 struct auxiliary_device *aux_dev;
41 void __iomem *reg_base;
42 raw_spinlock_t wa_lock;
43 struct gpio_chip gpio;
44 spinlock_t lock;
45 u32 gpio_wake_mask[3];
46 int irq_base;
47 u8 dev_rev;
48 };
49
pci1xxxx_gpio_get_device_revision(struct pci1xxxx_gpio * priv)50 static int pci1xxxx_gpio_get_device_revision(struct pci1xxxx_gpio *priv)
51 {
52 struct device *parent = priv->aux_dev->dev.parent;
53 struct pci_dev *pcidev = to_pci_dev(parent);
54 int ret;
55 u32 val;
56
57 ret = pci_read_config_dword(pcidev, PCI_DEV_REV_OFFSET, &val);
58 if (ret)
59 return ret;
60
61 priv->dev_rev = val;
62
63 return 0;
64 }
65
pci1xxxx_gpio_get_direction(struct gpio_chip * gpio,unsigned int nr)66 static int pci1xxxx_gpio_get_direction(struct gpio_chip *gpio, unsigned int nr)
67 {
68 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
69 u32 data;
70 int ret = -EINVAL;
71
72 data = readl(priv->reg_base + INP_EN_OFFSET(nr));
73 if (data & BIT(nr % 32)) {
74 ret = 1;
75 } else {
76 data = readl(priv->reg_base + OUT_EN_OFFSET(nr));
77 if (data & BIT(nr % 32))
78 ret = 0;
79 }
80
81 return ret;
82 }
83
pci1xxx_assign_bit(void __iomem * base_addr,unsigned int reg_offset,unsigned int bitpos,bool set)84 static inline void pci1xxx_assign_bit(void __iomem *base_addr, unsigned int reg_offset,
85 unsigned int bitpos, bool set)
86 {
87 u32 data;
88
89 data = readl(base_addr + reg_offset);
90 if (set)
91 data |= BIT(bitpos);
92 else
93 data &= ~BIT(bitpos);
94 writel(data, base_addr + reg_offset);
95 }
96
pci1xxxx_gpio_direction_input(struct gpio_chip * gpio,unsigned int nr)97 static int pci1xxxx_gpio_direction_input(struct gpio_chip *gpio, unsigned int nr)
98 {
99 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
100 unsigned long flags;
101
102 spin_lock_irqsave(&priv->lock, flags);
103 pci1xxx_assign_bit(priv->reg_base, INP_EN_OFFSET(nr), (nr % 32), true);
104 pci1xxx_assign_bit(priv->reg_base, OUT_EN_OFFSET(nr), (nr % 32), false);
105 spin_unlock_irqrestore(&priv->lock, flags);
106
107 return 0;
108 }
109
pci1xxxx_gpio_get(struct gpio_chip * gpio,unsigned int nr)110 static int pci1xxxx_gpio_get(struct gpio_chip *gpio, unsigned int nr)
111 {
112 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
113
114 return (readl(priv->reg_base + INP_OFFSET(nr)) >> (nr % 32)) & 1;
115 }
116
pci1xxxx_gpio_direction_output(struct gpio_chip * gpio,unsigned int nr,int val)117 static int pci1xxxx_gpio_direction_output(struct gpio_chip *gpio,
118 unsigned int nr, int val)
119 {
120 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
121 unsigned long flags;
122 u32 data;
123
124 spin_lock_irqsave(&priv->lock, flags);
125 pci1xxx_assign_bit(priv->reg_base, INP_EN_OFFSET(nr), (nr % 32), false);
126 pci1xxx_assign_bit(priv->reg_base, OUT_EN_OFFSET(nr), (nr % 32), true);
127 data = readl(priv->reg_base + OUT_OFFSET(nr));
128 if (val)
129 data |= (1 << (nr % 32));
130 else
131 data &= ~(1 << (nr % 32));
132 writel(data, priv->reg_base + OUT_OFFSET(nr));
133 spin_unlock_irqrestore(&priv->lock, flags);
134
135 return 0;
136 }
137
pci1xxxx_gpio_set(struct gpio_chip * gpio,unsigned int nr,int val)138 static int pci1xxxx_gpio_set(struct gpio_chip *gpio, unsigned int nr, int val)
139 {
140 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
141 unsigned long flags;
142
143 spin_lock_irqsave(&priv->lock, flags);
144 pci1xxx_assign_bit(priv->reg_base, OUT_OFFSET(nr), (nr % 32), val);
145 spin_unlock_irqrestore(&priv->lock, flags);
146
147 return 0;
148 }
149
pci1xxxx_gpio_set_config(struct gpio_chip * gpio,unsigned int offset,unsigned long config)150 static int pci1xxxx_gpio_set_config(struct gpio_chip *gpio, unsigned int offset,
151 unsigned long config)
152 {
153 struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
154 unsigned long flags;
155 int ret = 0;
156
157 spin_lock_irqsave(&priv->lock, flags);
158 switch (pinconf_to_config_param(config)) {
159 case PIN_CONFIG_BIAS_PULL_UP:
160 pci1xxx_assign_bit(priv->reg_base, PULLUP_OFFSET(offset), (offset % 32), true);
161 break;
162 case PIN_CONFIG_BIAS_PULL_DOWN:
163 pci1xxx_assign_bit(priv->reg_base, PULLDOWN_OFFSET(offset), (offset % 32), true);
164 break;
165 case PIN_CONFIG_BIAS_DISABLE:
166 pci1xxx_assign_bit(priv->reg_base, PULLUP_OFFSET(offset), (offset % 32), false);
167 pci1xxx_assign_bit(priv->reg_base, PULLDOWN_OFFSET(offset), (offset % 32), false);
168 break;
169 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
170 pci1xxx_assign_bit(priv->reg_base, OPENDRAIN_OFFSET(offset), (offset % 32), true);
171 break;
172 case PIN_CONFIG_DRIVE_PUSH_PULL:
173 pci1xxx_assign_bit(priv->reg_base, OPENDRAIN_OFFSET(offset), (offset % 32), false);
174 break;
175 default:
176 ret = -ENOTSUPP;
177 break;
178 }
179 spin_unlock_irqrestore(&priv->lock, flags);
180
181 return ret;
182 }
183
pci1xxxx_gpio_irq_ack(struct irq_data * data)184 static void pci1xxxx_gpio_irq_ack(struct irq_data *data)
185 {
186 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
187 struct pci1xxxx_gpio *priv = gpiochip_get_data(chip);
188 unsigned int gpio = irqd_to_hwirq(data);
189 unsigned long flags;
190
191 spin_lock_irqsave(&priv->lock, flags);
192 writel(BIT(gpio % 32), priv->reg_base + INTR_STAT_OFFSET(gpio));
193 spin_unlock_irqrestore(&priv->lock, flags);
194 }
195
pci1xxxx_gpio_irq_set_mask(struct irq_data * data,bool set)196 static void pci1xxxx_gpio_irq_set_mask(struct irq_data *data, bool set)
197 {
198 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
199 struct pci1xxxx_gpio *priv = gpiochip_get_data(chip);
200 unsigned int gpio = irqd_to_hwirq(data);
201 unsigned long flags;
202
203 if (!set)
204 gpiochip_enable_irq(chip, gpio);
205 spin_lock_irqsave(&priv->lock, flags);
206 pci1xxx_assign_bit(priv->reg_base, INTR_MASK_OFFSET(gpio), (gpio % 32), set);
207 spin_unlock_irqrestore(&priv->lock, flags);
208 if (set)
209 gpiochip_disable_irq(chip, gpio);
210 }
211
pci1xxxx_gpio_irq_mask(struct irq_data * data)212 static void pci1xxxx_gpio_irq_mask(struct irq_data *data)
213 {
214 pci1xxxx_gpio_irq_set_mask(data, true);
215 }
216
pci1xxxx_gpio_irq_unmask(struct irq_data * data)217 static void pci1xxxx_gpio_irq_unmask(struct irq_data *data)
218 {
219 pci1xxxx_gpio_irq_set_mask(data, false);
220 }
221
pci1xxxx_gpio_set_type(struct irq_data * data,unsigned int trigger_type)222 static int pci1xxxx_gpio_set_type(struct irq_data *data, unsigned int trigger_type)
223 {
224 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
225 struct pci1xxxx_gpio *priv = gpiochip_get_data(chip);
226 unsigned int gpio = irqd_to_hwirq(data);
227 unsigned int bitpos = gpio % 32;
228
229 if (trigger_type & IRQ_TYPE_EDGE_FALLING) {
230 pci1xxx_assign_bit(priv->reg_base, INTR_HI_TO_LO_EDGE_CONFIG(gpio),
231 bitpos, false);
232 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio),
233 bitpos, false);
234 irq_set_handler_locked(data, handle_edge_irq);
235 } else {
236 pci1xxx_assign_bit(priv->reg_base, INTR_HI_TO_LO_EDGE_CONFIG(gpio),
237 bitpos, true);
238 }
239
240 if (trigger_type & IRQ_TYPE_EDGE_RISING) {
241 pci1xxx_assign_bit(priv->reg_base, INTR_LO_TO_HI_EDGE_CONFIG(gpio),
242 bitpos, false);
243 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos,
244 false);
245 irq_set_handler_locked(data, handle_edge_irq);
246 } else {
247 pci1xxx_assign_bit(priv->reg_base, INTR_LO_TO_HI_EDGE_CONFIG(gpio),
248 bitpos, true);
249 }
250
251 if (trigger_type & IRQ_TYPE_LEVEL_LOW) {
252 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_CONFIG_OFFSET(gpio),
253 bitpos, true);
254 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio),
255 bitpos, false);
256 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos,
257 true);
258 irq_set_handler_locked(data, handle_edge_irq);
259 }
260
261 if (trigger_type & IRQ_TYPE_LEVEL_HIGH) {
262 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_CONFIG_OFFSET(gpio),
263 bitpos, false);
264 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio),
265 bitpos, false);
266 pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos,
267 true);
268 irq_set_handler_locked(data, handle_edge_irq);
269 }
270
271 if ((!(trigger_type & IRQ_TYPE_LEVEL_LOW)) && (!(trigger_type & IRQ_TYPE_LEVEL_HIGH)))
272 pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio), bitpos, true);
273
274 return true;
275 }
276
pci1xxxx_gpio_set_wake(struct irq_data * data,unsigned int enable)277 static int pci1xxxx_gpio_set_wake(struct irq_data *data, unsigned int enable)
278 {
279 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
280 struct pci1xxxx_gpio *priv = gpiochip_get_data(chip);
281 unsigned int gpio = irqd_to_hwirq(data);
282 unsigned int bitpos = gpio % 32;
283 unsigned int bank = gpio / 32;
284
285 if (enable)
286 priv->gpio_wake_mask[bank] |= (1 << bitpos);
287 else
288 priv->gpio_wake_mask[bank] &= ~(1 << bitpos);
289
290 return 0;
291 }
292
pci1xxxx_gpio_irq_handler(int irq,void * dev_id)293 static irqreturn_t pci1xxxx_gpio_irq_handler(int irq, void *dev_id)
294 {
295 struct pci1xxxx_gpio *priv = dev_id;
296 struct gpio_chip *gc = &priv->gpio;
297 unsigned long int_status = 0;
298 unsigned long wa_flags;
299 unsigned long flags;
300 u8 pincount;
301 int bit;
302 u8 gpiobank;
303
304 spin_lock_irqsave(&priv->lock, flags);
305 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, 16, true);
306 spin_unlock_irqrestore(&priv->lock, flags);
307 for (gpiobank = 0; gpiobank < 3; gpiobank++) {
308 spin_lock_irqsave(&priv->lock, flags);
309 int_status = readl(priv->reg_base + INTR_STATUS_OFFSET(gpiobank));
310 spin_unlock_irqrestore(&priv->lock, flags);
311 if (gpiobank == 2)
312 pincount = 29;
313 else
314 pincount = 32;
315 for_each_set_bit(bit, &int_status, pincount) {
316 unsigned int irq;
317
318 spin_lock_irqsave(&priv->lock, flags);
319 writel(BIT(bit), priv->reg_base + INTR_STATUS_OFFSET(gpiobank));
320 spin_unlock_irqrestore(&priv->lock, flags);
321 irq = irq_find_mapping(gc->irq.domain, (bit + (gpiobank * 32)));
322 raw_spin_lock_irqsave(&priv->wa_lock, wa_flags);
323 generic_handle_irq(irq);
324 raw_spin_unlock_irqrestore(&priv->wa_lock, wa_flags);
325 }
326 }
327 spin_lock_irqsave(&priv->lock, flags);
328 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET, 16, false);
329 spin_unlock_irqrestore(&priv->lock, flags);
330
331 return IRQ_HANDLED;
332 }
333
334 static const struct irq_chip pci1xxxx_gpio_irqchip = {
335 .name = "pci1xxxx_gpio",
336 .irq_ack = pci1xxxx_gpio_irq_ack,
337 .irq_mask = pci1xxxx_gpio_irq_mask,
338 .irq_unmask = pci1xxxx_gpio_irq_unmask,
339 .irq_set_type = pci1xxxx_gpio_set_type,
340 .irq_set_wake = pci1xxxx_gpio_set_wake,
341 .flags = IRQCHIP_IMMUTABLE,
342 GPIOCHIP_IRQ_RESOURCE_HELPERS,
343 };
344
pci1xxxx_gpio_suspend(struct device * dev)345 static int pci1xxxx_gpio_suspend(struct device *dev)
346 {
347 struct pci1xxxx_gpio *priv = dev_get_drvdata(dev);
348 struct device *parent = priv->aux_dev->dev.parent;
349 struct pci_dev *pcidev = to_pci_dev(parent);
350 unsigned int gpio_bank_base;
351 unsigned int wake_mask;
352 unsigned int gpiobank;
353 unsigned long flags;
354
355 for (gpiobank = 0; gpiobank < 3; gpiobank++) {
356 wake_mask = priv->gpio_wake_mask[gpiobank];
357
358 if (wake_mask) {
359 gpio_bank_base = gpiobank * 32;
360
361 pci1xxx_assign_bit(priv->reg_base,
362 PIO_PCI_CTRL_REG_OFFSET, 0, true);
363 writel(~wake_mask, priv->reg_base +
364 WAKEMASK_OFFSET(gpio_bank_base));
365 }
366 }
367
368 spin_lock_irqsave(&priv->lock, flags);
369 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET,
370 16, true);
371 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET,
372 17, false);
373 pci1xxx_assign_bit(priv->reg_base, PERI_GEN_RESET, 16, true);
374
375 if (priv->dev_rev >= 0xC0)
376 pci1xxx_assign_bit(priv->reg_base, PERI_GEN_RESET, 17, true);
377
378 spin_unlock_irqrestore(&priv->lock, flags);
379
380 device_set_wakeup_enable(&pcidev->dev, true);
381 pci_wake_from_d3(pcidev, true);
382
383 return 0;
384 }
385
pci1xxxx_gpio_resume(struct device * dev)386 static int pci1xxxx_gpio_resume(struct device *dev)
387 {
388 struct pci1xxxx_gpio *priv = dev_get_drvdata(dev);
389 struct device *parent = priv->aux_dev->dev.parent;
390 struct pci_dev *pcidev = to_pci_dev(parent);
391 unsigned int gpio_bank_base;
392 unsigned int wake_mask;
393 unsigned int gpiobank;
394 unsigned long flags;
395
396 for (gpiobank = 0; gpiobank < 3; gpiobank++) {
397 wake_mask = priv->gpio_wake_mask[gpiobank];
398
399 if (wake_mask) {
400 gpio_bank_base = gpiobank * 32;
401
402 writel(wake_mask, priv->reg_base +
403 INTR_STAT_OFFSET(gpio_bank_base));
404 pci1xxx_assign_bit(priv->reg_base,
405 PIO_PCI_CTRL_REG_OFFSET, 0, false);
406 writel(0xffffffff, priv->reg_base +
407 WAKEMASK_OFFSET(gpio_bank_base));
408 }
409 }
410
411 spin_lock_irqsave(&priv->lock, flags);
412 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET,
413 17, true);
414 pci1xxx_assign_bit(priv->reg_base, PIO_GLOBAL_CONFIG_OFFSET,
415 16, false);
416 pci1xxx_assign_bit(priv->reg_base, PERI_GEN_RESET, 16, false);
417
418 if (priv->dev_rev >= 0xC0)
419 pci1xxx_assign_bit(priv->reg_base, PERI_GEN_RESET, 17, false);
420
421 spin_unlock_irqrestore(&priv->lock, flags);
422
423 pci_wake_from_d3(pcidev, false);
424
425 return 0;
426 }
427
pci1xxxx_gpio_setup(struct pci1xxxx_gpio * priv,int irq)428 static int pci1xxxx_gpio_setup(struct pci1xxxx_gpio *priv, int irq)
429 {
430 struct gpio_chip *gchip = &priv->gpio;
431 struct gpio_irq_chip *girq;
432 int retval;
433
434 gchip->label = dev_name(&priv->aux_dev->dev);
435 gchip->parent = &priv->aux_dev->dev;
436 gchip->owner = THIS_MODULE;
437 gchip->direction_input = pci1xxxx_gpio_direction_input;
438 gchip->direction_output = pci1xxxx_gpio_direction_output;
439 gchip->get_direction = pci1xxxx_gpio_get_direction;
440 gchip->get = pci1xxxx_gpio_get;
441 gchip->set_rv = pci1xxxx_gpio_set;
442 gchip->set_config = pci1xxxx_gpio_set_config;
443 gchip->dbg_show = NULL;
444 gchip->base = -1;
445 gchip->ngpio = PCI1XXXX_NR_PINS;
446 gchip->can_sleep = false;
447
448 retval = devm_request_threaded_irq(&priv->aux_dev->dev, irq,
449 NULL, pci1xxxx_gpio_irq_handler,
450 IRQF_ONESHOT, "PCI1xxxxGPIO", priv);
451
452 if (retval)
453 return retval;
454
455 girq = &priv->gpio.irq;
456 gpio_irq_chip_set_chip(girq, &pci1xxxx_gpio_irqchip);
457 girq->parent_handler = NULL;
458 girq->num_parents = 0;
459 girq->parents = NULL;
460 girq->default_type = IRQ_TYPE_NONE;
461 girq->handler = handle_bad_irq;
462
463 return 0;
464 }
465
pci1xxxx_gpio_probe(struct auxiliary_device * aux_dev,const struct auxiliary_device_id * id)466 static int pci1xxxx_gpio_probe(struct auxiliary_device *aux_dev,
467 const struct auxiliary_device_id *id)
468
469 {
470 struct auxiliary_device_wrapper *aux_dev_wrapper;
471 struct gp_aux_data_type *pdata;
472 struct pci1xxxx_gpio *priv;
473 int retval;
474
475 aux_dev_wrapper = (struct auxiliary_device_wrapper *)
476 container_of(aux_dev, struct auxiliary_device_wrapper, aux_dev);
477
478 pdata = &aux_dev_wrapper->gp_aux_data;
479
480 if (!pdata)
481 return -EINVAL;
482
483 priv = devm_kzalloc(&aux_dev->dev, sizeof(struct pci1xxxx_gpio), GFP_KERNEL);
484 if (!priv)
485 return -ENOMEM;
486
487 spin_lock_init(&priv->lock);
488 priv->aux_dev = aux_dev;
489
490 if (!devm_request_mem_region(&aux_dev->dev, pdata->region_start, 0x800, aux_dev->name))
491 return -EBUSY;
492
493 priv->reg_base = devm_ioremap(&aux_dev->dev, pdata->region_start, 0x800);
494 if (!priv->reg_base)
495 return -ENOMEM;
496
497 writel(0x0264, (priv->reg_base + 0x400 + 0xF0));
498
499 retval = pci1xxxx_gpio_setup(priv, pdata->irq_num);
500
501 if (retval < 0)
502 return retval;
503
504 retval = pci1xxxx_gpio_get_device_revision(priv);
505 if (retval)
506 return retval;
507
508 dev_set_drvdata(&aux_dev->dev, priv);
509
510 return devm_gpiochip_add_data(&aux_dev->dev, &priv->gpio, priv);
511 }
512
513 static DEFINE_SIMPLE_DEV_PM_OPS(pci1xxxx_gpio_pm_ops, pci1xxxx_gpio_suspend, pci1xxxx_gpio_resume);
514
515 static const struct auxiliary_device_id pci1xxxx_gpio_auxiliary_id_table[] = {
516 {.name = "mchp_pci1xxxx_gp.gp_gpio"},
517 {}
518 };
519 MODULE_DEVICE_TABLE(auxiliary, pci1xxxx_gpio_auxiliary_id_table);
520
521 static struct auxiliary_driver pci1xxxx_gpio_driver = {
522 .driver = {
523 .name = "PCI1xxxxGPIO",
524 .pm = &pci1xxxx_gpio_pm_ops,
525 },
526 .probe = pci1xxxx_gpio_probe,
527 .id_table = pci1xxxx_gpio_auxiliary_id_table
528 };
529 module_auxiliary_driver(pci1xxxx_gpio_driver);
530
531 MODULE_DESCRIPTION("Microchip Technology Inc. PCI1xxxx GPIO controller");
532 MODULE_AUTHOR("Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>");
533 MODULE_LICENSE("GPL");
534