1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 */
5
6 #include <linux/bitfield.h>
7 #include <linux/irq.h>
8 #include <linux/irqchip.h>
9 #include <linux/irqchip/chained_irq.h>
10 #include <linux/irqdomain.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_address.h>
14 #include <linux/of_irq.h>
15
16 /* FIC Registers */
17 #define AL_FIC_CAUSE 0x00
18 #define AL_FIC_SET_CAUSE 0x08
19 #define AL_FIC_MASK 0x10
20 #define AL_FIC_CONTROL 0x28
21
22 #define CONTROL_TRIGGER_RISING BIT(3)
23 #define CONTROL_MASK_MSI_X BIT(5)
24
25 #define NR_FIC_IRQS 32
26
27 MODULE_AUTHOR("Talel Shenhar");
28 MODULE_DESCRIPTION("Amazon's Annapurna Labs Interrupt Controller Driver");
29
30 enum al_fic_state {
31 AL_FIC_UNCONFIGURED = 0,
32 AL_FIC_CONFIGURED_LEVEL,
33 AL_FIC_CONFIGURED_RISING_EDGE,
34 };
35
36 struct al_fic {
37 void __iomem *base;
38 struct irq_domain *domain;
39 const char *name;
40 unsigned int parent_irq;
41 enum al_fic_state state;
42 };
43
al_fic_set_trigger(struct al_fic * fic,struct irq_chip_generic * gc,enum al_fic_state new_state)44 static void al_fic_set_trigger(struct al_fic *fic,
45 struct irq_chip_generic *gc,
46 enum al_fic_state new_state)
47 {
48 irq_flow_handler_t handler;
49 u32 control = readl_relaxed(fic->base + AL_FIC_CONTROL);
50
51 if (new_state == AL_FIC_CONFIGURED_LEVEL) {
52 handler = handle_level_irq;
53 control &= ~CONTROL_TRIGGER_RISING;
54 } else {
55 handler = handle_edge_irq;
56 control |= CONTROL_TRIGGER_RISING;
57 }
58 gc->chip_types->handler = handler;
59 fic->state = new_state;
60 writel_relaxed(control, fic->base + AL_FIC_CONTROL);
61 }
62
al_fic_irq_set_type(struct irq_data * data,unsigned int flow_type)63 static int al_fic_irq_set_type(struct irq_data *data, unsigned int flow_type)
64 {
65 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
66 struct al_fic *fic = gc->private;
67 enum al_fic_state new_state;
68
69 guard(raw_spinlock)(&gc->lock);
70
71 if (((flow_type & IRQ_TYPE_SENSE_MASK) != IRQ_TYPE_LEVEL_HIGH) &&
72 ((flow_type & IRQ_TYPE_SENSE_MASK) != IRQ_TYPE_EDGE_RISING)) {
73 pr_debug("fic doesn't support flow type %d\n", flow_type);
74 return -EINVAL;
75 }
76
77 new_state = (flow_type & IRQ_TYPE_LEVEL_HIGH) ?
78 AL_FIC_CONFIGURED_LEVEL : AL_FIC_CONFIGURED_RISING_EDGE;
79
80 /*
81 * A given FIC instance can be either all level or all edge triggered.
82 * This is generally fixed depending on what pieces of HW it's wired up
83 * to.
84 *
85 * We configure it based on the sensitivity of the first source
86 * being setup, and reject any subsequent attempt at configuring it in a
87 * different way.
88 */
89 if (fic->state == AL_FIC_UNCONFIGURED) {
90 al_fic_set_trigger(fic, gc, new_state);
91 } else if (fic->state != new_state) {
92 pr_debug("fic %s state already configured to %d\n", fic->name, fic->state);
93 return -EINVAL;
94 }
95 return 0;
96 }
97
al_fic_irq_handler(struct irq_desc * desc)98 static void al_fic_irq_handler(struct irq_desc *desc)
99 {
100 struct al_fic *fic = irq_desc_get_handler_data(desc);
101 struct irq_domain *domain = fic->domain;
102 struct irq_chip *irqchip = irq_desc_get_chip(desc);
103 struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0);
104 unsigned long pending;
105 u32 hwirq;
106
107 chained_irq_enter(irqchip, desc);
108
109 pending = readl_relaxed(fic->base + AL_FIC_CAUSE);
110 pending &= ~gc->mask_cache;
111
112 for_each_set_bit(hwirq, &pending, NR_FIC_IRQS)
113 generic_handle_domain_irq(domain, hwirq);
114
115 chained_irq_exit(irqchip, desc);
116 }
117
al_fic_irq_retrigger(struct irq_data * data)118 static int al_fic_irq_retrigger(struct irq_data *data)
119 {
120 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
121 struct al_fic *fic = gc->private;
122
123 writel_relaxed(BIT(data->hwirq), fic->base + AL_FIC_SET_CAUSE);
124
125 return 1;
126 }
127
al_fic_register(struct device_node * node,struct al_fic * fic)128 static int al_fic_register(struct device_node *node,
129 struct al_fic *fic)
130 {
131 struct irq_chip_generic *gc;
132 int ret;
133
134 fic->domain = irq_domain_create_linear(of_fwnode_handle(node),
135 NR_FIC_IRQS,
136 &irq_generic_chip_ops,
137 fic);
138 if (!fic->domain) {
139 pr_err("fail to add irq domain\n");
140 return -ENOMEM;
141 }
142
143 ret = irq_alloc_domain_generic_chips(fic->domain,
144 NR_FIC_IRQS,
145 1, fic->name,
146 handle_level_irq,
147 0, 0, IRQ_GC_INIT_MASK_CACHE);
148 if (ret) {
149 pr_err("fail to allocate generic chip (%d)\n", ret);
150 goto err_domain_remove;
151 }
152
153 gc = irq_get_domain_generic_chip(fic->domain, 0);
154 gc->reg_base = fic->base;
155 gc->chip_types->regs.mask = AL_FIC_MASK;
156 gc->chip_types->regs.ack = AL_FIC_CAUSE;
157 gc->chip_types->chip.irq_mask = irq_gc_mask_set_bit;
158 gc->chip_types->chip.irq_unmask = irq_gc_mask_clr_bit;
159 gc->chip_types->chip.irq_ack = irq_gc_ack_clr_bit;
160 gc->chip_types->chip.irq_set_type = al_fic_irq_set_type;
161 gc->chip_types->chip.irq_retrigger = al_fic_irq_retrigger;
162 gc->chip_types->chip.flags = IRQCHIP_SKIP_SET_WAKE;
163 gc->private = fic;
164
165 irq_set_chained_handler_and_data(fic->parent_irq,
166 al_fic_irq_handler,
167 fic);
168 return 0;
169
170 err_domain_remove:
171 irq_domain_remove(fic->domain);
172
173 return ret;
174 }
175
176 /*
177 * al_fic_wire_init() - initialize and configure fic in wire mode
178 * @of_node: optional pointer to interrupt controller's device tree node.
179 * @base: mmio to fic register
180 * @name: name of the fic
181 * @parent_irq: interrupt of parent
182 *
183 * This API will configure the fic hardware to to work in wire mode.
184 * In wire mode, fic hardware is generating a wire ("wired") interrupt.
185 * Interrupt can be generated based on positive edge or level - configuration is
186 * to be determined based on connected hardware to this fic.
187 */
al_fic_wire_init(struct device_node * node,void __iomem * base,const char * name,unsigned int parent_irq)188 static struct al_fic *al_fic_wire_init(struct device_node *node,
189 void __iomem *base,
190 const char *name,
191 unsigned int parent_irq)
192 {
193 struct al_fic *fic;
194 int ret;
195 u32 control = CONTROL_MASK_MSI_X;
196
197 fic = kzalloc(sizeof(*fic), GFP_KERNEL);
198 if (!fic)
199 return ERR_PTR(-ENOMEM);
200
201 fic->base = base;
202 fic->parent_irq = parent_irq;
203 fic->name = name;
204
205 /* mask out all interrupts */
206 writel_relaxed(0xFFFFFFFF, fic->base + AL_FIC_MASK);
207
208 /* clear any pending interrupt */
209 writel_relaxed(0, fic->base + AL_FIC_CAUSE);
210
211 writel_relaxed(control, fic->base + AL_FIC_CONTROL);
212
213 ret = al_fic_register(node, fic);
214 if (ret) {
215 pr_err("fail to register irqchip\n");
216 goto err_free;
217 }
218
219 pr_debug("%s initialized successfully in Legacy mode (parent-irq=%u)\n",
220 fic->name, parent_irq);
221
222 return fic;
223
224 err_free:
225 kfree(fic);
226 return ERR_PTR(ret);
227 }
228
al_fic_init_dt(struct device_node * node,struct device_node * parent)229 static int __init al_fic_init_dt(struct device_node *node,
230 struct device_node *parent)
231 {
232 int ret;
233 void __iomem *base;
234 unsigned int parent_irq;
235 struct al_fic *fic;
236
237 if (!parent) {
238 pr_err("%s: unsupported - device require a parent\n",
239 node->name);
240 return -EINVAL;
241 }
242
243 base = of_iomap(node, 0);
244 if (!base) {
245 pr_err("%s: fail to map memory\n", node->name);
246 return -ENOMEM;
247 }
248
249 parent_irq = irq_of_parse_and_map(node, 0);
250 if (!parent_irq) {
251 pr_err("%s: fail to map irq\n", node->name);
252 ret = -EINVAL;
253 goto err_unmap;
254 }
255
256 fic = al_fic_wire_init(node,
257 base,
258 node->name,
259 parent_irq);
260 if (IS_ERR(fic)) {
261 pr_err("%s: fail to initialize irqchip (%lu)\n",
262 node->name,
263 PTR_ERR(fic));
264 ret = PTR_ERR(fic);
265 goto err_irq_dispose;
266 }
267
268 return 0;
269
270 err_irq_dispose:
271 irq_dispose_mapping(parent_irq);
272 err_unmap:
273 iounmap(base);
274
275 return ret;
276 }
277
278 IRQCHIP_DECLARE(al_fic, "amazon,al-fic", al_fic_init_dt);
279