1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * RZ/G2L A/D Converter driver
4 *
5 * Copyright (c) 2021 Renesas Electronics Europe GmbH
6 *
7 * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
8 */
9
10 #include <linux/bitfield.h>
11 #include <linux/cleanup.h>
12 #include <linux/completion.h>
13 #include <linux/delay.h>
14 #include <linux/iio/adc-helpers.h>
15 #include <linux/iio/iio.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/iopoll.h>
19 #include <linux/mod_devicetable.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/property.h>
24 #include <linux/reset.h>
25
26 #define DRIVER_NAME "rzg2l-adc"
27
28 #define RZG2L_ADM(n) ((n) * 0x4)
29 #define RZG2L_ADM0_ADCE BIT(0)
30 #define RZG2L_ADM0_ADBSY BIT(1)
31 #define RZG2L_ADM0_PWDWNB BIT(2)
32 #define RZG2L_ADM0_SRESB BIT(15)
33 #define RZG2L_ADM1_TRG BIT(0)
34 #define RZG2L_ADM1_MS BIT(2)
35 #define RZG2L_ADM1_BS BIT(4)
36 #define RZG2L_ADM1_EGA_MASK GENMASK(13, 12)
37 #define RZG2L_ADM3_ADIL_MASK GENMASK(31, 24)
38 #define RZG2L_ADM3_ADCMP_MASK GENMASK(23, 16)
39
40 #define RZG2L_ADINT 0x20
41 #define RZG2L_ADINT_CSEEN BIT(16)
42 #define RZG2L_ADINT_INTS BIT(31)
43
44 #define RZG2L_ADSTS 0x24
45 #define RZG2L_ADSTS_CSEST BIT(16)
46
47 #define RZG2L_ADIVC 0x28
48 #define RZG2L_ADIVC_DIVADC_MASK GENMASK(8, 0)
49 #define RZG2L_ADIVC_DIVADC_4 FIELD_PREP(RZG2L_ADIVC_DIVADC_MASK, 0x4)
50
51 #define RZG2L_ADFIL 0x2c
52
53 #define RZG2L_ADCR(n) (0x30 + ((n) * 0x4))
54 #define RZG2L_ADCR_AD_MASK GENMASK(11, 0)
55
56 #define RZG2L_ADC_MAX_CHANNELS 9
57 #define RZG2L_ADC_TIMEOUT usecs_to_jiffies(1 * 4)
58
59 /**
60 * struct rzg2l_adc_hw_params - ADC hardware specific parameters
61 * @default_adsmp: default ADC sampling period (see ADM3 register); index 0 is
62 * used for voltage channels, index 1 is used for temperature channel
63 * @adsmp_mask: ADC sampling period mask (see ADM3 register)
64 * @adint_inten_mask: conversion end interrupt mask (see ADINT register)
65 * @default_adcmp: default ADC cmp (see ADM3 register)
66 * @num_channels: number of supported channels
67 * @adivc: specifies if ADVIC register is available
68 */
69 struct rzg2l_adc_hw_params {
70 u16 default_adsmp[2];
71 u16 adsmp_mask;
72 u16 adint_inten_mask;
73 u8 default_adcmp;
74 u8 num_channels;
75 bool adivc;
76 };
77
78 struct rzg2l_adc_data {
79 const struct iio_chan_spec *channels;
80 u8 num_channels;
81 };
82
83 struct rzg2l_adc {
84 void __iomem *base;
85 struct reset_control *presetn;
86 struct reset_control *adrstn;
87 const struct rzg2l_adc_data *data;
88 const struct rzg2l_adc_hw_params *hw_params;
89 struct completion completion;
90 struct mutex lock;
91 u16 last_val[RZG2L_ADC_MAX_CHANNELS];
92 bool was_rpm_active;
93 };
94
95 /**
96 * struct rzg2l_adc_channel - ADC channel descriptor
97 * @name: ADC channel name
98 * @type: ADC channel type
99 */
100 struct rzg2l_adc_channel {
101 const char * const name;
102 enum iio_chan_type type;
103 };
104
105 static const struct rzg2l_adc_channel rzg2l_adc_channels[] = {
106 { "adc0", IIO_VOLTAGE },
107 { "adc1", IIO_VOLTAGE },
108 { "adc2", IIO_VOLTAGE },
109 { "adc3", IIO_VOLTAGE },
110 { "adc4", IIO_VOLTAGE },
111 { "adc5", IIO_VOLTAGE },
112 { "adc6", IIO_VOLTAGE },
113 { "adc7", IIO_VOLTAGE },
114 { "adc8", IIO_TEMP },
115 };
116
rzg2l_adc_readl(struct rzg2l_adc * adc,u32 reg)117 static unsigned int rzg2l_adc_readl(struct rzg2l_adc *adc, u32 reg)
118 {
119 return readl(adc->base + reg);
120 }
121
rzg2l_adc_writel(struct rzg2l_adc * adc,unsigned int reg,u32 val)122 static void rzg2l_adc_writel(struct rzg2l_adc *adc, unsigned int reg, u32 val)
123 {
124 writel(val, adc->base + reg);
125 }
126
rzg2l_adc_pwr(struct rzg2l_adc * adc,bool on)127 static void rzg2l_adc_pwr(struct rzg2l_adc *adc, bool on)
128 {
129 u32 reg;
130
131 reg = rzg2l_adc_readl(adc, RZG2L_ADM(0));
132 if (on)
133 reg |= RZG2L_ADM0_PWDWNB;
134 else
135 reg &= ~RZG2L_ADM0_PWDWNB;
136 rzg2l_adc_writel(adc, RZG2L_ADM(0), reg);
137 udelay(2);
138 }
139
rzg2l_adc_start_stop(struct rzg2l_adc * adc,bool start)140 static void rzg2l_adc_start_stop(struct rzg2l_adc *adc, bool start)
141 {
142 int ret;
143 u32 reg;
144
145 reg = rzg2l_adc_readl(adc, RZG2L_ADM(0));
146 if (start)
147 reg |= RZG2L_ADM0_ADCE;
148 else
149 reg &= ~RZG2L_ADM0_ADCE;
150 rzg2l_adc_writel(adc, RZG2L_ADM(0), reg);
151
152 if (start)
153 return;
154
155 ret = read_poll_timeout(rzg2l_adc_readl, reg, !(reg & (RZG2L_ADM0_ADBSY | RZG2L_ADM0_ADCE)),
156 200, 1000, true, adc, RZG2L_ADM(0));
157 if (ret)
158 pr_err("%s stopping ADC timed out\n", __func__);
159 }
160
rzg2l_set_trigger(struct rzg2l_adc * adc)161 static void rzg2l_set_trigger(struct rzg2l_adc *adc)
162 {
163 u32 reg;
164
165 /*
166 * Setup ADM1 for SW trigger
167 * EGA[13:12] - Set 00 to indicate hardware trigger is invalid
168 * BS[4] - Enable 1-buffer mode
169 * MS[1] - Enable Select mode
170 * TRG[0] - Enable software trigger mode
171 */
172 reg = rzg2l_adc_readl(adc, RZG2L_ADM(1));
173 reg &= ~RZG2L_ADM1_EGA_MASK;
174 reg &= ~RZG2L_ADM1_BS;
175 reg &= ~RZG2L_ADM1_TRG;
176 reg |= RZG2L_ADM1_MS;
177 rzg2l_adc_writel(adc, RZG2L_ADM(1), reg);
178 }
179
rzg2l_adc_ch_to_adsmp_index(u8 ch)180 static u8 rzg2l_adc_ch_to_adsmp_index(u8 ch)
181 {
182 if (rzg2l_adc_channels[ch].type == IIO_VOLTAGE)
183 return 0;
184
185 return 1;
186 }
187
rzg2l_adc_conversion_setup(struct rzg2l_adc * adc,u8 ch)188 static int rzg2l_adc_conversion_setup(struct rzg2l_adc *adc, u8 ch)
189 {
190 const struct rzg2l_adc_hw_params *hw_params = adc->hw_params;
191 u8 index = rzg2l_adc_ch_to_adsmp_index(ch);
192 u32 reg;
193
194 if (rzg2l_adc_readl(adc, RZG2L_ADM(0)) & RZG2L_ADM0_ADBSY)
195 return -EBUSY;
196
197 rzg2l_set_trigger(adc);
198
199 /* Select analog input channel subjected to conversion. */
200 reg = rzg2l_adc_readl(adc, RZG2L_ADM(2));
201 reg &= ~GENMASK(hw_params->num_channels - 1, 0);
202 reg |= BIT(ch);
203 rzg2l_adc_writel(adc, RZG2L_ADM(2), reg);
204
205 reg = rzg2l_adc_readl(adc, RZG2L_ADM(3));
206 reg &= ~hw_params->adsmp_mask;
207 reg |= hw_params->default_adsmp[index];
208 rzg2l_adc_writel(adc, RZG2L_ADM(3), reg);
209
210 /*
211 * Setup ADINT
212 * INTS[31] - Select pulse signal
213 * CSEEN[16] - Enable channel select error interrupt
214 * INTEN[7:0] - Select channel interrupt
215 */
216 reg = rzg2l_adc_readl(adc, RZG2L_ADINT);
217 reg &= ~RZG2L_ADINT_INTS;
218 reg &= ~hw_params->adint_inten_mask;
219 reg |= (RZG2L_ADINT_CSEEN | BIT(ch));
220 rzg2l_adc_writel(adc, RZG2L_ADINT, reg);
221
222 return 0;
223 }
224
rzg2l_adc_conversion(struct iio_dev * indio_dev,struct rzg2l_adc * adc,u8 ch)225 static int rzg2l_adc_conversion(struct iio_dev *indio_dev, struct rzg2l_adc *adc, u8 ch)
226 {
227 const struct rzg2l_adc_hw_params *hw_params = adc->hw_params;
228 struct device *dev = indio_dev->dev.parent;
229 int ret;
230
231 ret = pm_runtime_resume_and_get(dev);
232 if (ret)
233 return ret;
234
235 ret = rzg2l_adc_conversion_setup(adc, ch);
236 if (ret)
237 goto rpm_put;
238
239 reinit_completion(&adc->completion);
240
241 rzg2l_adc_start_stop(adc, true);
242
243 if (!wait_for_completion_timeout(&adc->completion, RZG2L_ADC_TIMEOUT)) {
244 rzg2l_adc_writel(adc, RZG2L_ADINT,
245 rzg2l_adc_readl(adc, RZG2L_ADINT) & ~hw_params->adint_inten_mask);
246 ret = -ETIMEDOUT;
247 }
248
249 rzg2l_adc_start_stop(adc, false);
250
251 rpm_put:
252 pm_runtime_mark_last_busy(dev);
253 pm_runtime_put_autosuspend(dev);
254 return ret;
255 }
256
rzg2l_adc_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)257 static int rzg2l_adc_read_raw(struct iio_dev *indio_dev,
258 struct iio_chan_spec const *chan,
259 int *val, int *val2, long mask)
260 {
261 struct rzg2l_adc *adc = iio_priv(indio_dev);
262 int ret;
263
264 switch (mask) {
265 case IIO_CHAN_INFO_RAW: {
266 if (chan->type != IIO_VOLTAGE && chan->type != IIO_TEMP)
267 return -EINVAL;
268
269 guard(mutex)(&adc->lock);
270
271 ret = rzg2l_adc_conversion(indio_dev, adc, chan->channel);
272 if (ret)
273 return ret;
274
275 *val = adc->last_val[chan->channel];
276
277 return IIO_VAL_INT;
278 }
279
280 default:
281 return -EINVAL;
282 }
283 }
284
rzg2l_adc_read_label(struct iio_dev * iio_dev,const struct iio_chan_spec * chan,char * label)285 static int rzg2l_adc_read_label(struct iio_dev *iio_dev,
286 const struct iio_chan_spec *chan,
287 char *label)
288 {
289 return sysfs_emit(label, "%s\n", rzg2l_adc_channels[chan->channel].name);
290 }
291
292 static const struct iio_info rzg2l_adc_iio_info = {
293 .read_raw = rzg2l_adc_read_raw,
294 .read_label = rzg2l_adc_read_label,
295 };
296
rzg2l_adc_isr(int irq,void * dev_id)297 static irqreturn_t rzg2l_adc_isr(int irq, void *dev_id)
298 {
299 struct rzg2l_adc *adc = dev_id;
300 const struct rzg2l_adc_hw_params *hw_params = adc->hw_params;
301 unsigned long intst;
302 u32 reg;
303 int ch;
304
305 reg = rzg2l_adc_readl(adc, RZG2L_ADSTS);
306
307 /* A/D conversion channel select error interrupt */
308 if (reg & RZG2L_ADSTS_CSEST) {
309 rzg2l_adc_writel(adc, RZG2L_ADSTS, reg);
310 return IRQ_HANDLED;
311 }
312
313 intst = reg & GENMASK(hw_params->num_channels - 1, 0);
314 if (!intst)
315 return IRQ_NONE;
316
317 for_each_set_bit(ch, &intst, hw_params->num_channels)
318 adc->last_val[ch] = rzg2l_adc_readl(adc, RZG2L_ADCR(ch)) & RZG2L_ADCR_AD_MASK;
319
320 /* clear the channel interrupt */
321 rzg2l_adc_writel(adc, RZG2L_ADSTS, reg);
322
323 complete(&adc->completion);
324
325 return IRQ_HANDLED;
326 }
327
328 static const struct iio_chan_spec rzg2l_adc_chan_template = {
329 .indexed = 1,
330 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
331 };
332
rzg2l_adc_parse_properties(struct platform_device * pdev,struct rzg2l_adc * adc)333 static int rzg2l_adc_parse_properties(struct platform_device *pdev, struct rzg2l_adc *adc)
334 {
335 const struct rzg2l_adc_hw_params *hw_params = adc->hw_params;
336 struct iio_chan_spec *chan_array;
337 struct rzg2l_adc_data *data;
338 int num_channels;
339 u8 i;
340
341 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
342 if (!data)
343 return -ENOMEM;
344
345 num_channels = devm_iio_adc_device_alloc_chaninfo_se(&pdev->dev,
346 &rzg2l_adc_chan_template,
347 hw_params->num_channels - 1,
348 &chan_array);
349 if (num_channels < 0)
350 return num_channels;
351
352 if (num_channels > hw_params->num_channels)
353 return dev_err_probe(&pdev->dev, -EINVAL,
354 "num of channel children out of range\n");
355
356 for (i = 0; i < num_channels; i++) {
357 int channel = chan_array[i].channel;
358
359 chan_array[i].datasheet_name = rzg2l_adc_channels[channel].name;
360 chan_array[i].type = rzg2l_adc_channels[channel].type;
361 }
362
363 data->num_channels = num_channels;
364 data->channels = chan_array;
365 adc->data = data;
366
367 return 0;
368 }
369
rzg2l_adc_hw_init(struct device * dev,struct rzg2l_adc * adc)370 static int rzg2l_adc_hw_init(struct device *dev, struct rzg2l_adc *adc)
371 {
372 const struct rzg2l_adc_hw_params *hw_params = adc->hw_params;
373 u32 reg;
374 int ret;
375
376 ret = pm_runtime_resume_and_get(dev);
377 if (ret)
378 return ret;
379
380 /* SW reset */
381 reg = rzg2l_adc_readl(adc, RZG2L_ADM(0));
382 reg |= RZG2L_ADM0_SRESB;
383 rzg2l_adc_writel(adc, RZG2L_ADM(0), reg);
384
385 ret = read_poll_timeout(rzg2l_adc_readl, reg, reg & RZG2L_ADM0_SRESB,
386 200, 1000, false, adc, RZG2L_ADM(0));
387 if (ret)
388 goto exit_hw_init;
389
390 if (hw_params->adivc) {
391 /* Only division by 4 can be set */
392 reg = rzg2l_adc_readl(adc, RZG2L_ADIVC);
393 reg &= ~RZG2L_ADIVC_DIVADC_MASK;
394 reg |= RZG2L_ADIVC_DIVADC_4;
395 rzg2l_adc_writel(adc, RZG2L_ADIVC, reg);
396 }
397
398 /*
399 * Setup AMD3
400 * ADIL[31:24] - Should be always set to 0
401 * ADCMP[23:16] - Should be always set to 0xe
402 * ADSMP[15:0] - Set default (0x578) sampling period
403 */
404 reg = rzg2l_adc_readl(adc, RZG2L_ADM(3));
405 reg &= ~RZG2L_ADM3_ADIL_MASK;
406 reg &= ~RZG2L_ADM3_ADCMP_MASK;
407 reg &= ~hw_params->adsmp_mask;
408 reg |= FIELD_PREP(RZG2L_ADM3_ADCMP_MASK, hw_params->default_adcmp) |
409 hw_params->default_adsmp[0];
410
411 rzg2l_adc_writel(adc, RZG2L_ADM(3), reg);
412
413 exit_hw_init:
414 pm_runtime_mark_last_busy(dev);
415 pm_runtime_put_autosuspend(dev);
416 return ret;
417 }
418
rzg2l_adc_probe(struct platform_device * pdev)419 static int rzg2l_adc_probe(struct platform_device *pdev)
420 {
421 struct device *dev = &pdev->dev;
422 struct iio_dev *indio_dev;
423 struct rzg2l_adc *adc;
424 int ret;
425 int irq;
426
427 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
428 if (!indio_dev)
429 return -ENOMEM;
430
431 adc = iio_priv(indio_dev);
432
433 adc->hw_params = device_get_match_data(dev);
434 if (!adc->hw_params || adc->hw_params->num_channels > RZG2L_ADC_MAX_CHANNELS)
435 return -EINVAL;
436
437 ret = rzg2l_adc_parse_properties(pdev, adc);
438 if (ret)
439 return ret;
440
441 mutex_init(&adc->lock);
442
443 adc->base = devm_platform_ioremap_resource(pdev, 0);
444 if (IS_ERR(adc->base))
445 return PTR_ERR(adc->base);
446
447 adc->adrstn = devm_reset_control_get_exclusive_deasserted(dev, "adrst-n");
448 if (IS_ERR(adc->adrstn))
449 return dev_err_probe(dev, PTR_ERR(adc->adrstn),
450 "failed to get/deassert adrst-n\n");
451
452 adc->presetn = devm_reset_control_get_exclusive_deasserted(dev, "presetn");
453 if (IS_ERR(adc->presetn))
454 return dev_err_probe(dev, PTR_ERR(adc->presetn),
455 "failed to get/deassert presetn\n");
456
457 pm_runtime_set_autosuspend_delay(dev, 300);
458 pm_runtime_use_autosuspend(dev);
459 ret = devm_pm_runtime_enable(dev);
460 if (ret)
461 return ret;
462
463 platform_set_drvdata(pdev, indio_dev);
464
465 ret = rzg2l_adc_hw_init(dev, adc);
466 if (ret)
467 return dev_err_probe(&pdev->dev, ret,
468 "failed to initialize ADC HW\n");
469
470 irq = platform_get_irq(pdev, 0);
471 if (irq < 0)
472 return irq;
473
474 ret = devm_request_irq(dev, irq, rzg2l_adc_isr,
475 0, dev_name(dev), adc);
476 if (ret < 0)
477 return ret;
478
479 init_completion(&adc->completion);
480
481 indio_dev->name = DRIVER_NAME;
482 indio_dev->info = &rzg2l_adc_iio_info;
483 indio_dev->modes = INDIO_DIRECT_MODE;
484 indio_dev->channels = adc->data->channels;
485 indio_dev->num_channels = adc->data->num_channels;
486
487 return devm_iio_device_register(dev, indio_dev);
488 }
489
490 static const struct rzg2l_adc_hw_params rzg2l_hw_params = {
491 .num_channels = 8,
492 .default_adcmp = 0xe,
493 .default_adsmp = { 0x578 },
494 .adsmp_mask = GENMASK(15, 0),
495 .adint_inten_mask = GENMASK(7, 0),
496 .adivc = true
497 };
498
499 static const struct rzg2l_adc_hw_params rzg3s_hw_params = {
500 .num_channels = 9,
501 .default_adcmp = 0x1d,
502 .default_adsmp = { 0x7f, 0xff },
503 .adsmp_mask = GENMASK(7, 0),
504 .adint_inten_mask = GENMASK(11, 0),
505 };
506
507 static const struct of_device_id rzg2l_adc_match[] = {
508 { .compatible = "renesas,r9a08g045-adc", .data = &rzg3s_hw_params },
509 { .compatible = "renesas,rzg2l-adc", .data = &rzg2l_hw_params },
510 { }
511 };
512 MODULE_DEVICE_TABLE(of, rzg2l_adc_match);
513
rzg2l_adc_pm_runtime_suspend(struct device * dev)514 static int rzg2l_adc_pm_runtime_suspend(struct device *dev)
515 {
516 struct iio_dev *indio_dev = dev_get_drvdata(dev);
517 struct rzg2l_adc *adc = iio_priv(indio_dev);
518
519 rzg2l_adc_pwr(adc, false);
520
521 return 0;
522 }
523
rzg2l_adc_pm_runtime_resume(struct device * dev)524 static int rzg2l_adc_pm_runtime_resume(struct device *dev)
525 {
526 struct iio_dev *indio_dev = dev_get_drvdata(dev);
527 struct rzg2l_adc *adc = iio_priv(indio_dev);
528
529 rzg2l_adc_pwr(adc, true);
530
531 return 0;
532 }
533
rzg2l_adc_suspend(struct device * dev)534 static int rzg2l_adc_suspend(struct device *dev)
535 {
536 struct iio_dev *indio_dev = dev_get_drvdata(dev);
537 struct rzg2l_adc *adc = iio_priv(indio_dev);
538 struct reset_control_bulk_data resets[] = {
539 { .rstc = adc->presetn },
540 { .rstc = adc->adrstn },
541 };
542 int ret;
543
544 if (pm_runtime_suspended(dev)) {
545 adc->was_rpm_active = false;
546 } else {
547 ret = pm_runtime_force_suspend(dev);
548 if (ret)
549 return ret;
550 adc->was_rpm_active = true;
551 }
552
553 ret = reset_control_bulk_assert(ARRAY_SIZE(resets), resets);
554 if (ret)
555 goto rpm_restore;
556
557 return 0;
558
559 rpm_restore:
560 if (adc->was_rpm_active)
561 pm_runtime_force_resume(dev);
562
563 return ret;
564 }
565
rzg2l_adc_resume(struct device * dev)566 static int rzg2l_adc_resume(struct device *dev)
567 {
568 struct iio_dev *indio_dev = dev_get_drvdata(dev);
569 struct rzg2l_adc *adc = iio_priv(indio_dev);
570 struct reset_control_bulk_data resets[] = {
571 { .rstc = adc->adrstn },
572 { .rstc = adc->presetn },
573 };
574 int ret;
575
576 ret = reset_control_bulk_deassert(ARRAY_SIZE(resets), resets);
577 if (ret)
578 return ret;
579
580 if (adc->was_rpm_active) {
581 ret = pm_runtime_force_resume(dev);
582 if (ret)
583 goto resets_restore;
584 }
585
586 ret = rzg2l_adc_hw_init(dev, adc);
587 if (ret)
588 goto rpm_restore;
589
590 return 0;
591
592 rpm_restore:
593 if (adc->was_rpm_active) {
594 pm_runtime_mark_last_busy(dev);
595 pm_runtime_put_autosuspend(dev);
596 }
597 resets_restore:
598 reset_control_bulk_assert(ARRAY_SIZE(resets), resets);
599 return ret;
600 }
601
602 static const struct dev_pm_ops rzg2l_adc_pm_ops = {
603 RUNTIME_PM_OPS(rzg2l_adc_pm_runtime_suspend, rzg2l_adc_pm_runtime_resume, NULL)
604 SYSTEM_SLEEP_PM_OPS(rzg2l_adc_suspend, rzg2l_adc_resume)
605 };
606
607 static struct platform_driver rzg2l_adc_driver = {
608 .probe = rzg2l_adc_probe,
609 .driver = {
610 .name = DRIVER_NAME,
611 .of_match_table = rzg2l_adc_match,
612 .pm = pm_ptr(&rzg2l_adc_pm_ops),
613 },
614 };
615
616 module_platform_driver(rzg2l_adc_driver);
617
618 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
619 MODULE_DESCRIPTION("Renesas RZ/G2L ADC driver");
620 MODULE_LICENSE("GPL v2");
621 MODULE_IMPORT_NS("IIO_DRIVER");
622