1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 /*
3 * Analog Devices MAX14001/MAX14002 ADC driver
4 *
5 * Copyright (C) 2023-2025 Analog Devices Inc.
6 * Copyright (C) 2023 Kim Seer Paller <kimseer.paller@analog.com>
7 * Copyright (c) 2025 Marilene Andrade Garcia <marilene.agarcia@gmail.com>
8 *
9 * Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/MAX14001-MAX14002.pdf
10 */
11
12 #include <linux/array_size.h>
13 #include <linux/bitfield.h>
14 #include <linux/bitrev.h>
15 #include <linux/bits.h>
16 #include <linux/cleanup.h>
17 #include <linux/device.h>
18 #include <linux/mod_devicetable.h>
19 #include <linux/module.h>
20 #include <linux/regmap.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/spi/spi.h>
23 #include <linux/types.h>
24 #include <linux/units.h>
25 #include <asm/byteorder.h>
26
27 #include <linux/iio/iio.h>
28 #include <linux/iio/types.h>
29
30 /* MAX14001 Registers Address */
31 #define MAX14001_REG_ADC 0x00
32 #define MAX14001_REG_FADC 0x01
33 #define MAX14001_REG_FLAGS 0x02
34 #define MAX14001_REG_FLTEN 0x03
35 #define MAX14001_REG_THL 0x04
36 #define MAX14001_REG_THU 0x05
37 #define MAX14001_REG_INRR 0x06
38 #define MAX14001_REG_INRT 0x07
39 #define MAX14001_REG_INRP 0x08
40 #define MAX14001_REG_CFG 0x09
41 #define MAX14001_REG_ENBL 0x0A
42 #define MAX14001_REG_ACT 0x0B
43 #define MAX14001_REG_WEN 0x0C
44
45 #define MAX14001_REG_VERIFICATION(x) ((x) + 0x10)
46
47 #define MAX14001_REG_CFG_BIT_EXRF BIT(5)
48
49 #define MAX14001_REG_WEN_VALUE_WRITE 0x294
50
51 #define MAX14001_MASK_ADDR GENMASK(15, 11)
52 #define MAX14001_MASK_WR BIT(10)
53 #define MAX14001_MASK_DATA GENMASK(9, 0)
54
55 struct max14001_state {
56 const struct max14001_chip_info *chip_info;
57 struct spi_device *spi;
58 struct regmap *regmap;
59 int vref_mV;
60 bool spi_hw_has_lsb_first;
61
62 /*
63 * The following buffers will be bit-reversed during device
64 * communication, because the device transmits and receives data
65 * LSB-first.
66 * DMA (thus cache coherency maintenance) requires the transfer
67 * buffers to live in their own cache lines.
68 */
69 union {
70 __be16 be;
71 __le16 le;
72 } spi_tx_buffer __aligned(IIO_DMA_MINALIGN);
73
74 union {
75 __be16 be;
76 __le16 le;
77 } spi_rx_buffer;
78 };
79
80 struct max14001_chip_info {
81 const char *name;
82 };
83
max14001_read(void * context,unsigned int reg,unsigned int * val)84 static int max14001_read(void *context, unsigned int reg, unsigned int *val)
85 {
86 struct max14001_state *st = context;
87 struct spi_transfer xfers[] = {
88 {
89 .tx_buf = &st->spi_tx_buffer,
90 .len = sizeof(st->spi_tx_buffer),
91 .cs_change = 1,
92 }, {
93 .rx_buf = &st->spi_rx_buffer,
94 .len = sizeof(st->spi_rx_buffer),
95 },
96 };
97 int ret;
98 unsigned int addr, data;
99
100 /*
101 * Prepare SPI transmit buffer 16 bit-value and reverse bit order
102 * to align with the LSB-first input on SDI port in order to meet
103 * the device communication requirements. If the controller supports
104 * SPI_LSB_FIRST, this step will be handled by the SPI controller.
105 */
106 addr = FIELD_PREP(MAX14001_MASK_ADDR, reg);
107
108 if (st->spi_hw_has_lsb_first)
109 st->spi_tx_buffer.le = cpu_to_le16(addr);
110 else
111 st->spi_tx_buffer.be = cpu_to_be16(bitrev16(addr));
112
113 ret = spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers));
114 if (ret)
115 return ret;
116
117 /*
118 * Convert received 16-bit value to cpu-endian format and reverse
119 * bit order. If the controller supports SPI_LSB_FIRST, this step
120 * will be handled by the SPI controller.
121 */
122 if (st->spi_hw_has_lsb_first)
123 data = le16_to_cpu(st->spi_rx_buffer.le);
124 else
125 data = bitrev16(be16_to_cpu(st->spi_rx_buffer.be));
126
127 *val = FIELD_GET(MAX14001_MASK_DATA, data);
128
129 return 0;
130 }
131
max14001_write(struct max14001_state * st,unsigned int reg,unsigned int val)132 static int max14001_write(struct max14001_state *st, unsigned int reg, unsigned int val)
133 {
134 unsigned int addr;
135
136 /*
137 * Prepare SPI transmit buffer 16 bit-value and reverse bit order
138 * to align with the LSB-first input on SDI port in order to meet
139 * the device communication requirements. If the controller supports
140 * SPI_LSB_FIRST, this step will be handled by the SPI controller.
141 */
142 addr = FIELD_PREP(MAX14001_MASK_ADDR, reg) |
143 FIELD_PREP(MAX14001_MASK_WR, 1) |
144 FIELD_PREP(MAX14001_MASK_DATA, val);
145
146 if (st->spi_hw_has_lsb_first)
147 st->spi_tx_buffer.le = cpu_to_le16(addr);
148 else
149 st->spi_tx_buffer.be = cpu_to_be16(bitrev16(addr));
150
151 return spi_write(st->spi, &st->spi_tx_buffer, sizeof(st->spi_tx_buffer));
152 }
153
max14001_write_single_reg(void * context,unsigned int reg,unsigned int val)154 static int max14001_write_single_reg(void *context, unsigned int reg, unsigned int val)
155 {
156 struct max14001_state *st = context;
157 int ret;
158
159 /* Enable writing to the SPI register. */
160 ret = max14001_write(st, MAX14001_REG_WEN, MAX14001_REG_WEN_VALUE_WRITE);
161 if (ret)
162 return ret;
163
164 /* Writing data into SPI register. */
165 ret = max14001_write(st, reg, val);
166 if (ret)
167 return ret;
168
169 /* Disable writing to the SPI register. */
170 return max14001_write(st, MAX14001_REG_WEN, 0);
171 }
172
max14001_write_verification_reg(struct max14001_state * st,unsigned int reg)173 static int max14001_write_verification_reg(struct max14001_state *st, unsigned int reg)
174 {
175 unsigned int val;
176 int ret;
177
178 ret = regmap_read(st->regmap, reg, &val);
179 if (ret)
180 return ret;
181
182 return max14001_write(st, MAX14001_REG_VERIFICATION(reg), val);
183 }
184
max14001_disable_mv_fault(struct max14001_state * st)185 static int max14001_disable_mv_fault(struct max14001_state *st)
186 {
187 unsigned int reg;
188 int ret;
189
190 /* Enable writing to the SPI registers. */
191 ret = max14001_write(st, MAX14001_REG_WEN, MAX14001_REG_WEN_VALUE_WRITE);
192 if (ret)
193 return ret;
194
195 /*
196 * Reads all registers and writes the values to their appropriate
197 * verification registers to clear the Memory Validation fault.
198 */
199 for (reg = MAX14001_REG_FLTEN; reg <= MAX14001_REG_ENBL; reg++) {
200 ret = max14001_write_verification_reg(st, reg);
201 if (ret)
202 return ret;
203 }
204
205 /* Disable writing to the SPI registers. */
206 return max14001_write(st, MAX14001_REG_WEN, 0);
207 }
208
max14001_debugfs_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)209 static int max14001_debugfs_reg_access(struct iio_dev *indio_dev,
210 unsigned int reg, unsigned int writeval,
211 unsigned int *readval)
212 {
213 struct max14001_state *st = iio_priv(indio_dev);
214
215 if (readval)
216 return regmap_read(st->regmap, reg, readval);
217
218 return regmap_write(st->regmap, reg, writeval);
219 }
220
max14001_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)221 static int max14001_read_raw(struct iio_dev *indio_dev,
222 struct iio_chan_spec const *chan,
223 int *val, int *val2, long mask)
224 {
225 struct max14001_state *st = iio_priv(indio_dev);
226 int ret;
227
228 switch (mask) {
229 case IIO_CHAN_INFO_RAW:
230 ret = regmap_read(st->regmap, MAX14001_REG_ADC, val);
231 if (ret)
232 return ret;
233
234 return IIO_VAL_INT;
235 case IIO_CHAN_INFO_SCALE:
236 *val = st->vref_mV;
237 *val2 = 10;
238
239 return IIO_VAL_FRACTIONAL_LOG2;
240 default:
241 return -EINVAL;
242 }
243 }
244
245 static const struct regmap_range max14001_regmap_rd_range[] = {
246 regmap_reg_range(MAX14001_REG_ADC, MAX14001_REG_ENBL),
247 regmap_reg_range(MAX14001_REG_WEN, MAX14001_REG_WEN),
248 regmap_reg_range(MAX14001_REG_VERIFICATION(MAX14001_REG_FLTEN),
249 MAX14001_REG_VERIFICATION(MAX14001_REG_ENBL)),
250 };
251
252 static const struct regmap_access_table max14001_regmap_rd_table = {
253 .yes_ranges = max14001_regmap_rd_range,
254 .n_yes_ranges = ARRAY_SIZE(max14001_regmap_rd_range),
255 };
256
257 static const struct regmap_range max14001_regmap_wr_range[] = {
258 regmap_reg_range(MAX14001_REG_FLTEN, MAX14001_REG_WEN),
259 regmap_reg_range(MAX14001_REG_VERIFICATION(MAX14001_REG_FLTEN),
260 MAX14001_REG_VERIFICATION(MAX14001_REG_ENBL)),
261 };
262
263 static const struct regmap_access_table max14001_regmap_wr_table = {
264 .yes_ranges = max14001_regmap_wr_range,
265 .n_yes_ranges = ARRAY_SIZE(max14001_regmap_wr_range),
266 };
267
268 static const struct regmap_config max14001_regmap_config = {
269 .reg_read = max14001_read,
270 .reg_write = max14001_write_single_reg,
271 .max_register = MAX14001_REG_VERIFICATION(MAX14001_REG_ENBL),
272 .rd_table = &max14001_regmap_rd_table,
273 .wr_table = &max14001_regmap_wr_table,
274 };
275
276 static const struct iio_info max14001_info = {
277 .read_raw = max14001_read_raw,
278 .debugfs_reg_access = max14001_debugfs_reg_access,
279 };
280
281 static const struct iio_chan_spec max14001_channel[] = {
282 {
283 .type = IIO_VOLTAGE,
284 .indexed = 1,
285 .channel = 0,
286 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
287 BIT(IIO_CHAN_INFO_SCALE),
288 },
289 };
290
max14001_probe(struct spi_device * spi)291 static int max14001_probe(struct spi_device *spi)
292 {
293 struct device *dev = &spi->dev;
294 struct iio_dev *indio_dev;
295 struct max14001_state *st;
296 int ret;
297 bool use_ext_vrefin = false;
298
299 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
300 if (!indio_dev)
301 return -ENOMEM;
302
303 st = iio_priv(indio_dev);
304 st->spi = spi;
305 st->spi_hw_has_lsb_first = spi->mode & SPI_LSB_FIRST;
306 st->chip_info = spi_get_device_match_data(spi);
307 if (!st->chip_info)
308 return -EINVAL;
309
310 indio_dev->name = st->chip_info->name;
311 indio_dev->info = &max14001_info;
312 indio_dev->channels = max14001_channel;
313 indio_dev->num_channels = ARRAY_SIZE(max14001_channel);
314 indio_dev->modes = INDIO_DIRECT_MODE;
315
316 st->regmap = devm_regmap_init(dev, NULL, st, &max14001_regmap_config);
317 if (IS_ERR(st->regmap))
318 return dev_err_probe(dev, PTR_ERR(st->regmap), "Failed to initialize regmap\n");
319
320 ret = devm_regulator_get_enable(dev, "vdd");
321 if (ret)
322 return dev_err_probe(dev, ret, "Failed to enable Vdd supply\n");
323
324 ret = devm_regulator_get_enable(dev, "vddl");
325 if (ret)
326 return dev_err_probe(dev, ret, "Failed to enable Vddl supply\n");
327
328 ret = devm_regulator_get_enable_read_voltage(dev, "refin");
329 if (ret < 0 && ret != -ENODEV)
330 return dev_err_probe(dev, ret, "Failed to get REFIN voltage\n");
331
332 if (ret == -ENODEV)
333 ret = 1250000;
334 else
335 use_ext_vrefin = true;
336 st->vref_mV = ret / (MICRO / MILLI);
337
338 if (use_ext_vrefin) {
339 /*
340 * Configure the MAX14001/MAX14002 to use an external voltage
341 * reference source by setting the bit 5 of the configuration register.
342 */
343 ret = regmap_set_bits(st->regmap, MAX14001_REG_CFG,
344 MAX14001_REG_CFG_BIT_EXRF);
345 if (ret)
346 return dev_err_probe(dev, ret,
347 "Failed to set External REFIN in Configuration Register\n");
348 }
349
350 ret = max14001_disable_mv_fault(st);
351 if (ret)
352 return dev_err_probe(dev, ret, "Failed to disable MV Fault\n");
353
354 return devm_iio_device_register(dev, indio_dev);
355 }
356
357 static struct max14001_chip_info max14001_chip_info = {
358 .name = "max14001",
359 };
360
361 static struct max14001_chip_info max14002_chip_info = {
362 .name = "max14002",
363 };
364
365 static const struct spi_device_id max14001_id_table[] = {
366 { "max14001", (kernel_ulong_t)&max14001_chip_info },
367 { "max14002", (kernel_ulong_t)&max14002_chip_info },
368 { }
369 };
370
371 static const struct of_device_id max14001_of_match[] = {
372 { .compatible = "adi,max14001", .data = &max14001_chip_info },
373 { .compatible = "adi,max14002", .data = &max14002_chip_info },
374 { }
375 };
376 MODULE_DEVICE_TABLE(of, max14001_of_match);
377
378 static struct spi_driver max14001_driver = {
379 .driver = {
380 .name = "max14001",
381 .of_match_table = max14001_of_match,
382 },
383 .probe = max14001_probe,
384 .id_table = max14001_id_table,
385 };
386 module_spi_driver(max14001_driver);
387
388 MODULE_AUTHOR("Kim Seer Paller <kimseer.paller@analog.com>");
389 MODULE_AUTHOR("Marilene Andrade Garcia <marilene.agarcia@gmail.com>");
390 MODULE_DESCRIPTION("Analog Devices MAX14001/MAX14002 ADCs driver");
391 MODULE_LICENSE("GPL");
392