1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * AD4000 SPI ADC driver
4 *
5 * Copyright 2024 Analog Devices Inc.
6 */
7 #include <linux/bits.h>
8 #include <linux/bitfield.h>
9 #include <linux/byteorder/generic.h>
10 #include <linux/cleanup.h>
11 #include <linux/device.h>
12 #include <linux/err.h>
13 #include <linux/math.h>
14 #include <linux/module.h>
15 #include <linux/mod_devicetable.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/spi/offload/consumer.h>
19 #include <linux/spi/spi.h>
20 #include <linux/units.h>
21 #include <linux/util_macros.h>
22
23 #include <linux/iio/iio.h>
24 #include <linux/iio/buffer.h>
25 #include <linux/iio/buffer-dmaengine.h>
26 #include <linux/iio/triggered_buffer.h>
27 #include <linux/iio/trigger_consumer.h>
28
29 #define AD4000_READ_COMMAND 0x54
30 #define AD4000_WRITE_COMMAND 0x14
31
32 #define AD4000_CONFIG_REG_DEFAULT 0xE1
33
34 /* AD4000 Configuration Register programmable bits */
35 #define AD4000_CFG_SPAN_COMP BIT(3) /* Input span compression */
36 #define AD4000_CFG_HIGHZ BIT(2) /* High impedance mode */
37 #define AD4000_CFG_TURBO BIT(1) /* Turbo mode */
38
39 #define AD4000_SCALE_OPTIONS 2
40
41 #define __AD4000_DIFF_CHANNEL(_sign, _real_bits, _storage_bits, _reg_access, _offl)\
42 { \
43 .type = IIO_VOLTAGE, \
44 .indexed = 1, \
45 .differential = 1, \
46 .channel = 0, \
47 .channel2 = 1, \
48 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
49 BIT(IIO_CHAN_INFO_SCALE) | \
50 (_offl ? BIT(IIO_CHAN_INFO_SAMP_FREQ) : 0), \
51 .info_mask_separate_available = _reg_access ? BIT(IIO_CHAN_INFO_SCALE) : 0,\
52 .scan_index = 0, \
53 .scan_type = { \
54 .sign = _sign, \
55 .realbits = _real_bits, \
56 .storagebits = _storage_bits, \
57 .shift = (_offl ? 0 : _storage_bits - _real_bits), \
58 .endianness = _offl ? IIO_CPU : IIO_BE \
59 }, \
60 }
61
62 #define AD4000_DIFF_CHANNEL(_sign, _real_bits, _reg_access, _offl) \
63 __AD4000_DIFF_CHANNEL((_sign), (_real_bits), \
64 (((_offl) || ((_real_bits) > 16)) ? 32 : 16), \
65 (_reg_access), (_offl))
66
67 /*
68 * When SPI offload is configured, transfers are executed without CPU
69 * intervention so no soft timestamp can be recorded when transfers run.
70 * Because of that, the macros that set timestamp channel are only used when
71 * transfers are not offloaded.
72 */
73 #define AD4000_DIFF_CHANNELS(_sign, _real_bits, _reg_access) \
74 { \
75 AD4000_DIFF_CHANNEL(_sign, _real_bits, _reg_access, 0), \
76 IIO_CHAN_SOFT_TIMESTAMP(1), \
77 }
78
79 #define __AD4000_PSEUDO_DIFF_CHANNEL(_sign, _real_bits, _storage_bits, \
80 _reg_access, _offl) \
81 { \
82 .type = IIO_VOLTAGE, \
83 .indexed = 1, \
84 .channel = 0, \
85 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
86 BIT(IIO_CHAN_INFO_SCALE) | \
87 BIT(IIO_CHAN_INFO_OFFSET) | \
88 (_offl ? BIT(IIO_CHAN_INFO_SAMP_FREQ) : 0), \
89 .info_mask_separate_available = _reg_access ? BIT(IIO_CHAN_INFO_SCALE) : 0,\
90 .scan_index = 0, \
91 .scan_type = { \
92 .sign = _sign, \
93 .realbits = _real_bits, \
94 .storagebits = _storage_bits, \
95 .shift = (_offl ? 0 : _storage_bits - _real_bits), \
96 .endianness = _offl ? IIO_CPU : IIO_BE \
97 }, \
98 }
99
100 #define AD4000_PSEUDO_DIFF_CHANNEL(_sign, _real_bits, _reg_access, _offl) \
101 __AD4000_PSEUDO_DIFF_CHANNEL((_sign), (_real_bits), \
102 (((_offl) || ((_real_bits) > 16)) ? 32 : 16),\
103 (_reg_access), (_offl))
104
105 #define AD4000_PSEUDO_DIFF_CHANNELS(_sign, _real_bits, _reg_access) \
106 { \
107 AD4000_PSEUDO_DIFF_CHANNEL(_sign, _real_bits, _reg_access, 0), \
108 IIO_CHAN_SOFT_TIMESTAMP(1), \
109 }
110
111 static const char * const ad4000_power_supplies[] = {
112 "vdd", "vio"
113 };
114
115 enum ad4000_sdi {
116 AD4000_SDI_MOSI,
117 AD4000_SDI_VIO,
118 AD4000_SDI_CS,
119 AD4000_SDI_GND,
120 };
121
122 /* maps adi,sdi-pin property value to enum */
123 static const char * const ad4000_sdi_pin[] = {
124 [AD4000_SDI_MOSI] = "sdi",
125 [AD4000_SDI_VIO] = "high",
126 [AD4000_SDI_CS] = "cs",
127 [AD4000_SDI_GND] = "low",
128 };
129
130 /* Gains stored as fractions of 1000 so they can be expressed by integers. */
131 static const int ad4000_gains[] = {
132 454, 909, 1000, 1900,
133 };
134
135 struct ad4000_time_spec {
136 int t_conv_ns;
137 int t_quiet2_ns;
138 };
139
140 /*
141 * Same timing specifications for all of AD4000, AD4001, ..., AD4008, AD4010,
142 * ADAQ4001, and ADAQ4003.
143 */
144 static const struct ad4000_time_spec ad4000_t_spec = {
145 .t_conv_ns = 320,
146 .t_quiet2_ns = 60,
147 };
148
149 /* AD4020, AD4021, AD4022 */
150 static const struct ad4000_time_spec ad4020_t_spec = {
151 .t_conv_ns = 350,
152 .t_quiet2_ns = 60,
153 };
154
155 /* AD7983, AD7984 */
156 static const struct ad4000_time_spec ad7983_t_spec = {
157 .t_conv_ns = 500,
158 .t_quiet2_ns = 0,
159 };
160
161 /* AD7980, AD7982 */
162 static const struct ad4000_time_spec ad7980_t_spec = {
163 .t_conv_ns = 800,
164 .t_quiet2_ns = 0,
165 };
166
167 /* AD7946, AD7686, AD7688, AD7988-5, AD7693 */
168 static const struct ad4000_time_spec ad7686_t_spec = {
169 .t_conv_ns = 1600,
170 .t_quiet2_ns = 0,
171 };
172
173 /* AD7690 */
174 static const struct ad4000_time_spec ad7690_t_spec = {
175 .t_conv_ns = 2100,
176 .t_quiet2_ns = 0,
177 };
178
179 /* AD7942, AD7685, AD7687 */
180 static const struct ad4000_time_spec ad7687_t_spec = {
181 .t_conv_ns = 3200,
182 .t_quiet2_ns = 0,
183 };
184
185 /* AD7691 */
186 static const struct ad4000_time_spec ad7691_t_spec = {
187 .t_conv_ns = 3700,
188 .t_quiet2_ns = 0,
189 };
190
191 /* AD7988-1 */
192 static const struct ad4000_time_spec ad7988_1_t_spec = {
193 .t_conv_ns = 9500,
194 .t_quiet2_ns = 0,
195 };
196
197 struct ad4000_chip_info {
198 const char *dev_name;
199 struct iio_chan_spec chan_spec[2];
200 struct iio_chan_spec reg_access_chan_spec[2];
201 struct iio_chan_spec offload_chan_spec;
202 struct iio_chan_spec reg_access_offload_chan_spec;
203 const struct ad4000_time_spec *time_spec;
204 bool has_hardware_gain;
205 int max_rate_hz;
206 };
207
208 static const struct ad4000_chip_info ad4000_chip_info = {
209 .dev_name = "ad4000",
210 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0),
211 .reg_access_chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 1),
212 .offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 0, 1),
213 .reg_access_offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 1, 1),
214 .time_spec = &ad4000_t_spec,
215 .max_rate_hz = 2 * MEGA,
216 };
217
218 static const struct ad4000_chip_info ad4001_chip_info = {
219 .dev_name = "ad4001",
220 .chan_spec = AD4000_DIFF_CHANNELS('s', 16, 0),
221 .reg_access_chan_spec = AD4000_DIFF_CHANNELS('s', 16, 1),
222 .offload_chan_spec = AD4000_DIFF_CHANNEL('s', 16, 0, 1),
223 .reg_access_offload_chan_spec = AD4000_DIFF_CHANNEL('s', 16, 1, 1),
224 .time_spec = &ad4000_t_spec,
225 .max_rate_hz = 2 * MEGA,
226 };
227
228 static const struct ad4000_chip_info ad4002_chip_info = {
229 .dev_name = "ad4002",
230 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 0),
231 .reg_access_chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 1),
232 .offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 18, 0, 1),
233 .reg_access_offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 18, 1, 1),
234 .time_spec = &ad4000_t_spec,
235 .max_rate_hz = 2 * MEGA,
236 };
237
238 static const struct ad4000_chip_info ad4003_chip_info = {
239 .dev_name = "ad4003",
240 .chan_spec = AD4000_DIFF_CHANNELS('s', 18, 0),
241 .reg_access_chan_spec = AD4000_DIFF_CHANNELS('s', 18, 1),
242 .offload_chan_spec = AD4000_DIFF_CHANNEL('s', 18, 0, 1),
243 .reg_access_offload_chan_spec = AD4000_DIFF_CHANNEL('s', 18, 1, 1),
244 .time_spec = &ad4000_t_spec,
245 .max_rate_hz = 2 * MEGA,
246 };
247
248 static const struct ad4000_chip_info ad4004_chip_info = {
249 .dev_name = "ad4004",
250 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0),
251 .reg_access_chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 1),
252 .offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 0, 1),
253 .reg_access_offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 1, 1),
254 .time_spec = &ad4000_t_spec,
255 .max_rate_hz = 1 * MEGA,
256 };
257
258 static const struct ad4000_chip_info ad4005_chip_info = {
259 .dev_name = "ad4005",
260 .chan_spec = AD4000_DIFF_CHANNELS('s', 16, 0),
261 .reg_access_chan_spec = AD4000_DIFF_CHANNELS('s', 16, 1),
262 .offload_chan_spec = AD4000_DIFF_CHANNEL('s', 16, 0, 1),
263 .reg_access_offload_chan_spec = AD4000_DIFF_CHANNEL('s', 16, 1, 1),
264 .time_spec = &ad4000_t_spec,
265 .max_rate_hz = 1 * MEGA,
266 };
267
268 static const struct ad4000_chip_info ad4006_chip_info = {
269 .dev_name = "ad4006",
270 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 0),
271 .reg_access_chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 1),
272 .offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 18, 0, 1),
273 .reg_access_offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 18, 1, 1),
274 .time_spec = &ad4000_t_spec,
275 .max_rate_hz = 1 * MEGA,
276 };
277
278 static const struct ad4000_chip_info ad4007_chip_info = {
279 .dev_name = "ad4007",
280 .chan_spec = AD4000_DIFF_CHANNELS('s', 18, 0),
281 .reg_access_chan_spec = AD4000_DIFF_CHANNELS('s', 18, 1),
282 .offload_chan_spec = AD4000_DIFF_CHANNEL('s', 18, 0, 1),
283 .reg_access_offload_chan_spec = AD4000_DIFF_CHANNEL('s', 18, 1, 1),
284 .time_spec = &ad4000_t_spec,
285 .max_rate_hz = 1 * MEGA,
286 };
287
288 static const struct ad4000_chip_info ad4008_chip_info = {
289 .dev_name = "ad4008",
290 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0),
291 .reg_access_chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 1),
292 .offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 0, 1),
293 .reg_access_offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 1, 1),
294 .time_spec = &ad4000_t_spec,
295 .max_rate_hz = 500 * KILO,
296 };
297
298 static const struct ad4000_chip_info ad4010_chip_info = {
299 .dev_name = "ad4010",
300 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 0),
301 .reg_access_chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 1),
302 .offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 18, 0, 1),
303 .reg_access_offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 18, 1, 1),
304 .time_spec = &ad4000_t_spec,
305 .max_rate_hz = 500 * KILO,
306 };
307
308 static const struct ad4000_chip_info ad4011_chip_info = {
309 .dev_name = "ad4011",
310 .chan_spec = AD4000_DIFF_CHANNELS('s', 18, 0),
311 .reg_access_chan_spec = AD4000_DIFF_CHANNELS('s', 18, 1),
312 .offload_chan_spec = AD4000_DIFF_CHANNEL('s', 18, 0, 1),
313 .reg_access_offload_chan_spec = AD4000_DIFF_CHANNEL('s', 18, 1, 1),
314 .time_spec = &ad4000_t_spec,
315 .max_rate_hz = 500 * KILO,
316 };
317
318 static const struct ad4000_chip_info ad4020_chip_info = {
319 .dev_name = "ad4020",
320 .chan_spec = AD4000_DIFF_CHANNELS('s', 20, 0),
321 .reg_access_chan_spec = AD4000_DIFF_CHANNELS('s', 20, 1),
322 .offload_chan_spec = AD4000_DIFF_CHANNEL('s', 20, 0, 1),
323 .reg_access_offload_chan_spec = AD4000_DIFF_CHANNEL('s', 20, 1, 1),
324 .time_spec = &ad4020_t_spec,
325 .max_rate_hz = 1800 * KILO,
326 };
327
328 static const struct ad4000_chip_info ad4021_chip_info = {
329 .dev_name = "ad4021",
330 .chan_spec = AD4000_DIFF_CHANNELS('s', 20, 0),
331 .reg_access_chan_spec = AD4000_DIFF_CHANNELS('s', 20, 1),
332 .offload_chan_spec = AD4000_DIFF_CHANNEL('s', 20, 0, 1),
333 .reg_access_offload_chan_spec = AD4000_DIFF_CHANNEL('s', 20, 1, 1),
334 .time_spec = &ad4020_t_spec,
335 .max_rate_hz = 1 * MEGA,
336 };
337
338 static const struct ad4000_chip_info ad4022_chip_info = {
339 .dev_name = "ad4022",
340 .chan_spec = AD4000_DIFF_CHANNELS('s', 20, 0),
341 .reg_access_chan_spec = AD4000_DIFF_CHANNELS('s', 20, 1),
342 .offload_chan_spec = AD4000_DIFF_CHANNEL('s', 20, 0, 1),
343 .reg_access_offload_chan_spec = AD4000_DIFF_CHANNEL('s', 20, 1, 1),
344 .time_spec = &ad4020_t_spec,
345 .max_rate_hz = 500 * KILO,
346 };
347
348 static const struct ad4000_chip_info adaq4001_chip_info = {
349 .dev_name = "adaq4001",
350 .chan_spec = AD4000_DIFF_CHANNELS('s', 16, 0),
351 .reg_access_chan_spec = AD4000_DIFF_CHANNELS('s', 16, 1),
352 .offload_chan_spec = AD4000_DIFF_CHANNEL('s', 16, 0, 1),
353 .reg_access_offload_chan_spec = AD4000_DIFF_CHANNEL('s', 16, 1, 1),
354 .time_spec = &ad4000_t_spec,
355 .has_hardware_gain = true,
356 .max_rate_hz = 2 * MEGA,
357 };
358
359 static const struct ad4000_chip_info adaq4003_chip_info = {
360 .dev_name = "adaq4003",
361 .chan_spec = AD4000_DIFF_CHANNELS('s', 18, 0),
362 .reg_access_chan_spec = AD4000_DIFF_CHANNELS('s', 18, 1),
363 .offload_chan_spec = AD4000_DIFF_CHANNEL('s', 18, 0, 1),
364 .reg_access_offload_chan_spec = AD4000_DIFF_CHANNEL('s', 18, 1, 1),
365 .time_spec = &ad4000_t_spec,
366 .has_hardware_gain = true,
367 .max_rate_hz = 2 * MEGA,
368 };
369
370 static const struct ad4000_chip_info ad7685_chip_info = {
371 .dev_name = "ad7685",
372 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0),
373 .offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 0, 1),
374 .time_spec = &ad7687_t_spec,
375 .max_rate_hz = 250 * KILO,
376 };
377
378 static const struct ad4000_chip_info ad7686_chip_info = {
379 .dev_name = "ad7686",
380 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0),
381 .offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 0, 1),
382 .time_spec = &ad7686_t_spec,
383 .max_rate_hz = 500 * KILO,
384 };
385
386 static const struct ad4000_chip_info ad7687_chip_info = {
387 .dev_name = "ad7687",
388 .chan_spec = AD4000_DIFF_CHANNELS('s', 16, 0),
389 .offload_chan_spec = AD4000_DIFF_CHANNEL('s', 16, 0, 1),
390 .time_spec = &ad7687_t_spec,
391 .max_rate_hz = 250 * KILO,
392 };
393
394 static const struct ad4000_chip_info ad7688_chip_info = {
395 .dev_name = "ad7688",
396 .chan_spec = AD4000_DIFF_CHANNELS('s', 16, 0),
397 .offload_chan_spec = AD4000_DIFF_CHANNEL('s', 16, 0, 1),
398 .time_spec = &ad7686_t_spec,
399 .max_rate_hz = 500 * KILO,
400 };
401
402 static const struct ad4000_chip_info ad7690_chip_info = {
403 .dev_name = "ad7690",
404 .chan_spec = AD4000_DIFF_CHANNELS('s', 18, 0),
405 .offload_chan_spec = AD4000_DIFF_CHANNEL('s', 18, 0, 1),
406 .time_spec = &ad7690_t_spec,
407 .max_rate_hz = 400 * KILO,
408 };
409
410 static const struct ad4000_chip_info ad7691_chip_info = {
411 .dev_name = "ad7691",
412 .chan_spec = AD4000_DIFF_CHANNELS('s', 18, 0),
413 .offload_chan_spec = AD4000_DIFF_CHANNEL('s', 18, 0, 1),
414 .time_spec = &ad7691_t_spec,
415 .max_rate_hz = 250 * KILO,
416 };
417
418 static const struct ad4000_chip_info ad7693_chip_info = {
419 .dev_name = "ad7693",
420 .chan_spec = AD4000_DIFF_CHANNELS('s', 16, 0),
421 .offload_chan_spec = AD4000_DIFF_CHANNEL('s', 16, 0, 1),
422 .time_spec = &ad7686_t_spec,
423 .max_rate_hz = 500 * KILO,
424 };
425
426 static const struct ad4000_chip_info ad7942_chip_info = {
427 .dev_name = "ad7942",
428 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 14, 0),
429 .offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 14, 0, 1),
430 .time_spec = &ad7687_t_spec,
431 .max_rate_hz = 250 * KILO,
432 };
433
434 static const struct ad4000_chip_info ad7946_chip_info = {
435 .dev_name = "ad7946",
436 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 14, 0),
437 .offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 14, 0, 1),
438 .time_spec = &ad7686_t_spec,
439 .max_rate_hz = 500 * KILO,
440 };
441
442 static const struct ad4000_chip_info ad7980_chip_info = {
443 .dev_name = "ad7980",
444 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0),
445 .offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 0, 1),
446 .time_spec = &ad7980_t_spec,
447 .max_rate_hz = 1 * MEGA,
448 };
449
450 static const struct ad4000_chip_info ad7982_chip_info = {
451 .dev_name = "ad7982",
452 .chan_spec = AD4000_DIFF_CHANNELS('s', 18, 0),
453 .offload_chan_spec = AD4000_DIFF_CHANNEL('s', 18, 0, 1),
454 .time_spec = &ad7980_t_spec,
455 .max_rate_hz = 1 * MEGA,
456 };
457
458 static const struct ad4000_chip_info ad7983_chip_info = {
459 .dev_name = "ad7983",
460 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0),
461 .offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 0, 1),
462 .time_spec = &ad7983_t_spec,
463 .max_rate_hz = 1 * MEGA + 333 * KILO + 333,
464 };
465
466 static const struct ad4000_chip_info ad7984_chip_info = {
467 .dev_name = "ad7984",
468 .chan_spec = AD4000_DIFF_CHANNELS('s', 18, 0),
469 .offload_chan_spec = AD4000_DIFF_CHANNEL('s', 18, 0, 1),
470 .time_spec = &ad7983_t_spec,
471 .max_rate_hz = 1 * MEGA + 333 * KILO + 333,
472 };
473
474 static const struct ad4000_chip_info ad7988_1_chip_info = {
475 .dev_name = "ad7988-1",
476 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0),
477 .offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 0, 1),
478 .time_spec = &ad7988_1_t_spec,
479 .max_rate_hz = 100 * KILO,
480 };
481
482 static const struct ad4000_chip_info ad7988_5_chip_info = {
483 .dev_name = "ad7988-5",
484 .chan_spec = AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0),
485 .offload_chan_spec = AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 0, 1),
486 .time_spec = &ad7686_t_spec,
487 .max_rate_hz = 500 * KILO,
488 };
489
490 static const struct spi_offload_config ad4000_offload_config = {
491 .capability_flags = SPI_OFFLOAD_CAP_TRIGGER |
492 SPI_OFFLOAD_CAP_RX_STREAM_DMA,
493 };
494
495 struct ad4000_state {
496 struct spi_device *spi;
497 struct gpio_desc *cnv_gpio;
498 struct spi_transfer xfers[2];
499 struct spi_message msg;
500 struct spi_transfer offload_xfer;
501 struct spi_message offload_msg;
502 struct spi_offload *offload;
503 struct spi_offload_trigger *offload_trigger;
504 bool using_offload;
505 unsigned long offload_trigger_hz;
506 int max_rate_hz;
507 struct mutex lock; /* Protect read modify write cycle */
508 int vref_mv;
509 enum ad4000_sdi sdi_pin;
510 bool span_comp;
511 u16 gain_milli;
512 int scale_tbl[AD4000_SCALE_OPTIONS][2];
513 const struct ad4000_time_spec *time_spec;
514
515 /*
516 * DMA (thus cache coherency maintenance) requires the transfer buffers
517 * to live in their own cache lines.
518 */
519 struct {
520 union {
521 __be16 sample_buf16_be;
522 __be32 sample_buf32_be;
523 u16 sample_buf16;
524 u32 sample_buf32;
525 } data;
526 aligned_s64 timestamp;
527 } scan __aligned(IIO_DMA_MINALIGN);
528 u8 tx_buf[2];
529 u8 rx_buf[2];
530 };
531
ad4000_fill_scale_tbl(struct ad4000_state * st,struct iio_chan_spec const * chan)532 static void ad4000_fill_scale_tbl(struct ad4000_state *st,
533 struct iio_chan_spec const *chan)
534 {
535 int val, tmp0, tmp1;
536 int scale_bits;
537 u64 tmp2;
538
539 /*
540 * ADCs that output two's complement code have one less bit to express
541 * voltage magnitude.
542 */
543 if (chan->scan_type.sign == 's')
544 scale_bits = chan->scan_type.realbits - 1;
545 else
546 scale_bits = chan->scan_type.realbits;
547
548 /*
549 * The gain is stored as a fraction of 1000 and, as we need to
550 * divide vref_mv by the gain, we invert the gain/1000 fraction.
551 * Also multiply by an extra MILLI to preserve precision.
552 * Thus, we have MILLI * MILLI equals MICRO as fraction numerator.
553 */
554 val = mult_frac(st->vref_mv, MICRO, st->gain_milli);
555
556 /* Would multiply by NANO here but we multiplied by extra MILLI */
557 tmp2 = shift_right((u64)val * MICRO, scale_bits);
558 tmp0 = div_s64_rem(tmp2, NANO, &tmp1);
559
560 /* Store scale for when span compression is disabled */
561 st->scale_tbl[0][0] = tmp0; /* Integer part */
562 st->scale_tbl[0][1] = abs(tmp1); /* Fractional part */
563
564 /* Store scale for when span compression is enabled */
565 st->scale_tbl[1][0] = tmp0;
566
567 /* The integer part is always zero so don't bother to divide it. */
568 if (chan->differential)
569 st->scale_tbl[1][1] = DIV_ROUND_CLOSEST(abs(tmp1) * 4, 5);
570 else
571 st->scale_tbl[1][1] = DIV_ROUND_CLOSEST(abs(tmp1) * 9, 10);
572 }
573
ad4000_write_reg(struct ad4000_state * st,uint8_t val)574 static int ad4000_write_reg(struct ad4000_state *st, uint8_t val)
575 {
576 st->tx_buf[0] = AD4000_WRITE_COMMAND;
577 st->tx_buf[1] = val;
578 return spi_write(st->spi, st->tx_buf, ARRAY_SIZE(st->tx_buf));
579 }
580
ad4000_read_reg(struct ad4000_state * st,unsigned int * val)581 static int ad4000_read_reg(struct ad4000_state *st, unsigned int *val)
582 {
583 struct spi_transfer t = {
584 .tx_buf = st->tx_buf,
585 .rx_buf = st->rx_buf,
586 .len = 2,
587 };
588 int ret;
589
590 st->tx_buf[0] = AD4000_READ_COMMAND;
591 ret = spi_sync_transfer(st->spi, &t, 1);
592 if (ret < 0)
593 return ret;
594
595 *val = st->rx_buf[1];
596 return ret;
597 }
598
ad4000_set_sampling_freq(struct ad4000_state * st,int freq)599 static int ad4000_set_sampling_freq(struct ad4000_state *st, int freq)
600 {
601 struct spi_offload_trigger_config config = {
602 .type = SPI_OFFLOAD_TRIGGER_PERIODIC,
603 .periodic = {
604 .frequency_hz = freq,
605 },
606 };
607 int ret;
608
609 ret = spi_offload_trigger_validate(st->offload_trigger, &config);
610 if (ret)
611 return ret;
612
613 st->offload_trigger_hz = config.periodic.frequency_hz;
614
615 return 0;
616 }
617
ad4000_convert_and_acquire(struct ad4000_state * st)618 static int ad4000_convert_and_acquire(struct ad4000_state *st)
619 {
620 int ret;
621
622 /*
623 * In 4-wire mode, the CNV line is held high for the entire conversion
624 * and acquisition process. In other modes, the CNV GPIO is optional
625 * and, if provided, replaces controller CS. If CNV GPIO is not defined
626 * gpiod_set_value_cansleep() has no effect.
627 */
628 gpiod_set_value_cansleep(st->cnv_gpio, 1);
629 ret = spi_sync(st->spi, &st->msg);
630 gpiod_set_value_cansleep(st->cnv_gpio, 0);
631
632 return ret;
633 }
634
ad4000_single_conversion(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * val)635 static int ad4000_single_conversion(struct iio_dev *indio_dev,
636 const struct iio_chan_spec *chan, int *val)
637 {
638 struct ad4000_state *st = iio_priv(indio_dev);
639 u32 sample;
640 int ret;
641
642 ret = ad4000_convert_and_acquire(st);
643 if (ret < 0)
644 return ret;
645
646 if (chan->scan_type.endianness == IIO_BE) {
647 if (chan->scan_type.realbits > 16)
648 sample = be32_to_cpu(st->scan.data.sample_buf32_be);
649 else
650 sample = be16_to_cpu(st->scan.data.sample_buf16_be);
651 } else {
652 if (chan->scan_type.realbits > 16)
653 sample = st->scan.data.sample_buf32;
654 else
655 sample = st->scan.data.sample_buf16;
656 }
657
658 sample >>= chan->scan_type.shift;
659
660 if (chan->scan_type.sign == 's')
661 *val = sign_extend32(sample, chan->scan_type.realbits - 1);
662 else
663 *val = sample;
664
665 return IIO_VAL_INT;
666 }
667
ad4000_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)668 static int ad4000_read_raw(struct iio_dev *indio_dev,
669 struct iio_chan_spec const *chan, int *val,
670 int *val2, long info)
671 {
672 struct ad4000_state *st = iio_priv(indio_dev);
673 int ret;
674
675 switch (info) {
676 case IIO_CHAN_INFO_RAW:
677 if (!iio_device_claim_direct(indio_dev))
678 return -EBUSY;
679
680 ret = ad4000_single_conversion(indio_dev, chan, val);
681 iio_device_release_direct(indio_dev);
682 return ret;
683 case IIO_CHAN_INFO_SCALE:
684 *val = st->scale_tbl[st->span_comp][0];
685 *val2 = st->scale_tbl[st->span_comp][1];
686 return IIO_VAL_INT_PLUS_NANO;
687 case IIO_CHAN_INFO_OFFSET:
688 *val = 0;
689 if (st->span_comp)
690 *val = mult_frac(st->vref_mv, 1, 10);
691
692 return IIO_VAL_INT;
693 case IIO_CHAN_INFO_SAMP_FREQ:
694 *val = st->offload_trigger_hz;
695 return IIO_VAL_INT;
696 default:
697 return -EINVAL;
698 }
699 }
700
ad4000_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long info)701 static int ad4000_read_avail(struct iio_dev *indio_dev,
702 struct iio_chan_spec const *chan,
703 const int **vals, int *type, int *length,
704 long info)
705 {
706 struct ad4000_state *st = iio_priv(indio_dev);
707
708 switch (info) {
709 case IIO_CHAN_INFO_SCALE:
710 *vals = (int *)st->scale_tbl;
711 *length = AD4000_SCALE_OPTIONS * 2;
712 *type = IIO_VAL_INT_PLUS_NANO;
713 return IIO_AVAIL_LIST;
714 default:
715 return -EINVAL;
716 }
717 }
718
ad4000_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)719 static int ad4000_write_raw_get_fmt(struct iio_dev *indio_dev,
720 struct iio_chan_spec const *chan, long mask)
721 {
722 switch (mask) {
723 case IIO_CHAN_INFO_SCALE:
724 return IIO_VAL_INT_PLUS_NANO;
725 default:
726 return IIO_VAL_INT_PLUS_MICRO;
727 }
728 }
729
__ad4000_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val2)730 static int __ad4000_write_raw(struct iio_dev *indio_dev,
731 struct iio_chan_spec const *chan,
732 int val2)
733 {
734 struct ad4000_state *st = iio_priv(indio_dev);
735 unsigned int reg_val;
736 bool span_comp_en;
737 int ret;
738
739 guard(mutex)(&st->lock);
740
741 ret = ad4000_read_reg(st, ®_val);
742 if (ret < 0)
743 return ret;
744
745 span_comp_en = val2 == st->scale_tbl[1][1];
746 reg_val &= ~AD4000_CFG_SPAN_COMP;
747 reg_val |= FIELD_PREP(AD4000_CFG_SPAN_COMP, span_comp_en);
748
749 ret = ad4000_write_reg(st, reg_val);
750 if (ret < 0)
751 return ret;
752
753 st->span_comp = span_comp_en;
754 return 0;
755 }
756
ad4000_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)757 static int ad4000_write_raw(struct iio_dev *indio_dev,
758 struct iio_chan_spec const *chan,
759 int val, int val2, long mask)
760 {
761 struct ad4000_state *st = iio_priv(indio_dev);
762 int ret;
763
764 switch (mask) {
765 case IIO_CHAN_INFO_SCALE:
766 if (!iio_device_claim_direct(indio_dev))
767 return -EBUSY;
768 ret = __ad4000_write_raw(indio_dev, chan, val2);
769 iio_device_release_direct(indio_dev);
770 return ret;
771 case IIO_CHAN_INFO_SAMP_FREQ:
772 if (val < 1 || val > st->max_rate_hz)
773 return -EINVAL;
774
775 if (!iio_device_claim_direct(indio_dev))
776 return -EBUSY;
777 ret = ad4000_set_sampling_freq(st, val);
778 iio_device_release_direct(indio_dev);
779 return ret;
780 default:
781 return -EINVAL;
782 }
783 }
784
ad4000_trigger_handler(int irq,void * p)785 static irqreturn_t ad4000_trigger_handler(int irq, void *p)
786 {
787 struct iio_poll_func *pf = p;
788 struct iio_dev *indio_dev = pf->indio_dev;
789 struct ad4000_state *st = iio_priv(indio_dev);
790 int ret;
791
792 ret = ad4000_convert_and_acquire(st);
793 if (ret < 0)
794 goto err_out;
795
796 iio_push_to_buffers_with_ts(indio_dev, &st->scan, sizeof(st->scan),
797 pf->timestamp);
798
799 err_out:
800 iio_trigger_notify_done(indio_dev->trig);
801 return IRQ_HANDLED;
802 }
803
804 static const struct iio_info ad4000_reg_access_info = {
805 .read_raw = &ad4000_read_raw,
806 .read_avail = &ad4000_read_avail,
807 .write_raw = &ad4000_write_raw,
808 .write_raw_get_fmt = &ad4000_write_raw_get_fmt,
809 };
810
811 static const struct iio_info ad4000_offload_info = {
812 .read_raw = &ad4000_read_raw,
813 .write_raw = &ad4000_write_raw,
814 .write_raw_get_fmt = &ad4000_write_raw_get_fmt,
815 };
816
817 static const struct iio_info ad4000_info = {
818 .read_raw = &ad4000_read_raw,
819 };
820
ad4000_offload_buffer_postenable(struct iio_dev * indio_dev)821 static int ad4000_offload_buffer_postenable(struct iio_dev *indio_dev)
822 {
823 struct ad4000_state *st = iio_priv(indio_dev);
824 struct spi_offload_trigger_config config = {
825 .type = SPI_OFFLOAD_TRIGGER_PERIODIC,
826 .periodic = {
827 .frequency_hz = st->offload_trigger_hz,
828 },
829 };
830
831 return spi_offload_trigger_enable(st->offload, st->offload_trigger,
832 &config);
833 }
834
ad4000_offload_buffer_predisable(struct iio_dev * indio_dev)835 static int ad4000_offload_buffer_predisable(struct iio_dev *indio_dev)
836 {
837 struct ad4000_state *st = iio_priv(indio_dev);
838
839 spi_offload_trigger_disable(st->offload, st->offload_trigger);
840
841 return 0;
842 }
843
844 static const struct iio_buffer_setup_ops ad4000_offload_buffer_setup_ops = {
845 .postenable = &ad4000_offload_buffer_postenable,
846 .predisable = &ad4000_offload_buffer_predisable,
847 };
848
ad4000_spi_offload_setup(struct iio_dev * indio_dev,struct ad4000_state * st)849 static int ad4000_spi_offload_setup(struct iio_dev *indio_dev,
850 struct ad4000_state *st)
851 {
852 struct spi_device *spi = st->spi;
853 struct device *dev = &spi->dev;
854 struct dma_chan *rx_dma;
855 int ret;
856
857 st->offload_trigger = devm_spi_offload_trigger_get(dev, st->offload,
858 SPI_OFFLOAD_TRIGGER_PERIODIC);
859 if (IS_ERR(st->offload_trigger))
860 return dev_err_probe(dev, PTR_ERR(st->offload_trigger),
861 "Failed to get offload trigger\n");
862
863 ret = ad4000_set_sampling_freq(st, st->max_rate_hz);
864 if (ret)
865 return dev_err_probe(dev, ret,
866 "Failed to set sampling frequency\n");
867
868 rx_dma = devm_spi_offload_rx_stream_request_dma_chan(dev, st->offload);
869 if (IS_ERR(rx_dma))
870 return dev_err_probe(dev, PTR_ERR(rx_dma),
871 "Failed to get offload RX DMA\n");
872
873 ret = devm_iio_dmaengine_buffer_setup_with_handle(dev, indio_dev, rx_dma,
874 IIO_BUFFER_DIRECTION_IN);
875 if (ret)
876 return dev_err_probe(dev, ret, "Failed to setup DMA buffer\n");
877
878 return 0;
879 }
880
881 /*
882 * This executes a data sample transfer when using SPI offloading. The device
883 * connections should be in "3-wire" mode, selected either when the adi,sdi-pin
884 * device tree property is absent or set to "high". Also, the ADC CNV pin must
885 * be connected to a SPI controller CS (it can't be connected to a GPIO).
886 *
887 * In order to achieve the maximum sample rate, we only do one transfer per
888 * SPI offload trigger. Because the ADC output has a one sample latency (delay)
889 * when the device is wired in "3-wire" mode and only one transfer per sample is
890 * being made in turbo mode, the first data sample is not valid because it
891 * contains the output of an earlier conversion result. We also set transfer
892 * `bits_per_word` to achieve higher throughput by using the minimum number of
893 * SCLK cycles. Also, a delay is added to make sure we meet the minimum quiet
894 * time before releasing the CS line.
895 *
896 * Note that, with `bits_per_word` set to the number of ADC precision bits,
897 * transfers use larger word sizes that get stored in 'in-memory wordsizes' that
898 * are always in native CPU byte order. Because of that, IIO buffer elements
899 * ought to be read in CPU endianness which requires setting IIO scan_type
900 * endianness accordingly (i.e. IIO_CPU).
901 */
ad4000_prepare_offload_message(struct ad4000_state * st,const struct iio_chan_spec * chan)902 static int ad4000_prepare_offload_message(struct ad4000_state *st,
903 const struct iio_chan_spec *chan)
904 {
905 struct spi_transfer *xfer = &st->offload_xfer;
906
907 xfer->bits_per_word = chan->scan_type.realbits;
908 xfer->len = chan->scan_type.realbits > 16 ? 4 : 2;
909 xfer->delay.value = st->time_spec->t_quiet2_ns;
910 xfer->delay.unit = SPI_DELAY_UNIT_NSECS;
911 xfer->offload_flags = SPI_OFFLOAD_XFER_RX_STREAM;
912
913 spi_message_init_with_transfers(&st->offload_msg, xfer, 1);
914 st->offload_msg.offload = st->offload;
915
916 return devm_spi_optimize_message(&st->spi->dev, st->spi, &st->offload_msg);
917 }
918
919 /*
920 * This executes a data sample transfer for when the device connections are
921 * in "3-wire" mode, selected when the adi,sdi-pin device tree property is
922 * absent or set to "high". In this connection mode, the ADC SDI pin is
923 * connected to MOSI or to VIO and ADC CNV pin is connected either to a SPI
924 * controller CS or to a GPIO.
925 * AD4000 series of devices initiate conversions on the rising edge of CNV pin.
926 *
927 * If the CNV pin is connected to an SPI controller CS line (which is by default
928 * active low), the ADC readings would have a latency (delay) of one read.
929 * Moreover, since we also do ADC sampling for filling the buffer on triggered
930 * buffer mode, the timestamps of buffer readings would be disarranged.
931 * To prevent the read latency and reduce the time discrepancy between the
932 * sample read request and the time of actual sampling by the ADC, do a
933 * preparatory transfer to pulse the CS/CNV line.
934 */
ad4000_prepare_3wire_mode_message(struct ad4000_state * st,const struct iio_chan_spec * chan)935 static int ad4000_prepare_3wire_mode_message(struct ad4000_state *st,
936 const struct iio_chan_spec *chan)
937 {
938 struct spi_transfer *xfers = st->xfers;
939
940 xfers[0].cs_change = 1;
941 xfers[0].cs_change_delay.value = st->time_spec->t_conv_ns;
942 xfers[0].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS;
943
944 xfers[1].rx_buf = &st->scan.data;
945 xfers[1].len = chan->scan_type.realbits > 16 ? 4 : 2;
946
947 /*
948 * If the device is set up for SPI offloading, IIO channel scan_type is
949 * set to IIO_CPU. When that is the case, use larger SPI word sizes for
950 * single-shot reads too. Thus, sample data can be correctly handled in
951 * ad4000_single_conversion() according to scan_type endianness.
952 */
953 if (chan->scan_type.endianness != IIO_BE)
954 xfers[1].bits_per_word = chan->scan_type.realbits;
955 xfers[1].delay.value = st->time_spec->t_quiet2_ns;
956 xfers[1].delay.unit = SPI_DELAY_UNIT_NSECS;
957
958 spi_message_init_with_transfers(&st->msg, st->xfers, 2);
959
960 return devm_spi_optimize_message(&st->spi->dev, st->spi, &st->msg);
961 }
962
963 /*
964 * This executes a data sample transfer for when the device connections are
965 * in "4-wire" mode, selected when the adi,sdi-pin device tree property is
966 * set to "cs". In this connection mode, the controller CS pin is connected to
967 * ADC SDI pin and a GPIO is connected to ADC CNV pin.
968 * The GPIO connected to ADC CNV pin is set outside of the SPI transfer.
969 */
ad4000_prepare_4wire_mode_message(struct ad4000_state * st,const struct iio_chan_spec * chan)970 static int ad4000_prepare_4wire_mode_message(struct ad4000_state *st,
971 const struct iio_chan_spec *chan)
972 {
973 struct spi_transfer *xfers = st->xfers;
974
975 /*
976 * Dummy transfer to cause enough delay between CNV going high and SDI
977 * going low.
978 */
979 xfers[0].cs_off = 1;
980 xfers[0].delay.value = st->time_spec->t_conv_ns;
981 xfers[0].delay.unit = SPI_DELAY_UNIT_NSECS;
982
983 xfers[1].rx_buf = &st->scan.data;
984 xfers[1].len = BITS_TO_BYTES(chan->scan_type.storagebits);
985
986 spi_message_init_with_transfers(&st->msg, st->xfers, 2);
987
988 return devm_spi_optimize_message(&st->spi->dev, st->spi, &st->msg);
989 }
990
ad4000_config(struct ad4000_state * st)991 static int ad4000_config(struct ad4000_state *st)
992 {
993 unsigned int reg_val = AD4000_CONFIG_REG_DEFAULT;
994
995 if (device_property_present(&st->spi->dev, "adi,high-z-input"))
996 reg_val |= FIELD_PREP(AD4000_CFG_HIGHZ, 1);
997
998 if (st->using_offload)
999 reg_val |= FIELD_PREP(AD4000_CFG_TURBO, 1);
1000
1001 return ad4000_write_reg(st, reg_val);
1002 }
1003
ad4000_probe(struct spi_device * spi)1004 static int ad4000_probe(struct spi_device *spi)
1005 {
1006 const struct ad4000_chip_info *chip;
1007 struct device *dev = &spi->dev;
1008 struct iio_dev *indio_dev;
1009 struct ad4000_state *st;
1010 int gain_idx, ret;
1011
1012 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1013 if (!indio_dev)
1014 return -ENOMEM;
1015
1016 chip = spi_get_device_match_data(spi);
1017 if (!chip)
1018 return -EINVAL;
1019
1020 st = iio_priv(indio_dev);
1021 st->spi = spi;
1022 st->time_spec = chip->time_spec;
1023 st->max_rate_hz = chip->max_rate_hz;
1024
1025 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(ad4000_power_supplies),
1026 ad4000_power_supplies);
1027 if (ret)
1028 return dev_err_probe(dev, ret, "Failed to enable power supplies\n");
1029
1030 ret = devm_regulator_get_enable_read_voltage(dev, "ref");
1031 if (ret < 0)
1032 return dev_err_probe(dev, ret,
1033 "Failed to get ref regulator reference\n");
1034 st->vref_mv = ret / 1000;
1035
1036 st->cnv_gpio = devm_gpiod_get_optional(dev, "cnv", GPIOD_OUT_HIGH);
1037 if (IS_ERR(st->cnv_gpio))
1038 return dev_err_probe(dev, PTR_ERR(st->cnv_gpio),
1039 "Failed to get CNV GPIO");
1040
1041 st->offload = devm_spi_offload_get(dev, spi, &ad4000_offload_config);
1042 ret = PTR_ERR_OR_ZERO(st->offload);
1043 if (ret && ret != -ENODEV)
1044 return dev_err_probe(dev, ret, "Failed to get offload\n");
1045
1046 st->using_offload = !IS_ERR(st->offload);
1047 if (st->using_offload) {
1048 indio_dev->setup_ops = &ad4000_offload_buffer_setup_ops;
1049 ret = ad4000_spi_offload_setup(indio_dev, st);
1050 if (ret)
1051 return ret;
1052 } else {
1053 ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
1054 &iio_pollfunc_store_time,
1055 &ad4000_trigger_handler,
1056 NULL);
1057 if (ret)
1058 return ret;
1059 }
1060
1061 ret = device_property_match_property_string(dev, "adi,sdi-pin",
1062 ad4000_sdi_pin,
1063 ARRAY_SIZE(ad4000_sdi_pin));
1064 if (ret < 0 && ret != -EINVAL)
1065 return dev_err_probe(dev, ret,
1066 "getting adi,sdi-pin property failed\n");
1067
1068 /* Default to usual SPI connections if pin properties are not present */
1069 st->sdi_pin = ret == -EINVAL ? AD4000_SDI_MOSI : ret;
1070 switch (st->sdi_pin) {
1071 case AD4000_SDI_MOSI:
1072 indio_dev->info = &ad4000_reg_access_info;
1073
1074 /*
1075 * In "3-wire mode", the ADC SDI line must be kept high when
1076 * data is not being clocked out of the controller.
1077 * Request the SPI controller to make MOSI idle high.
1078 */
1079 spi->mode |= SPI_MOSI_IDLE_HIGH;
1080 ret = spi_setup(spi);
1081 if (ret < 0)
1082 return ret;
1083
1084 if (st->using_offload) {
1085 indio_dev->channels = &chip->reg_access_offload_chan_spec;
1086 indio_dev->num_channels = 1;
1087 ret = ad4000_prepare_offload_message(st, indio_dev->channels);
1088 if (ret)
1089 return dev_err_probe(dev, ret,
1090 "Failed to optimize SPI msg\n");
1091 } else {
1092 indio_dev->channels = chip->reg_access_chan_spec;
1093 indio_dev->num_channels = ARRAY_SIZE(chip->reg_access_chan_spec);
1094 }
1095
1096 /*
1097 * Call ad4000_prepare_3wire_mode_message() so single-shot read
1098 * SPI messages are always initialized.
1099 */
1100 ret = ad4000_prepare_3wire_mode_message(st, &indio_dev->channels[0]);
1101 if (ret)
1102 return dev_err_probe(dev, ret,
1103 "Failed to optimize SPI msg\n");
1104
1105 ret = ad4000_config(st);
1106 if (ret < 0)
1107 return dev_err_probe(dev, ret, "Failed to config device\n");
1108
1109 break;
1110 case AD4000_SDI_VIO:
1111 if (st->using_offload) {
1112 indio_dev->info = &ad4000_offload_info;
1113 indio_dev->channels = &chip->offload_chan_spec;
1114 indio_dev->num_channels = 1;
1115
1116 ret = ad4000_prepare_offload_message(st, indio_dev->channels);
1117 if (ret)
1118 return dev_err_probe(dev, ret,
1119 "Failed to optimize SPI msg\n");
1120 } else {
1121 indio_dev->info = &ad4000_info;
1122 indio_dev->channels = chip->chan_spec;
1123 indio_dev->num_channels = ARRAY_SIZE(chip->chan_spec);
1124 }
1125
1126 ret = ad4000_prepare_3wire_mode_message(st, &indio_dev->channels[0]);
1127 if (ret)
1128 return dev_err_probe(dev, ret,
1129 "Failed to optimize SPI msg\n");
1130
1131 break;
1132 case AD4000_SDI_CS:
1133 if (st->using_offload)
1134 return dev_err_probe(dev, -EPROTONOSUPPORT,
1135 "Unsupported sdi-pin + offload config\n");
1136 indio_dev->info = &ad4000_info;
1137 indio_dev->channels = chip->chan_spec;
1138 indio_dev->num_channels = ARRAY_SIZE(chip->chan_spec);
1139 ret = ad4000_prepare_4wire_mode_message(st, &indio_dev->channels[0]);
1140 if (ret)
1141 return dev_err_probe(dev, ret,
1142 "Failed to optimize SPI msg\n");
1143
1144 break;
1145 case AD4000_SDI_GND:
1146 return dev_err_probe(dev, -EPROTONOSUPPORT,
1147 "Unsupported connection mode\n");
1148
1149 default:
1150 return dev_err_probe(dev, -EINVAL, "Unrecognized connection mode\n");
1151 }
1152
1153 indio_dev->name = chip->dev_name;
1154
1155 ret = devm_mutex_init(dev, &st->lock);
1156 if (ret)
1157 return ret;
1158
1159 st->gain_milli = 1000;
1160 if (chip->has_hardware_gain) {
1161 ret = device_property_read_u16(dev, "adi,gain-milli",
1162 &st->gain_milli);
1163 if (!ret) {
1164 /* Match gain value from dt to one of supported gains */
1165 gain_idx = find_closest(st->gain_milli, ad4000_gains,
1166 ARRAY_SIZE(ad4000_gains));
1167 st->gain_milli = ad4000_gains[gain_idx];
1168 } else {
1169 return dev_err_probe(dev, ret,
1170 "Failed to read gain property\n");
1171 }
1172 }
1173
1174 ad4000_fill_scale_tbl(st, &indio_dev->channels[0]);
1175
1176 return devm_iio_device_register(dev, indio_dev);
1177 }
1178
1179 static const struct spi_device_id ad4000_id[] = {
1180 { "ad4000", (kernel_ulong_t)&ad4000_chip_info },
1181 { "ad4001", (kernel_ulong_t)&ad4001_chip_info },
1182 { "ad4002", (kernel_ulong_t)&ad4002_chip_info },
1183 { "ad4003", (kernel_ulong_t)&ad4003_chip_info },
1184 { "ad4004", (kernel_ulong_t)&ad4004_chip_info },
1185 { "ad4005", (kernel_ulong_t)&ad4005_chip_info },
1186 { "ad4006", (kernel_ulong_t)&ad4006_chip_info },
1187 { "ad4007", (kernel_ulong_t)&ad4007_chip_info },
1188 { "ad4008", (kernel_ulong_t)&ad4008_chip_info },
1189 { "ad4010", (kernel_ulong_t)&ad4010_chip_info },
1190 { "ad4011", (kernel_ulong_t)&ad4011_chip_info },
1191 { "ad4020", (kernel_ulong_t)&ad4020_chip_info },
1192 { "ad4021", (kernel_ulong_t)&ad4021_chip_info },
1193 { "ad4022", (kernel_ulong_t)&ad4022_chip_info },
1194 { "adaq4001", (kernel_ulong_t)&adaq4001_chip_info },
1195 { "adaq4003", (kernel_ulong_t)&adaq4003_chip_info },
1196 { "ad7685", (kernel_ulong_t)&ad7685_chip_info },
1197 { "ad7686", (kernel_ulong_t)&ad7686_chip_info },
1198 { "ad7687", (kernel_ulong_t)&ad7687_chip_info },
1199 { "ad7688", (kernel_ulong_t)&ad7688_chip_info },
1200 { "ad7690", (kernel_ulong_t)&ad7690_chip_info },
1201 { "ad7691", (kernel_ulong_t)&ad7691_chip_info },
1202 { "ad7693", (kernel_ulong_t)&ad7693_chip_info },
1203 { "ad7942", (kernel_ulong_t)&ad7942_chip_info },
1204 { "ad7946", (kernel_ulong_t)&ad7946_chip_info },
1205 { "ad7980", (kernel_ulong_t)&ad7980_chip_info },
1206 { "ad7982", (kernel_ulong_t)&ad7982_chip_info },
1207 { "ad7983", (kernel_ulong_t)&ad7983_chip_info },
1208 { "ad7984", (kernel_ulong_t)&ad7984_chip_info },
1209 { "ad7988-1", (kernel_ulong_t)&ad7988_1_chip_info },
1210 { "ad7988-5", (kernel_ulong_t)&ad7988_5_chip_info },
1211 { }
1212 };
1213 MODULE_DEVICE_TABLE(spi, ad4000_id);
1214
1215 static const struct of_device_id ad4000_of_match[] = {
1216 { .compatible = "adi,ad4000", .data = &ad4000_chip_info },
1217 { .compatible = "adi,ad4001", .data = &ad4001_chip_info },
1218 { .compatible = "adi,ad4002", .data = &ad4002_chip_info },
1219 { .compatible = "adi,ad4003", .data = &ad4003_chip_info },
1220 { .compatible = "adi,ad4004", .data = &ad4004_chip_info },
1221 { .compatible = "adi,ad4005", .data = &ad4005_chip_info },
1222 { .compatible = "adi,ad4006", .data = &ad4006_chip_info },
1223 { .compatible = "adi,ad4007", .data = &ad4007_chip_info },
1224 { .compatible = "adi,ad4008", .data = &ad4008_chip_info },
1225 { .compatible = "adi,ad4010", .data = &ad4010_chip_info },
1226 { .compatible = "adi,ad4011", .data = &ad4011_chip_info },
1227 { .compatible = "adi,ad4020", .data = &ad4020_chip_info },
1228 { .compatible = "adi,ad4021", .data = &ad4021_chip_info },
1229 { .compatible = "adi,ad4022", .data = &ad4022_chip_info },
1230 { .compatible = "adi,adaq4001", .data = &adaq4001_chip_info },
1231 { .compatible = "adi,adaq4003", .data = &adaq4003_chip_info },
1232 { .compatible = "adi,ad7685", .data = &ad7685_chip_info },
1233 { .compatible = "adi,ad7686", .data = &ad7686_chip_info },
1234 { .compatible = "adi,ad7687", .data = &ad7687_chip_info },
1235 { .compatible = "adi,ad7688", .data = &ad7688_chip_info },
1236 { .compatible = "adi,ad7690", .data = &ad7690_chip_info },
1237 { .compatible = "adi,ad7691", .data = &ad7691_chip_info },
1238 { .compatible = "adi,ad7693", .data = &ad7693_chip_info },
1239 { .compatible = "adi,ad7942", .data = &ad7942_chip_info },
1240 { .compatible = "adi,ad7946", .data = &ad7946_chip_info },
1241 { .compatible = "adi,ad7980", .data = &ad7980_chip_info },
1242 { .compatible = "adi,ad7982", .data = &ad7982_chip_info },
1243 { .compatible = "adi,ad7983", .data = &ad7983_chip_info },
1244 { .compatible = "adi,ad7984", .data = &ad7984_chip_info },
1245 { .compatible = "adi,ad7988-1", .data = &ad7988_1_chip_info },
1246 { .compatible = "adi,ad7988-5", .data = &ad7988_5_chip_info },
1247 { }
1248 };
1249 MODULE_DEVICE_TABLE(of, ad4000_of_match);
1250
1251 static struct spi_driver ad4000_driver = {
1252 .driver = {
1253 .name = "ad4000",
1254 .of_match_table = ad4000_of_match,
1255 },
1256 .probe = ad4000_probe,
1257 .id_table = ad4000_id,
1258 };
1259 module_spi_driver(ad4000_driver);
1260
1261 MODULE_AUTHOR("Marcelo Schmitt <marcelo.schmitt@analog.com>");
1262 MODULE_DESCRIPTION("Analog Devices AD4000 ADC driver");
1263 MODULE_LICENSE("GPL");
1264 MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER");
1265