1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <linux/bits.h>
4 #include <linux/i2c.h>
5 #include <linux/i2c-mux.h>
6 #include <linux/mod_devicetable.h>
7 #include <linux/mfd/syscon.h>
8 #include <linux/mutex.h>
9 #include <linux/platform_device.h>
10 #include <linux/regmap.h>
11
12 enum rtl9300_bus_freq {
13 RTL9300_I2C_STD_FREQ,
14 RTL9300_I2C_FAST_FREQ,
15 };
16
17 struct rtl9300_i2c;
18
19 struct rtl9300_i2c_chan {
20 struct i2c_adapter adap;
21 struct rtl9300_i2c *i2c;
22 enum rtl9300_bus_freq bus_freq;
23 u8 sda_pin;
24 };
25
26 #define RTL9300_I2C_MUX_NCHAN 8
27
28 struct rtl9300_i2c {
29 struct regmap *regmap;
30 struct device *dev;
31 struct rtl9300_i2c_chan chans[RTL9300_I2C_MUX_NCHAN];
32 u32 reg_base;
33 u8 sda_pin;
34 struct mutex lock;
35 };
36
37 #define RTL9300_I2C_MST_CTRL1 0x0
38 #define RTL9300_I2C_MST_CTRL1_MEM_ADDR_OFS 8
39 #define RTL9300_I2C_MST_CTRL1_MEM_ADDR_MASK GENMASK(31, 8)
40 #define RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_OFS 4
41 #define RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_MASK GENMASK(6, 4)
42 #define RTL9300_I2C_MST_CTRL1_GPIO_SCL_SEL BIT(3)
43 #define RTL9300_I2C_MST_CTRL1_RWOP BIT(2)
44 #define RTL9300_I2C_MST_CTRL1_I2C_FAIL BIT(1)
45 #define RTL9300_I2C_MST_CTRL1_I2C_TRIG BIT(0)
46 #define RTL9300_I2C_MST_CTRL2 0x4
47 #define RTL9300_I2C_MST_CTRL2_RD_MODE BIT(15)
48 #define RTL9300_I2C_MST_CTRL2_DEV_ADDR_OFS 8
49 #define RTL9300_I2C_MST_CTRL2_DEV_ADDR_MASK GENMASK(14, 8)
50 #define RTL9300_I2C_MST_CTRL2_DATA_WIDTH_OFS 4
51 #define RTL9300_I2C_MST_CTRL2_DATA_WIDTH_MASK GENMASK(7, 4)
52 #define RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_OFS 2
53 #define RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_MASK GENMASK(3, 2)
54 #define RTL9300_I2C_MST_CTRL2_SCL_FREQ_OFS 0
55 #define RTL9300_I2C_MST_CTRL2_SCL_FREQ_MASK GENMASK(1, 0)
56 #define RTL9300_I2C_MST_DATA_WORD0 0x8
57 #define RTL9300_I2C_MST_DATA_WORD1 0xc
58 #define RTL9300_I2C_MST_DATA_WORD2 0x10
59 #define RTL9300_I2C_MST_DATA_WORD3 0x14
60
61 #define RTL9300_I2C_MST_GLB_CTRL 0x384
62
rtl9300_i2c_reg_addr_set(struct rtl9300_i2c * i2c,u32 reg,u16 len)63 static int rtl9300_i2c_reg_addr_set(struct rtl9300_i2c *i2c, u32 reg, u16 len)
64 {
65 u32 val, mask;
66 int ret;
67
68 val = len << RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_OFS;
69 mask = RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_MASK;
70
71 ret = regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL2, mask, val);
72 if (ret)
73 return ret;
74
75 val = reg << RTL9300_I2C_MST_CTRL1_MEM_ADDR_OFS;
76 mask = RTL9300_I2C_MST_CTRL1_MEM_ADDR_MASK;
77
78 return regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL1, mask, val);
79 }
80
rtl9300_i2c_config_io(struct rtl9300_i2c * i2c,u8 sda_pin)81 static int rtl9300_i2c_config_io(struct rtl9300_i2c *i2c, u8 sda_pin)
82 {
83 int ret;
84 u32 val, mask;
85
86 ret = regmap_update_bits(i2c->regmap, RTL9300_I2C_MST_GLB_CTRL, BIT(sda_pin), BIT(sda_pin));
87 if (ret)
88 return ret;
89
90 val = (sda_pin << RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_OFS) |
91 RTL9300_I2C_MST_CTRL1_GPIO_SCL_SEL;
92 mask = RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_MASK | RTL9300_I2C_MST_CTRL1_GPIO_SCL_SEL;
93
94 return regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL1, mask, val);
95 }
96
rtl9300_i2c_config_xfer(struct rtl9300_i2c * i2c,struct rtl9300_i2c_chan * chan,u16 addr,u16 len)97 static int rtl9300_i2c_config_xfer(struct rtl9300_i2c *i2c, struct rtl9300_i2c_chan *chan,
98 u16 addr, u16 len)
99 {
100 u32 val, mask;
101
102 if (len < 1 || len > 16)
103 return -EINVAL;
104
105 val = chan->bus_freq << RTL9300_I2C_MST_CTRL2_SCL_FREQ_OFS;
106 mask = RTL9300_I2C_MST_CTRL2_SCL_FREQ_MASK;
107
108 val |= addr << RTL9300_I2C_MST_CTRL2_DEV_ADDR_OFS;
109 mask |= RTL9300_I2C_MST_CTRL2_DEV_ADDR_MASK;
110
111 val |= ((len - 1) & 0xf) << RTL9300_I2C_MST_CTRL2_DATA_WIDTH_OFS;
112 mask |= RTL9300_I2C_MST_CTRL2_DATA_WIDTH_MASK;
113
114 mask |= RTL9300_I2C_MST_CTRL2_RD_MODE;
115
116 return regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL2, mask, val);
117 }
118
rtl9300_i2c_read(struct rtl9300_i2c * i2c,u8 * buf,int len)119 static int rtl9300_i2c_read(struct rtl9300_i2c *i2c, u8 *buf, int len)
120 {
121 u32 vals[4] = {};
122 int i, ret;
123
124 if (len > 16)
125 return -EIO;
126
127 ret = regmap_bulk_read(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0,
128 vals, ARRAY_SIZE(vals));
129 if (ret)
130 return ret;
131
132 for (i = 0; i < len; i++) {
133 buf[i] = vals[i/4] & 0xff;
134 vals[i/4] >>= 8;
135 }
136
137 return 0;
138 }
139
rtl9300_i2c_write(struct rtl9300_i2c * i2c,u8 * buf,int len)140 static int rtl9300_i2c_write(struct rtl9300_i2c *i2c, u8 *buf, int len)
141 {
142 u32 vals[4] = {};
143 int i;
144
145 if (len > 16)
146 return -EIO;
147
148 for (i = 0; i < len; i++) {
149 unsigned int shift = (i % 4) * 8;
150 unsigned int reg = i / 4;
151
152 vals[reg] |= buf[i] << shift;
153 }
154
155 return regmap_bulk_write(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0,
156 vals, ARRAY_SIZE(vals));
157 }
158
rtl9300_i2c_writel(struct rtl9300_i2c * i2c,u32 data)159 static int rtl9300_i2c_writel(struct rtl9300_i2c *i2c, u32 data)
160 {
161 return regmap_write(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0, data);
162 }
163
rtl9300_i2c_execute_xfer(struct rtl9300_i2c * i2c,char read_write,int size,union i2c_smbus_data * data,int len)164 static int rtl9300_i2c_execute_xfer(struct rtl9300_i2c *i2c, char read_write,
165 int size, union i2c_smbus_data *data, int len)
166 {
167 u32 val, mask;
168 int ret;
169
170 val = read_write == I2C_SMBUS_WRITE ? RTL9300_I2C_MST_CTRL1_RWOP : 0;
171 mask = RTL9300_I2C_MST_CTRL1_RWOP;
172
173 val |= RTL9300_I2C_MST_CTRL1_I2C_TRIG;
174 mask |= RTL9300_I2C_MST_CTRL1_I2C_TRIG;
175
176 ret = regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL1, mask, val);
177 if (ret)
178 return ret;
179
180 ret = regmap_read_poll_timeout(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL1,
181 val, !(val & RTL9300_I2C_MST_CTRL1_I2C_TRIG), 100, 100000);
182 if (ret)
183 return ret;
184
185 if (val & RTL9300_I2C_MST_CTRL1_I2C_FAIL)
186 return -EIO;
187
188 if (read_write == I2C_SMBUS_READ) {
189 if (size == I2C_SMBUS_BYTE || size == I2C_SMBUS_BYTE_DATA) {
190 ret = regmap_read(i2c->regmap,
191 i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0, &val);
192 if (ret)
193 return ret;
194 data->byte = val & 0xff;
195 } else if (size == I2C_SMBUS_WORD_DATA) {
196 ret = regmap_read(i2c->regmap,
197 i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0, &val);
198 if (ret)
199 return ret;
200 data->word = val & 0xffff;
201 } else {
202 ret = rtl9300_i2c_read(i2c, &data->block[0], len);
203 if (ret)
204 return ret;
205 }
206 }
207
208 return 0;
209 }
210
rtl9300_i2c_smbus_xfer(struct i2c_adapter * adap,u16 addr,unsigned short flags,char read_write,u8 command,int size,union i2c_smbus_data * data)211 static int rtl9300_i2c_smbus_xfer(struct i2c_adapter *adap, u16 addr, unsigned short flags,
212 char read_write, u8 command, int size,
213 union i2c_smbus_data *data)
214 {
215 struct rtl9300_i2c_chan *chan = i2c_get_adapdata(adap);
216 struct rtl9300_i2c *i2c = chan->i2c;
217 int len = 0, ret;
218
219 mutex_lock(&i2c->lock);
220 if (chan->sda_pin != i2c->sda_pin) {
221 ret = rtl9300_i2c_config_io(i2c, chan->sda_pin);
222 if (ret)
223 goto out_unlock;
224 i2c->sda_pin = chan->sda_pin;
225 }
226
227 switch (size) {
228 case I2C_SMBUS_BYTE:
229 if (read_write == I2C_SMBUS_WRITE) {
230 ret = rtl9300_i2c_config_xfer(i2c, chan, addr, 0);
231 if (ret)
232 goto out_unlock;
233 ret = rtl9300_i2c_reg_addr_set(i2c, command, 1);
234 if (ret)
235 goto out_unlock;
236 } else {
237 ret = rtl9300_i2c_config_xfer(i2c, chan, addr, 1);
238 if (ret)
239 goto out_unlock;
240 ret = rtl9300_i2c_reg_addr_set(i2c, 0, 0);
241 if (ret)
242 goto out_unlock;
243 }
244 break;
245
246 case I2C_SMBUS_BYTE_DATA:
247 ret = rtl9300_i2c_reg_addr_set(i2c, command, 1);
248 if (ret)
249 goto out_unlock;
250 ret = rtl9300_i2c_config_xfer(i2c, chan, addr, 1);
251 if (ret)
252 goto out_unlock;
253 if (read_write == I2C_SMBUS_WRITE) {
254 ret = rtl9300_i2c_writel(i2c, data->byte);
255 if (ret)
256 goto out_unlock;
257 }
258 break;
259
260 case I2C_SMBUS_WORD_DATA:
261 ret = rtl9300_i2c_reg_addr_set(i2c, command, 1);
262 if (ret)
263 goto out_unlock;
264 ret = rtl9300_i2c_config_xfer(i2c, chan, addr, 2);
265 if (ret)
266 goto out_unlock;
267 if (read_write == I2C_SMBUS_WRITE) {
268 ret = rtl9300_i2c_writel(i2c, data->word);
269 if (ret)
270 goto out_unlock;
271 }
272 break;
273
274 case I2C_SMBUS_BLOCK_DATA:
275 ret = rtl9300_i2c_reg_addr_set(i2c, command, 1);
276 if (ret)
277 goto out_unlock;
278 if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX) {
279 ret = -EINVAL;
280 goto out_unlock;
281 }
282 ret = rtl9300_i2c_config_xfer(i2c, chan, addr, data->block[0] + 1);
283 if (ret)
284 goto out_unlock;
285 if (read_write == I2C_SMBUS_WRITE) {
286 ret = rtl9300_i2c_write(i2c, &data->block[0], data->block[0] + 1);
287 if (ret)
288 goto out_unlock;
289 }
290 len = data->block[0] + 1;
291 break;
292
293 default:
294 dev_err(&adap->dev, "Unsupported transaction %d\n", size);
295 ret = -EOPNOTSUPP;
296 goto out_unlock;
297 }
298
299 ret = rtl9300_i2c_execute_xfer(i2c, read_write, size, data, len);
300
301 out_unlock:
302 mutex_unlock(&i2c->lock);
303
304 return ret;
305 }
306
rtl9300_i2c_func(struct i2c_adapter * a)307 static u32 rtl9300_i2c_func(struct i2c_adapter *a)
308 {
309 return I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA |
310 I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_BLOCK_DATA |
311 I2C_FUNC_SMBUS_I2C_BLOCK;
312 }
313
314 static const struct i2c_algorithm rtl9300_i2c_algo = {
315 .smbus_xfer = rtl9300_i2c_smbus_xfer,
316 .functionality = rtl9300_i2c_func,
317 };
318
319 static struct i2c_adapter_quirks rtl9300_i2c_quirks = {
320 .flags = I2C_AQ_NO_CLK_STRETCH | I2C_AQ_NO_ZERO_LEN,
321 .max_read_len = 16,
322 .max_write_len = 16,
323 };
324
rtl9300_i2c_probe(struct platform_device * pdev)325 static int rtl9300_i2c_probe(struct platform_device *pdev)
326 {
327 struct device *dev = &pdev->dev;
328 struct rtl9300_i2c *i2c;
329 u32 clock_freq, sda_pin;
330 int ret, i = 0;
331 struct fwnode_handle *child;
332
333 i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL);
334 if (!i2c)
335 return -ENOMEM;
336
337 i2c->regmap = syscon_node_to_regmap(dev->parent->of_node);
338 if (IS_ERR(i2c->regmap))
339 return PTR_ERR(i2c->regmap);
340 i2c->dev = dev;
341
342 mutex_init(&i2c->lock);
343
344 ret = device_property_read_u32(dev, "reg", &i2c->reg_base);
345 if (ret)
346 return ret;
347
348 platform_set_drvdata(pdev, i2c);
349
350 if (device_get_child_node_count(dev) > RTL9300_I2C_MUX_NCHAN)
351 return dev_err_probe(dev, -EINVAL, "Too many channels\n");
352
353 device_for_each_child_node(dev, child) {
354 struct rtl9300_i2c_chan *chan = &i2c->chans[i];
355 struct i2c_adapter *adap = &chan->adap;
356
357 ret = fwnode_property_read_u32(child, "reg", &sda_pin);
358 if (ret)
359 return ret;
360
361 ret = fwnode_property_read_u32(child, "clock-frequency", &clock_freq);
362 if (ret)
363 clock_freq = I2C_MAX_STANDARD_MODE_FREQ;
364
365 switch (clock_freq) {
366 case I2C_MAX_STANDARD_MODE_FREQ:
367 chan->bus_freq = RTL9300_I2C_STD_FREQ;
368 break;
369
370 case I2C_MAX_FAST_MODE_FREQ:
371 chan->bus_freq = RTL9300_I2C_FAST_FREQ;
372 break;
373 default:
374 dev_warn(i2c->dev, "SDA%d clock-frequency %d not supported using default\n",
375 sda_pin, clock_freq);
376 break;
377 }
378
379 chan->sda_pin = sda_pin;
380 chan->i2c = i2c;
381 adap = &i2c->chans[i].adap;
382 adap->owner = THIS_MODULE;
383 adap->algo = &rtl9300_i2c_algo;
384 adap->quirks = &rtl9300_i2c_quirks;
385 adap->retries = 3;
386 adap->dev.parent = dev;
387 i2c_set_adapdata(adap, chan);
388 adap->dev.of_node = to_of_node(child);
389 snprintf(adap->name, sizeof(adap->name), "%s SDA%d\n", dev_name(dev), sda_pin);
390 i++;
391
392 ret = devm_i2c_add_adapter(dev, adap);
393 if (ret)
394 return ret;
395 }
396 i2c->sda_pin = 0xff;
397
398 return 0;
399 }
400
401 static const struct of_device_id i2c_rtl9300_dt_ids[] = {
402 { .compatible = "realtek,rtl9301-i2c" },
403 { .compatible = "realtek,rtl9302b-i2c" },
404 { .compatible = "realtek,rtl9302c-i2c" },
405 { .compatible = "realtek,rtl9303-i2c" },
406 {}
407 };
408 MODULE_DEVICE_TABLE(of, i2c_rtl9300_dt_ids);
409
410 static struct platform_driver rtl9300_i2c_driver = {
411 .probe = rtl9300_i2c_probe,
412 .driver = {
413 .name = "i2c-rtl9300",
414 .of_match_table = i2c_rtl9300_dt_ids,
415 },
416 };
417
418 module_platform_driver(rtl9300_i2c_driver);
419
420 MODULE_DESCRIPTION("RTL9300 I2C controller driver");
421 MODULE_LICENSE("GPL");
422