1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Renesas RIIC driver
4 *
5 * Copyright (C) 2013 Wolfram Sang <wsa@sang-engineering.com>
6 * Copyright (C) 2013 Renesas Solutions Corp.
7 */
8
9 /*
10 * This i2c core has a lot of interrupts, namely 8. We use their chaining as
11 * some kind of state machine.
12 *
13 * 1) The main xfer routine kicks off a transmission by putting the start bit
14 * (or repeated start) on the bus and enabling the transmit interrupt (TIE)
15 * since we need to send the target address + RW bit in every case.
16 *
17 * 2) TIE sends target address + RW bit and selects how to continue.
18 *
19 * 3a) Write case: We keep utilizing TIE as long as we have data to send. If we
20 * are done, we switch over to the transmission done interrupt (TEIE) and mark
21 * the message as completed (includes sending STOP) there.
22 *
23 * 3b) Read case: We switch over to receive interrupt (RIE). One dummy read is
24 * needed to start clocking, then we keep receiving until we are done. Note
25 * that we use the RDRFS mode all the time, i.e. we ACK/NACK every byte by
26 * writing to the ACKBT bit. I tried using the RDRFS mode only at the end of a
27 * message to create the final NACK as sketched in the datasheet. This caused
28 * some subtle races (when byte n was processed and byte n+1 was already
29 * waiting), though, and I started with the safe approach.
30 *
31 * 4) If we got a NACK somewhere, we flag the error and stop the transmission
32 * via NAKIE.
33 *
34 * Also check the comments in the interrupt routines for some gory details.
35 */
36
37 #include <linux/bits.h>
38 #include <linux/clk.h>
39 #include <linux/completion.h>
40 #include <linux/err.h>
41 #include <linux/i2c.h>
42 #include <linux/interrupt.h>
43 #include <linux/io.h>
44 #include <linux/iopoll.h>
45 #include <linux/module.h>
46 #include <linux/of.h>
47 #include <linux/platform_device.h>
48 #include <linux/pm_runtime.h>
49 #include <linux/reset.h>
50 #include <linux/time.h>
51
52 #define ICCR1_ICE BIT(7)
53 #define ICCR1_IICRST BIT(6)
54 #define ICCR1_SOWP BIT(4)
55 #define ICCR1_SCLO BIT(3)
56 #define ICCR1_SDAO BIT(2)
57 #define ICCR1_SCLI BIT(1)
58 #define ICCR1_SDAI BIT(0)
59
60 #define ICCR2_BBSY BIT(7)
61 #define ICCR2_SP BIT(3)
62 #define ICCR2_RS BIT(2)
63 #define ICCR2_ST BIT(1)
64
65 #define ICMR1_CKS_MASK GENMASK(6, 4)
66 #define ICMR1_BCWP BIT(3)
67 #define ICMR1_CKS(_x) ((((_x) << 4) & ICMR1_CKS_MASK) | ICMR1_BCWP)
68
69 #define ICMR3_RDRFS BIT(5)
70 #define ICMR3_ACKWP BIT(4)
71 #define ICMR3_ACKBT BIT(3)
72
73 #define ICFER_FMPE BIT(7)
74
75 #define ICIER_TIE BIT(7)
76 #define ICIER_TEIE BIT(6)
77 #define ICIER_RIE BIT(5)
78 #define ICIER_NAKIE BIT(4)
79 #define ICIER_SPIE BIT(3)
80
81 #define ICSR2_NACKF BIT(4)
82 #define ICSR2_STOP BIT(3)
83
84 #define ICBR_RESERVED GENMASK(7, 5) /* Should be 1 on writes */
85
86 #define RIIC_INIT_MSG -1
87
88 enum riic_reg_list {
89 RIIC_ICCR1 = 0,
90 RIIC_ICCR2,
91 RIIC_ICMR1,
92 RIIC_ICMR3,
93 RIIC_ICFER,
94 RIIC_ICSER,
95 RIIC_ICIER,
96 RIIC_ICSR2,
97 RIIC_ICBRL,
98 RIIC_ICBRH,
99 RIIC_ICDRT,
100 RIIC_ICDRR,
101 RIIC_REG_END,
102 };
103
104 struct riic_of_data {
105 const u8 *regs;
106 const struct riic_irq_desc *irqs;
107 u8 num_irqs;
108 bool fast_mode_plus;
109 };
110
111 struct riic_dev {
112 void __iomem *base;
113 u8 *buf;
114 struct i2c_msg *msg;
115 int bytes_left;
116 int err;
117 int is_last;
118 const struct riic_of_data *info;
119 struct completion msg_done;
120 struct i2c_adapter adapter;
121 struct clk *clk;
122 struct reset_control *rstc;
123 struct i2c_timings i2c_t;
124 };
125
126 struct riic_irq_desc {
127 int res_num;
128 irq_handler_t isr;
129 char *name;
130 };
131
riic_writeb(struct riic_dev * riic,u8 val,u8 offset)132 static inline void riic_writeb(struct riic_dev *riic, u8 val, u8 offset)
133 {
134 writeb(val, riic->base + riic->info->regs[offset]);
135 }
136
riic_readb(struct riic_dev * riic,u8 offset)137 static inline u8 riic_readb(struct riic_dev *riic, u8 offset)
138 {
139 return readb(riic->base + riic->info->regs[offset]);
140 }
141
riic_clear_set_bit(struct riic_dev * riic,u8 clear,u8 set,u8 reg)142 static inline void riic_clear_set_bit(struct riic_dev *riic, u8 clear, u8 set, u8 reg)
143 {
144 riic_writeb(riic, (riic_readb(riic, reg) & ~clear) | set, reg);
145 }
146
riic_bus_barrier(struct riic_dev * riic)147 static int riic_bus_barrier(struct riic_dev *riic)
148 {
149 int ret;
150 u8 val;
151
152 /*
153 * The SDA line can still be low even when BBSY = 0. Therefore, after checking
154 * the BBSY flag, also verify that the SDA and SCL lines are not being held low.
155 */
156 ret = readb_poll_timeout(riic->base + riic->info->regs[RIIC_ICCR2], val,
157 !(val & ICCR2_BBSY), 10, riic->adapter.timeout);
158 if (ret)
159 return i2c_recover_bus(&riic->adapter);
160
161 if ((riic_readb(riic, RIIC_ICCR1) & (ICCR1_SDAI | ICCR1_SCLI)) !=
162 (ICCR1_SDAI | ICCR1_SCLI))
163 return i2c_recover_bus(&riic->adapter);
164
165 return 0;
166 }
167
riic_xfer(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)168 static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
169 {
170 struct riic_dev *riic = i2c_get_adapdata(adap);
171 struct device *dev = adap->dev.parent;
172 unsigned long time_left;
173 int i, ret;
174 u8 start_bit;
175
176 ret = pm_runtime_resume_and_get(dev);
177 if (ret)
178 return ret;
179
180 riic->err = riic_bus_barrier(riic);
181 if (riic->err)
182 goto out;
183
184 reinit_completion(&riic->msg_done);
185
186 riic_writeb(riic, 0, RIIC_ICSR2);
187
188 for (i = 0, start_bit = ICCR2_ST; i < num; i++) {
189 riic->bytes_left = RIIC_INIT_MSG;
190 riic->buf = msgs[i].buf;
191 riic->msg = &msgs[i];
192 riic->is_last = (i == num - 1);
193
194 riic_writeb(riic, ICIER_NAKIE | ICIER_TIE, RIIC_ICIER);
195
196 riic_writeb(riic, start_bit, RIIC_ICCR2);
197
198 time_left = wait_for_completion_timeout(&riic->msg_done, riic->adapter.timeout);
199 if (time_left == 0)
200 riic->err = -ETIMEDOUT;
201
202 if (riic->err)
203 break;
204
205 start_bit = ICCR2_RS;
206 }
207
208 out:
209 pm_runtime_mark_last_busy(dev);
210 pm_runtime_put_autosuspend(dev);
211
212 return riic->err ?: num;
213 }
214
riic_tdre_isr(int irq,void * data)215 static irqreturn_t riic_tdre_isr(int irq, void *data)
216 {
217 struct riic_dev *riic = data;
218 u8 val;
219
220 if (!riic->bytes_left)
221 return IRQ_NONE;
222
223 if (riic->bytes_left == RIIC_INIT_MSG) {
224 if (riic->msg->flags & I2C_M_RD)
225 /* On read, switch over to receive interrupt */
226 riic_clear_set_bit(riic, ICIER_TIE, ICIER_RIE, RIIC_ICIER);
227 else
228 /* On write, initialize length */
229 riic->bytes_left = riic->msg->len;
230
231 val = i2c_8bit_addr_from_msg(riic->msg);
232 } else {
233 val = *riic->buf;
234 riic->buf++;
235 riic->bytes_left--;
236 }
237
238 /*
239 * Switch to transmission ended interrupt when done. Do check here
240 * after bytes_left was initialized to support SMBUS_QUICK (new msg has
241 * 0 length then)
242 */
243 if (riic->bytes_left == 0)
244 riic_clear_set_bit(riic, ICIER_TIE, ICIER_TEIE, RIIC_ICIER);
245
246 /*
247 * This acks the TIE interrupt. We get another TIE immediately if our
248 * value could be moved to the shadow shift register right away. So
249 * this must be after updates to ICIER (where we want to disable TIE)!
250 */
251 riic_writeb(riic, val, RIIC_ICDRT);
252
253 return IRQ_HANDLED;
254 }
255
riic_tend_isr(int irq,void * data)256 static irqreturn_t riic_tend_isr(int irq, void *data)
257 {
258 struct riic_dev *riic = data;
259
260 if (riic_readb(riic, RIIC_ICSR2) & ICSR2_NACKF) {
261 /* We got a NACKIE */
262 riic_readb(riic, RIIC_ICDRR); /* dummy read */
263 riic_clear_set_bit(riic, ICSR2_NACKF, 0, RIIC_ICSR2);
264 riic->err = -ENXIO;
265 } else if (riic->bytes_left) {
266 return IRQ_NONE;
267 }
268
269 if (riic->is_last || riic->err) {
270 riic_clear_set_bit(riic, ICIER_TEIE, ICIER_SPIE, RIIC_ICIER);
271 riic_writeb(riic, ICCR2_SP, RIIC_ICCR2);
272 } else {
273 /* Transfer is complete, but do not send STOP */
274 riic_clear_set_bit(riic, ICIER_TEIE, 0, RIIC_ICIER);
275 complete(&riic->msg_done);
276 }
277
278 return IRQ_HANDLED;
279 }
280
riic_rdrf_isr(int irq,void * data)281 static irqreturn_t riic_rdrf_isr(int irq, void *data)
282 {
283 struct riic_dev *riic = data;
284
285 if (!riic->bytes_left)
286 return IRQ_NONE;
287
288 if (riic->bytes_left == RIIC_INIT_MSG) {
289 riic->bytes_left = riic->msg->len;
290 riic_readb(riic, RIIC_ICDRR); /* dummy read */
291 return IRQ_HANDLED;
292 }
293
294 if (riic->bytes_left == 1) {
295 /* STOP must come before we set ACKBT! */
296 if (riic->is_last) {
297 riic_clear_set_bit(riic, 0, ICIER_SPIE, RIIC_ICIER);
298 riic_writeb(riic, ICCR2_SP, RIIC_ICCR2);
299 }
300
301 riic_clear_set_bit(riic, 0, ICMR3_ACKBT, RIIC_ICMR3);
302
303 } else {
304 riic_clear_set_bit(riic, ICMR3_ACKBT, 0, RIIC_ICMR3);
305 }
306
307 /* Reading acks the RIE interrupt */
308 *riic->buf = riic_readb(riic, RIIC_ICDRR);
309 riic->buf++;
310 riic->bytes_left--;
311
312 return IRQ_HANDLED;
313 }
314
riic_stop_isr(int irq,void * data)315 static irqreturn_t riic_stop_isr(int irq, void *data)
316 {
317 struct riic_dev *riic = data;
318
319 /* read back registers to confirm writes have fully propagated */
320 riic_writeb(riic, 0, RIIC_ICSR2);
321 riic_readb(riic, RIIC_ICSR2);
322 riic_writeb(riic, 0, RIIC_ICIER);
323 riic_readb(riic, RIIC_ICIER);
324
325 complete(&riic->msg_done);
326
327 return IRQ_HANDLED;
328 }
329
riic_eei_isr(int irq,void * data)330 static irqreturn_t riic_eei_isr(int irq, void *data)
331 {
332 u8 icsr2 = riic_readb(data, RIIC_ICSR2);
333
334 if (icsr2 & ICSR2_NACKF)
335 return riic_tend_isr(irq, data);
336
337 if (icsr2 & ICSR2_STOP)
338 return riic_stop_isr(irq, data);
339
340 return IRQ_NONE;
341 }
342
riic_func(struct i2c_adapter * adap)343 static u32 riic_func(struct i2c_adapter *adap)
344 {
345 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
346 }
347
348 static const struct i2c_algorithm riic_algo = {
349 .xfer = riic_xfer,
350 .functionality = riic_func,
351 };
352
riic_init_hw(struct riic_dev * riic)353 static int riic_init_hw(struct riic_dev *riic)
354 {
355 int ret;
356 unsigned long rate;
357 unsigned long ns_per_tick;
358 int total_ticks, cks, brl, brh;
359 struct i2c_timings *t = &riic->i2c_t;
360 struct device *dev = riic->adapter.dev.parent;
361 bool fast_mode_plus = riic->info->fast_mode_plus;
362 u32 max_freq = fast_mode_plus ? I2C_MAX_FAST_MODE_PLUS_FREQ
363 : I2C_MAX_FAST_MODE_FREQ;
364
365 if (t->bus_freq_hz > max_freq)
366 return dev_err_probe(dev, -EINVAL,
367 "unsupported bus speed %uHz (%u max)\n",
368 t->bus_freq_hz, max_freq);
369
370 rate = clk_get_rate(riic->clk);
371
372 /*
373 * Assume the default register settings:
374 * FER.SCLE = 1 (SCL sync circuit enabled, adds 2 or 3 cycles)
375 * FER.NFE = 1 (noise circuit enabled)
376 * MR3.NF = 0 (1 cycle of noise filtered out)
377 *
378 * Freq (CKS=000) = (I2CCLK + tr + tf)/ (BRH + 3 + 1) + (BRL + 3 + 1)
379 * Freq (CKS!=000) = (I2CCLK + tr + tf)/ (BRH + 2 + 1) + (BRL + 2 + 1)
380 */
381
382 /*
383 * Determine reference clock rate. We must be able to get the desired
384 * frequency with only 62 clock ticks max (31 high, 31 low).
385 * Aim for a duty of 60% LOW, 40% HIGH.
386 */
387 total_ticks = DIV_ROUND_UP(rate, t->bus_freq_hz ?: 1);
388
389 for (cks = 0; cks < 7; cks++) {
390 /*
391 * 60% low time must be less than BRL + 2 + 1
392 * BRL max register value is 0x1F.
393 */
394 brl = ((total_ticks * 6) / 10);
395 if (brl <= (0x1F + 3))
396 break;
397
398 total_ticks = DIV_ROUND_UP(total_ticks, 2);
399 rate /= 2;
400 }
401
402 if (brl > (0x1F + 3))
403 return dev_err_probe(dev, -EINVAL, "invalid speed (%uHz). Too slow.\n",
404 t->bus_freq_hz);
405
406 brh = total_ticks - brl;
407
408 /* Remove automatic clock ticks for sync circuit and NF */
409 if (cks == 0) {
410 brl -= 4;
411 brh -= 4;
412 } else {
413 brl -= 3;
414 brh -= 3;
415 }
416
417 /*
418 * Remove clock ticks for rise and fall times. Convert ns to clock
419 * ticks.
420 */
421 ns_per_tick = NSEC_PER_SEC / rate;
422 brl -= t->scl_fall_ns / ns_per_tick;
423 brh -= t->scl_rise_ns / ns_per_tick;
424
425 /* Adjust for min register values for when SCLE=1 and NFE=1 */
426 if (brl < 1)
427 brl = 1;
428 if (brh < 1)
429 brh = 1;
430
431 pr_debug("i2c-riic: freq=%lu, duty=%d, fall=%lu, rise=%lu, cks=%d, brl=%d, brh=%d\n",
432 rate / total_ticks, ((brl + 3) * 100) / (brl + brh + 6),
433 t->scl_fall_ns / ns_per_tick, t->scl_rise_ns / ns_per_tick, cks, brl, brh);
434
435 ret = pm_runtime_resume_and_get(dev);
436 if (ret)
437 return ret;
438
439 /* Changing the order of accessing IICRST and ICE may break things! */
440 riic_writeb(riic, ICCR1_IICRST | ICCR1_SOWP, RIIC_ICCR1);
441 riic_clear_set_bit(riic, 0, ICCR1_ICE, RIIC_ICCR1);
442
443 riic_writeb(riic, ICMR1_CKS(cks), RIIC_ICMR1);
444 riic_writeb(riic, brh | ICBR_RESERVED, RIIC_ICBRH);
445 riic_writeb(riic, brl | ICBR_RESERVED, RIIC_ICBRL);
446
447 riic_writeb(riic, 0, RIIC_ICSER);
448 riic_writeb(riic, ICMR3_ACKWP | ICMR3_RDRFS, RIIC_ICMR3);
449
450 if (fast_mode_plus && t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ)
451 riic_clear_set_bit(riic, 0, ICFER_FMPE, RIIC_ICFER);
452
453 riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1);
454
455 pm_runtime_mark_last_busy(dev);
456 pm_runtime_put_autosuspend(dev);
457 return 0;
458 }
459
riic_get_scl(struct i2c_adapter * adap)460 static int riic_get_scl(struct i2c_adapter *adap)
461 {
462 struct riic_dev *riic = i2c_get_adapdata(adap);
463
464 return !!(riic_readb(riic, RIIC_ICCR1) & ICCR1_SCLI);
465 }
466
riic_get_sda(struct i2c_adapter * adap)467 static int riic_get_sda(struct i2c_adapter *adap)
468 {
469 struct riic_dev *riic = i2c_get_adapdata(adap);
470
471 return !!(riic_readb(riic, RIIC_ICCR1) & ICCR1_SDAI);
472 }
473
riic_set_scl(struct i2c_adapter * adap,int val)474 static void riic_set_scl(struct i2c_adapter *adap, int val)
475 {
476 struct riic_dev *riic = i2c_get_adapdata(adap);
477
478 if (val)
479 riic_clear_set_bit(riic, ICCR1_SOWP, ICCR1_SCLO, RIIC_ICCR1);
480 else
481 riic_clear_set_bit(riic, ICCR1_SOWP | ICCR1_SCLO, 0, RIIC_ICCR1);
482
483 riic_clear_set_bit(riic, 0, ICCR1_SOWP, RIIC_ICCR1);
484 }
485
riic_set_sda(struct i2c_adapter * adap,int val)486 static void riic_set_sda(struct i2c_adapter *adap, int val)
487 {
488 struct riic_dev *riic = i2c_get_adapdata(adap);
489
490 if (val)
491 riic_clear_set_bit(riic, ICCR1_SOWP, ICCR1_SDAO, RIIC_ICCR1);
492 else
493 riic_clear_set_bit(riic, ICCR1_SOWP | ICCR1_SDAO, 0, RIIC_ICCR1);
494
495 riic_clear_set_bit(riic, 0, ICCR1_SOWP, RIIC_ICCR1);
496 }
497
498 static struct i2c_bus_recovery_info riic_bri = {
499 .recover_bus = i2c_generic_scl_recovery,
500 .get_scl = riic_get_scl,
501 .set_scl = riic_set_scl,
502 .get_sda = riic_get_sda,
503 .set_sda = riic_set_sda,
504 };
505
506 static const struct riic_irq_desc riic_irqs[] = {
507 { .res_num = 0, .isr = riic_tend_isr, .name = "riic-tend" },
508 { .res_num = 1, .isr = riic_rdrf_isr, .name = "riic-rdrf" },
509 { .res_num = 2, .isr = riic_tdre_isr, .name = "riic-tdre" },
510 { .res_num = 3, .isr = riic_stop_isr, .name = "riic-stop" },
511 { .res_num = 5, .isr = riic_tend_isr, .name = "riic-nack" },
512 };
513
514 static const struct riic_irq_desc riic_rzt2h_irqs[] = {
515 { .res_num = 0, .isr = riic_eei_isr, .name = "riic-eei" },
516 { .res_num = 1, .isr = riic_rdrf_isr, .name = "riic-rxi" },
517 { .res_num = 2, .isr = riic_tdre_isr, .name = "riic-txi" },
518 { .res_num = 3, .isr = riic_tend_isr, .name = "riic-tei" },
519 };
520
riic_i2c_probe(struct platform_device * pdev)521 static int riic_i2c_probe(struct platform_device *pdev)
522 {
523 struct device *dev = &pdev->dev;
524 struct riic_dev *riic;
525 struct i2c_adapter *adap;
526 int i, ret;
527
528 riic = devm_kzalloc(dev, sizeof(*riic), GFP_KERNEL);
529 if (!riic)
530 return -ENOMEM;
531
532 riic->base = devm_platform_ioremap_resource(pdev, 0);
533 if (IS_ERR(riic->base))
534 return PTR_ERR(riic->base);
535
536 riic->clk = devm_clk_get(dev, NULL);
537 if (IS_ERR(riic->clk))
538 return dev_err_probe(dev, PTR_ERR(riic->clk),
539 "missing controller clock");
540
541 riic->rstc = devm_reset_control_get_optional_exclusive_deasserted(dev, NULL);
542 if (IS_ERR(riic->rstc))
543 return dev_err_probe(dev, PTR_ERR(riic->rstc),
544 "failed to acquire deasserted reset\n");
545
546 riic->info = of_device_get_match_data(dev);
547
548 for (i = 0; i < riic->info->num_irqs; i++) {
549 const struct riic_irq_desc *irq_desc;
550 int irq;
551
552 irq_desc = &riic->info->irqs[i];
553 irq = platform_get_irq(pdev, irq_desc->res_num);
554 if (irq < 0)
555 return irq;
556
557 ret = devm_request_irq(dev, irq, irq_desc->isr, 0, irq_desc->name, riic);
558 if (ret)
559 return dev_err_probe(dev, ret, "failed to request irq %s\n",
560 irq_desc->name);
561 }
562
563
564 adap = &riic->adapter;
565 i2c_set_adapdata(adap, riic);
566 strscpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name));
567 adap->owner = THIS_MODULE;
568 adap->algo = &riic_algo;
569 adap->dev.parent = dev;
570 adap->dev.of_node = dev->of_node;
571 adap->bus_recovery_info = &riic_bri;
572
573 init_completion(&riic->msg_done);
574
575 i2c_parse_fw_timings(dev, &riic->i2c_t, true);
576
577 /* Default 0 to save power. Can be overridden via sysfs for lower latency. */
578 pm_runtime_set_autosuspend_delay(dev, 0);
579 pm_runtime_use_autosuspend(dev);
580 pm_runtime_enable(dev);
581
582 ret = riic_init_hw(riic);
583 if (ret)
584 goto out;
585
586 ret = i2c_add_adapter(adap);
587 if (ret)
588 goto out;
589
590 platform_set_drvdata(pdev, riic);
591
592 dev_info(dev, "registered with %dHz bus speed\n", riic->i2c_t.bus_freq_hz);
593 return 0;
594
595 out:
596 pm_runtime_disable(dev);
597 pm_runtime_dont_use_autosuspend(dev);
598 return ret;
599 }
600
riic_i2c_remove(struct platform_device * pdev)601 static void riic_i2c_remove(struct platform_device *pdev)
602 {
603 struct riic_dev *riic = platform_get_drvdata(pdev);
604 struct device *dev = &pdev->dev;
605 int ret;
606
607 ret = pm_runtime_resume_and_get(dev);
608 if (!ret) {
609 riic_writeb(riic, 0, RIIC_ICIER);
610 pm_runtime_put(dev);
611 }
612 i2c_del_adapter(&riic->adapter);
613 pm_runtime_disable(dev);
614 pm_runtime_dont_use_autosuspend(dev);
615 }
616
617 static const u8 riic_rz_a_regs[RIIC_REG_END] = {
618 [RIIC_ICCR1] = 0x00,
619 [RIIC_ICCR2] = 0x04,
620 [RIIC_ICMR1] = 0x08,
621 [RIIC_ICMR3] = 0x10,
622 [RIIC_ICFER] = 0x14,
623 [RIIC_ICSER] = 0x18,
624 [RIIC_ICIER] = 0x1c,
625 [RIIC_ICSR2] = 0x24,
626 [RIIC_ICBRL] = 0x34,
627 [RIIC_ICBRH] = 0x38,
628 [RIIC_ICDRT] = 0x3c,
629 [RIIC_ICDRR] = 0x40,
630 };
631
632 static const struct riic_of_data riic_rz_a_info = {
633 .regs = riic_rz_a_regs,
634 .irqs = riic_irqs,
635 .num_irqs = ARRAY_SIZE(riic_irqs),
636 .fast_mode_plus = true,
637 };
638
639 static const struct riic_of_data riic_rz_a1h_info = {
640 .regs = riic_rz_a_regs,
641 .irqs = riic_irqs,
642 .num_irqs = ARRAY_SIZE(riic_irqs),
643 };
644
645 static const u8 riic_rz_v2h_regs[RIIC_REG_END] = {
646 [RIIC_ICCR1] = 0x00,
647 [RIIC_ICCR2] = 0x01,
648 [RIIC_ICMR1] = 0x02,
649 [RIIC_ICMR3] = 0x04,
650 [RIIC_ICFER] = 0x05,
651 [RIIC_ICSER] = 0x06,
652 [RIIC_ICIER] = 0x07,
653 [RIIC_ICSR2] = 0x09,
654 [RIIC_ICBRL] = 0x10,
655 [RIIC_ICBRH] = 0x11,
656 [RIIC_ICDRT] = 0x12,
657 [RIIC_ICDRR] = 0x13,
658 };
659
660 static const struct riic_of_data riic_rz_v2h_info = {
661 .regs = riic_rz_v2h_regs,
662 .irqs = riic_irqs,
663 .num_irqs = ARRAY_SIZE(riic_irqs),
664 .fast_mode_plus = true,
665 };
666
667 static const struct riic_of_data riic_rz_t2h_info = {
668 .regs = riic_rz_v2h_regs,
669 .irqs = riic_rzt2h_irqs,
670 .num_irqs = ARRAY_SIZE(riic_rzt2h_irqs),
671 };
672
riic_i2c_suspend(struct device * dev)673 static int riic_i2c_suspend(struct device *dev)
674 {
675 struct riic_dev *riic = dev_get_drvdata(dev);
676 int ret;
677
678 ret = pm_runtime_resume_and_get(dev);
679 if (ret)
680 return ret;
681
682 i2c_mark_adapter_suspended(&riic->adapter);
683
684 /* Disable output on SDA, SCL pins. */
685 riic_clear_set_bit(riic, ICCR1_ICE, 0, RIIC_ICCR1);
686
687 pm_runtime_mark_last_busy(dev);
688 pm_runtime_put_sync(dev);
689
690 return reset_control_assert(riic->rstc);
691 }
692
riic_i2c_resume(struct device * dev)693 static int riic_i2c_resume(struct device *dev)
694 {
695 struct riic_dev *riic = dev_get_drvdata(dev);
696 int ret;
697
698 ret = reset_control_deassert(riic->rstc);
699 if (ret)
700 return ret;
701
702 ret = riic_init_hw(riic);
703 if (ret) {
704 /*
705 * In case this happens there is no way to recover from this
706 * state. The driver will remain loaded. We want to avoid
707 * keeping the reset line de-asserted for no reason.
708 */
709 reset_control_assert(riic->rstc);
710 return ret;
711 }
712
713 i2c_mark_adapter_resumed(&riic->adapter);
714
715 return 0;
716 }
717
718 static const struct dev_pm_ops riic_i2c_pm_ops = {
719 SYSTEM_SLEEP_PM_OPS(riic_i2c_suspend, riic_i2c_resume)
720 };
721
722 static const struct of_device_id riic_i2c_dt_ids[] = {
723 { .compatible = "renesas,riic-r7s72100", .data = &riic_rz_a1h_info, },
724 { .compatible = "renesas,riic-r9a09g057", .data = &riic_rz_v2h_info },
725 { .compatible = "renesas,riic-r9a09g077", .data = &riic_rz_t2h_info },
726 { .compatible = "renesas,riic-rz", .data = &riic_rz_a_info },
727 { /* Sentinel */ }
728 };
729
730 static struct platform_driver riic_i2c_driver = {
731 .probe = riic_i2c_probe,
732 .remove = riic_i2c_remove,
733 .driver = {
734 .name = "i2c-riic",
735 .of_match_table = riic_i2c_dt_ids,
736 .pm = pm_ptr(&riic_i2c_pm_ops),
737 },
738 };
739
740 module_platform_driver(riic_i2c_driver);
741
742 MODULE_DESCRIPTION("Renesas RIIC adapter");
743 MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>");
744 MODULE_LICENSE("GPL v2");
745 MODULE_DEVICE_TABLE(of, riic_i2c_dt_ids);
746