1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2009-2013, 2016-2018, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2014, Sony Mobile Communications AB.
5 *
6 */
7
8 #include <linux/acpi.h>
9 #include <linux/atomic.h>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/dmaengine.h>
13 #include <linux/dmapool.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/err.h>
16 #include <linux/i2c.h>
17 #include <linux/interconnect.h>
18 #include <linux/interrupt.h>
19 #include <linux/io.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/property.h>
24 #include <linux/scatterlist.h>
25
26 /* QUP Registers */
27 #define QUP_CONFIG 0x000
28 #define QUP_STATE 0x004
29 #define QUP_IO_MODE 0x008
30 #define QUP_SW_RESET 0x00c
31 #define QUP_OPERATIONAL 0x018
32 #define QUP_ERROR_FLAGS 0x01c
33 #define QUP_ERROR_FLAGS_EN 0x020
34 #define QUP_OPERATIONAL_MASK 0x028
35 #define QUP_HW_VERSION 0x030
36 #define QUP_MX_OUTPUT_CNT 0x100
37 #define QUP_OUT_FIFO_BASE 0x110
38 #define QUP_MX_WRITE_CNT 0x150
39 #define QUP_MX_INPUT_CNT 0x200
40 #define QUP_MX_READ_CNT 0x208
41 #define QUP_IN_FIFO_BASE 0x218
42 #define QUP_I2C_CLK_CTL 0x400
43 #define QUP_I2C_STATUS 0x404
44 #define QUP_I2C_MASTER_GEN 0x408
45
46 /* QUP States and reset values */
47 #define QUP_RESET_STATE 0
48 #define QUP_RUN_STATE 1
49 #define QUP_PAUSE_STATE 3
50 #define QUP_STATE_MASK 3
51
52 #define QUP_STATE_VALID BIT(2)
53 #define QUP_I2C_MAST_GEN BIT(4)
54 #define QUP_I2C_FLUSH BIT(6)
55
56 #define QUP_OPERATIONAL_RESET 0x000ff0
57 #define QUP_I2C_STATUS_RESET 0xfffffc
58
59 /* QUP OPERATIONAL FLAGS */
60 #define QUP_I2C_NACK_FLAG BIT(3)
61 #define QUP_OUT_NOT_EMPTY BIT(4)
62 #define QUP_IN_NOT_EMPTY BIT(5)
63 #define QUP_OUT_FULL BIT(6)
64 #define QUP_OUT_SVC_FLAG BIT(8)
65 #define QUP_IN_SVC_FLAG BIT(9)
66 #define QUP_MX_OUTPUT_DONE BIT(10)
67 #define QUP_MX_INPUT_DONE BIT(11)
68 #define OUT_BLOCK_WRITE_REQ BIT(12)
69 #define IN_BLOCK_READ_REQ BIT(13)
70
71 /* I2C mini core related values */
72 #define QUP_NO_INPUT BIT(7)
73 #define QUP_CLOCK_AUTO_GATE BIT(13)
74 #define I2C_MINI_CORE (2 << 8)
75 #define I2C_N_VAL 15
76 #define I2C_N_VAL_V2 7
77
78 /* Most significant word offset in FIFO port */
79 #define QUP_MSW_SHIFT (I2C_N_VAL + 1)
80
81 /* Packing/Unpacking words in FIFOs, and IO modes */
82 #define QUP_OUTPUT_BLK_MODE (1 << 10)
83 #define QUP_OUTPUT_BAM_MODE (3 << 10)
84 #define QUP_INPUT_BLK_MODE (1 << 12)
85 #define QUP_INPUT_BAM_MODE (3 << 12)
86 #define QUP_BAM_MODE (QUP_OUTPUT_BAM_MODE | QUP_INPUT_BAM_MODE)
87 #define QUP_UNPACK_EN BIT(14)
88 #define QUP_PACK_EN BIT(15)
89
90 #define QUP_REPACK_EN (QUP_UNPACK_EN | QUP_PACK_EN)
91 #define QUP_V2_TAGS_EN 1
92
93 #define QUP_OUTPUT_BLOCK_SIZE(x)(((x) >> 0) & 0x03)
94 #define QUP_OUTPUT_FIFO_SIZE(x) (((x) >> 2) & 0x07)
95 #define QUP_INPUT_BLOCK_SIZE(x) (((x) >> 5) & 0x03)
96 #define QUP_INPUT_FIFO_SIZE(x) (((x) >> 7) & 0x07)
97
98 /* QUP tags */
99 #define QUP_TAG_START (1 << 8)
100 #define QUP_TAG_DATA (2 << 8)
101 #define QUP_TAG_STOP (3 << 8)
102 #define QUP_TAG_REC (4 << 8)
103 #define QUP_BAM_INPUT_EOT 0x93
104 #define QUP_BAM_FLUSH_STOP 0x96
105
106 /* QUP v2 tags */
107 #define QUP_TAG_V2_START 0x81
108 #define QUP_TAG_V2_DATAWR 0x82
109 #define QUP_TAG_V2_DATAWR_STOP 0x83
110 #define QUP_TAG_V2_DATARD 0x85
111 #define QUP_TAG_V2_DATARD_NACK 0x86
112 #define QUP_TAG_V2_DATARD_STOP 0x87
113
114 /* Status, Error flags */
115 #define I2C_STATUS_WR_BUFFER_FULL BIT(0)
116 #define I2C_STATUS_BUS_ACTIVE BIT(8)
117 #define I2C_STATUS_ERROR_MASK 0x38000fc
118 #define QUP_STATUS_ERROR_FLAGS 0x7c
119
120 #define QUP_READ_LIMIT 256
121 #define SET_BIT 0x1
122 #define RESET_BIT 0x0
123 #define ONE_BYTE 0x1
124 #define QUP_I2C_MX_CONFIG_DURING_RUN BIT(31)
125
126 /* Maximum transfer length for single DMA descriptor */
127 #define MX_TX_RX_LEN SZ_64K
128 #define MX_BLOCKS (MX_TX_RX_LEN / QUP_READ_LIMIT)
129 /* Maximum transfer length for all DMA descriptors */
130 #define MX_DMA_TX_RX_LEN (2 * MX_TX_RX_LEN)
131 #define MX_DMA_BLOCKS (MX_DMA_TX_RX_LEN / QUP_READ_LIMIT)
132
133 /*
134 * Minimum transfer timeout for i2c transfers in seconds. It will be added on
135 * the top of maximum transfer time calculated from i2c bus speed to compensate
136 * the overheads.
137 */
138 #define TOUT_MIN 2
139
140 /* Default values. Use these if FW query fails */
141 #define DEFAULT_CLK_FREQ I2C_MAX_STANDARD_MODE_FREQ
142 #define DEFAULT_SRC_CLK 20000000
143
144 /*
145 * Max tags length (start, stop and maximum 2 bytes address) for each QUP
146 * data transfer
147 */
148 #define QUP_MAX_TAGS_LEN 4
149 /* Max data length for each DATARD tags */
150 #define RECV_MAX_DATA_LEN 254
151 /* TAG length for DATA READ in RX FIFO */
152 #define READ_RX_TAGS_LEN 2
153
154 #define QUP_BUS_WIDTH 8
155
156 static unsigned int scl_freq;
157 module_param_named(scl_freq, scl_freq, uint, 0444);
158 MODULE_PARM_DESC(scl_freq, "SCL frequency override");
159
160 /*
161 * count: no of blocks
162 * pos: current block number
163 * tx_tag_len: tx tag length for current block
164 * rx_tag_len: rx tag length for current block
165 * data_len: remaining data length for current message
166 * cur_blk_len: data length for current block
167 * total_tx_len: total tx length including tag bytes for current QUP transfer
168 * total_rx_len: total rx length including tag bytes for current QUP transfer
169 * tx_fifo_data_pos: current byte number in TX FIFO word
170 * tx_fifo_free: number of free bytes in current QUP block write.
171 * rx_fifo_data_pos: current byte number in RX FIFO word
172 * fifo_available: number of available bytes in RX FIFO for current
173 * QUP block read
174 * tx_fifo_data: QUP TX FIFO write works on word basis (4 bytes). New byte write
175 * to TX FIFO will be appended in this data and will be written to
176 * TX FIFO when all the 4 bytes are available.
177 * rx_fifo_data: QUP RX FIFO read works on word basis (4 bytes). This will
178 * contains the 4 bytes of RX data.
179 * cur_data: pointer to tell cur data position for current message
180 * cur_tx_tags: pointer to tell cur position in tags
181 * tx_tags_sent: all tx tag bytes have been written in FIFO word
182 * send_last_word: for tx FIFO, last word send is pending in current block
183 * rx_bytes_read: if all the bytes have been read from rx FIFO.
184 * rx_tags_fetched: all the rx tag bytes have been fetched from rx fifo word
185 * is_tx_blk_mode: whether tx uses block or FIFO mode in case of non BAM xfer.
186 * is_rx_blk_mode: whether rx uses block or FIFO mode in case of non BAM xfer.
187 * tags: contains tx tag bytes for current QUP transfer
188 */
189 struct qup_i2c_block {
190 int count;
191 int pos;
192 int tx_tag_len;
193 int rx_tag_len;
194 int data_len;
195 int cur_blk_len;
196 int total_tx_len;
197 int total_rx_len;
198 int tx_fifo_data_pos;
199 int tx_fifo_free;
200 int rx_fifo_data_pos;
201 int fifo_available;
202 u32 tx_fifo_data;
203 u32 rx_fifo_data;
204 u8 *cur_data;
205 u8 *cur_tx_tags;
206 bool tx_tags_sent;
207 bool send_last_word;
208 bool rx_tags_fetched;
209 bool rx_bytes_read;
210 bool is_tx_blk_mode;
211 bool is_rx_blk_mode;
212 u8 tags[6];
213 };
214
215 struct qup_i2c_tag {
216 u8 *start;
217 dma_addr_t addr;
218 };
219
220 struct qup_i2c_bam {
221 struct qup_i2c_tag tag;
222 struct dma_chan *dma;
223 struct scatterlist *sg;
224 unsigned int sg_cnt;
225 };
226
227 struct qup_i2c_dev {
228 struct device *dev;
229 void __iomem *base;
230 int irq;
231 struct clk *clk;
232 struct clk *pclk;
233 struct icc_path *icc_path;
234 struct i2c_adapter adap;
235
236 int clk_ctl;
237 int out_fifo_sz;
238 int in_fifo_sz;
239 int out_blk_sz;
240 int in_blk_sz;
241
242 int blk_xfer_limit;
243 unsigned long one_byte_t;
244 unsigned long xfer_timeout;
245 struct qup_i2c_block blk;
246
247 struct i2c_msg *msg;
248 /* Current posion in user message buffer */
249 int pos;
250 /* I2C protocol errors */
251 u32 bus_err;
252 /* QUP core errors */
253 u32 qup_err;
254
255 /* To check if this is the last msg */
256 bool is_last;
257 bool is_smbus_read;
258
259 /* To configure when bus is in run state */
260 u32 config_run;
261
262 /* bandwidth votes */
263 u32 src_clk_freq;
264 u32 cur_bw_clk_freq;
265
266 /* dma parameters */
267 bool is_dma;
268 /* To check if the current transfer is using DMA */
269 bool use_dma;
270 unsigned int max_xfer_sg_len;
271 unsigned int tag_buf_pos;
272 /* The threshold length above which block mode will be used */
273 unsigned int blk_mode_threshold;
274 struct dma_pool *dpool;
275 struct qup_i2c_tag start_tag;
276 struct qup_i2c_bam brx;
277 struct qup_i2c_bam btx;
278
279 struct completion xfer;
280 /* function to write data in tx fifo */
281 void (*write_tx_fifo)(struct qup_i2c_dev *qup);
282 /* function to read data from rx fifo */
283 void (*read_rx_fifo)(struct qup_i2c_dev *qup);
284 /* function to write tags in tx fifo for i2c read transfer */
285 void (*write_rx_tags)(struct qup_i2c_dev *qup);
286 };
287
qup_i2c_interrupt(int irq,void * dev)288 static irqreturn_t qup_i2c_interrupt(int irq, void *dev)
289 {
290 struct qup_i2c_dev *qup = dev;
291 struct qup_i2c_block *blk = &qup->blk;
292 u32 bus_err;
293 u32 qup_err;
294 u32 opflags;
295
296 bus_err = readl(qup->base + QUP_I2C_STATUS);
297 qup_err = readl(qup->base + QUP_ERROR_FLAGS);
298 opflags = readl(qup->base + QUP_OPERATIONAL);
299
300 if (!qup->msg) {
301 /* Clear Error interrupt */
302 writel(QUP_RESET_STATE, qup->base + QUP_STATE);
303 return IRQ_HANDLED;
304 }
305
306 bus_err &= I2C_STATUS_ERROR_MASK;
307 qup_err &= QUP_STATUS_ERROR_FLAGS;
308
309 /* Clear the error bits in QUP_ERROR_FLAGS */
310 if (qup_err)
311 writel(qup_err, qup->base + QUP_ERROR_FLAGS);
312
313 /* Clear the error bits in QUP_I2C_STATUS */
314 if (bus_err)
315 writel(bus_err, qup->base + QUP_I2C_STATUS);
316
317 /*
318 * Check for BAM mode and returns if already error has come for current
319 * transfer. In Error case, sometimes, QUP generates more than one
320 * interrupt.
321 */
322 if (qup->use_dma && (qup->qup_err || qup->bus_err))
323 return IRQ_HANDLED;
324
325 /* Reset the QUP State in case of error */
326 if (qup_err || bus_err) {
327 /*
328 * Don’t reset the QUP state in case of BAM mode. The BAM
329 * flush operation needs to be scheduled in transfer function
330 * which will clear the remaining schedule descriptors in BAM
331 * HW FIFO and generates the BAM interrupt.
332 */
333 if (!qup->use_dma)
334 writel(QUP_RESET_STATE, qup->base + QUP_STATE);
335 goto done;
336 }
337
338 if (opflags & QUP_OUT_SVC_FLAG) {
339 writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL);
340
341 if (opflags & OUT_BLOCK_WRITE_REQ) {
342 blk->tx_fifo_free += qup->out_blk_sz;
343 if (qup->msg->flags & I2C_M_RD)
344 qup->write_rx_tags(qup);
345 else
346 qup->write_tx_fifo(qup);
347 }
348 }
349
350 if (opflags & QUP_IN_SVC_FLAG) {
351 writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL);
352
353 if (!blk->is_rx_blk_mode) {
354 blk->fifo_available += qup->in_fifo_sz;
355 qup->read_rx_fifo(qup);
356 } else if (opflags & IN_BLOCK_READ_REQ) {
357 blk->fifo_available += qup->in_blk_sz;
358 qup->read_rx_fifo(qup);
359 }
360 }
361
362 if (qup->msg->flags & I2C_M_RD) {
363 if (!blk->rx_bytes_read)
364 return IRQ_HANDLED;
365 } else {
366 /*
367 * Ideally, QUP_MAX_OUTPUT_DONE_FLAG should be checked
368 * for FIFO mode also. But, QUP_MAX_OUTPUT_DONE_FLAG lags
369 * behind QUP_OUTPUT_SERVICE_FLAG sometimes. The only reason
370 * of interrupt for write message in FIFO mode is
371 * QUP_MAX_OUTPUT_DONE_FLAG condition.
372 */
373 if (blk->is_tx_blk_mode && !(opflags & QUP_MX_OUTPUT_DONE))
374 return IRQ_HANDLED;
375 }
376
377 done:
378 qup->qup_err = qup_err;
379 qup->bus_err = bus_err;
380 complete(&qup->xfer);
381 return IRQ_HANDLED;
382 }
383
qup_i2c_poll_state_mask(struct qup_i2c_dev * qup,u32 req_state,u32 req_mask)384 static int qup_i2c_poll_state_mask(struct qup_i2c_dev *qup,
385 u32 req_state, u32 req_mask)
386 {
387 int retries = 1;
388 u32 state;
389
390 /*
391 * State transition takes 3 AHB clocks cycles + 3 I2C master clock
392 * cycles. So retry once after a 1uS delay.
393 */
394 do {
395 state = readl(qup->base + QUP_STATE);
396
397 if (state & QUP_STATE_VALID &&
398 (state & req_mask) == req_state)
399 return 0;
400
401 udelay(1);
402 } while (retries--);
403
404 return -ETIMEDOUT;
405 }
406
qup_i2c_poll_state(struct qup_i2c_dev * qup,u32 req_state)407 static int qup_i2c_poll_state(struct qup_i2c_dev *qup, u32 req_state)
408 {
409 return qup_i2c_poll_state_mask(qup, req_state, QUP_STATE_MASK);
410 }
411
qup_i2c_flush(struct qup_i2c_dev * qup)412 static void qup_i2c_flush(struct qup_i2c_dev *qup)
413 {
414 u32 val = readl(qup->base + QUP_STATE);
415
416 val |= QUP_I2C_FLUSH;
417 writel(val, qup->base + QUP_STATE);
418 }
419
qup_i2c_poll_state_valid(struct qup_i2c_dev * qup)420 static int qup_i2c_poll_state_valid(struct qup_i2c_dev *qup)
421 {
422 return qup_i2c_poll_state_mask(qup, 0, 0);
423 }
424
qup_i2c_poll_state_i2c_master(struct qup_i2c_dev * qup)425 static int qup_i2c_poll_state_i2c_master(struct qup_i2c_dev *qup)
426 {
427 return qup_i2c_poll_state_mask(qup, QUP_I2C_MAST_GEN, QUP_I2C_MAST_GEN);
428 }
429
qup_i2c_change_state(struct qup_i2c_dev * qup,u32 state)430 static int qup_i2c_change_state(struct qup_i2c_dev *qup, u32 state)
431 {
432 if (qup_i2c_poll_state_valid(qup) != 0)
433 return -EIO;
434
435 writel(state, qup->base + QUP_STATE);
436
437 if (qup_i2c_poll_state(qup, state) != 0)
438 return -EIO;
439 return 0;
440 }
441
442 /* Check if I2C bus returns to IDLE state */
qup_i2c_bus_active(struct qup_i2c_dev * qup,int len)443 static int qup_i2c_bus_active(struct qup_i2c_dev *qup, int len)
444 {
445 unsigned long timeout;
446 u32 status;
447 int ret = 0;
448
449 timeout = jiffies + len * 4;
450 for (;;) {
451 status = readl(qup->base + QUP_I2C_STATUS);
452 if (!(status & I2C_STATUS_BUS_ACTIVE))
453 break;
454
455 if (time_after(jiffies, timeout))
456 ret = -ETIMEDOUT;
457
458 usleep_range(len, len * 2);
459 }
460
461 return ret;
462 }
463
qup_i2c_vote_bw(struct qup_i2c_dev * qup,u32 clk_freq)464 static int qup_i2c_vote_bw(struct qup_i2c_dev *qup, u32 clk_freq)
465 {
466 u32 needed_peak_bw;
467 int ret;
468
469 if (qup->cur_bw_clk_freq == clk_freq)
470 return 0;
471
472 needed_peak_bw = Bps_to_icc(clk_freq * QUP_BUS_WIDTH);
473 ret = icc_set_bw(qup->icc_path, 0, needed_peak_bw);
474 if (ret)
475 return ret;
476
477 qup->cur_bw_clk_freq = clk_freq;
478 return 0;
479 }
480
qup_i2c_write_tx_fifo_v1(struct qup_i2c_dev * qup)481 static void qup_i2c_write_tx_fifo_v1(struct qup_i2c_dev *qup)
482 {
483 struct qup_i2c_block *blk = &qup->blk;
484 struct i2c_msg *msg = qup->msg;
485 u32 addr = i2c_8bit_addr_from_msg(msg);
486 u32 qup_tag;
487 int idx;
488 u32 val;
489
490 if (qup->pos == 0) {
491 val = QUP_TAG_START | addr;
492 idx = 1;
493 blk->tx_fifo_free--;
494 } else {
495 val = 0;
496 idx = 0;
497 }
498
499 while (blk->tx_fifo_free && qup->pos < msg->len) {
500 if (qup->pos == msg->len - 1)
501 qup_tag = QUP_TAG_STOP;
502 else
503 qup_tag = QUP_TAG_DATA;
504
505 if (idx & 1)
506 val |= (qup_tag | msg->buf[qup->pos]) << QUP_MSW_SHIFT;
507 else
508 val = qup_tag | msg->buf[qup->pos];
509
510 /* Write out the pair and the last odd value */
511 if (idx & 1 || qup->pos == msg->len - 1)
512 writel(val, qup->base + QUP_OUT_FIFO_BASE);
513
514 qup->pos++;
515 idx++;
516 blk->tx_fifo_free--;
517 }
518 }
519
qup_i2c_set_blk_data(struct qup_i2c_dev * qup,struct i2c_msg * msg)520 static void qup_i2c_set_blk_data(struct qup_i2c_dev *qup,
521 struct i2c_msg *msg)
522 {
523 qup->blk.pos = 0;
524 qup->blk.data_len = msg->len;
525 qup->blk.count = DIV_ROUND_UP(msg->len, qup->blk_xfer_limit);
526 }
527
qup_i2c_get_data_len(struct qup_i2c_dev * qup)528 static int qup_i2c_get_data_len(struct qup_i2c_dev *qup)
529 {
530 int data_len;
531
532 if (qup->blk.data_len > qup->blk_xfer_limit)
533 data_len = qup->blk_xfer_limit;
534 else
535 data_len = qup->blk.data_len;
536
537 return data_len;
538 }
539
qup_i2c_check_msg_len(struct i2c_msg * msg)540 static bool qup_i2c_check_msg_len(struct i2c_msg *msg)
541 {
542 return ((msg->flags & I2C_M_RD) && (msg->flags & I2C_M_RECV_LEN));
543 }
544
qup_i2c_set_tags_smb(u16 addr,u8 * tags,struct qup_i2c_dev * qup,struct i2c_msg * msg)545 static int qup_i2c_set_tags_smb(u16 addr, u8 *tags, struct qup_i2c_dev *qup,
546 struct i2c_msg *msg)
547 {
548 int len = 0;
549
550 if (qup->is_smbus_read) {
551 tags[len++] = QUP_TAG_V2_DATARD_STOP;
552 tags[len++] = qup_i2c_get_data_len(qup);
553 } else {
554 tags[len++] = QUP_TAG_V2_START;
555 tags[len++] = addr & 0xff;
556
557 if (msg->flags & I2C_M_TEN)
558 tags[len++] = addr >> 8;
559
560 tags[len++] = QUP_TAG_V2_DATARD;
561 /* Read 1 byte indicating the length of the SMBus message */
562 tags[len++] = 1;
563 }
564 return len;
565 }
566
qup_i2c_set_tags(u8 * tags,struct qup_i2c_dev * qup,struct i2c_msg * msg)567 static int qup_i2c_set_tags(u8 *tags, struct qup_i2c_dev *qup,
568 struct i2c_msg *msg)
569 {
570 u16 addr = i2c_8bit_addr_from_msg(msg);
571 int len = 0;
572 int data_len;
573
574 int last = (qup->blk.pos == (qup->blk.count - 1)) && (qup->is_last);
575
576 /* Handle tags for SMBus block read */
577 if (qup_i2c_check_msg_len(msg))
578 return qup_i2c_set_tags_smb(addr, tags, qup, msg);
579
580 if (qup->blk.pos == 0) {
581 tags[len++] = QUP_TAG_V2_START;
582 tags[len++] = addr & 0xff;
583
584 if (msg->flags & I2C_M_TEN)
585 tags[len++] = addr >> 8;
586 }
587
588 /* Send _STOP commands for the last block */
589 if (last) {
590 if (msg->flags & I2C_M_RD)
591 tags[len++] = QUP_TAG_V2_DATARD_STOP;
592 else
593 tags[len++] = QUP_TAG_V2_DATAWR_STOP;
594 } else {
595 if (msg->flags & I2C_M_RD)
596 tags[len++] = qup->blk.pos == (qup->blk.count - 1) ?
597 QUP_TAG_V2_DATARD_NACK :
598 QUP_TAG_V2_DATARD;
599 else
600 tags[len++] = QUP_TAG_V2_DATAWR;
601 }
602
603 data_len = qup_i2c_get_data_len(qup);
604
605 /* 0 implies 256 bytes */
606 if (data_len == QUP_READ_LIMIT)
607 tags[len++] = 0;
608 else
609 tags[len++] = data_len;
610
611 return len;
612 }
613
614
qup_i2c_bam_cb(void * data)615 static void qup_i2c_bam_cb(void *data)
616 {
617 struct qup_i2c_dev *qup = data;
618
619 complete(&qup->xfer);
620 }
621
qup_sg_set_buf(struct scatterlist * sg,void * buf,unsigned int buflen,struct qup_i2c_dev * qup,int dir)622 static int qup_sg_set_buf(struct scatterlist *sg, void *buf,
623 unsigned int buflen, struct qup_i2c_dev *qup,
624 int dir)
625 {
626 int ret;
627
628 sg_set_buf(sg, buf, buflen);
629 ret = dma_map_sg(qup->dev, sg, 1, dir);
630 if (!ret)
631 return -EINVAL;
632
633 return 0;
634 }
635
qup_i2c_rel_dma(struct qup_i2c_dev * qup)636 static void qup_i2c_rel_dma(struct qup_i2c_dev *qup)
637 {
638 if (qup->btx.dma)
639 dma_release_channel(qup->btx.dma);
640 if (qup->brx.dma)
641 dma_release_channel(qup->brx.dma);
642 qup->btx.dma = NULL;
643 qup->brx.dma = NULL;
644 }
645
qup_i2c_req_dma(struct qup_i2c_dev * qup)646 static int qup_i2c_req_dma(struct qup_i2c_dev *qup)
647 {
648 int err;
649
650 if (!qup->btx.dma) {
651 qup->btx.dma = dma_request_chan(qup->dev, "tx");
652 if (IS_ERR(qup->btx.dma)) {
653 err = PTR_ERR(qup->btx.dma);
654 qup->btx.dma = NULL;
655 dev_err(qup->dev, "\n tx channel not available");
656 return err;
657 }
658 }
659
660 if (!qup->brx.dma) {
661 qup->brx.dma = dma_request_chan(qup->dev, "rx");
662 if (IS_ERR(qup->brx.dma)) {
663 dev_err(qup->dev, "\n rx channel not available");
664 err = PTR_ERR(qup->brx.dma);
665 qup->brx.dma = NULL;
666 qup_i2c_rel_dma(qup);
667 return err;
668 }
669 }
670 return 0;
671 }
672
qup_i2c_bam_make_desc(struct qup_i2c_dev * qup,struct i2c_msg * msg)673 static int qup_i2c_bam_make_desc(struct qup_i2c_dev *qup, struct i2c_msg *msg)
674 {
675 int ret = 0, limit = QUP_READ_LIMIT;
676 u32 len = 0, blocks, rem;
677 u32 i = 0, tlen, tx_len = 0;
678 u8 *tags;
679
680 qup->blk_xfer_limit = QUP_READ_LIMIT;
681 qup_i2c_set_blk_data(qup, msg);
682
683 blocks = qup->blk.count;
684 rem = msg->len - (blocks - 1) * limit;
685
686 if (msg->flags & I2C_M_RD) {
687 while (qup->blk.pos < blocks) {
688 tlen = (i == (blocks - 1)) ? rem : limit;
689 tags = &qup->start_tag.start[qup->tag_buf_pos + len];
690 len += qup_i2c_set_tags(tags, qup, msg);
691 qup->blk.data_len -= tlen;
692
693 /* scratch buf to read the start and len tags */
694 ret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++],
695 &qup->brx.tag.start[0],
696 2, qup, DMA_FROM_DEVICE);
697
698 if (ret)
699 return ret;
700
701 ret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++],
702 &msg->buf[limit * i],
703 tlen, qup,
704 DMA_FROM_DEVICE);
705 if (ret)
706 return ret;
707
708 i++;
709 qup->blk.pos = i;
710 }
711 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++],
712 &qup->start_tag.start[qup->tag_buf_pos],
713 len, qup, DMA_TO_DEVICE);
714 if (ret)
715 return ret;
716
717 qup->tag_buf_pos += len;
718 } else {
719 while (qup->blk.pos < blocks) {
720 tlen = (i == (blocks - 1)) ? rem : limit;
721 tags = &qup->start_tag.start[qup->tag_buf_pos + tx_len];
722 len = qup_i2c_set_tags(tags, qup, msg);
723 qup->blk.data_len -= tlen;
724
725 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++],
726 tags, len,
727 qup, DMA_TO_DEVICE);
728 if (ret)
729 return ret;
730
731 tx_len += len;
732 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++],
733 &msg->buf[limit * i],
734 tlen, qup, DMA_TO_DEVICE);
735 if (ret)
736 return ret;
737 i++;
738 qup->blk.pos = i;
739 }
740
741 qup->tag_buf_pos += tx_len;
742 }
743
744 return 0;
745 }
746
qup_i2c_bam_schedule_desc(struct qup_i2c_dev * qup)747 static int qup_i2c_bam_schedule_desc(struct qup_i2c_dev *qup)
748 {
749 struct dma_async_tx_descriptor *txd, *rxd = NULL;
750 int ret = 0;
751 dma_cookie_t cookie_rx, cookie_tx;
752 u32 len = 0;
753 u32 tx_cnt = qup->btx.sg_cnt, rx_cnt = qup->brx.sg_cnt;
754
755 /* schedule the EOT and FLUSH I2C tags */
756 len = 1;
757 if (rx_cnt) {
758 qup->btx.tag.start[0] = QUP_BAM_INPUT_EOT;
759 len++;
760
761 /* scratch buf to read the BAM EOT FLUSH tags */
762 ret = qup_sg_set_buf(&qup->brx.sg[rx_cnt++],
763 &qup->brx.tag.start[0],
764 1, qup, DMA_FROM_DEVICE);
765 if (ret)
766 return ret;
767 }
768
769 qup->btx.tag.start[len - 1] = QUP_BAM_FLUSH_STOP;
770 ret = qup_sg_set_buf(&qup->btx.sg[tx_cnt++], &qup->btx.tag.start[0],
771 len, qup, DMA_TO_DEVICE);
772 if (ret)
773 return ret;
774
775 txd = dmaengine_prep_slave_sg(qup->btx.dma, qup->btx.sg, tx_cnt,
776 DMA_MEM_TO_DEV,
777 DMA_PREP_INTERRUPT | DMA_PREP_FENCE);
778 if (!txd) {
779 dev_err(qup->dev, "failed to get tx desc\n");
780 ret = -EINVAL;
781 goto desc_err;
782 }
783
784 if (!rx_cnt) {
785 txd->callback = qup_i2c_bam_cb;
786 txd->callback_param = qup;
787 }
788
789 cookie_tx = dmaengine_submit(txd);
790 if (dma_submit_error(cookie_tx)) {
791 ret = -EINVAL;
792 goto desc_err;
793 }
794
795 dma_async_issue_pending(qup->btx.dma);
796
797 if (rx_cnt) {
798 rxd = dmaengine_prep_slave_sg(qup->brx.dma, qup->brx.sg,
799 rx_cnt, DMA_DEV_TO_MEM,
800 DMA_PREP_INTERRUPT);
801 if (!rxd) {
802 dev_err(qup->dev, "failed to get rx desc\n");
803 ret = -EINVAL;
804
805 /* abort TX descriptors */
806 dmaengine_terminate_sync(qup->btx.dma);
807 goto desc_err;
808 }
809
810 rxd->callback = qup_i2c_bam_cb;
811 rxd->callback_param = qup;
812 cookie_rx = dmaengine_submit(rxd);
813 if (dma_submit_error(cookie_rx)) {
814 ret = -EINVAL;
815 goto desc_err;
816 }
817
818 dma_async_issue_pending(qup->brx.dma);
819 }
820
821 if (!wait_for_completion_timeout(&qup->xfer, qup->xfer_timeout))
822 ret = -ETIMEDOUT;
823
824 if (ret || qup->bus_err || qup->qup_err) {
825 reinit_completion(&qup->xfer);
826
827 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
828 if (ret) {
829 dev_err(qup->dev, "change to run state timed out");
830 goto desc_err;
831 }
832
833 qup_i2c_flush(qup);
834
835 /* wait for remaining interrupts to occur */
836 if (!wait_for_completion_timeout(&qup->xfer, HZ))
837 dev_err(qup->dev, "flush timed out\n");
838
839 ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO;
840 }
841
842 desc_err:
843 dma_unmap_sg(qup->dev, qup->btx.sg, tx_cnt, DMA_TO_DEVICE);
844
845 if (rx_cnt)
846 dma_unmap_sg(qup->dev, qup->brx.sg, rx_cnt,
847 DMA_FROM_DEVICE);
848
849 return ret;
850 }
851
qup_i2c_bam_clear_tag_buffers(struct qup_i2c_dev * qup)852 static void qup_i2c_bam_clear_tag_buffers(struct qup_i2c_dev *qup)
853 {
854 qup->btx.sg_cnt = 0;
855 qup->brx.sg_cnt = 0;
856 qup->tag_buf_pos = 0;
857 }
858
qup_i2c_bam_xfer(struct i2c_adapter * adap,struct i2c_msg * msg,int num)859 static int qup_i2c_bam_xfer(struct i2c_adapter *adap, struct i2c_msg *msg,
860 int num)
861 {
862 struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
863 int ret = 0;
864 int idx = 0;
865
866 ret = qup_i2c_vote_bw(qup, qup->src_clk_freq);
867 if (ret)
868 return ret;
869
870 enable_irq(qup->irq);
871 ret = qup_i2c_req_dma(qup);
872
873 if (ret)
874 goto out;
875
876 writel(0, qup->base + QUP_MX_INPUT_CNT);
877 writel(0, qup->base + QUP_MX_OUTPUT_CNT);
878
879 /* set BAM mode */
880 writel(QUP_REPACK_EN | QUP_BAM_MODE, qup->base + QUP_IO_MODE);
881
882 /* mask fifo irqs */
883 writel((0x3 << 8), qup->base + QUP_OPERATIONAL_MASK);
884
885 /* set RUN STATE */
886 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
887 if (ret)
888 goto out;
889
890 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
891 qup_i2c_bam_clear_tag_buffers(qup);
892
893 for (idx = 0; idx < num; idx++) {
894 qup->msg = msg + idx;
895 qup->is_last = idx == (num - 1);
896
897 ret = qup_i2c_bam_make_desc(qup, qup->msg);
898 if (ret)
899 break;
900
901 /*
902 * Make DMA descriptor and schedule the BAM transfer if its
903 * already crossed the maximum length. Since the memory for all
904 * tags buffers have been taken for 2 maximum possible
905 * transfers length so it will never cross the buffer actual
906 * length.
907 */
908 if (qup->btx.sg_cnt > qup->max_xfer_sg_len ||
909 qup->brx.sg_cnt > qup->max_xfer_sg_len ||
910 qup->is_last) {
911 ret = qup_i2c_bam_schedule_desc(qup);
912 if (ret)
913 break;
914
915 qup_i2c_bam_clear_tag_buffers(qup);
916 }
917 }
918
919 out:
920 disable_irq(qup->irq);
921
922 qup->msg = NULL;
923 return ret;
924 }
925
qup_i2c_wait_for_complete(struct qup_i2c_dev * qup,struct i2c_msg * msg)926 static int qup_i2c_wait_for_complete(struct qup_i2c_dev *qup,
927 struct i2c_msg *msg)
928 {
929 unsigned long left;
930 int ret = 0;
931
932 left = wait_for_completion_timeout(&qup->xfer, qup->xfer_timeout);
933 if (!left) {
934 writel(1, qup->base + QUP_SW_RESET);
935 ret = -ETIMEDOUT;
936 }
937
938 if (qup->bus_err || qup->qup_err)
939 ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO;
940
941 return ret;
942 }
943
qup_i2c_read_rx_fifo_v1(struct qup_i2c_dev * qup)944 static void qup_i2c_read_rx_fifo_v1(struct qup_i2c_dev *qup)
945 {
946 struct qup_i2c_block *blk = &qup->blk;
947 struct i2c_msg *msg = qup->msg;
948 u32 val = 0;
949 int idx = 0;
950
951 while (blk->fifo_available && qup->pos < msg->len) {
952 if ((idx & 1) == 0) {
953 /* Reading 2 words at time */
954 val = readl(qup->base + QUP_IN_FIFO_BASE);
955 msg->buf[qup->pos++] = val & 0xFF;
956 } else {
957 msg->buf[qup->pos++] = val >> QUP_MSW_SHIFT;
958 }
959 idx++;
960 blk->fifo_available--;
961 }
962
963 if (qup->pos == msg->len)
964 blk->rx_bytes_read = true;
965 }
966
qup_i2c_write_rx_tags_v1(struct qup_i2c_dev * qup)967 static void qup_i2c_write_rx_tags_v1(struct qup_i2c_dev *qup)
968 {
969 struct i2c_msg *msg = qup->msg;
970 u32 addr, len, val;
971
972 addr = i2c_8bit_addr_from_msg(msg);
973
974 /* 0 is used to specify a length 256 (QUP_READ_LIMIT) */
975 len = (msg->len == QUP_READ_LIMIT) ? 0 : msg->len;
976
977 val = ((QUP_TAG_REC | len) << QUP_MSW_SHIFT) | QUP_TAG_START | addr;
978 writel(val, qup->base + QUP_OUT_FIFO_BASE);
979 }
980
qup_i2c_conf_v1(struct qup_i2c_dev * qup)981 static void qup_i2c_conf_v1(struct qup_i2c_dev *qup)
982 {
983 struct qup_i2c_block *blk = &qup->blk;
984 u32 qup_config = I2C_MINI_CORE | I2C_N_VAL;
985 u32 io_mode = QUP_REPACK_EN;
986
987 blk->is_tx_blk_mode = blk->total_tx_len > qup->out_fifo_sz;
988 blk->is_rx_blk_mode = blk->total_rx_len > qup->in_fifo_sz;
989
990 if (blk->is_tx_blk_mode) {
991 io_mode |= QUP_OUTPUT_BLK_MODE;
992 writel(0, qup->base + QUP_MX_WRITE_CNT);
993 writel(blk->total_tx_len, qup->base + QUP_MX_OUTPUT_CNT);
994 } else {
995 writel(0, qup->base + QUP_MX_OUTPUT_CNT);
996 writel(blk->total_tx_len, qup->base + QUP_MX_WRITE_CNT);
997 }
998
999 if (blk->total_rx_len) {
1000 if (blk->is_rx_blk_mode) {
1001 io_mode |= QUP_INPUT_BLK_MODE;
1002 writel(0, qup->base + QUP_MX_READ_CNT);
1003 writel(blk->total_rx_len, qup->base + QUP_MX_INPUT_CNT);
1004 } else {
1005 writel(0, qup->base + QUP_MX_INPUT_CNT);
1006 writel(blk->total_rx_len, qup->base + QUP_MX_READ_CNT);
1007 }
1008 } else {
1009 qup_config |= QUP_NO_INPUT;
1010 }
1011
1012 writel(qup_config, qup->base + QUP_CONFIG);
1013 writel(io_mode, qup->base + QUP_IO_MODE);
1014 }
1015
qup_i2c_clear_blk_v1(struct qup_i2c_block * blk)1016 static void qup_i2c_clear_blk_v1(struct qup_i2c_block *blk)
1017 {
1018 blk->tx_fifo_free = 0;
1019 blk->fifo_available = 0;
1020 blk->rx_bytes_read = false;
1021 }
1022
qup_i2c_conf_xfer_v1(struct qup_i2c_dev * qup,bool is_rx)1023 static int qup_i2c_conf_xfer_v1(struct qup_i2c_dev *qup, bool is_rx)
1024 {
1025 struct qup_i2c_block *blk = &qup->blk;
1026 int ret;
1027
1028 qup_i2c_clear_blk_v1(blk);
1029 qup_i2c_conf_v1(qup);
1030 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1031 if (ret)
1032 return ret;
1033
1034 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
1035
1036 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
1037 if (ret)
1038 return ret;
1039
1040 reinit_completion(&qup->xfer);
1041 enable_irq(qup->irq);
1042 if (!blk->is_tx_blk_mode) {
1043 blk->tx_fifo_free = qup->out_fifo_sz;
1044
1045 if (is_rx)
1046 qup_i2c_write_rx_tags_v1(qup);
1047 else
1048 qup_i2c_write_tx_fifo_v1(qup);
1049 }
1050
1051 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1052 if (ret)
1053 goto err;
1054
1055 ret = qup_i2c_wait_for_complete(qup, qup->msg);
1056 if (ret)
1057 goto err;
1058
1059 ret = qup_i2c_bus_active(qup, ONE_BYTE);
1060
1061 err:
1062 disable_irq(qup->irq);
1063 return ret;
1064 }
1065
qup_i2c_write_one(struct qup_i2c_dev * qup)1066 static int qup_i2c_write_one(struct qup_i2c_dev *qup)
1067 {
1068 struct i2c_msg *msg = qup->msg;
1069 struct qup_i2c_block *blk = &qup->blk;
1070
1071 qup->pos = 0;
1072 blk->total_tx_len = msg->len + 1;
1073 blk->total_rx_len = 0;
1074
1075 return qup_i2c_conf_xfer_v1(qup, false);
1076 }
1077
qup_i2c_read_one(struct qup_i2c_dev * qup)1078 static int qup_i2c_read_one(struct qup_i2c_dev *qup)
1079 {
1080 struct qup_i2c_block *blk = &qup->blk;
1081
1082 qup->pos = 0;
1083 blk->total_tx_len = 2;
1084 blk->total_rx_len = qup->msg->len;
1085
1086 return qup_i2c_conf_xfer_v1(qup, true);
1087 }
1088
qup_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)1089 static int qup_i2c_xfer(struct i2c_adapter *adap,
1090 struct i2c_msg msgs[],
1091 int num)
1092 {
1093 struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
1094 int ret, idx;
1095
1096 ret = pm_runtime_get_sync(qup->dev);
1097 if (ret < 0)
1098 goto out;
1099
1100 qup->bus_err = 0;
1101 qup->qup_err = 0;
1102
1103 writel(1, qup->base + QUP_SW_RESET);
1104 ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
1105 if (ret)
1106 goto out;
1107
1108 /* Configure QUP as I2C mini core */
1109 writel(I2C_MINI_CORE | I2C_N_VAL, qup->base + QUP_CONFIG);
1110
1111 for (idx = 0; idx < num; idx++) {
1112 if (qup_i2c_poll_state_i2c_master(qup)) {
1113 ret = -EIO;
1114 goto out;
1115 }
1116
1117 if (qup_i2c_check_msg_len(&msgs[idx])) {
1118 ret = -EINVAL;
1119 goto out;
1120 }
1121
1122 qup->msg = &msgs[idx];
1123 if (msgs[idx].flags & I2C_M_RD)
1124 ret = qup_i2c_read_one(qup);
1125 else
1126 ret = qup_i2c_write_one(qup);
1127
1128 if (ret)
1129 break;
1130
1131 ret = qup_i2c_change_state(qup, QUP_RESET_STATE);
1132 if (ret)
1133 break;
1134 }
1135
1136 if (ret == 0)
1137 ret = num;
1138 out:
1139
1140 pm_runtime_mark_last_busy(qup->dev);
1141 pm_runtime_put_autosuspend(qup->dev);
1142
1143 return ret;
1144 }
1145
1146 /*
1147 * Configure registers related with reconfiguration during run and call it
1148 * before each i2c sub transfer.
1149 */
qup_i2c_conf_count_v2(struct qup_i2c_dev * qup)1150 static void qup_i2c_conf_count_v2(struct qup_i2c_dev *qup)
1151 {
1152 struct qup_i2c_block *blk = &qup->blk;
1153 u32 qup_config = I2C_MINI_CORE | I2C_N_VAL_V2;
1154
1155 if (blk->is_tx_blk_mode)
1156 writel(qup->config_run | blk->total_tx_len,
1157 qup->base + QUP_MX_OUTPUT_CNT);
1158 else
1159 writel(qup->config_run | blk->total_tx_len,
1160 qup->base + QUP_MX_WRITE_CNT);
1161
1162 if (blk->total_rx_len) {
1163 if (blk->is_rx_blk_mode)
1164 writel(qup->config_run | blk->total_rx_len,
1165 qup->base + QUP_MX_INPUT_CNT);
1166 else
1167 writel(qup->config_run | blk->total_rx_len,
1168 qup->base + QUP_MX_READ_CNT);
1169 } else {
1170 qup_config |= QUP_NO_INPUT;
1171 }
1172
1173 writel(qup_config, qup->base + QUP_CONFIG);
1174 }
1175
1176 /*
1177 * Configure registers related with transfer mode (FIFO/Block)
1178 * before starting of i2c transfer. It will be called only once in
1179 * QUP RESET state.
1180 */
qup_i2c_conf_mode_v2(struct qup_i2c_dev * qup)1181 static void qup_i2c_conf_mode_v2(struct qup_i2c_dev *qup)
1182 {
1183 struct qup_i2c_block *blk = &qup->blk;
1184 u32 io_mode = QUP_REPACK_EN;
1185
1186 if (blk->is_tx_blk_mode) {
1187 io_mode |= QUP_OUTPUT_BLK_MODE;
1188 writel(0, qup->base + QUP_MX_WRITE_CNT);
1189 } else {
1190 writel(0, qup->base + QUP_MX_OUTPUT_CNT);
1191 }
1192
1193 if (blk->is_rx_blk_mode) {
1194 io_mode |= QUP_INPUT_BLK_MODE;
1195 writel(0, qup->base + QUP_MX_READ_CNT);
1196 } else {
1197 writel(0, qup->base + QUP_MX_INPUT_CNT);
1198 }
1199
1200 writel(io_mode, qup->base + QUP_IO_MODE);
1201 }
1202
1203 /* Clear required variables before starting of any QUP v2 sub transfer. */
qup_i2c_clear_blk_v2(struct qup_i2c_block * blk)1204 static void qup_i2c_clear_blk_v2(struct qup_i2c_block *blk)
1205 {
1206 blk->send_last_word = false;
1207 blk->tx_tags_sent = false;
1208 blk->tx_fifo_data = 0;
1209 blk->tx_fifo_data_pos = 0;
1210 blk->tx_fifo_free = 0;
1211
1212 blk->rx_tags_fetched = false;
1213 blk->rx_bytes_read = false;
1214 blk->rx_fifo_data = 0;
1215 blk->rx_fifo_data_pos = 0;
1216 blk->fifo_available = 0;
1217 }
1218
1219 /* Receive data from RX FIFO for read message in QUP v2 i2c transfer. */
qup_i2c_recv_data(struct qup_i2c_dev * qup)1220 static void qup_i2c_recv_data(struct qup_i2c_dev *qup)
1221 {
1222 struct qup_i2c_block *blk = &qup->blk;
1223 int j;
1224
1225 for (j = blk->rx_fifo_data_pos;
1226 blk->cur_blk_len && blk->fifo_available;
1227 blk->cur_blk_len--, blk->fifo_available--) {
1228 if (j == 0)
1229 blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE);
1230
1231 *(blk->cur_data++) = blk->rx_fifo_data;
1232 blk->rx_fifo_data >>= 8;
1233
1234 if (j == 3)
1235 j = 0;
1236 else
1237 j++;
1238 }
1239
1240 blk->rx_fifo_data_pos = j;
1241 }
1242
1243 /* Receive tags for read message in QUP v2 i2c transfer. */
qup_i2c_recv_tags(struct qup_i2c_dev * qup)1244 static void qup_i2c_recv_tags(struct qup_i2c_dev *qup)
1245 {
1246 struct qup_i2c_block *blk = &qup->blk;
1247
1248 blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE);
1249 blk->rx_fifo_data >>= blk->rx_tag_len * 8;
1250 blk->rx_fifo_data_pos = blk->rx_tag_len;
1251 blk->fifo_available -= blk->rx_tag_len;
1252 }
1253
1254 /*
1255 * Read the data and tags from RX FIFO. Since in read case, the tags will be
1256 * preceded by received data bytes so
1257 * 1. Check if rx_tags_fetched is false i.e. the start of QUP block so receive
1258 * all tag bytes and discard that.
1259 * 2. Read the data from RX FIFO. When all the data bytes have been read then
1260 * set rx_bytes_read to true.
1261 */
qup_i2c_read_rx_fifo_v2(struct qup_i2c_dev * qup)1262 static void qup_i2c_read_rx_fifo_v2(struct qup_i2c_dev *qup)
1263 {
1264 struct qup_i2c_block *blk = &qup->blk;
1265
1266 if (!blk->rx_tags_fetched) {
1267 qup_i2c_recv_tags(qup);
1268 blk->rx_tags_fetched = true;
1269 }
1270
1271 qup_i2c_recv_data(qup);
1272 if (!blk->cur_blk_len)
1273 blk->rx_bytes_read = true;
1274 }
1275
1276 /*
1277 * Write bytes in TX FIFO for write message in QUP v2 i2c transfer. QUP TX FIFO
1278 * write works on word basis (4 bytes). Append new data byte write for TX FIFO
1279 * in tx_fifo_data and write to TX FIFO when all the 4 bytes are present.
1280 */
1281 static void
qup_i2c_write_blk_data(struct qup_i2c_dev * qup,u8 ** data,unsigned int * len)1282 qup_i2c_write_blk_data(struct qup_i2c_dev *qup, u8 **data, unsigned int *len)
1283 {
1284 struct qup_i2c_block *blk = &qup->blk;
1285 unsigned int j;
1286
1287 for (j = blk->tx_fifo_data_pos; *len && blk->tx_fifo_free;
1288 (*len)--, blk->tx_fifo_free--) {
1289 blk->tx_fifo_data |= *(*data)++ << (j * 8);
1290 if (j == 3) {
1291 writel(blk->tx_fifo_data,
1292 qup->base + QUP_OUT_FIFO_BASE);
1293 blk->tx_fifo_data = 0x0;
1294 j = 0;
1295 } else {
1296 j++;
1297 }
1298 }
1299
1300 blk->tx_fifo_data_pos = j;
1301 }
1302
1303 /* Transfer tags for read message in QUP v2 i2c transfer. */
qup_i2c_write_rx_tags_v2(struct qup_i2c_dev * qup)1304 static void qup_i2c_write_rx_tags_v2(struct qup_i2c_dev *qup)
1305 {
1306 struct qup_i2c_block *blk = &qup->blk;
1307
1308 qup_i2c_write_blk_data(qup, &blk->cur_tx_tags, &blk->tx_tag_len);
1309 if (blk->tx_fifo_data_pos)
1310 writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE);
1311 }
1312
1313 /*
1314 * Write the data and tags in TX FIFO. Since in write case, both tags and data
1315 * need to be written and QUP write tags can have maximum 256 data length, so
1316 *
1317 * 1. Check if tx_tags_sent is false i.e. the start of QUP block so write the
1318 * tags to TX FIFO and set tx_tags_sent to true.
1319 * 2. Check if send_last_word is true. It will be set when last few data bytes
1320 * (less than 4 bytes) are remaining to be written in FIFO because of no FIFO
1321 * space. All this data bytes are available in tx_fifo_data so write this
1322 * in FIFO.
1323 * 3. Write the data to TX FIFO and check for cur_blk_len. If it is non zero
1324 * then more data is pending otherwise following 3 cases can be possible
1325 * a. if tx_fifo_data_pos is zero i.e. all the data bytes in this block
1326 * have been written in TX FIFO so nothing else is required.
1327 * b. tx_fifo_free is non zero i.e tx FIFO is free so copy the remaining data
1328 * from tx_fifo_data to tx FIFO. Since, qup_i2c_write_blk_data do write
1329 * in 4 bytes and FIFO space is in multiple of 4 bytes so tx_fifo_free
1330 * will be always greater than or equal to 4 bytes.
1331 * c. tx_fifo_free is zero. In this case, last few bytes (less than 4
1332 * bytes) are copied to tx_fifo_data but couldn't be sent because of
1333 * FIFO full so make send_last_word true.
1334 */
qup_i2c_write_tx_fifo_v2(struct qup_i2c_dev * qup)1335 static void qup_i2c_write_tx_fifo_v2(struct qup_i2c_dev *qup)
1336 {
1337 struct qup_i2c_block *blk = &qup->blk;
1338
1339 if (!blk->tx_tags_sent) {
1340 qup_i2c_write_blk_data(qup, &blk->cur_tx_tags,
1341 &blk->tx_tag_len);
1342 blk->tx_tags_sent = true;
1343 }
1344
1345 if (blk->send_last_word)
1346 goto send_last_word;
1347
1348 qup_i2c_write_blk_data(qup, &blk->cur_data, &blk->cur_blk_len);
1349 if (!blk->cur_blk_len) {
1350 if (!blk->tx_fifo_data_pos)
1351 return;
1352
1353 if (blk->tx_fifo_free)
1354 goto send_last_word;
1355
1356 blk->send_last_word = true;
1357 }
1358
1359 return;
1360
1361 send_last_word:
1362 writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE);
1363 }
1364
1365 /*
1366 * Main transfer function which read or write i2c data.
1367 * The QUP v2 supports reconfiguration during run in which multiple i2c sub
1368 * transfers can be scheduled.
1369 */
1370 static int
qup_i2c_conf_xfer_v2(struct qup_i2c_dev * qup,bool is_rx,bool is_first,bool change_pause_state)1371 qup_i2c_conf_xfer_v2(struct qup_i2c_dev *qup, bool is_rx, bool is_first,
1372 bool change_pause_state)
1373 {
1374 struct qup_i2c_block *blk = &qup->blk;
1375 struct i2c_msg *msg = qup->msg;
1376 int ret;
1377
1378 /*
1379 * Check if its SMBus Block read for which the top level read will be
1380 * done into 2 QUP reads. One with message length 1 while other one is
1381 * with actual length.
1382 */
1383 if (qup_i2c_check_msg_len(msg)) {
1384 if (qup->is_smbus_read) {
1385 /*
1386 * If the message length is already read in
1387 * the first byte of the buffer, account for
1388 * that by setting the offset
1389 */
1390 blk->cur_data += 1;
1391 is_first = false;
1392 } else {
1393 change_pause_state = false;
1394 }
1395 }
1396
1397 qup->config_run = is_first ? 0 : QUP_I2C_MX_CONFIG_DURING_RUN;
1398
1399 qup_i2c_clear_blk_v2(blk);
1400 qup_i2c_conf_count_v2(qup);
1401
1402 /* If it is first sub transfer, then configure i2c bus clocks */
1403 if (is_first) {
1404 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1405 if (ret)
1406 return ret;
1407
1408 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
1409
1410 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
1411 if (ret)
1412 return ret;
1413 }
1414
1415 reinit_completion(&qup->xfer);
1416 enable_irq(qup->irq);
1417 /*
1418 * In FIFO mode, tx FIFO can be written directly while in block mode the
1419 * it will be written after getting OUT_BLOCK_WRITE_REQ interrupt
1420 */
1421 if (!blk->is_tx_blk_mode) {
1422 blk->tx_fifo_free = qup->out_fifo_sz;
1423
1424 if (is_rx)
1425 qup_i2c_write_rx_tags_v2(qup);
1426 else
1427 qup_i2c_write_tx_fifo_v2(qup);
1428 }
1429
1430 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1431 if (ret)
1432 goto err;
1433
1434 ret = qup_i2c_wait_for_complete(qup, msg);
1435 if (ret)
1436 goto err;
1437
1438 /* Move to pause state for all the transfers, except last one */
1439 if (change_pause_state) {
1440 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
1441 if (ret)
1442 goto err;
1443 }
1444
1445 err:
1446 disable_irq(qup->irq);
1447 return ret;
1448 }
1449
1450 /*
1451 * Transfer one read/write message in i2c transfer. It splits the message into
1452 * multiple of blk_xfer_limit data length blocks and schedule each
1453 * QUP block individually.
1454 */
qup_i2c_xfer_v2_msg(struct qup_i2c_dev * qup,int msg_id,bool is_rx)1455 static int qup_i2c_xfer_v2_msg(struct qup_i2c_dev *qup, int msg_id, bool is_rx)
1456 {
1457 int ret = 0;
1458 unsigned int data_len, i;
1459 struct i2c_msg *msg = qup->msg;
1460 struct qup_i2c_block *blk = &qup->blk;
1461 u8 *msg_buf = msg->buf;
1462
1463 qup->blk_xfer_limit = is_rx ? RECV_MAX_DATA_LEN : QUP_READ_LIMIT;
1464 qup_i2c_set_blk_data(qup, msg);
1465
1466 for (i = 0; i < blk->count; i++) {
1467 data_len = qup_i2c_get_data_len(qup);
1468 blk->pos = i;
1469 blk->cur_tx_tags = blk->tags;
1470 blk->cur_blk_len = data_len;
1471 blk->tx_tag_len =
1472 qup_i2c_set_tags(blk->cur_tx_tags, qup, qup->msg);
1473
1474 blk->cur_data = msg_buf;
1475
1476 if (is_rx) {
1477 blk->total_tx_len = blk->tx_tag_len;
1478 blk->rx_tag_len = 2;
1479 blk->total_rx_len = blk->rx_tag_len + data_len;
1480 } else {
1481 blk->total_tx_len = blk->tx_tag_len + data_len;
1482 blk->total_rx_len = 0;
1483 }
1484
1485 ret = qup_i2c_conf_xfer_v2(qup, is_rx, !msg_id && !i,
1486 !qup->is_last || i < blk->count - 1);
1487 if (ret)
1488 return ret;
1489
1490 /* Handle SMBus block read length */
1491 if (qup_i2c_check_msg_len(msg) && msg->len == 1 &&
1492 !qup->is_smbus_read) {
1493 if (msg->buf[0] > I2C_SMBUS_BLOCK_MAX)
1494 return -EPROTO;
1495
1496 msg->len = msg->buf[0];
1497 qup->is_smbus_read = true;
1498 ret = qup_i2c_xfer_v2_msg(qup, msg_id, true);
1499 qup->is_smbus_read = false;
1500 if (ret)
1501 return ret;
1502
1503 msg->len += 1;
1504 }
1505
1506 msg_buf += data_len;
1507 blk->data_len -= qup->blk_xfer_limit;
1508 }
1509
1510 return ret;
1511 }
1512
1513 /*
1514 * QUP v2 supports 3 modes
1515 * Programmed IO using FIFO mode : Less than FIFO size
1516 * Programmed IO using Block mode : Greater than FIFO size
1517 * DMA using BAM : Appropriate for any transaction size but the address should
1518 * be DMA applicable
1519 *
1520 * This function determines the mode which will be used for this transfer. An
1521 * i2c transfer contains multiple message. Following are the rules to determine
1522 * the mode used.
1523 * 1. Determine complete length, maximum tx and rx length for complete transfer.
1524 * 2. If complete transfer length is greater than fifo size then use the DMA
1525 * mode.
1526 * 3. In FIFO or block mode, tx and rx can operate in different mode so check
1527 * for maximum tx and rx length to determine mode.
1528 */
1529 static int
qup_i2c_determine_mode_v2(struct qup_i2c_dev * qup,struct i2c_msg msgs[],int num)1530 qup_i2c_determine_mode_v2(struct qup_i2c_dev *qup,
1531 struct i2c_msg msgs[], int num)
1532 {
1533 int idx;
1534 bool no_dma = false;
1535 unsigned int max_tx_len = 0, max_rx_len = 0, total_len = 0;
1536
1537 /* All i2c_msgs should be transferred using either dma or cpu */
1538 for (idx = 0; idx < num; idx++) {
1539 if (msgs[idx].flags & I2C_M_RD)
1540 max_rx_len = max_t(unsigned int, max_rx_len,
1541 msgs[idx].len);
1542 else
1543 max_tx_len = max_t(unsigned int, max_tx_len,
1544 msgs[idx].len);
1545
1546 if (is_vmalloc_addr(msgs[idx].buf))
1547 no_dma = true;
1548
1549 total_len += msgs[idx].len;
1550 }
1551
1552 if (!no_dma && qup->is_dma &&
1553 (total_len > qup->out_fifo_sz || total_len > qup->in_fifo_sz)) {
1554 qup->use_dma = true;
1555 } else {
1556 qup->blk.is_tx_blk_mode = max_tx_len > qup->out_fifo_sz -
1557 QUP_MAX_TAGS_LEN;
1558 qup->blk.is_rx_blk_mode = max_rx_len > qup->in_fifo_sz -
1559 READ_RX_TAGS_LEN;
1560 }
1561
1562 return 0;
1563 }
1564
qup_i2c_xfer_v2(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)1565 static int qup_i2c_xfer_v2(struct i2c_adapter *adap,
1566 struct i2c_msg msgs[],
1567 int num)
1568 {
1569 struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
1570 int ret, idx = 0;
1571
1572 qup->bus_err = 0;
1573 qup->qup_err = 0;
1574
1575 ret = pm_runtime_get_sync(qup->dev);
1576 if (ret < 0)
1577 goto out;
1578
1579 ret = qup_i2c_determine_mode_v2(qup, msgs, num);
1580 if (ret)
1581 goto out;
1582
1583 writel(1, qup->base + QUP_SW_RESET);
1584 ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
1585 if (ret)
1586 goto out;
1587
1588 /* Configure QUP as I2C mini core */
1589 writel(I2C_MINI_CORE | I2C_N_VAL_V2, qup->base + QUP_CONFIG);
1590 writel(QUP_V2_TAGS_EN, qup->base + QUP_I2C_MASTER_GEN);
1591
1592 if (qup_i2c_poll_state_i2c_master(qup)) {
1593 ret = -EIO;
1594 goto out;
1595 }
1596
1597 if (qup->use_dma) {
1598 reinit_completion(&qup->xfer);
1599 ret = qup_i2c_bam_xfer(adap, &msgs[0], num);
1600 qup->use_dma = false;
1601 } else {
1602 qup_i2c_conf_mode_v2(qup);
1603
1604 for (idx = 0; idx < num; idx++) {
1605 qup->msg = &msgs[idx];
1606 qup->is_last = idx == (num - 1);
1607
1608 ret = qup_i2c_xfer_v2_msg(qup, idx,
1609 !!(msgs[idx].flags & I2C_M_RD));
1610 if (ret)
1611 break;
1612 }
1613 qup->msg = NULL;
1614 }
1615
1616 if (!ret)
1617 ret = qup_i2c_bus_active(qup, ONE_BYTE);
1618
1619 if (!ret)
1620 qup_i2c_change_state(qup, QUP_RESET_STATE);
1621
1622 if (ret == 0)
1623 ret = num;
1624 out:
1625 pm_runtime_mark_last_busy(qup->dev);
1626 pm_runtime_put_autosuspend(qup->dev);
1627
1628 return ret;
1629 }
1630
qup_i2c_func(struct i2c_adapter * adap)1631 static u32 qup_i2c_func(struct i2c_adapter *adap)
1632 {
1633 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL_ALL & ~I2C_FUNC_SMBUS_QUICK);
1634 }
1635
1636 static const struct i2c_algorithm qup_i2c_algo = {
1637 .xfer = qup_i2c_xfer,
1638 .functionality = qup_i2c_func,
1639 };
1640
1641 static const struct i2c_algorithm qup_i2c_algo_v2 = {
1642 .xfer = qup_i2c_xfer_v2,
1643 .functionality = qup_i2c_func,
1644 };
1645
1646 /*
1647 * The QUP block will issue a NACK and STOP on the bus when reaching
1648 * the end of the read, the length of the read is specified as one byte
1649 * which limits the possible read to 256 (QUP_READ_LIMIT) bytes.
1650 */
1651 static const struct i2c_adapter_quirks qup_i2c_quirks = {
1652 .flags = I2C_AQ_NO_ZERO_LEN,
1653 .max_read_len = QUP_READ_LIMIT,
1654 };
1655
1656 static const struct i2c_adapter_quirks qup_i2c_quirks_v2 = {
1657 .flags = I2C_AQ_NO_ZERO_LEN,
1658 };
1659
qup_i2c_enable_clocks(struct qup_i2c_dev * qup)1660 static void qup_i2c_enable_clocks(struct qup_i2c_dev *qup)
1661 {
1662 clk_prepare_enable(qup->clk);
1663 clk_prepare_enable(qup->pclk);
1664 }
1665
qup_i2c_disable_clocks(struct qup_i2c_dev * qup)1666 static void qup_i2c_disable_clocks(struct qup_i2c_dev *qup)
1667 {
1668 u32 config;
1669
1670 qup_i2c_change_state(qup, QUP_RESET_STATE);
1671 clk_disable_unprepare(qup->clk);
1672 config = readl(qup->base + QUP_CONFIG);
1673 config |= QUP_CLOCK_AUTO_GATE;
1674 writel(config, qup->base + QUP_CONFIG);
1675 qup_i2c_vote_bw(qup, 0);
1676 clk_disable_unprepare(qup->pclk);
1677 }
1678
1679 static const struct acpi_device_id qup_i2c_acpi_match[] = {
1680 { "QCOM8010"},
1681 { }
1682 };
1683 MODULE_DEVICE_TABLE(acpi, qup_i2c_acpi_match);
1684
qup_i2c_probe(struct platform_device * pdev)1685 static int qup_i2c_probe(struct platform_device *pdev)
1686 {
1687 static const int blk_sizes[] = {4, 16, 32};
1688 struct qup_i2c_dev *qup;
1689 unsigned long one_bit_t;
1690 u32 io_mode, hw_ver, size;
1691 int ret, fs_div, hs_div;
1692 u32 src_clk_freq = DEFAULT_SRC_CLK;
1693 u32 clk_freq = DEFAULT_CLK_FREQ;
1694 int blocks;
1695 bool is_qup_v1;
1696
1697 qup = devm_kzalloc(&pdev->dev, sizeof(*qup), GFP_KERNEL);
1698 if (!qup)
1699 return -ENOMEM;
1700
1701 qup->dev = &pdev->dev;
1702 init_completion(&qup->xfer);
1703 platform_set_drvdata(pdev, qup);
1704
1705 if (scl_freq) {
1706 dev_notice(qup->dev, "Using override frequency of %u\n", scl_freq);
1707 clk_freq = scl_freq;
1708 } else {
1709 ret = device_property_read_u32(qup->dev, "clock-frequency", &clk_freq);
1710 if (ret) {
1711 dev_notice(qup->dev, "using default clock-frequency %d",
1712 DEFAULT_CLK_FREQ);
1713 }
1714 }
1715
1716 if (device_is_compatible(&pdev->dev, "qcom,i2c-qup-v1.1.1")) {
1717 qup->adap.algo = &qup_i2c_algo;
1718 qup->adap.quirks = &qup_i2c_quirks;
1719 is_qup_v1 = true;
1720 } else {
1721 qup->adap.algo = &qup_i2c_algo_v2;
1722 qup->adap.quirks = &qup_i2c_quirks_v2;
1723 is_qup_v1 = false;
1724 if (acpi_match_device(qup_i2c_acpi_match, qup->dev))
1725 goto nodma;
1726 else
1727 ret = qup_i2c_req_dma(qup);
1728
1729 if (ret == -EPROBE_DEFER)
1730 goto fail_dma;
1731 else if (ret != 0)
1732 goto nodma;
1733
1734 qup->max_xfer_sg_len = (MX_BLOCKS << 1);
1735 blocks = (MX_DMA_BLOCKS << 1) + 1;
1736 qup->btx.sg = devm_kcalloc(&pdev->dev,
1737 blocks, sizeof(*qup->btx.sg),
1738 GFP_KERNEL);
1739 if (!qup->btx.sg) {
1740 ret = -ENOMEM;
1741 goto fail_dma;
1742 }
1743 sg_init_table(qup->btx.sg, blocks);
1744
1745 qup->brx.sg = devm_kcalloc(&pdev->dev,
1746 blocks, sizeof(*qup->brx.sg),
1747 GFP_KERNEL);
1748 if (!qup->brx.sg) {
1749 ret = -ENOMEM;
1750 goto fail_dma;
1751 }
1752 sg_init_table(qup->brx.sg, blocks);
1753
1754 /* 2 tag bytes for each block + 5 for start, stop tags */
1755 size = blocks * 2 + 5;
1756
1757 qup->start_tag.start = devm_kzalloc(&pdev->dev,
1758 size, GFP_KERNEL);
1759 if (!qup->start_tag.start) {
1760 ret = -ENOMEM;
1761 goto fail_dma;
1762 }
1763
1764 qup->brx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL);
1765 if (!qup->brx.tag.start) {
1766 ret = -ENOMEM;
1767 goto fail_dma;
1768 }
1769
1770 qup->btx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL);
1771 if (!qup->btx.tag.start) {
1772 ret = -ENOMEM;
1773 goto fail_dma;
1774 }
1775 qup->is_dma = true;
1776
1777 qup->icc_path = devm_of_icc_get(&pdev->dev, NULL);
1778 if (IS_ERR(qup->icc_path))
1779 return dev_err_probe(&pdev->dev, PTR_ERR(qup->icc_path),
1780 "failed to get interconnect path\n");
1781 }
1782
1783 nodma:
1784 /* We support frequencies up to FAST Mode Plus (1MHz) */
1785 if (!clk_freq || clk_freq > I2C_MAX_FAST_MODE_PLUS_FREQ) {
1786 dev_err(qup->dev, "clock frequency not supported %d\n",
1787 clk_freq);
1788 ret = -EINVAL;
1789 goto fail_dma;
1790 }
1791
1792 qup->base = devm_platform_ioremap_resource(pdev, 0);
1793 if (IS_ERR(qup->base)) {
1794 ret = PTR_ERR(qup->base);
1795 goto fail_dma;
1796 }
1797
1798 qup->irq = platform_get_irq(pdev, 0);
1799 if (qup->irq < 0) {
1800 ret = qup->irq;
1801 goto fail_dma;
1802 }
1803
1804 if (has_acpi_companion(qup->dev)) {
1805 ret = device_property_read_u32(qup->dev,
1806 "src-clock-hz", &src_clk_freq);
1807 if (ret) {
1808 dev_notice(qup->dev, "using default src-clock-hz %d",
1809 DEFAULT_SRC_CLK);
1810 }
1811 ACPI_COMPANION_SET(&qup->adap.dev, ACPI_COMPANION(qup->dev));
1812 } else {
1813 qup->clk = devm_clk_get(qup->dev, "core");
1814 if (IS_ERR(qup->clk)) {
1815 dev_err(qup->dev, "Could not get core clock\n");
1816 ret = PTR_ERR(qup->clk);
1817 goto fail_dma;
1818 }
1819
1820 qup->pclk = devm_clk_get(qup->dev, "iface");
1821 if (IS_ERR(qup->pclk)) {
1822 dev_err(qup->dev, "Could not get iface clock\n");
1823 ret = PTR_ERR(qup->pclk);
1824 goto fail_dma;
1825 }
1826 qup_i2c_enable_clocks(qup);
1827 src_clk_freq = clk_get_rate(qup->clk);
1828 }
1829 qup->src_clk_freq = src_clk_freq;
1830
1831 /*
1832 * Bootloaders might leave a pending interrupt on certain QUP's,
1833 * so we reset the core before registering for interrupts.
1834 */
1835 writel(1, qup->base + QUP_SW_RESET);
1836 ret = qup_i2c_poll_state_valid(qup);
1837 if (ret)
1838 goto fail;
1839
1840 ret = devm_request_irq(qup->dev, qup->irq, qup_i2c_interrupt,
1841 IRQF_TRIGGER_HIGH | IRQF_NO_AUTOEN,
1842 "i2c_qup", qup);
1843 if (ret) {
1844 dev_err(qup->dev, "Request %d IRQ failed\n", qup->irq);
1845 goto fail;
1846 }
1847
1848 hw_ver = readl(qup->base + QUP_HW_VERSION);
1849 dev_dbg(qup->dev, "Revision %x\n", hw_ver);
1850
1851 io_mode = readl(qup->base + QUP_IO_MODE);
1852
1853 /*
1854 * The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag'
1855 * associated with each byte written/received
1856 */
1857 size = QUP_OUTPUT_BLOCK_SIZE(io_mode);
1858 if (size >= ARRAY_SIZE(blk_sizes)) {
1859 ret = -EIO;
1860 goto fail;
1861 }
1862 qup->out_blk_sz = blk_sizes[size];
1863
1864 size = QUP_INPUT_BLOCK_SIZE(io_mode);
1865 if (size >= ARRAY_SIZE(blk_sizes)) {
1866 ret = -EIO;
1867 goto fail;
1868 }
1869 qup->in_blk_sz = blk_sizes[size];
1870
1871 if (is_qup_v1) {
1872 /*
1873 * in QUP v1, QUP_CONFIG uses N as 15 i.e 16 bits constitutes a
1874 * single transfer but the block size is in bytes so divide the
1875 * in_blk_sz and out_blk_sz by 2
1876 */
1877 qup->in_blk_sz /= 2;
1878 qup->out_blk_sz /= 2;
1879 qup->write_tx_fifo = qup_i2c_write_tx_fifo_v1;
1880 qup->read_rx_fifo = qup_i2c_read_rx_fifo_v1;
1881 qup->write_rx_tags = qup_i2c_write_rx_tags_v1;
1882 } else {
1883 qup->write_tx_fifo = qup_i2c_write_tx_fifo_v2;
1884 qup->read_rx_fifo = qup_i2c_read_rx_fifo_v2;
1885 qup->write_rx_tags = qup_i2c_write_rx_tags_v2;
1886 }
1887
1888 size = QUP_OUTPUT_FIFO_SIZE(io_mode);
1889 qup->out_fifo_sz = qup->out_blk_sz * (2 << size);
1890
1891 size = QUP_INPUT_FIFO_SIZE(io_mode);
1892 qup->in_fifo_sz = qup->in_blk_sz * (2 << size);
1893
1894 hs_div = 3;
1895 if (clk_freq <= I2C_MAX_STANDARD_MODE_FREQ) {
1896 fs_div = ((src_clk_freq / clk_freq) / 2) - 3;
1897 qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff);
1898 } else {
1899 /* 33%/66% duty cycle */
1900 fs_div = ((src_clk_freq / clk_freq) - 6) * 2 / 3;
1901 qup->clk_ctl = ((fs_div / 2) << 16) | (hs_div << 8) | (fs_div & 0xff);
1902 }
1903
1904 /*
1905 * Time it takes for a byte to be clocked out on the bus.
1906 * Each byte takes 9 clock cycles (8 bits + 1 ack).
1907 */
1908 one_bit_t = (USEC_PER_SEC / clk_freq) + 1;
1909 qup->one_byte_t = one_bit_t * 9;
1910 qup->xfer_timeout = TOUT_MIN * HZ +
1911 usecs_to_jiffies(MX_DMA_TX_RX_LEN * qup->one_byte_t);
1912
1913 dev_dbg(qup->dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
1914 qup->in_blk_sz, qup->in_fifo_sz,
1915 qup->out_blk_sz, qup->out_fifo_sz);
1916
1917 i2c_set_adapdata(&qup->adap, qup);
1918 qup->adap.dev.parent = qup->dev;
1919 qup->adap.dev.of_node = pdev->dev.of_node;
1920 qup->is_last = true;
1921
1922 strscpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name));
1923
1924 pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC);
1925 pm_runtime_use_autosuspend(qup->dev);
1926 pm_runtime_set_active(qup->dev);
1927 pm_runtime_enable(qup->dev);
1928
1929 ret = i2c_add_adapter(&qup->adap);
1930 if (ret)
1931 goto fail_runtime;
1932
1933 return 0;
1934
1935 fail_runtime:
1936 pm_runtime_disable(qup->dev);
1937 pm_runtime_set_suspended(qup->dev);
1938 fail:
1939 qup_i2c_disable_clocks(qup);
1940 fail_dma:
1941 if (qup->btx.dma)
1942 dma_release_channel(qup->btx.dma);
1943 if (qup->brx.dma)
1944 dma_release_channel(qup->brx.dma);
1945 return ret;
1946 }
1947
qup_i2c_remove(struct platform_device * pdev)1948 static void qup_i2c_remove(struct platform_device *pdev)
1949 {
1950 struct qup_i2c_dev *qup = platform_get_drvdata(pdev);
1951
1952 if (qup->is_dma) {
1953 dma_release_channel(qup->btx.dma);
1954 dma_release_channel(qup->brx.dma);
1955 }
1956
1957 disable_irq(qup->irq);
1958 qup_i2c_disable_clocks(qup);
1959 i2c_del_adapter(&qup->adap);
1960 pm_runtime_disable(qup->dev);
1961 pm_runtime_set_suspended(qup->dev);
1962 }
1963
qup_i2c_pm_suspend_runtime(struct device * device)1964 static int qup_i2c_pm_suspend_runtime(struct device *device)
1965 {
1966 struct qup_i2c_dev *qup = dev_get_drvdata(device);
1967
1968 dev_dbg(device, "pm_runtime: suspending...\n");
1969 qup_i2c_disable_clocks(qup);
1970 return 0;
1971 }
1972
qup_i2c_pm_resume_runtime(struct device * device)1973 static int qup_i2c_pm_resume_runtime(struct device *device)
1974 {
1975 struct qup_i2c_dev *qup = dev_get_drvdata(device);
1976
1977 dev_dbg(device, "pm_runtime: resuming...\n");
1978 qup_i2c_enable_clocks(qup);
1979 return 0;
1980 }
1981
qup_i2c_suspend(struct device * device)1982 static int qup_i2c_suspend(struct device *device)
1983 {
1984 if (!pm_runtime_suspended(device))
1985 return qup_i2c_pm_suspend_runtime(device);
1986 return 0;
1987 }
1988
qup_i2c_resume(struct device * device)1989 static int qup_i2c_resume(struct device *device)
1990 {
1991 qup_i2c_pm_resume_runtime(device);
1992 pm_runtime_mark_last_busy(device);
1993 pm_request_autosuspend(device);
1994 return 0;
1995 }
1996
1997 static const struct dev_pm_ops qup_i2c_qup_pm_ops = {
1998 SYSTEM_SLEEP_PM_OPS(qup_i2c_suspend, qup_i2c_resume)
1999 RUNTIME_PM_OPS(qup_i2c_pm_suspend_runtime,
2000 qup_i2c_pm_resume_runtime, NULL)
2001 };
2002
2003 static const struct of_device_id qup_i2c_dt_match[] = {
2004 { .compatible = "qcom,i2c-qup-v1.1.1" },
2005 { .compatible = "qcom,i2c-qup-v2.1.1" },
2006 { .compatible = "qcom,i2c-qup-v2.2.1" },
2007 {}
2008 };
2009 MODULE_DEVICE_TABLE(of, qup_i2c_dt_match);
2010
2011 static struct platform_driver qup_i2c_driver = {
2012 .probe = qup_i2c_probe,
2013 .remove = qup_i2c_remove,
2014 .driver = {
2015 .name = "i2c_qup",
2016 .pm = pm_ptr(&qup_i2c_qup_pm_ops),
2017 .of_match_table = qup_i2c_dt_match,
2018 .acpi_match_table = ACPI_PTR(qup_i2c_acpi_match),
2019 },
2020 };
2021
2022 module_platform_driver(qup_i2c_driver);
2023
2024 MODULE_DESCRIPTION("Qualcomm QUP based I2C controller");
2025 MODULE_LICENSE("GPL v2");
2026 MODULE_ALIAS("platform:i2c_qup");
2027