1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
4 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
5 <mdsxyz123@yahoo.com>
6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de>
7 Copyright (C) 2010 Intel Corporation,
8 David Woodhouse <dwmw2@infradead.org>
9
10 */
11
12 /*
13 * Supports the following Intel I/O Controller Hubs (ICH):
14 *
15 * I/O Block I2C
16 * region SMBus Block proc. block
17 * Chip name PCI ID size PEC buffer call read
18 * ---------------------------------------------------------------------------
19 * 82801AA (ICH) 0x2413 16 no no no no
20 * 82801AB (ICH0) 0x2423 16 no no no no
21 * 82801BA (ICH2) 0x2443 16 no no no no
22 * 82801CA (ICH3) 0x2483 32 soft no no no
23 * 82801DB (ICH4) 0x24c3 32 hard yes no no
24 * 82801E (ICH5) 0x24d3 32 hard yes yes yes
25 * 6300ESB 0x25a4 32 hard yes yes yes
26 * 82801F (ICH6) 0x266a 32 hard yes yes yes
27 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes
28 * 82801G (ICH7) 0x27da 32 hard yes yes yes
29 * 82801H (ICH8) 0x283e 32 hard yes yes yes
30 * 82801I (ICH9) 0x2930 32 hard yes yes yes
31 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes
32 * ICH10 0x3a30 32 hard yes yes yes
33 * ICH10 0x3a60 32 hard yes yes yes
34 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
35 * 6 Series (PCH) 0x1c22 32 hard yes yes yes
36 * Patsburg (PCH) 0x1d22 32 hard yes yes yes
37 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
38 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
39 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
40 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes
41 * Panther Point (PCH) 0x1e22 32 hard yes yes yes
42 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes
43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
44 * Avoton (SOC) 0x1f3c 32 hard yes yes yes
45 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes
46 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
47 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
48 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
49 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
50 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes
51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
52 * BayTrail (SOC) 0x0f12 32 hard yes yes yes
53 * Braswell (SOC) 0x2292 32 hard yes yes yes
54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
56 * DNV (SOC) 0x19df 32 hard yes yes yes
57 * Emmitsburg (PCH) 0x1bc9 32 hard yes yes yes
58 * Broxton (SOC) 0x5ad4 32 hard yes yes yes
59 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes
60 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes
61 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes
62 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes
63 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes
64 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes
65 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes
66 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes
67 * Ice Lake-N (PCH) 0x38a3 32 hard yes yes yes
68 * Comet Lake (PCH) 0x02a3 32 hard yes yes yes
69 * Comet Lake-H (PCH) 0x06a3 32 hard yes yes yes
70 * Elkhart Lake (PCH) 0x4b23 32 hard yes yes yes
71 * Tiger Lake-LP (PCH) 0xa0a3 32 hard yes yes yes
72 * Tiger Lake-H (PCH) 0x43a3 32 hard yes yes yes
73 * Jasper Lake (SOC) 0x4da3 32 hard yes yes yes
74 * Comet Lake-V (PCH) 0xa3a3 32 hard yes yes yes
75 * Alder Lake-S (PCH) 0x7aa3 32 hard yes yes yes
76 * Alder Lake-P (PCH) 0x51a3 32 hard yes yes yes
77 * Alder Lake-M (PCH) 0x54a3 32 hard yes yes yes
78 * Raptor Lake-S (PCH) 0x7a23 32 hard yes yes yes
79 * Meteor Lake-P (SOC) 0x7e22 32 hard yes yes yes
80 * Meteor Lake SoC-S (SOC) 0xae22 32 hard yes yes yes
81 * Meteor Lake PCH-S (PCH) 0x7f23 32 hard yes yes yes
82 * Birch Stream (SOC) 0x5796 32 hard yes yes yes
83 * Arrow Lake-H (SOC) 0x7722 32 hard yes yes yes
84 * Panther Lake-H (SOC) 0xe322 32 hard yes yes yes
85 * Panther Lake-P (SOC) 0xe422 32 hard yes yes yes
86 * Wildcat Lake-U (SOC) 0x4d22 32 hard yes yes yes
87 *
88 * Features supported by this driver:
89 * Software PEC no
90 * Hardware PEC yes
91 * Block buffer yes
92 * Block process call transaction yes
93 * I2C block read transaction yes (doesn't use the block buffer)
94 * Target mode no
95 * SMBus Host Notify yes
96 * Interrupt processing yes
97 *
98 * See the file Documentation/i2c/busses/i2c-i801.rst for details.
99 */
100
101 #define DRV_NAME "i801_smbus"
102
103 #include <linux/interrupt.h>
104 #include <linux/module.h>
105 #include <linux/pci.h>
106 #include <linux/kernel.h>
107 #include <linux/stddef.h>
108 #include <linux/delay.h>
109 #include <linux/ioport.h>
110 #include <linux/init.h>
111 #include <linux/i2c.h>
112 #include <linux/i2c-mux.h>
113 #include <linux/i2c-smbus.h>
114 #include <linux/acpi.h>
115 #include <linux/io.h>
116 #include <linux/dmi.h>
117 #include <linux/slab.h>
118 #include <linux/string.h>
119 #include <linux/completion.h>
120 #include <linux/err.h>
121 #include <linux/platform_device.h>
122 #include <linux/platform_data/itco_wdt.h>
123 #include <linux/platform_data/x86/p2sb.h>
124 #include <linux/pm_runtime.h>
125 #include <linux/mutex.h>
126
127 #ifdef CONFIG_I2C_I801_MUX
128 #include <linux/gpio/machine.h>
129 #include <linux/platform_data/i2c-mux-gpio.h>
130 #endif
131
132 /* I801 SMBus address offsets */
133 #define SMBHSTSTS(p) (0 + (p)->smba)
134 #define SMBHSTCNT(p) (2 + (p)->smba)
135 #define SMBHSTCMD(p) (3 + (p)->smba)
136 #define SMBHSTADD(p) (4 + (p)->smba)
137 #define SMBHSTDAT0(p) (5 + (p)->smba)
138 #define SMBHSTDAT1(p) (6 + (p)->smba)
139 #define SMBBLKDAT(p) (7 + (p)->smba)
140 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
141 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
142 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
143 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */
144 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */
145 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */
146
147 /* PCI Address Constants */
148 #define SMBBAR_MMIO 0
149 #define SMBBAR 4
150 #define SMBHSTCFG 0x040
151 #define TCOBASE 0x050
152 #define TCOCTL 0x054
153
154 #define SBREG_SMBCTRL 0xc6000c
155 #define SBREG_SMBCTRL_DNV 0xcf000c
156
157 /* Host configuration bits for SMBHSTCFG */
158 #define SMBHSTCFG_HST_EN BIT(0)
159 #define SMBHSTCFG_SMB_SMI_EN BIT(1)
160 #define SMBHSTCFG_I2C_EN BIT(2)
161 #define SMBHSTCFG_SPD_WD BIT(4)
162
163 /* TCO configuration bits for TCOCTL */
164 #define TCOCTL_EN BIT(8)
165
166 /* Auxiliary status register bits, ICH4+ only */
167 #define SMBAUXSTS_CRCE BIT(0)
168 #define SMBAUXSTS_STCO BIT(1)
169
170 /* Auxiliary control register bits, ICH4+ only */
171 #define SMBAUXCTL_CRC BIT(0)
172 #define SMBAUXCTL_E32B BIT(1)
173
174 /* I801 command constants */
175 #define I801_QUICK 0x00
176 #define I801_BYTE 0x04
177 #define I801_BYTE_DATA 0x08
178 #define I801_WORD_DATA 0x0C
179 #define I801_PROC_CALL 0x10
180 #define I801_BLOCK_DATA 0x14
181 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
182 #define I801_BLOCK_PROC_CALL 0x1C
183
184 /* I801 Host Control register bits */
185 #define SMBHSTCNT_INTREN BIT(0)
186 #define SMBHSTCNT_KILL BIT(1)
187 #define SMBHSTCNT_LAST_BYTE BIT(5)
188 #define SMBHSTCNT_START BIT(6)
189 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */
190
191 /* I801 Hosts Status register bits */
192 #define SMBHSTSTS_BYTE_DONE BIT(7)
193 #define SMBHSTSTS_INUSE_STS BIT(6)
194 #define SMBHSTSTS_SMBALERT_STS BIT(5)
195 #define SMBHSTSTS_FAILED BIT(4)
196 #define SMBHSTSTS_BUS_ERR BIT(3)
197 #define SMBHSTSTS_DEV_ERR BIT(2)
198 #define SMBHSTSTS_INTR BIT(1)
199 #define SMBHSTSTS_HOST_BUSY BIT(0)
200
201 /* Host Notify Status register bits */
202 #define SMBSLVSTS_HST_NTFY_STS BIT(0)
203
204 /* Host Notify Command register bits */
205 #define SMBSLVCMD_SMBALERT_DISABLE BIT(2)
206 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0)
207
208 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
209 SMBHSTSTS_DEV_ERR)
210
211 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
212 STATUS_ERROR_FLAGS)
213
214 #define SMBUS_LEN_SENTINEL (I2C_SMBUS_BLOCK_MAX + 1)
215
216 /* Older devices have their ID defined in <linux/pci_ids.h> */
217 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3
218 #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS 0x06a3
219 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12
220 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df
221 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df
222 #define PCI_DEVICE_ID_INTEL_EBG_SMBUS 0x1bc9
223 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
224 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
225 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
226 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
227 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
228 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
229 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
230 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
231 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292
232 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
233 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
234 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4
235 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3
236 #define PCI_DEVICE_ID_INTEL_ICELAKE_N_SMBUS 0x38a3
237 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
238 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS 0x43a3
239 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23
240 #define PCI_DEVICE_ID_INTEL_WILDCAT_LAKE_U_SMBUS 0x4d22
241 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3
242 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS 0x51a3
243 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS 0x54a3
244 #define PCI_DEVICE_ID_INTEL_BIRCH_STREAM_SMBUS 0x5796
245 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4
246 #define PCI_DEVICE_ID_INTEL_ARROW_LAKE_H_SMBUS 0x7722
247 #define PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_S_SMBUS 0x7a23
248 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS 0x7aa3
249 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_P_SMBUS 0x7e22
250 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_PCH_S_SMBUS 0x7f23
251 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
252 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2
253 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
254 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
255 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
256 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
257 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
258 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
259 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23
260 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3
261 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS 0xa0a3
262 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123
263 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3
264 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223
265 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3
266 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323
267 #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS 0xa3a3
268 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_SOC_S_SMBUS 0xae22
269 #define PCI_DEVICE_ID_INTEL_PANTHER_LAKE_H_SMBUS 0xe322
270 #define PCI_DEVICE_ID_INTEL_PANTHER_LAKE_P_SMBUS 0xe422
271
272 struct i801_mux_config {
273 char *gpio_chip;
274 unsigned values[3];
275 int n_values;
276 unsigned gpios[2]; /* Relative to gpio_chip->base */
277 int n_gpios;
278 };
279
280 struct i801_priv {
281 struct i2c_adapter adapter;
282 void __iomem *smba;
283 unsigned char original_hstcfg;
284 unsigned char original_hstcnt;
285 unsigned char original_slvcmd;
286 struct pci_dev *pci_dev;
287 unsigned int features;
288
289 /* isr processing */
290 struct completion done;
291 u8 status;
292
293 /* Command state used by isr for byte-by-byte block transactions */
294 u8 cmd;
295 bool is_read;
296 int count;
297 int len;
298 u8 *data;
299
300 #ifdef CONFIG_I2C_I801_MUX
301 struct platform_device *mux_pdev;
302 struct gpiod_lookup_table *lookup;
303 struct notifier_block mux_notifier_block;
304 #endif
305 struct platform_device *tco_pdev;
306
307 /*
308 * If set to true the host controller registers are reserved for
309 * ACPI AML use.
310 */
311 bool acpi_reserved;
312 };
313
314 #define FEATURE_SMBUS_PEC BIT(0)
315 #define FEATURE_BLOCK_BUFFER BIT(1)
316 #define FEATURE_BLOCK_PROC BIT(2)
317 #define FEATURE_I2C_BLOCK_READ BIT(3)
318 #define FEATURE_IRQ BIT(4)
319 #define FEATURE_HOST_NOTIFY BIT(5)
320 /* Not really a feature, but it's convenient to handle it as such */
321 #define FEATURE_IDF BIT(15)
322 #define FEATURE_TCO_SPT BIT(16)
323 #define FEATURE_TCO_CNL BIT(17)
324
325 static const char *i801_feature_names[] = {
326 "SMBus PEC",
327 "Block buffer",
328 "Block process call",
329 "I2C block read",
330 "Interrupt",
331 "SMBus Host Notify",
332 };
333
334 static unsigned int disable_features;
335 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
336 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
337 "\t\t 0x01 disable SMBus PEC\n"
338 "\t\t 0x02 disable the block buffer\n"
339 "\t\t 0x08 disable the I2C block read functionality\n"
340 "\t\t 0x10 don't use interrupts\n"
341 "\t\t 0x20 disable SMBus Host Notify ");
342
343 /* Wait for BUSY being cleared and either INTR or an error flag being set */
i801_wait_intr(struct i801_priv * priv)344 static int i801_wait_intr(struct i801_priv *priv)
345 {
346 unsigned long timeout = jiffies + priv->adapter.timeout;
347 int status, busy;
348
349 do {
350 usleep_range(250, 500);
351 status = ioread8(SMBHSTSTS(priv));
352 busy = status & SMBHSTSTS_HOST_BUSY;
353 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR;
354 if (!busy && status)
355 return status & STATUS_ERROR_FLAGS;
356 } while (time_is_after_eq_jiffies(timeout));
357
358 return -ETIMEDOUT;
359 }
360
361 /* Wait for either BYTE_DONE or an error flag being set */
i801_wait_byte_done(struct i801_priv * priv)362 static int i801_wait_byte_done(struct i801_priv *priv)
363 {
364 unsigned long timeout = jiffies + priv->adapter.timeout;
365 int status;
366
367 do {
368 usleep_range(250, 500);
369 status = ioread8(SMBHSTSTS(priv));
370 if (status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE))
371 return status & STATUS_ERROR_FLAGS;
372 } while (time_is_after_eq_jiffies(timeout));
373
374 return -ETIMEDOUT;
375 }
376
i801_get_block_len(struct i801_priv * priv)377 static int i801_get_block_len(struct i801_priv *priv)
378 {
379 u8 len = ioread8(SMBHSTDAT0(priv));
380
381 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
382 pci_err(priv->pci_dev, "Illegal SMBus block read size %u\n", len);
383 return -EPROTO;
384 }
385
386 return len;
387 }
388
i801_check_and_clear_pec_error(struct i801_priv * priv)389 static int i801_check_and_clear_pec_error(struct i801_priv *priv)
390 {
391 u8 status;
392
393 if (!(priv->features & FEATURE_SMBUS_PEC))
394 return 0;
395
396 status = ioread8(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
397 if (status) {
398 iowrite8(status, SMBAUXSTS(priv));
399 return -EBADMSG;
400 }
401
402 return 0;
403 }
404
405 /* Make sure the SMBus host is ready to start transmitting.
406 Return 0 if it is, -EBUSY if it is not. */
i801_check_pre(struct i801_priv * priv)407 static int i801_check_pre(struct i801_priv *priv)
408 {
409 int status, result;
410
411 status = ioread8(SMBHSTSTS(priv));
412 if (status & SMBHSTSTS_HOST_BUSY) {
413 pci_err(priv->pci_dev, "SMBus is busy, can't use it!\n");
414 return -EBUSY;
415 }
416
417 status &= STATUS_FLAGS;
418 if (status) {
419 pci_dbg(priv->pci_dev, "Clearing status flags (%02x)\n", status);
420 iowrite8(status, SMBHSTSTS(priv));
421 }
422
423 /*
424 * Clear CRC status if needed.
425 * During normal operation, i801_check_post() takes care
426 * of it after every operation. We do it here only in case
427 * the hardware was already in this state when the driver
428 * started.
429 */
430 result = i801_check_and_clear_pec_error(priv);
431 if (result)
432 pci_dbg(priv->pci_dev, "Clearing aux status flag CRCE\n");
433
434 return 0;
435 }
436
i801_check_post(struct i801_priv * priv,int status)437 static int i801_check_post(struct i801_priv *priv, int status)
438 {
439 int result = 0;
440
441 /*
442 * If the SMBus is still busy, we give up
443 */
444 if (unlikely(status < 0)) {
445 /* try to stop the current command */
446 iowrite8(SMBHSTCNT_KILL, SMBHSTCNT(priv));
447 status = i801_wait_intr(priv);
448 iowrite8(0, SMBHSTCNT(priv));
449
450 /* Check if it worked */
451 if (status < 0 || !(status & SMBHSTSTS_FAILED))
452 pci_dbg(priv->pci_dev, "Failed terminating the transaction\n");
453 return -ETIMEDOUT;
454 }
455
456 if (status & SMBHSTSTS_FAILED) {
457 result = -EIO;
458 pci_err(priv->pci_dev, "Transaction failed\n");
459 }
460 if (status & SMBHSTSTS_DEV_ERR) {
461 /*
462 * This may be a PEC error, check and clear it.
463 *
464 * AUXSTS is handled differently from HSTSTS.
465 * For HSTSTS, i801_isr() or i801_wait_intr()
466 * has already cleared the error bits in hardware,
467 * and we are passed a copy of the original value
468 * in "status".
469 * For AUXSTS, the hardware register is left
470 * for us to handle here.
471 * This is asymmetric, slightly iffy, but safe,
472 * since all this code is serialized and the CRCE
473 * bit is harmless as long as it's cleared before
474 * the next operation.
475 */
476 result = i801_check_and_clear_pec_error(priv);
477 if (result) {
478 pci_dbg(priv->pci_dev, "PEC error\n");
479 } else {
480 result = -ENXIO;
481 pci_dbg(priv->pci_dev, "No response\n");
482 }
483 }
484 if (status & SMBHSTSTS_BUS_ERR) {
485 result = -EAGAIN;
486 pci_dbg(priv->pci_dev, "Lost arbitration\n");
487 }
488
489 return result;
490 }
491
i801_transaction(struct i801_priv * priv,int xact)492 static int i801_transaction(struct i801_priv *priv, int xact)
493 {
494 unsigned long result;
495 const struct i2c_adapter *adap = &priv->adapter;
496
497 if (priv->features & FEATURE_IRQ) {
498 reinit_completion(&priv->done);
499 iowrite8(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
500 SMBHSTCNT(priv));
501 result = wait_for_completion_timeout(&priv->done, adap->timeout);
502 return result ? priv->status : -ETIMEDOUT;
503 }
504
505 iowrite8(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
506
507 return i801_wait_intr(priv);
508 }
509
i801_block_transaction_by_block(struct i801_priv * priv,union i2c_smbus_data * data,char read_write,int command)510 static int i801_block_transaction_by_block(struct i801_priv *priv,
511 union i2c_smbus_data *data,
512 char read_write, int command)
513 {
514 int len, status, xact;
515
516 switch (command) {
517 case I2C_SMBUS_BLOCK_PROC_CALL:
518 xact = I801_BLOCK_PROC_CALL;
519 break;
520 case I2C_SMBUS_BLOCK_DATA:
521 xact = I801_BLOCK_DATA;
522 break;
523 default:
524 return -EOPNOTSUPP;
525 }
526
527 /* Set block buffer mode */
528 iowrite8(ioread8(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
529
530 if (read_write == I2C_SMBUS_WRITE) {
531 len = data->block[0];
532 iowrite8(len, SMBHSTDAT0(priv));
533 ioread8(SMBHSTCNT(priv)); /* reset the data buffer index */
534 iowrite8_rep(SMBBLKDAT(priv), data->block + 1, len);
535 }
536
537 status = i801_transaction(priv, xact);
538 if (status)
539 goto out;
540
541 if (read_write == I2C_SMBUS_READ ||
542 command == I2C_SMBUS_BLOCK_PROC_CALL) {
543 len = i801_get_block_len(priv);
544 if (len < 0) {
545 status = len;
546 goto out;
547 }
548
549 data->block[0] = len;
550 ioread8(SMBHSTCNT(priv)); /* reset the data buffer index */
551 ioread8_rep(SMBBLKDAT(priv), data->block + 1, len);
552 }
553 out:
554 iowrite8(ioread8(SMBAUXCTL(priv)) & ~SMBAUXCTL_E32B, SMBAUXCTL(priv));
555 return status;
556 }
557
i801_isr_byte_done(struct i801_priv * priv)558 static void i801_isr_byte_done(struct i801_priv *priv)
559 {
560 if (priv->is_read) {
561 /*
562 * At transfer start i801_smbus_block_transaction() marks
563 * the block length as invalid. Check for this sentinel value
564 * and read the block length from SMBHSTDAT0.
565 */
566 if (priv->len == SMBUS_LEN_SENTINEL) {
567 priv->len = i801_get_block_len(priv);
568 if (priv->len < 0)
569 /* FIXME: Recover */
570 priv->len = I2C_SMBUS_BLOCK_MAX;
571
572 priv->data[-1] = priv->len;
573 }
574
575 /* Read next byte */
576 if (priv->count < priv->len)
577 priv->data[priv->count++] = ioread8(SMBBLKDAT(priv));
578 else
579 pci_dbg(priv->pci_dev, "Discarding extra byte on block read\n");
580
581 /* Set LAST_BYTE for last byte of read transaction */
582 if (priv->count == priv->len - 1)
583 iowrite8(priv->cmd | SMBHSTCNT_LAST_BYTE,
584 SMBHSTCNT(priv));
585 } else if (priv->count < priv->len - 1) {
586 /* Write next byte, except for IRQ after last byte */
587 iowrite8(priv->data[++priv->count], SMBBLKDAT(priv));
588 }
589 }
590
i801_host_notify_isr(struct i801_priv * priv)591 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
592 {
593 unsigned short addr;
594
595 addr = ioread8(SMBNTFDADD(priv)) >> 1;
596
597 /*
598 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
599 * always returns 0. Our current implementation doesn't provide
600 * data, so we just ignore it.
601 */
602 i2c_handle_smbus_host_notify(&priv->adapter, addr);
603
604 /* clear Host Notify bit and return */
605 iowrite8(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
606 return IRQ_HANDLED;
607 }
608
609 /*
610 * There are three kinds of interrupts:
611 *
612 * 1) i801 signals transaction completion with one of these interrupts:
613 * INTR - Success
614 * DEV_ERR - Invalid command, NAK or communication timeout
615 * BUS_ERR - SMI# transaction collision
616 * FAILED - transaction was canceled due to a KILL request
617 * When any of these occur, update ->status and signal completion.
618 *
619 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
620 * occurs for each byte of a byte-by-byte to prepare the next byte.
621 *
622 * 3) Host Notify interrupts
623 */
i801_isr(int irq,void * dev_id)624 static irqreturn_t i801_isr(int irq, void *dev_id)
625 {
626 struct i801_priv *priv = dev_id;
627 u16 pcists;
628 u8 status;
629
630 /* Confirm this is our interrupt */
631 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists);
632 if (!(pcists & PCI_STATUS_INTERRUPT))
633 return IRQ_NONE;
634
635 if (priv->features & FEATURE_HOST_NOTIFY) {
636 status = ioread8(SMBSLVSTS(priv));
637 if (status & SMBSLVSTS_HST_NTFY_STS)
638 return i801_host_notify_isr(priv);
639 }
640
641 status = ioread8(SMBHSTSTS(priv));
642 if ((status & (SMBHSTSTS_BYTE_DONE | STATUS_ERROR_FLAGS)) == SMBHSTSTS_BYTE_DONE)
643 i801_isr_byte_done(priv);
644
645 /*
646 * Clear IRQ sources: SMB_ALERT status is set after signal assertion
647 * independently of the interrupt generation being blocked or not
648 * so clear it always when the status is set.
649 */
650 status &= STATUS_FLAGS | SMBHSTSTS_SMBALERT_STS;
651 iowrite8(status, SMBHSTSTS(priv));
652
653 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR;
654 if (status) {
655 priv->status = status & STATUS_ERROR_FLAGS;
656 complete(&priv->done);
657 }
658
659 return IRQ_HANDLED;
660 }
661
662 /*
663 * For "byte-by-byte" block transactions:
664 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
665 * I2C read uses cmd=I801_I2C_BLOCK_DATA
666 */
i801_block_transaction_byte_by_byte(struct i801_priv * priv,union i2c_smbus_data * data,char read_write,int command)667 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
668 union i2c_smbus_data *data,
669 char read_write, int command)
670 {
671 int i, len;
672 int smbcmd;
673 int status;
674 unsigned long result;
675 const struct i2c_adapter *adap = &priv->adapter;
676
677 if (command == I2C_SMBUS_BLOCK_PROC_CALL)
678 return -EOPNOTSUPP;
679
680 len = data->block[0];
681
682 if (read_write == I2C_SMBUS_WRITE) {
683 iowrite8(len, SMBHSTDAT0(priv));
684 iowrite8(data->block[1], SMBBLKDAT(priv));
685 }
686
687 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
688 read_write == I2C_SMBUS_READ)
689 smbcmd = I801_I2C_BLOCK_DATA;
690 else
691 smbcmd = I801_BLOCK_DATA;
692
693 if (priv->features & FEATURE_IRQ) {
694 priv->is_read = (read_write == I2C_SMBUS_READ);
695 if (len == 1 && priv->is_read)
696 smbcmd |= SMBHSTCNT_LAST_BYTE;
697 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
698 priv->len = len;
699 priv->count = 0;
700 priv->data = &data->block[1];
701
702 reinit_completion(&priv->done);
703 iowrite8(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
704 result = wait_for_completion_timeout(&priv->done, adap->timeout);
705 return result ? priv->status : -ETIMEDOUT;
706 }
707
708 if (len == 1 && read_write == I2C_SMBUS_READ)
709 smbcmd |= SMBHSTCNT_LAST_BYTE;
710 iowrite8(smbcmd | SMBHSTCNT_START, SMBHSTCNT(priv));
711
712 for (i = 1; i <= len; i++) {
713 status = i801_wait_byte_done(priv);
714 if (status)
715 return status;
716
717 /*
718 * At transfer start i801_smbus_block_transaction() marks
719 * the block length as invalid. Check for this sentinel value
720 * and read the block length from SMBHSTDAT0.
721 */
722 if (len == SMBUS_LEN_SENTINEL) {
723 len = i801_get_block_len(priv);
724 if (len < 0) {
725 /* Recover */
726 while (ioread8(SMBHSTSTS(priv)) &
727 SMBHSTSTS_HOST_BUSY)
728 iowrite8(SMBHSTSTS_BYTE_DONE,
729 SMBHSTSTS(priv));
730 iowrite8(SMBHSTSTS_INTR, SMBHSTSTS(priv));
731 return -EPROTO;
732 }
733 data->block[0] = len;
734 }
735
736 if (read_write == I2C_SMBUS_READ) {
737 data->block[i] = ioread8(SMBBLKDAT(priv));
738 if (i == len - 1)
739 iowrite8(smbcmd | SMBHSTCNT_LAST_BYTE, SMBHSTCNT(priv));
740 }
741
742 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
743 iowrite8(data->block[i+1], SMBBLKDAT(priv));
744
745 /* signals SMBBLKDAT ready */
746 iowrite8(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
747 }
748
749 return i801_wait_intr(priv);
750 }
751
i801_set_hstadd(struct i801_priv * priv,u8 addr,char read_write)752 static void i801_set_hstadd(struct i801_priv *priv, u8 addr, char read_write)
753 {
754 iowrite8((addr << 1) | (read_write & 0x01), SMBHSTADD(priv));
755 }
756
757 /* Single value transaction function */
i801_simple_transaction(struct i801_priv * priv,union i2c_smbus_data * data,u8 addr,u8 hstcmd,char read_write,int command)758 static int i801_simple_transaction(struct i801_priv *priv, union i2c_smbus_data *data,
759 u8 addr, u8 hstcmd, char read_write, int command)
760 {
761 int xact, ret;
762
763 switch (command) {
764 case I2C_SMBUS_QUICK:
765 i801_set_hstadd(priv, addr, read_write);
766 xact = I801_QUICK;
767 break;
768 case I2C_SMBUS_BYTE:
769 i801_set_hstadd(priv, addr, read_write);
770 if (read_write == I2C_SMBUS_WRITE)
771 iowrite8(hstcmd, SMBHSTCMD(priv));
772 xact = I801_BYTE;
773 break;
774 case I2C_SMBUS_BYTE_DATA:
775 i801_set_hstadd(priv, addr, read_write);
776 if (read_write == I2C_SMBUS_WRITE)
777 iowrite8(data->byte, SMBHSTDAT0(priv));
778 iowrite8(hstcmd, SMBHSTCMD(priv));
779 xact = I801_BYTE_DATA;
780 break;
781 case I2C_SMBUS_WORD_DATA:
782 i801_set_hstadd(priv, addr, read_write);
783 if (read_write == I2C_SMBUS_WRITE) {
784 iowrite8(data->word & 0xff, SMBHSTDAT0(priv));
785 iowrite8((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
786 }
787 iowrite8(hstcmd, SMBHSTCMD(priv));
788 xact = I801_WORD_DATA;
789 break;
790 case I2C_SMBUS_PROC_CALL:
791 i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE);
792 iowrite8(data->word & 0xff, SMBHSTDAT0(priv));
793 iowrite8((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
794 iowrite8(hstcmd, SMBHSTCMD(priv));
795 read_write = I2C_SMBUS_READ;
796 xact = I801_PROC_CALL;
797 break;
798 default:
799 pci_err(priv->pci_dev, "Unsupported transaction %d\n", command);
800 return -EOPNOTSUPP;
801 }
802
803 ret = i801_transaction(priv, xact);
804 if (ret || read_write == I2C_SMBUS_WRITE)
805 return ret;
806
807 switch (command) {
808 case I2C_SMBUS_BYTE:
809 case I2C_SMBUS_BYTE_DATA:
810 data->byte = ioread8(SMBHSTDAT0(priv));
811 break;
812 case I2C_SMBUS_WORD_DATA:
813 case I2C_SMBUS_PROC_CALL:
814 data->word = ioread8(SMBHSTDAT0(priv)) +
815 (ioread8(SMBHSTDAT1(priv)) << 8);
816 break;
817 }
818
819 return 0;
820 }
821
i801_smbus_block_transaction(struct i801_priv * priv,union i2c_smbus_data * data,u8 addr,u8 hstcmd,char read_write,int command)822 static int i801_smbus_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data,
823 u8 addr, u8 hstcmd, char read_write, int command)
824 {
825 if (read_write == I2C_SMBUS_READ && command == I2C_SMBUS_BLOCK_DATA)
826 /* Mark block length as invalid */
827 data->block[0] = SMBUS_LEN_SENTINEL;
828 else if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
829 return -EPROTO;
830
831 if (command == I2C_SMBUS_BLOCK_PROC_CALL)
832 /* Needs to be flagged as write transaction */
833 i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE);
834 else
835 i801_set_hstadd(priv, addr, read_write);
836 iowrite8(hstcmd, SMBHSTCMD(priv));
837
838 if (priv->features & FEATURE_BLOCK_BUFFER)
839 return i801_block_transaction_by_block(priv, data, read_write, command);
840 else
841 return i801_block_transaction_byte_by_byte(priv, data, read_write, command);
842 }
843
i801_i2c_block_transaction(struct i801_priv * priv,union i2c_smbus_data * data,u8 addr,u8 hstcmd,char read_write,int command)844 static int i801_i2c_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data,
845 u8 addr, u8 hstcmd, char read_write, int command)
846 {
847 int result;
848 u8 hostc;
849
850 if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
851 return -EPROTO;
852 /*
853 * NB: page 240 of ICH5 datasheet shows that the R/#W bit should be cleared here,
854 * even when reading. However if SPD Write Disable is set (Lynx Point and later),
855 * the read will fail if we don't set the R/#W bit.
856 */
857 i801_set_hstadd(priv, addr,
858 priv->original_hstcfg & SMBHSTCFG_SPD_WD ? read_write : I2C_SMBUS_WRITE);
859
860 /* NB: page 240 of ICH5 datasheet shows that DATA1 is the cmd field when reading */
861 if (read_write == I2C_SMBUS_READ)
862 iowrite8(hstcmd, SMBHSTDAT1(priv));
863 else
864 iowrite8(hstcmd, SMBHSTCMD(priv));
865
866 if (read_write == I2C_SMBUS_WRITE) {
867 /* set I2C_EN bit in configuration register */
868 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
869 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc | SMBHSTCFG_I2C_EN);
870 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
871 pci_err(priv->pci_dev, "I2C block read is unsupported!\n");
872 return -EOPNOTSUPP;
873 }
874
875 /* Block buffer isn't supported for I2C block transactions */
876 result = i801_block_transaction_byte_by_byte(priv, data, read_write, command);
877
878 /* restore saved configuration register value */
879 if (read_write == I2C_SMBUS_WRITE)
880 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
881
882 return result;
883 }
884
885 /* Return negative errno on error. */
i801_access(struct i2c_adapter * adap,u16 addr,unsigned short flags,char read_write,u8 command,int size,union i2c_smbus_data * data)886 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
887 unsigned short flags, char read_write, u8 command,
888 int size, union i2c_smbus_data *data)
889 {
890 int hwpec, ret;
891 struct i801_priv *priv = i2c_get_adapdata(adap);
892
893 if (priv->acpi_reserved)
894 return -EBUSY;
895
896 pm_runtime_get_sync(&priv->pci_dev->dev);
897
898 ret = i801_check_pre(priv);
899 if (ret)
900 goto out;
901
902 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
903 && size != I2C_SMBUS_QUICK
904 && size != I2C_SMBUS_I2C_BLOCK_DATA;
905
906 if (hwpec) /* enable/disable hardware PEC */
907 iowrite8(ioread8(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
908 else
909 iowrite8(ioread8(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
910 SMBAUXCTL(priv));
911
912 if (size == I2C_SMBUS_BLOCK_DATA || size == I2C_SMBUS_BLOCK_PROC_CALL)
913 ret = i801_smbus_block_transaction(priv, data, addr, command, read_write, size);
914 else if (size == I2C_SMBUS_I2C_BLOCK_DATA)
915 ret = i801_i2c_block_transaction(priv, data, addr, command, read_write, size);
916 else
917 ret = i801_simple_transaction(priv, data, addr, command, read_write, size);
918
919 ret = i801_check_post(priv, ret);
920
921 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
922 * time, so we forcibly disable it after every transaction.
923 */
924 if (hwpec)
925 iowrite8(ioread8(SMBAUXCTL(priv)) & ~SMBAUXCTL_CRC, SMBAUXCTL(priv));
926 out:
927 /*
928 * Unlock the SMBus device for use by BIOS/ACPI,
929 * and clear status flags if not done already.
930 */
931 iowrite8(SMBHSTSTS_INUSE_STS | STATUS_FLAGS, SMBHSTSTS(priv));
932
933 pm_runtime_put_autosuspend(&priv->pci_dev->dev);
934 return ret;
935 }
936
937
i801_func(struct i2c_adapter * adapter)938 static u32 i801_func(struct i2c_adapter *adapter)
939 {
940 struct i801_priv *priv = i2c_get_adapdata(adapter);
941
942 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
943 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
944 I2C_FUNC_SMBUS_PROC_CALL |
945 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
946 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
947 ((priv->features & FEATURE_BLOCK_PROC) ?
948 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) |
949 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
950 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
951 ((priv->features & FEATURE_HOST_NOTIFY) ?
952 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
953 }
954
i801_enable_host_notify(struct i2c_adapter * adapter)955 static void i801_enable_host_notify(struct i2c_adapter *adapter)
956 {
957 struct i801_priv *priv = i2c_get_adapdata(adapter);
958
959 if (!(priv->features & FEATURE_HOST_NOTIFY))
960 return;
961
962 /*
963 * Enable host notify interrupt and block the generation of interrupt
964 * from the SMB_ALERT signal because the driver does not support
965 * SMBus Alert.
966 */
967 iowrite8(SMBSLVCMD_HST_NTFY_INTREN | SMBSLVCMD_SMBALERT_DISABLE |
968 priv->original_slvcmd, SMBSLVCMD(priv));
969
970 /* clear Host Notify bit to allow a new notification */
971 iowrite8(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
972 }
973
i801_disable_host_notify(struct i801_priv * priv)974 static void i801_disable_host_notify(struct i801_priv *priv)
975 {
976 if (!(priv->features & FEATURE_HOST_NOTIFY))
977 return;
978
979 iowrite8(priv->original_slvcmd, SMBSLVCMD(priv));
980 }
981
982 static const struct i2c_algorithm smbus_algorithm = {
983 .smbus_xfer = i801_access,
984 .functionality = i801_func,
985 };
986
987 #define FEATURES_ICH4 (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER | \
988 FEATURE_HOST_NOTIFY)
989 #define FEATURES_ICH5 (FEATURES_ICH4 | FEATURE_BLOCK_PROC | \
990 FEATURE_I2C_BLOCK_READ | FEATURE_IRQ)
991
992 static const struct pci_device_id i801_ids[] = {
993 { PCI_DEVICE_DATA(INTEL, 82801AA_3, 0) },
994 { PCI_DEVICE_DATA(INTEL, 82801AB_3, 0) },
995 { PCI_DEVICE_DATA(INTEL, 82801BA_2, 0) },
996 { PCI_DEVICE_DATA(INTEL, 82801CA_3, FEATURE_HOST_NOTIFY) },
997 { PCI_DEVICE_DATA(INTEL, 82801DB_3, FEATURES_ICH4) },
998 { PCI_DEVICE_DATA(INTEL, 82801EB_3, FEATURES_ICH5) },
999 { PCI_DEVICE_DATA(INTEL, ESB_4, FEATURES_ICH5) },
1000 { PCI_DEVICE_DATA(INTEL, ICH6_16, FEATURES_ICH5) },
1001 { PCI_DEVICE_DATA(INTEL, ICH7_17, FEATURES_ICH5) },
1002 { PCI_DEVICE_DATA(INTEL, ESB2_17, FEATURES_ICH5) },
1003 { PCI_DEVICE_DATA(INTEL, ICH8_5, FEATURES_ICH5) },
1004 { PCI_DEVICE_DATA(INTEL, ICH9_6, FEATURES_ICH5) },
1005 { PCI_DEVICE_DATA(INTEL, EP80579_1, FEATURES_ICH5) },
1006 { PCI_DEVICE_DATA(INTEL, ICH10_4, FEATURES_ICH5) },
1007 { PCI_DEVICE_DATA(INTEL, ICH10_5, FEATURES_ICH5) },
1008 { PCI_DEVICE_DATA(INTEL, 5_3400_SERIES_SMBUS, FEATURES_ICH5) },
1009 { PCI_DEVICE_DATA(INTEL, COUGARPOINT_SMBUS, FEATURES_ICH5) },
1010 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS, FEATURES_ICH5) },
1011 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF0, FEATURES_ICH5 | FEATURE_IDF) },
1012 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF1, FEATURES_ICH5 | FEATURE_IDF) },
1013 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF2, FEATURES_ICH5 | FEATURE_IDF) },
1014 { PCI_DEVICE_DATA(INTEL, DH89XXCC_SMBUS, FEATURES_ICH5) },
1015 { PCI_DEVICE_DATA(INTEL, PANTHERPOINT_SMBUS, FEATURES_ICH5) },
1016 { PCI_DEVICE_DATA(INTEL, LYNXPOINT_SMBUS, FEATURES_ICH5) },
1017 { PCI_DEVICE_DATA(INTEL, LYNXPOINT_LP_SMBUS, FEATURES_ICH5) },
1018 { PCI_DEVICE_DATA(INTEL, AVOTON_SMBUS, FEATURES_ICH5) },
1019 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS, FEATURES_ICH5) },
1020 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS0, FEATURES_ICH5 | FEATURE_IDF) },
1021 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS1, FEATURES_ICH5 | FEATURE_IDF) },
1022 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS2, FEATURES_ICH5 | FEATURE_IDF) },
1023 { PCI_DEVICE_DATA(INTEL, COLETOCREEK_SMBUS, FEATURES_ICH5) },
1024 { PCI_DEVICE_DATA(INTEL, GEMINILAKE_SMBUS, FEATURES_ICH5) },
1025 { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_SMBUS, FEATURES_ICH5) },
1026 { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_LP_SMBUS, FEATURES_ICH5) },
1027 { PCI_DEVICE_DATA(INTEL, BAYTRAIL_SMBUS, FEATURES_ICH5) },
1028 { PCI_DEVICE_DATA(INTEL, BRASWELL_SMBUS, FEATURES_ICH5) },
1029 { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1030 { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1031 { PCI_DEVICE_DATA(INTEL, CDF_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1032 { PCI_DEVICE_DATA(INTEL, DNV_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1033 { PCI_DEVICE_DATA(INTEL, EBG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1034 { PCI_DEVICE_DATA(INTEL, BROXTON_SMBUS, FEATURES_ICH5) },
1035 { PCI_DEVICE_DATA(INTEL, LEWISBURG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1036 { PCI_DEVICE_DATA(INTEL, LEWISBURG_SSKU_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1037 { PCI_DEVICE_DATA(INTEL, KABYLAKE_PCH_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1038 { PCI_DEVICE_DATA(INTEL, CANNONLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1039 { PCI_DEVICE_DATA(INTEL, CANNONLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1040 { PCI_DEVICE_DATA(INTEL, ICELAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1041 { PCI_DEVICE_DATA(INTEL, ICELAKE_N_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1042 { PCI_DEVICE_DATA(INTEL, COMETLAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1043 { PCI_DEVICE_DATA(INTEL, COMETLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1044 { PCI_DEVICE_DATA(INTEL, COMETLAKE_V_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1045 { PCI_DEVICE_DATA(INTEL, ELKHART_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1046 { PCI_DEVICE_DATA(INTEL, TIGERLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1047 { PCI_DEVICE_DATA(INTEL, TIGERLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1048 { PCI_DEVICE_DATA(INTEL, JASPER_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1049 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1050 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1051 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_M_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1052 { PCI_DEVICE_DATA(INTEL, RAPTOR_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1053 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1054 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_SOC_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1055 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_PCH_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1056 { PCI_DEVICE_DATA(INTEL, BIRCH_STREAM_SMBUS, FEATURES_ICH5) },
1057 { PCI_DEVICE_DATA(INTEL, ARROW_LAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1058 { PCI_DEVICE_DATA(INTEL, PANTHER_LAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1059 { PCI_DEVICE_DATA(INTEL, PANTHER_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1060 { PCI_DEVICE_DATA(INTEL, WILDCAT_LAKE_U_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1061 { 0, }
1062 };
1063
1064 MODULE_DEVICE_TABLE(pci, i801_ids);
1065
1066 #if defined CONFIG_X86 && defined CONFIG_DMI
1067 static unsigned char apanel_addr __ro_after_init;
1068
1069 /* Scan the system ROM for the signature "FJKEYINF" */
bios_signature(const void __iomem * bios)1070 static __init const void __iomem *bios_signature(const void __iomem *bios)
1071 {
1072 ssize_t offset;
1073 const unsigned char signature[] = "FJKEYINF";
1074
1075 for (offset = 0; offset < 0x10000; offset += 0x10) {
1076 if (check_signature(bios + offset, signature,
1077 sizeof(signature)-1))
1078 return bios + offset;
1079 }
1080 return NULL;
1081 }
1082
input_apanel_init(void)1083 static void __init input_apanel_init(void)
1084 {
1085 void __iomem *bios;
1086 const void __iomem *p;
1087
1088 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1089 p = bios_signature(bios);
1090 if (p) {
1091 /* just use the first address */
1092 apanel_addr = readb(p + 8 + 3) >> 1;
1093 }
1094 iounmap(bios);
1095 }
1096
1097 struct dmi_onboard_device_info {
1098 const char *name;
1099 u8 type;
1100 unsigned short i2c_addr;
1101 const char *i2c_type;
1102 };
1103
1104 static const struct dmi_onboard_device_info dmi_devices[] = {
1105 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1106 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1107 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1108 };
1109
dmi_check_onboard_device(u8 type,const char * name,struct i2c_adapter * adap)1110 static void dmi_check_onboard_device(u8 type, const char *name,
1111 struct i2c_adapter *adap)
1112 {
1113 int i;
1114 struct i2c_board_info info;
1115
1116 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1117 /* & ~0x80, ignore enabled/disabled bit */
1118 if ((type & ~0x80) != dmi_devices[i].type)
1119 continue;
1120 if (strcasecmp(name, dmi_devices[i].name))
1121 continue;
1122
1123 memset(&info, 0, sizeof(struct i2c_board_info));
1124 info.addr = dmi_devices[i].i2c_addr;
1125 strscpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1126 i2c_new_client_device(adap, &info);
1127 break;
1128 }
1129 }
1130
1131 /* We use our own function to check for onboard devices instead of
1132 dmi_find_device() as some buggy BIOS's have the devices we are interested
1133 in marked as disabled */
dmi_check_onboard_devices(const struct dmi_header * dm,void * adap)1134 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1135 {
1136 int i, count;
1137
1138 if (dm->type != DMI_ENTRY_ONBOARD_DEVICE)
1139 return;
1140
1141 count = (dm->length - sizeof(struct dmi_header)) / 2;
1142 for (i = 0; i < count; i++) {
1143 const u8 *d = (char *)(dm + 1) + (i * 2);
1144 const char *name = ((char *) dm) + dm->length;
1145 u8 type = d[0];
1146 u8 s = d[1];
1147
1148 if (!s)
1149 continue;
1150 s--;
1151 while (s > 0 && name[0]) {
1152 name += strlen(name) + 1;
1153 s--;
1154 }
1155 if (name[0] == 0) /* Bogus string reference */
1156 continue;
1157
1158 dmi_check_onboard_device(type, name, adap);
1159 }
1160 }
1161
1162 /* Register optional targets */
i801_probe_optional_targets(struct i801_priv * priv)1163 static void i801_probe_optional_targets(struct i801_priv *priv)
1164 {
1165 /* Only register targets on main SMBus channel */
1166 if (priv->features & FEATURE_IDF)
1167 return;
1168
1169 if (apanel_addr) {
1170 struct i2c_board_info info = {
1171 .addr = apanel_addr,
1172 .type = "fujitsu_apanel",
1173 };
1174
1175 i2c_new_client_device(&priv->adapter, &info);
1176 }
1177
1178 if (dmi_name_in_vendors("FUJITSU"))
1179 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1180
1181 /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */
1182 #ifdef CONFIG_I2C_I801_MUX
1183 if (!priv->mux_pdev)
1184 #endif
1185 i2c_register_spd_write_enable(&priv->adapter);
1186 }
1187 #else
input_apanel_init(void)1188 static void __init input_apanel_init(void) {}
i801_probe_optional_targets(struct i801_priv * priv)1189 static void i801_probe_optional_targets(struct i801_priv *priv) {}
1190 #endif /* CONFIG_X86 && CONFIG_DMI */
1191
1192 #ifdef CONFIG_I2C_I801_MUX
1193 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1194 .gpio_chip = "gpio_ich",
1195 .values = { 0x02, 0x03 },
1196 .n_values = 2,
1197 .gpios = { 52, 53 },
1198 .n_gpios = 2,
1199 };
1200
1201 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1202 .gpio_chip = "gpio_ich",
1203 .values = { 0x02, 0x03, 0x01 },
1204 .n_values = 3,
1205 .gpios = { 52, 53 },
1206 .n_gpios = 2,
1207 };
1208
1209 static const struct dmi_system_id mux_dmi_table[] = {
1210 {
1211 .matches = {
1212 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1213 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1214 },
1215 .driver_data = &i801_mux_config_asus_z8_d12,
1216 },
1217 {
1218 .matches = {
1219 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1220 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1221 },
1222 .driver_data = &i801_mux_config_asus_z8_d12,
1223 },
1224 {
1225 .matches = {
1226 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1227 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1228 },
1229 .driver_data = &i801_mux_config_asus_z8_d12,
1230 },
1231 {
1232 .matches = {
1233 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1234 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1235 },
1236 .driver_data = &i801_mux_config_asus_z8_d12,
1237 },
1238 {
1239 .matches = {
1240 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1241 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1242 },
1243 .driver_data = &i801_mux_config_asus_z8_d12,
1244 },
1245 {
1246 .matches = {
1247 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1248 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1249 },
1250 .driver_data = &i801_mux_config_asus_z8_d12,
1251 },
1252 {
1253 .matches = {
1254 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1255 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1256 },
1257 .driver_data = &i801_mux_config_asus_z8_d18,
1258 },
1259 {
1260 .matches = {
1261 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1262 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1263 },
1264 .driver_data = &i801_mux_config_asus_z8_d18,
1265 },
1266 {
1267 .matches = {
1268 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1269 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1270 },
1271 .driver_data = &i801_mux_config_asus_z8_d12,
1272 },
1273 { }
1274 };
1275
i801_notifier_call(struct notifier_block * nb,unsigned long action,void * data)1276 static int i801_notifier_call(struct notifier_block *nb, unsigned long action,
1277 void *data)
1278 {
1279 struct i801_priv *priv = container_of(nb, struct i801_priv, mux_notifier_block);
1280 struct device *dev = data;
1281
1282 if (action != BUS_NOTIFY_ADD_DEVICE ||
1283 dev->type != &i2c_adapter_type ||
1284 i2c_root_adapter(dev) != &priv->adapter)
1285 return NOTIFY_DONE;
1286
1287 /* Call i2c_register_spd for muxed child segments */
1288 i2c_register_spd_write_enable(to_i2c_adapter(dev));
1289
1290 return NOTIFY_OK;
1291 }
1292
1293 /* Setup multiplexing if needed */
i801_add_mux(struct i801_priv * priv)1294 static void i801_add_mux(struct i801_priv *priv)
1295 {
1296 struct device *dev = &priv->adapter.dev;
1297 const struct i801_mux_config *mux_config;
1298 struct i2c_mux_gpio_platform_data gpio_data;
1299 struct gpiod_lookup_table *lookup;
1300 const struct dmi_system_id *id;
1301 int i;
1302
1303 id = dmi_first_match(mux_dmi_table);
1304 if (!id)
1305 return;
1306
1307 mux_config = id->driver_data;
1308
1309 /* Prepare the platform data */
1310 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1311 gpio_data.parent = priv->adapter.nr;
1312 gpio_data.values = mux_config->values;
1313 gpio_data.n_values = mux_config->n_values;
1314 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1315
1316 /* Register GPIO descriptor lookup table */
1317 lookup = devm_kzalloc(dev,
1318 struct_size(lookup, table, mux_config->n_gpios + 1),
1319 GFP_KERNEL);
1320 if (!lookup)
1321 return;
1322 lookup->dev_id = "i2c-mux-gpio";
1323 for (i = 0; i < mux_config->n_gpios; i++)
1324 lookup->table[i] = GPIO_LOOKUP(mux_config->gpio_chip,
1325 mux_config->gpios[i], "mux", 0);
1326 gpiod_add_lookup_table(lookup);
1327
1328 priv->mux_notifier_block.notifier_call = i801_notifier_call;
1329 if (bus_register_notifier(&i2c_bus_type, &priv->mux_notifier_block))
1330 return;
1331 /*
1332 * Register the mux device, we use PLATFORM_DEVID_NONE here
1333 * because since we are referring to the GPIO chip by name we are
1334 * anyways in deep trouble if there is more than one of these
1335 * devices, and there should likely only be one platform controller
1336 * hub.
1337 */
1338 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1339 PLATFORM_DEVID_NONE, &gpio_data,
1340 sizeof(struct i2c_mux_gpio_platform_data));
1341 if (IS_ERR(priv->mux_pdev)) {
1342 gpiod_remove_lookup_table(lookup);
1343 devm_kfree(dev, lookup);
1344 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1345 } else {
1346 priv->lookup = lookup;
1347 }
1348 }
1349
i801_del_mux(struct i801_priv * priv)1350 static void i801_del_mux(struct i801_priv *priv)
1351 {
1352 bus_unregister_notifier(&i2c_bus_type, &priv->mux_notifier_block);
1353 platform_device_unregister(priv->mux_pdev);
1354 gpiod_remove_lookup_table(priv->lookup);
1355 }
1356 #else
i801_add_mux(struct i801_priv * priv)1357 static inline void i801_add_mux(struct i801_priv *priv) { }
i801_del_mux(struct i801_priv * priv)1358 static inline void i801_del_mux(struct i801_priv *priv) { }
1359 #endif
1360
1361 static struct platform_device *
i801_add_tco_spt(struct pci_dev * pci_dev,struct resource * tco_res)1362 i801_add_tco_spt(struct pci_dev *pci_dev, struct resource *tco_res)
1363 {
1364 static const struct itco_wdt_platform_data pldata = {
1365 .name = "Intel PCH",
1366 .version = 4,
1367 };
1368 struct resource *res;
1369 int ret;
1370
1371 /*
1372 * We must access the NO_REBOOT bit over the Primary to Sideband
1373 * (P2SB) bridge.
1374 */
1375
1376 res = &tco_res[1];
1377 ret = p2sb_bar(pci_dev->bus, 0, res);
1378 if (ret)
1379 return ERR_PTR(ret);
1380
1381 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1382 res->start += SBREG_SMBCTRL_DNV;
1383 else
1384 res->start += SBREG_SMBCTRL;
1385
1386 res->end = res->start + 3;
1387
1388 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1389 tco_res, 2, &pldata, sizeof(pldata));
1390 }
1391
1392 static struct platform_device *
i801_add_tco_cnl(struct pci_dev * pci_dev,struct resource * tco_res)1393 i801_add_tco_cnl(struct pci_dev *pci_dev, struct resource *tco_res)
1394 {
1395 static const struct itco_wdt_platform_data pldata = {
1396 .name = "Intel PCH",
1397 .version = 6,
1398 };
1399
1400 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1401 tco_res, 1, &pldata, sizeof(pldata));
1402 }
1403
i801_add_tco(struct i801_priv * priv)1404 static void i801_add_tco(struct i801_priv *priv)
1405 {
1406 struct pci_dev *pci_dev = priv->pci_dev;
1407 struct resource tco_res[2], *res;
1408 u32 tco_base, tco_ctl;
1409
1410 /* If we have ACPI based watchdog use that instead */
1411 if (acpi_has_watchdog())
1412 return;
1413
1414 if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL)))
1415 return;
1416
1417 pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1418 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1419 if (!(tco_ctl & TCOCTL_EN))
1420 return;
1421
1422 memset(tco_res, 0, sizeof(tco_res));
1423 /*
1424 * Always populate the main iTCO IO resource here. The second entry
1425 * for NO_REBOOT MMIO is filled by the SPT specific function.
1426 */
1427 res = &tco_res[0];
1428 res->start = tco_base & ~1;
1429 res->end = res->start + 32 - 1;
1430 res->flags = IORESOURCE_IO;
1431
1432 if (priv->features & FEATURE_TCO_CNL)
1433 priv->tco_pdev = i801_add_tco_cnl(pci_dev, tco_res);
1434 else
1435 priv->tco_pdev = i801_add_tco_spt(pci_dev, tco_res);
1436
1437 if (IS_ERR(priv->tco_pdev))
1438 pci_warn(pci_dev, "failed to create iTCO device\n");
1439 }
1440
1441 #ifdef CONFIG_ACPI
i801_acpi_is_smbus_ioport(const struct i801_priv * priv,acpi_physical_address address)1442 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1443 acpi_physical_address address)
1444 {
1445 return address >= pci_resource_start(priv->pci_dev, SMBBAR) &&
1446 address <= pci_resource_end(priv->pci_dev, SMBBAR);
1447 }
1448
1449 static acpi_status
i801_acpi_io_handler(u32 function,acpi_physical_address address,u32 bits,u64 * value,void * handler_context,void * region_context)1450 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1451 u64 *value, void *handler_context, void *region_context)
1452 {
1453 struct i801_priv *priv = handler_context;
1454 struct pci_dev *pdev = priv->pci_dev;
1455 acpi_status status;
1456
1457 /*
1458 * Once BIOS AML code touches the OpRegion we warn and inhibit any
1459 * further access from the driver itself. This device is now owned
1460 * by the system firmware.
1461 */
1462 i2c_lock_bus(&priv->adapter, I2C_LOCK_SEGMENT);
1463
1464 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
1465 priv->acpi_reserved = true;
1466
1467 pci_warn(pdev, "BIOS is accessing SMBus registers\n");
1468 pci_warn(pdev, "Driver SMBus register access inhibited\n");
1469
1470 /*
1471 * BIOS is accessing the host controller so prevent it from
1472 * suspending automatically from now on.
1473 */
1474 pm_runtime_get_sync(&pdev->dev);
1475 }
1476
1477 if ((function & ACPI_IO_MASK) == ACPI_READ)
1478 status = acpi_os_read_port(address, (u32 *)value, bits);
1479 else
1480 status = acpi_os_write_port(address, (u32)*value, bits);
1481
1482 i2c_unlock_bus(&priv->adapter, I2C_LOCK_SEGMENT);
1483
1484 return status;
1485 }
1486
i801_acpi_probe(struct i801_priv * priv)1487 static int i801_acpi_probe(struct i801_priv *priv)
1488 {
1489 acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev);
1490 acpi_status status;
1491
1492 status = acpi_install_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO,
1493 i801_acpi_io_handler, NULL, priv);
1494 if (ACPI_SUCCESS(status))
1495 return 0;
1496
1497 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1498 }
1499
i801_acpi_remove(struct i801_priv * priv)1500 static void i801_acpi_remove(struct i801_priv *priv)
1501 {
1502 acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev);
1503
1504 acpi_remove_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1505 }
1506 #else
i801_acpi_probe(struct i801_priv * priv)1507 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
i801_acpi_remove(struct i801_priv * priv)1508 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1509 #endif
1510
i801_setup_hstcfg(struct i801_priv * priv)1511 static void i801_setup_hstcfg(struct i801_priv *priv)
1512 {
1513 unsigned char hstcfg = priv->original_hstcfg;
1514
1515 hstcfg &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
1516 hstcfg |= SMBHSTCFG_HST_EN;
1517 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg);
1518 }
1519
i801_restore_regs(struct i801_priv * priv)1520 static void i801_restore_regs(struct i801_priv *priv)
1521 {
1522 iowrite8(priv->original_hstcnt, SMBHSTCNT(priv));
1523 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, priv->original_hstcfg);
1524 }
1525
i801_probe(struct pci_dev * dev,const struct pci_device_id * id)1526 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1527 {
1528 int err, i, bar = SMBBAR;
1529 struct i801_priv *priv;
1530
1531 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1532 if (!priv)
1533 return -ENOMEM;
1534
1535 i2c_set_adapdata(&priv->adapter, priv);
1536 priv->adapter.owner = THIS_MODULE;
1537 priv->adapter.class = I2C_CLASS_HWMON;
1538 priv->adapter.algo = &smbus_algorithm;
1539 priv->adapter.dev.parent = &dev->dev;
1540 acpi_use_parent_companion(&priv->adapter.dev);
1541 priv->adapter.retries = 3;
1542
1543 priv->pci_dev = dev;
1544 priv->features = id->driver_data;
1545
1546 /* Disable features on user request */
1547 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1548 if (priv->features & disable_features & (1 << i))
1549 pci_notice(dev, "%s disabled by user\n", i801_feature_names[i]);
1550 }
1551 priv->features &= ~disable_features;
1552
1553 /* The block process call uses block buffer mode */
1554 if (!(priv->features & FEATURE_BLOCK_BUFFER))
1555 priv->features &= ~FEATURE_BLOCK_PROC;
1556
1557 /*
1558 * Do not call pcim_enable_device(), because the device has to remain
1559 * enabled on driver detach. See i801_remove() for the reasoning.
1560 */
1561 err = pci_enable_device(dev);
1562 if (err) {
1563 pci_err(dev, "Failed to enable SMBus PCI device (%d)\n", err);
1564 return err;
1565 }
1566
1567 /* Determine the address of the SMBus area */
1568 if (!pci_resource_start(dev, SMBBAR)) {
1569 pci_err(dev, "SMBus base address uninitialized, upgrade BIOS\n");
1570 return -ENODEV;
1571 }
1572
1573 if (i801_acpi_probe(priv))
1574 return -ENODEV;
1575
1576 if (pci_resource_flags(dev, SMBBAR_MMIO) & IORESOURCE_MEM)
1577 bar = SMBBAR_MMIO;
1578
1579 priv->smba = pcim_iomap_region(dev, bar, DRV_NAME);
1580 if (IS_ERR(priv->smba)) {
1581 pci_err(dev, "Failed to request SMBus region %pr\n",
1582 pci_resource_n(dev, bar));
1583 i801_acpi_remove(priv);
1584 return PTR_ERR(priv->smba);
1585 }
1586
1587 pci_read_config_byte(dev, SMBHSTCFG, &priv->original_hstcfg);
1588 i801_setup_hstcfg(priv);
1589 if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN))
1590 pci_info(dev, "Enabling SMBus device\n");
1591
1592 if (priv->original_hstcfg & SMBHSTCFG_SMB_SMI_EN) {
1593 pci_dbg(dev, "SMBus using interrupt SMI#\n");
1594 /* Disable SMBus interrupt feature if SMBus using SMI# */
1595 priv->features &= ~FEATURE_IRQ;
1596 }
1597 if (priv->original_hstcfg & SMBHSTCFG_SPD_WD)
1598 pci_info(dev, "SPD Write Disable is set\n");
1599
1600 /* Clear special mode bits */
1601 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1602 iowrite8(ioread8(SMBAUXCTL(priv)) &
1603 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1604
1605 /* Default timeout in interrupt mode: 200 ms */
1606 priv->adapter.timeout = HZ / 5;
1607
1608 if (dev->irq == IRQ_NOTCONNECTED)
1609 priv->features &= ~FEATURE_IRQ;
1610
1611 if (priv->features & FEATURE_IRQ) {
1612 u16 pcists;
1613
1614 /* Complain if an interrupt is already pending */
1615 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists);
1616 if (pcists & PCI_STATUS_INTERRUPT)
1617 pci_warn(dev, "An interrupt is pending!\n");
1618 }
1619
1620 if (priv->features & FEATURE_IRQ) {
1621 init_completion(&priv->done);
1622
1623 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1624 IRQF_SHARED, DRV_NAME, priv);
1625 if (err) {
1626 pci_err(dev, "Failed to allocate irq %d: %d\n", dev->irq, err);
1627 priv->features &= ~FEATURE_IRQ;
1628 }
1629 }
1630 pci_info(dev, "SMBus using %s\n",
1631 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1632
1633 /* Host notification uses an interrupt */
1634 if (!(priv->features & FEATURE_IRQ))
1635 priv->features &= ~FEATURE_HOST_NOTIFY;
1636
1637 /* Remember original Interrupt and Host Notify settings */
1638 priv->original_hstcnt = ioread8(SMBHSTCNT(priv)) & ~SMBHSTCNT_KILL;
1639 if (priv->features & FEATURE_HOST_NOTIFY)
1640 priv->original_slvcmd = ioread8(SMBSLVCMD(priv));
1641
1642 i801_add_tco(priv);
1643
1644 /*
1645 * adapter.name is used by platform code to find the main I801 adapter
1646 * to instantiante i2c_clients, do not change.
1647 */
1648 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1649 "SMBus %s adapter at %s",
1650 (priv->features & FEATURE_IDF) ? "I801 IDF" : "I801",
1651 pci_name(dev));
1652
1653 err = i2c_add_adapter(&priv->adapter);
1654 if (err) {
1655 platform_device_unregister(priv->tco_pdev);
1656 i801_acpi_remove(priv);
1657 i801_restore_regs(priv);
1658 return err;
1659 }
1660
1661 i801_enable_host_notify(&priv->adapter);
1662
1663 /* We ignore errors - multiplexing is optional */
1664 i801_add_mux(priv);
1665 i801_probe_optional_targets(priv);
1666
1667 pci_set_drvdata(dev, priv);
1668
1669 dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
1670 pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1671 pm_runtime_use_autosuspend(&dev->dev);
1672 pm_runtime_put_autosuspend(&dev->dev);
1673 pm_runtime_allow(&dev->dev);
1674
1675 return 0;
1676 }
1677
i801_remove(struct pci_dev * dev)1678 static void i801_remove(struct pci_dev *dev)
1679 {
1680 struct i801_priv *priv = pci_get_drvdata(dev);
1681
1682 i801_disable_host_notify(priv);
1683 i801_del_mux(priv);
1684 i2c_del_adapter(&priv->adapter);
1685 i801_acpi_remove(priv);
1686
1687 platform_device_unregister(priv->tco_pdev);
1688
1689 /* if acpi_reserved is set then usage_count is incremented already */
1690 if (!priv->acpi_reserved)
1691 pm_runtime_get_noresume(&dev->dev);
1692
1693 i801_restore_regs(priv);
1694
1695 /*
1696 * do not call pci_disable_device(dev) since it can cause hard hangs on
1697 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1698 */
1699 }
1700
i801_shutdown(struct pci_dev * dev)1701 static void i801_shutdown(struct pci_dev *dev)
1702 {
1703 struct i801_priv *priv = pci_get_drvdata(dev);
1704
1705 i801_disable_host_notify(priv);
1706 /* Restore config registers to avoid hard hang on some systems */
1707 i801_restore_regs(priv);
1708 }
1709
i801_suspend(struct device * dev)1710 static int i801_suspend(struct device *dev)
1711 {
1712 struct i801_priv *priv = dev_get_drvdata(dev);
1713
1714 i2c_mark_adapter_suspended(&priv->adapter);
1715 i801_restore_regs(priv);
1716
1717 return 0;
1718 }
1719
i801_resume(struct device * dev)1720 static int i801_resume(struct device *dev)
1721 {
1722 struct i801_priv *priv = dev_get_drvdata(dev);
1723
1724 i801_setup_hstcfg(priv);
1725 i801_enable_host_notify(&priv->adapter);
1726 i2c_mark_adapter_resumed(&priv->adapter);
1727
1728 return 0;
1729 }
1730
1731 static DEFINE_SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume);
1732
1733 static struct pci_driver i801_driver = {
1734 .name = DRV_NAME,
1735 .id_table = i801_ids,
1736 .probe = i801_probe,
1737 .remove = i801_remove,
1738 .shutdown = i801_shutdown,
1739 .driver = {
1740 .pm = pm_sleep_ptr(&i801_pm_ops),
1741 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1742 },
1743 };
1744
i2c_i801_init(struct pci_driver * drv)1745 static int __init i2c_i801_init(struct pci_driver *drv)
1746 {
1747 if (dmi_name_in_vendors("FUJITSU"))
1748 input_apanel_init();
1749 return pci_register_driver(drv);
1750 }
1751
1752 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>");
1753 MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>");
1754 MODULE_DESCRIPTION("I801 SMBus driver");
1755 MODULE_LICENSE("GPL");
1756
1757 module_driver(i801_driver, i2c_i801_init, pci_unregister_driver);
1758