1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * based on nouveau_prime.c
23 *
24 * Authors: Alex Deucher
25 */
26
27 /**
28 * DOC: PRIME Buffer Sharing
29 *
30 * The following callback implementations are used for :ref:`sharing GEM buffer
31 * objects between different devices via PRIME <prime_buffer_sharing>`.
32 */
33
34 #include "amdgpu.h"
35 #include "amdgpu_display.h"
36 #include "amdgpu_gem.h"
37 #include "amdgpu_dma_buf.h"
38 #include "amdgpu_xgmi.h"
39 #include "amdgpu_vm.h"
40 #include <drm/amdgpu_drm.h>
41 #include <drm/ttm/ttm_tt.h>
42 #include <linux/dma-buf.h>
43 #include <linux/dma-fence-array.h>
44 #include <linux/pci-p2pdma.h>
45
46 static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops;
47
48 /**
49 * dma_buf_attach_adev - Helper to get adev of an attachment
50 *
51 * @attach: attachment
52 *
53 * Returns:
54 * A struct amdgpu_device * if the attaching device is an amdgpu device or
55 * partition, NULL otherwise.
56 */
dma_buf_attach_adev(struct dma_buf_attachment * attach)57 static struct amdgpu_device *dma_buf_attach_adev(struct dma_buf_attachment *attach)
58 {
59 if (attach->importer_ops == &amdgpu_dma_buf_attach_ops) {
60 struct drm_gem_object *obj = attach->importer_priv;
61 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
62
63 return amdgpu_ttm_adev(bo->tbo.bdev);
64 }
65
66 return NULL;
67 }
68
69 /**
70 * amdgpu_dma_buf_attach - &dma_buf_ops.attach implementation
71 *
72 * @dmabuf: DMA-buf where we attach to
73 * @attach: attachment to add
74 *
75 * Add the attachment as user to the exported DMA-buf.
76 */
amdgpu_dma_buf_attach(struct dma_buf * dmabuf,struct dma_buf_attachment * attach)77 static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf,
78 struct dma_buf_attachment *attach)
79 {
80 struct amdgpu_device *attach_adev = dma_buf_attach_adev(attach);
81 struct drm_gem_object *obj = dmabuf->priv;
82 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
83 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
84
85 if (!amdgpu_dmabuf_is_xgmi_accessible(attach_adev, bo) &&
86 pci_p2pdma_distance(adev->pdev, attach->dev, false) < 0)
87 attach->peer2peer = false;
88
89 amdgpu_vm_bo_update_shared(bo);
90
91 return 0;
92 }
93
94 /**
95 * amdgpu_dma_buf_pin - &dma_buf_ops.pin implementation
96 *
97 * @attach: attachment to pin down
98 *
99 * Pin the BO which is backing the DMA-buf so that it can't move any more.
100 */
amdgpu_dma_buf_pin(struct dma_buf_attachment * attach)101 static int amdgpu_dma_buf_pin(struct dma_buf_attachment *attach)
102 {
103 struct dma_buf *dmabuf = attach->dmabuf;
104 struct amdgpu_bo *bo = gem_to_amdgpu_bo(dmabuf->priv);
105 u32 domains = bo->allowed_domains;
106
107 dma_resv_assert_held(dmabuf->resv);
108
109 /* Try pinning into VRAM to allow P2P with RDMA NICs without ODP
110 * support if all attachments can do P2P. If any attachment can't do
111 * P2P just pin into GTT instead.
112 *
113 * To avoid with conflicting pinnings between GPUs and RDMA when move
114 * notifiers are disabled, only allow pinning in VRAM when move
115 * notiers are enabled.
116 */
117 if (!IS_ENABLED(CONFIG_DMABUF_MOVE_NOTIFY)) {
118 domains &= ~AMDGPU_GEM_DOMAIN_VRAM;
119 } else {
120 list_for_each_entry(attach, &dmabuf->attachments, node)
121 if (!attach->peer2peer)
122 domains &= ~AMDGPU_GEM_DOMAIN_VRAM;
123 }
124
125 if (domains & AMDGPU_GEM_DOMAIN_VRAM)
126 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
127
128 if (WARN_ON(!domains))
129 return -EINVAL;
130
131 return amdgpu_bo_pin(bo, domains);
132 }
133
134 /**
135 * amdgpu_dma_buf_unpin - &dma_buf_ops.unpin implementation
136 *
137 * @attach: attachment to unpin
138 *
139 * Unpin a previously pinned BO to make it movable again.
140 */
amdgpu_dma_buf_unpin(struct dma_buf_attachment * attach)141 static void amdgpu_dma_buf_unpin(struct dma_buf_attachment *attach)
142 {
143 struct drm_gem_object *obj = attach->dmabuf->priv;
144 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
145
146 amdgpu_bo_unpin(bo);
147 }
148
149 /**
150 * amdgpu_dma_buf_map - &dma_buf_ops.map_dma_buf implementation
151 * @attach: DMA-buf attachment
152 * @dir: DMA direction
153 *
154 * Makes sure that the shared DMA buffer can be accessed by the target device.
155 * For now, simply pins it to the GTT domain, where it should be accessible by
156 * all DMA devices.
157 *
158 * Returns:
159 * sg_table filled with the DMA addresses to use or ERR_PRT with negative error
160 * code.
161 */
amdgpu_dma_buf_map(struct dma_buf_attachment * attach,enum dma_data_direction dir)162 static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach,
163 enum dma_data_direction dir)
164 {
165 struct dma_buf *dma_buf = attach->dmabuf;
166 struct drm_gem_object *obj = dma_buf->priv;
167 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
168 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
169 struct sg_table *sgt;
170 long r;
171
172 if (!bo->tbo.pin_count) {
173 /* move buffer into GTT or VRAM */
174 struct ttm_operation_ctx ctx = { false, false };
175 unsigned int domains = AMDGPU_GEM_DOMAIN_GTT;
176
177 if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM &&
178 attach->peer2peer) {
179 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
180 domains |= AMDGPU_GEM_DOMAIN_VRAM;
181 }
182 amdgpu_bo_placement_from_domain(bo, domains);
183 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
184 if (r)
185 return ERR_PTR(r);
186 }
187
188 switch (bo->tbo.resource->mem_type) {
189 case TTM_PL_TT:
190 sgt = drm_prime_pages_to_sg(obj->dev,
191 bo->tbo.ttm->pages,
192 bo->tbo.ttm->num_pages);
193 if (IS_ERR(sgt))
194 return sgt;
195
196 if (dma_map_sgtable(attach->dev, sgt, dir,
197 DMA_ATTR_SKIP_CPU_SYNC))
198 goto error_free;
199 break;
200
201 case TTM_PL_VRAM:
202 /* XGMI-accessible memory should never be DMA-mapped */
203 if (WARN_ON(amdgpu_dmabuf_is_xgmi_accessible(
204 dma_buf_attach_adev(attach), bo)))
205 return ERR_PTR(-EINVAL);
206
207 r = amdgpu_vram_mgr_alloc_sgt(adev, bo->tbo.resource, 0,
208 bo->tbo.base.size, attach->dev,
209 dir, &sgt);
210 if (r)
211 return ERR_PTR(r);
212 break;
213 default:
214 return ERR_PTR(-EINVAL);
215 }
216
217 return sgt;
218
219 error_free:
220 sg_free_table(sgt);
221 kfree(sgt);
222 return ERR_PTR(-EBUSY);
223 }
224
225 /**
226 * amdgpu_dma_buf_unmap - &dma_buf_ops.unmap_dma_buf implementation
227 * @attach: DMA-buf attachment
228 * @sgt: sg_table to unmap
229 * @dir: DMA direction
230 *
231 * This is called when a shared DMA buffer no longer needs to be accessible by
232 * another device. For now, simply unpins the buffer from GTT.
233 */
amdgpu_dma_buf_unmap(struct dma_buf_attachment * attach,struct sg_table * sgt,enum dma_data_direction dir)234 static void amdgpu_dma_buf_unmap(struct dma_buf_attachment *attach,
235 struct sg_table *sgt,
236 enum dma_data_direction dir)
237 {
238 if (sg_page(sgt->sgl)) {
239 dma_unmap_sgtable(attach->dev, sgt, dir, 0);
240 sg_free_table(sgt);
241 kfree(sgt);
242 } else {
243 amdgpu_vram_mgr_free_sgt(attach->dev, dir, sgt);
244 }
245 }
246
247 /**
248 * amdgpu_dma_buf_begin_cpu_access - &dma_buf_ops.begin_cpu_access implementation
249 * @dma_buf: Shared DMA buffer
250 * @direction: Direction of DMA transfer
251 *
252 * This is called before CPU access to the shared DMA buffer's memory. If it's
253 * a read access, the buffer is moved to the GTT domain if possible, for optimal
254 * CPU read performance.
255 *
256 * Returns:
257 * 0 on success or a negative error code on failure.
258 */
amdgpu_dma_buf_begin_cpu_access(struct dma_buf * dma_buf,enum dma_data_direction direction)259 static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf,
260 enum dma_data_direction direction)
261 {
262 struct amdgpu_bo *bo = gem_to_amdgpu_bo(dma_buf->priv);
263 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
264 struct ttm_operation_ctx ctx = { true, false };
265 u32 domain = amdgpu_display_supported_domains(adev, bo->flags);
266 int ret;
267 bool reads = (direction == DMA_BIDIRECTIONAL ||
268 direction == DMA_FROM_DEVICE);
269
270 if (!reads || !(domain & AMDGPU_GEM_DOMAIN_GTT))
271 return 0;
272
273 /* move to gtt */
274 ret = amdgpu_bo_reserve(bo, false);
275 if (unlikely(ret != 0))
276 return ret;
277
278 if (!bo->tbo.pin_count &&
279 (bo->allowed_domains & AMDGPU_GEM_DOMAIN_GTT)) {
280 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
281 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
282 }
283
284 amdgpu_bo_unreserve(bo);
285 return ret;
286 }
287
288 const struct dma_buf_ops amdgpu_dmabuf_ops = {
289 .attach = amdgpu_dma_buf_attach,
290 .pin = amdgpu_dma_buf_pin,
291 .unpin = amdgpu_dma_buf_unpin,
292 .map_dma_buf = amdgpu_dma_buf_map,
293 .unmap_dma_buf = amdgpu_dma_buf_unmap,
294 .release = drm_gem_dmabuf_release,
295 .begin_cpu_access = amdgpu_dma_buf_begin_cpu_access,
296 .mmap = drm_gem_dmabuf_mmap,
297 .vmap = drm_gem_dmabuf_vmap,
298 .vunmap = drm_gem_dmabuf_vunmap,
299 };
300
301 /**
302 * amdgpu_gem_prime_export - &drm_driver.gem_prime_export implementation
303 * @gobj: GEM BO
304 * @flags: Flags such as DRM_CLOEXEC and DRM_RDWR.
305 *
306 * The main work is done by the &drm_gem_prime_export helper.
307 *
308 * Returns:
309 * Shared DMA buffer representing the GEM BO from the given device.
310 */
amdgpu_gem_prime_export(struct drm_gem_object * gobj,int flags)311 struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj,
312 int flags)
313 {
314 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
315 struct dma_buf *buf;
316
317 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
318 bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
319 return ERR_PTR(-EPERM);
320
321 buf = drm_gem_prime_export(gobj, flags);
322 if (!IS_ERR(buf))
323 buf->ops = &amdgpu_dmabuf_ops;
324
325 return buf;
326 }
327
328 /**
329 * amdgpu_dma_buf_create_obj - create BO for DMA-buf import
330 *
331 * @dev: DRM device
332 * @dma_buf: DMA-buf
333 *
334 * Creates an empty SG BO for DMA-buf import.
335 *
336 * Returns:
337 * A new GEM BO of the given DRM device, representing the memory
338 * described by the given DMA-buf attachment and scatter/gather table.
339 */
340 static struct drm_gem_object *
amdgpu_dma_buf_create_obj(struct drm_device * dev,struct dma_buf * dma_buf)341 amdgpu_dma_buf_create_obj(struct drm_device *dev, struct dma_buf *dma_buf)
342 {
343 struct dma_resv *resv = dma_buf->resv;
344 struct amdgpu_device *adev = drm_to_adev(dev);
345 struct drm_gem_object *gobj;
346 struct amdgpu_bo *bo;
347 uint64_t flags = 0;
348 int ret;
349
350 dma_resv_lock(resv, NULL);
351
352 if (dma_buf->ops == &amdgpu_dmabuf_ops) {
353 struct amdgpu_bo *other = gem_to_amdgpu_bo(dma_buf->priv);
354
355 flags |= other->flags & (AMDGPU_GEM_CREATE_CPU_GTT_USWC |
356 AMDGPU_GEM_CREATE_COHERENT |
357 AMDGPU_GEM_CREATE_EXT_COHERENT |
358 AMDGPU_GEM_CREATE_UNCACHED);
359 }
360
361 ret = amdgpu_gem_object_create(adev, dma_buf->size, PAGE_SIZE,
362 AMDGPU_GEM_DOMAIN_CPU, flags,
363 ttm_bo_type_sg, resv, &gobj, 0);
364 if (ret)
365 goto error;
366
367 bo = gem_to_amdgpu_bo(gobj);
368 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
369 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
370
371 dma_resv_unlock(resv);
372 return gobj;
373
374 error:
375 dma_resv_unlock(resv);
376 return ERR_PTR(ret);
377 }
378
379 /**
380 * amdgpu_dma_buf_move_notify - &attach.move_notify implementation
381 *
382 * @attach: the DMA-buf attachment
383 *
384 * Invalidate the DMA-buf attachment, making sure that the we re-create the
385 * mapping before the next use.
386 */
387 static void
amdgpu_dma_buf_move_notify(struct dma_buf_attachment * attach)388 amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach)
389 {
390 struct drm_gem_object *obj = attach->importer_priv;
391 struct ww_acquire_ctx *ticket = dma_resv_locking_ctx(obj->resv);
392 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
393 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
394 struct ttm_operation_ctx ctx = { false, false };
395 struct ttm_placement placement = {};
396 struct amdgpu_vm_bo_base *bo_base;
397 int r;
398
399 /* FIXME: This should be after the "if", but needs a fix to make sure
400 * DMABuf imports are initialized in the right VM list.
401 */
402 amdgpu_vm_bo_invalidate(bo, false);
403 if (!bo->tbo.resource || bo->tbo.resource->mem_type == TTM_PL_SYSTEM)
404 return;
405
406 r = ttm_bo_validate(&bo->tbo, &placement, &ctx);
407 if (r) {
408 DRM_ERROR("Failed to invalidate DMA-buf import (%d))\n", r);
409 return;
410 }
411
412 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
413 struct amdgpu_vm *vm = bo_base->vm;
414 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
415
416 if (ticket) {
417 /* When we get an error here it means that somebody
418 * else is holding the VM lock and updating page tables
419 * So we can just continue here.
420 */
421 r = dma_resv_lock(resv, ticket);
422 if (r)
423 continue;
424
425 } else {
426 /* TODO: This is more problematic and we actually need
427 * to allow page tables updates without holding the
428 * lock.
429 */
430 if (!dma_resv_trylock(resv))
431 continue;
432 }
433
434 /* Reserve fences for two SDMA page table updates */
435 r = dma_resv_reserve_fences(resv, 2);
436 if (!r)
437 r = amdgpu_vm_clear_freed(adev, vm, NULL);
438 if (!r)
439 r = amdgpu_vm_handle_moved(adev, vm, ticket);
440
441 if (r && r != -EBUSY)
442 DRM_ERROR("Failed to invalidate VM page tables (%d))\n",
443 r);
444
445 dma_resv_unlock(resv);
446 }
447 }
448
449 static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops = {
450 .allow_peer2peer = true,
451 .move_notify = amdgpu_dma_buf_move_notify
452 };
453
454 /**
455 * amdgpu_gem_prime_import - &drm_driver.gem_prime_import implementation
456 * @dev: DRM device
457 * @dma_buf: Shared DMA buffer
458 *
459 * Import a dma_buf into a the driver and potentially create a new GEM object.
460 *
461 * Returns:
462 * GEM BO representing the shared DMA buffer for the given device.
463 */
amdgpu_gem_prime_import(struct drm_device * dev,struct dma_buf * dma_buf)464 struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev,
465 struct dma_buf *dma_buf)
466 {
467 struct dma_buf_attachment *attach;
468 struct drm_gem_object *obj;
469
470 if (dma_buf->ops == &amdgpu_dmabuf_ops) {
471 obj = dma_buf->priv;
472 if (obj->dev == dev) {
473 /*
474 * Importing dmabuf exported from out own gem increases
475 * refcount on gem itself instead of f_count of dmabuf.
476 */
477 drm_gem_object_get(obj);
478 return obj;
479 }
480 }
481
482 obj = amdgpu_dma_buf_create_obj(dev, dma_buf);
483 if (IS_ERR(obj))
484 return obj;
485
486 attach = dma_buf_dynamic_attach(dma_buf, dev->dev,
487 &amdgpu_dma_buf_attach_ops, obj);
488 if (IS_ERR(attach)) {
489 drm_gem_object_put(obj);
490 return ERR_CAST(attach);
491 }
492
493 get_dma_buf(dma_buf);
494 obj->import_attach = attach;
495 return obj;
496 }
497
498 /**
499 * amdgpu_dmabuf_is_xgmi_accessible - Check if xgmi available for P2P transfer
500 *
501 * @adev: amdgpu_device pointer of the importer
502 * @bo: amdgpu buffer object
503 *
504 * Returns:
505 * True if dmabuf accessible over xgmi, false otherwise.
506 */
amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device * adev,struct amdgpu_bo * bo)507 bool amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device *adev,
508 struct amdgpu_bo *bo)
509 {
510 struct drm_gem_object *obj = &bo->tbo.base;
511 struct drm_gem_object *gobj;
512
513 if (!adev)
514 return false;
515
516 if (obj->import_attach) {
517 struct dma_buf *dma_buf = obj->import_attach->dmabuf;
518
519 if (dma_buf->ops != &amdgpu_dmabuf_ops)
520 /* No XGMI with non AMD GPUs */
521 return false;
522
523 gobj = dma_buf->priv;
524 bo = gem_to_amdgpu_bo(gobj);
525 }
526
527 if (amdgpu_xgmi_same_hive(adev, amdgpu_ttm_adev(bo->tbo.bdev)) &&
528 (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM))
529 return true;
530
531 return false;
532 }
533