xref: /linux/drivers/gpu/drm/msm/dp/dp_panel.h (revision 2c1ed907520c50326b8f604907a8478b27881a2e)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
4  */
5 
6 #ifndef _DP_PANEL_H_
7 #define _DP_PANEL_H_
8 
9 #include <drm/msm_drm.h>
10 
11 #include "dp_aux.h"
12 #include "dp_link.h"
13 
14 struct edid;
15 
16 struct msm_dp_display_mode {
17 	struct drm_display_mode drm_mode;
18 	u32 bpp;
19 	u32 h_active_low;
20 	u32 v_active_low;
21 	bool out_fmt_is_yuv_420;
22 };
23 
24 struct msm_dp_panel_psr {
25 	u8 version;
26 	u8 capabilities;
27 };
28 
29 struct msm_dp_panel {
30 	/* dpcd raw data */
31 	u8 dpcd[DP_RECEIVER_CAP_SIZE];
32 	u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
33 
34 	struct msm_dp_link_info link_info;
35 	const struct drm_edid *drm_edid;
36 	struct drm_connector *connector;
37 	struct msm_dp_display_mode msm_dp_mode;
38 	struct msm_dp_panel_psr psr_cap;
39 	bool video_test;
40 	bool vsc_sdp_supported;
41 
42 	u32 max_dp_lanes;
43 	u32 max_dp_link_rate;
44 
45 	u32 max_bw_code;
46 };
47 
48 int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel);
49 int msm_dp_panel_deinit(struct msm_dp_panel *msm_dp_panel);
50 int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel);
51 int msm_dp_panel_read_sink_caps(struct msm_dp_panel *msm_dp_panel,
52 		struct drm_connector *connector);
53 u32 msm_dp_panel_get_mode_bpp(struct msm_dp_panel *msm_dp_panel, u32 mode_max_bpp,
54 			u32 mode_pclk_khz);
55 int msm_dp_panel_get_modes(struct msm_dp_panel *msm_dp_panel,
56 		struct drm_connector *connector);
57 void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel);
58 void msm_dp_panel_tpg_config(struct msm_dp_panel *msm_dp_panel, bool enable);
59 
60 /**
61  * is_link_rate_valid() - validates the link rate
62  * @lane_rate: link rate requested by the sink
63  *
64  * Returns true if the requested link rate is supported.
65  */
is_link_rate_valid(u32 bw_code)66 static inline bool is_link_rate_valid(u32 bw_code)
67 {
68 	return (bw_code == DP_LINK_BW_1_62 ||
69 		bw_code == DP_LINK_BW_2_7 ||
70 		bw_code == DP_LINK_BW_5_4 ||
71 		bw_code == DP_LINK_BW_8_1);
72 }
73 
74 /**
75  * msm_dp_link_is_lane_count_valid() - validates the lane count
76  * @lane_count: lane count requested by the sink
77  *
78  * Returns true if the requested lane count is supported.
79  */
is_lane_count_valid(u32 lane_count)80 static inline bool is_lane_count_valid(u32 lane_count)
81 {
82 	return (lane_count == 1 ||
83 		lane_count == 2 ||
84 		lane_count == 4);
85 }
86 
87 struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux,
88 			      struct msm_dp_link *link, struct msm_dp_catalog *catalog);
89 void msm_dp_panel_put(struct msm_dp_panel *msm_dp_panel);
90 #endif /* _DP_PANEL_H_ */
91