1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
4 */
5
6 #ifndef _DP_PANEL_H_
7 #define _DP_PANEL_H_
8
9 #include <drm/drm_modes.h>
10 #include <drm/msm_drm.h>
11
12 #include "dp_aux.h"
13 #include "dp_link.h"
14
15 struct edid;
16
17 struct msm_dp_display_mode {
18 struct drm_display_mode drm_mode;
19 u32 bpp;
20 u32 h_active_low;
21 u32 v_active_low;
22 bool out_fmt_is_yuv_420;
23 };
24
25 struct msm_dp_panel_psr {
26 u8 version;
27 u8 capabilities;
28 };
29
30 struct msm_dp_panel {
31 /* dpcd raw data */
32 u8 dpcd[DP_RECEIVER_CAP_SIZE];
33 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
34
35 struct msm_dp_link_info link_info;
36 const struct drm_edid *drm_edid;
37 struct drm_connector *connector;
38 struct msm_dp_display_mode msm_dp_mode;
39 struct msm_dp_panel_psr psr_cap;
40 bool video_test;
41 bool vsc_sdp_supported;
42 u32 hw_revision;
43
44 u32 max_bw_code;
45 };
46
47 int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel);
48 int msm_dp_panel_deinit(struct msm_dp_panel *msm_dp_panel);
49 int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en);
50 int msm_dp_panel_read_sink_caps(struct msm_dp_panel *msm_dp_panel,
51 struct drm_connector *connector);
52 u32 msm_dp_panel_get_mode_bpp(struct msm_dp_panel *msm_dp_panel, u32 mode_max_bpp,
53 u32 mode_pclk_khz);
54 int msm_dp_panel_get_modes(struct msm_dp_panel *msm_dp_panel,
55 struct drm_connector *connector);
56 void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel);
57 void msm_dp_panel_tpg_config(struct msm_dp_panel *msm_dp_panel, bool enable);
58
59 void msm_dp_panel_clear_dsc_dto(struct msm_dp_panel *msm_dp_panel);
60
61 void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *msm_dp_panel, struct dp_sdp *vsc_sdp);
62 void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel *msm_dp_panel);
63
64 /**
65 * is_link_rate_valid() - validates the link rate
66 * @lane_rate: link rate requested by the sink
67 *
68 * Returns true if the requested link rate is supported.
69 */
is_link_rate_valid(u32 bw_code)70 static inline bool is_link_rate_valid(u32 bw_code)
71 {
72 return (bw_code == DP_LINK_BW_1_62 ||
73 bw_code == DP_LINK_BW_2_7 ||
74 bw_code == DP_LINK_BW_5_4 ||
75 bw_code == DP_LINK_BW_8_1);
76 }
77
78 /**
79 * msm_dp_link_is_lane_count_valid() - validates the lane count
80 * @lane_count: lane count requested by the sink
81 *
82 * Returns true if the requested lane count is supported.
83 */
is_lane_count_valid(u32 lane_count)84 static inline bool is_lane_count_valid(u32 lane_count)
85 {
86 return (lane_count == 1 ||
87 lane_count == 2 ||
88 lane_count == 4);
89 }
90
91 struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux,
92 struct msm_dp_link *link,
93 void __iomem *link_base,
94 void __iomem *p0_base);
95 void msm_dp_panel_put(struct msm_dp_panel *msm_dp_panel);
96 #endif /* _DP_PANEL_H_ */
97