1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 #ifndef __DML2_CORE_UTILS_H__ 6 #define __DML2_CORE_UTILS_H__ 7 #include "dml2_internal_shared_types.h" 8 #include "dml2_debug.h" 9 #include "lib_float_math.h" 10 11 double dml2_core_utils_div_rem(double dividend, unsigned int divisor, unsigned int *remainder); 12 const char *dml2_core_utils_internal_bw_type_str(enum dml2_core_internal_bw_type bw_type); 13 bool dml2_core_utils_is_420(enum dml2_source_format_class source_format); 14 bool dml2_core_utils_is_422_planar(enum dml2_source_format_class source_format); 15 bool dml2_core_utils_is_422_packed(enum dml2_source_format_class source_format); 16 void dml2_core_utils_print_mode_support_info(const struct dml2_core_internal_mode_support_info *support, bool fail_only); 17 const char *dml2_core_utils_internal_soc_state_type_str(enum dml2_core_internal_soc_state_type dml2_core_internal_soc_state_type); 18 void dml2_core_utils_get_stream_output_bpp(double *out_bpp, const struct dml2_display_cfg *display_cfg); 19 unsigned int dml2_core_utils_round_to_multiple(unsigned int num, unsigned int multiple, bool up); 20 unsigned int dml2_core_util_get_num_active_pipes(int unsigned num_planes, const struct core_display_cfg_support_info *cfg_support_info); 21 void dml2_core_utils_pipe_plane_mapping(const struct core_display_cfg_support_info *cfg_support_info, unsigned int *pipe_plane); 22 bool dml2_core_utils_is_phantom_pipe(const struct dml2_plane_parameters *plane_cfg); 23 unsigned int dml2_core_utils_get_tile_block_size_bytes(enum dml2_swizzle_mode sw_mode, unsigned int byte_per_pixel); 24 bool dml2_core_utils_get_segment_horizontal_contiguous(enum dml2_swizzle_mode sw_mode, unsigned int byte_per_pixel); 25 bool dml2_core_utils_is_vertical_rotation(enum dml2_rotation_angle Scan); 26 bool dml2_core_utils_is_linear(enum dml2_swizzle_mode sw_mode); 27 int unsigned dml2_core_utils_get_gfx_version(enum dml2_swizzle_mode sw_mode); 28 unsigned int dml2_core_utils_get_qos_param_index(unsigned long uclk_freq_khz, const struct dml2_dcn4_uclk_dpm_dependent_qos_params *per_uclk_dpm_params); 29 unsigned int dml2_core_utils_get_active_min_uclk_dpm_index(unsigned long uclk_freq_khz, const struct dml2_soc_state_table *clk_table); 30 bool dml2_core_utils_is_dual_plane(enum dml2_source_format_class source_format); 31 unsigned int dml2_core_utils_log_and_substract_if_non_zero(unsigned int a, unsigned int subtrahend); 32 void dml2_core_utils_expand_implict_subvp(const struct display_configuation_with_meta *display_cfg, struct dml2_display_cfg *svp_expanded_display_cfg, 33 struct dml2_core_scratch *scratch); 34 bool dml2_core_utils_is_stream_encoder_required(const struct dml2_stream_parameters *stream_descriptor); 35 bool dml2_core_utils_is_encoder_dsc_capable(const struct dml2_stream_parameters *stream_descriptor); 36 bool dml2_core_utils_is_dp_encoder(const struct dml2_stream_parameters *stream_descriptor); 37 bool dml2_core_utils_is_dio_dp_encoder(const struct dml2_stream_parameters *stream_descriptor); 38 bool dml2_core_utils_is_hpo_dp_encoder(const struct dml2_stream_parameters *stream_descriptor); 39 bool dml2_core_utils_is_dp_8b_10b_link_rate(enum dml2_output_link_dp_rate rate); 40 bool dml2_core_utils_is_dp_128b_132b_link_rate(enum dml2_output_link_dp_rate rate); 41 bool dml2_core_utils_is_odm_split(enum dml2_odm_mode odm_mode); 42 double dml2_core_utils_get_frame_time_us(const struct dml2_stream_parameters *stream); 43 44 #endif /* __DML2_CORE_UTILS_H__ */ 45