1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_DMA_IF_W_S_DOWN_CH1_REGS_H_ 14 #define ASIC_REG_DMA_IF_W_S_DOWN_CH1_REGS_H_ 15 16 /* 17 ***************************************** 18 * DMA_IF_W_S_DOWN_CH1 (Prototype: RTR_CTRL) 19 ***************************************** 20 */ 21 22 #define mmDMA_IF_W_S_DOWN_CH1_PERM_SEL 0x482108 23 24 #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_0 0x482114 25 26 #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_1 0x482118 27 28 #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_2 0x48211C 29 30 #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_3 0x482120 31 32 #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_4 0x482124 33 34 #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_5 0x482128 35 36 #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_6 0x48212C 37 38 #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_7 0x482130 39 40 #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_8 0x482134 41 42 #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_9 0x482138 43 44 #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_10 0x48213C 45 46 #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_11 0x482140 47 48 #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_12 0x482144 49 50 #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_13 0x482148 51 52 #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_14 0x48214C 53 54 #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_15 0x482150 55 56 #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_16 0x482154 57 58 #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_17 0x482158 59 60 #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_18 0x48215C 61 62 #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_19 0x482160 63 64 #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_20 0x482164 65 66 #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_21 0x482168 67 68 #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_22 0x48216C 69 70 #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_23 0x482170 71 72 #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_24 0x482174 73 74 #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_25 0x482178 75 76 #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_26 0x48217C 77 78 #define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_27 0x482180 79 80 #define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_0 0x482184 81 82 #define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_1 0x482188 83 84 #define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_2 0x48218C 85 86 #define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_3 0x482190 87 88 #define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_4 0x482194 89 90 #define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_5 0x482198 91 92 #define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_6 0x48219C 93 94 #define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_7 0x4821A0 95 96 #define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_8 0x4821A4 97 98 #define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_9 0x4821A8 99 100 #define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_10 0x4821AC 101 102 #define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_11 0x4821B0 103 104 #define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_12 0x4821B4 105 106 #define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_13 0x4821B8 107 108 #define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_14 0x4821BC 109 110 #define mmDMA_IF_W_S_DOWN_CH1_SCRAM_SRAM_EN 0x48226C 111 112 #define mmDMA_IF_W_S_DOWN_CH1_RL_HBM_EN 0x482274 113 114 #define mmDMA_IF_W_S_DOWN_CH1_RL_HBM_SAT 0x482278 115 116 #define mmDMA_IF_W_S_DOWN_CH1_RL_HBM_RST 0x48227C 117 118 #define mmDMA_IF_W_S_DOWN_CH1_RL_HBM_TIMEOUT 0x482280 119 120 #define mmDMA_IF_W_S_DOWN_CH1_SCRAM_HBM_EN 0x482284 121 122 #define mmDMA_IF_W_S_DOWN_CH1_RL_PCI_EN 0x482288 123 124 #define mmDMA_IF_W_S_DOWN_CH1_RL_PCI_SAT 0x48228C 125 126 #define mmDMA_IF_W_S_DOWN_CH1_RL_PCI_RST 0x482290 127 128 #define mmDMA_IF_W_S_DOWN_CH1_RL_PCI_TIMEOUT 0x482294 129 130 #define mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_EN 0x48229C 131 132 #define mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_SAT 0x4822A0 133 134 #define mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_RST 0x4822A4 135 136 #define mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_TIMEOUT 0x4822AC 137 138 #define mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_RED 0x4822B4 139 140 #define mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_EN 0x4822EC 141 142 #define mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_EN 0x4822F0 143 144 #define mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_WR_SIZE 0x4822F4 145 146 #define mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_WR_SIZE 0x4822F8 147 148 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_PCI_CTR_SET_EN 0x482404 149 150 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_PCI_CTR_SET 0x482408 151 152 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_PCI_CTR_WRAP 0x48240C 153 154 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_PCI_CTR_CNT 0x482410 155 156 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM_CTR_SET_EN 0x482414 157 158 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM_CTR_SET 0x482418 159 160 #define mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_RD_SIZE 0x48241C 161 162 #define mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_RD_SIZE 0x482420 163 164 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_PCI_CTR_SET_EN 0x482424 165 166 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_PCI_CTR_SET 0x482428 167 168 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_PCI_CTR_WRAP 0x48242C 169 170 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_PCI_CTR_CNT 0x482430 171 172 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM_CTR_SET_EN 0x482434 173 174 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM_CTR_SET 0x482438 175 176 #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_SEL_0 0x482450 177 178 #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_SEL_1 0x482454 179 180 #define mmDMA_IF_W_S_DOWN_CH1_NON_LIN_EN 0x482480 181 182 #define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_BANK_0 0x482500 183 184 #define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_BANK_1 0x482504 185 186 #define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_BANK_2 0x482508 187 188 #define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_BANK_3 0x48250C 189 190 #define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_BANK_4 0x482510 191 192 #define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_0 0x482514 193 194 #define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_1 0x482520 195 196 #define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_2 0x482524 197 198 #define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_3 0x482528 199 200 #define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_4 0x48252C 201 202 #define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_5 0x482530 203 204 #define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_6 0x482534 205 206 #define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_7 0x482538 207 208 #define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_8 0x48253C 209 210 #define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_9 0x482540 211 212 #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_0 0x482550 213 214 #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_1 0x482554 215 216 #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_2 0x482558 217 218 #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_3 0x48255C 219 220 #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_4 0x482560 221 222 #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_5 0x482564 223 224 #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_6 0x482568 225 226 #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_7 0x48256C 227 228 #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_8 0x482570 229 230 #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_9 0x482574 231 232 #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_10 0x482578 233 234 #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_11 0x48257C 235 236 #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_12 0x482580 237 238 #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_13 0x482584 239 240 #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_14 0x482588 241 242 #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_15 0x48258C 243 244 #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_16 0x482590 245 246 #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_17 0x482594 247 248 #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_18 0x482598 249 250 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0 0x4825E4 251 252 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_1 0x4825E8 253 254 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_2 0x4825EC 255 256 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_3 0x4825F0 257 258 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_4 0x4825F4 259 260 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_5 0x4825F8 261 262 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_6 0x4825FC 263 264 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_7 0x482600 265 266 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_8 0x482604 267 268 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_9 0x482608 269 270 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_10 0x48260C 271 272 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_11 0x482610 273 274 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_12 0x482614 275 276 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_13 0x482618 277 278 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_14 0x48261C 279 280 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_15 0x482620 281 282 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0 0x482624 283 284 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_1 0x482628 285 286 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_2 0x48262C 287 288 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_3 0x482630 289 290 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_4 0x482634 291 292 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_5 0x482638 293 294 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_6 0x48263C 295 296 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_7 0x482640 297 298 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_8 0x482644 299 300 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_9 0x482648 301 302 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_10 0x48264C 303 304 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_11 0x482650 305 306 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_12 0x482654 307 308 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_13 0x482658 309 310 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_14 0x48265C 311 312 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_15 0x482660 313 314 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0 0x482664 315 316 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_1 0x482668 317 318 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_2 0x48266C 319 320 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_3 0x482670 321 322 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_4 0x482674 323 324 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_5 0x482678 325 326 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_6 0x48267C 327 328 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_7 0x482680 329 330 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_8 0x482684 331 332 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_9 0x482688 333 334 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_10 0x48268C 335 336 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_11 0x482690 337 338 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_12 0x482694 339 340 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_13 0x482698 341 342 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_14 0x48269C 343 344 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_15 0x4826A0 345 346 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0 0x4826A4 347 348 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_1 0x4826A8 349 350 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_2 0x4826AC 351 352 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_3 0x4826B0 353 354 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_4 0x4826B4 355 356 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_5 0x4826B8 357 358 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_6 0x4826BC 359 360 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_7 0x4826C0 361 362 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_8 0x4826C4 363 364 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_9 0x4826C8 365 366 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_10 0x4826CC 367 368 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_11 0x4826D0 369 370 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_12 0x4826D4 371 372 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_13 0x4826D8 373 374 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_14 0x4826DC 375 376 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_15 0x4826E0 377 378 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_0 0x4826E4 379 380 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_1 0x4826E8 381 382 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_2 0x4826EC 383 384 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_3 0x4826F0 385 386 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_4 0x4826F4 387 388 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_5 0x4826F8 389 390 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_6 0x4826FC 391 392 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_7 0x482700 393 394 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_8 0x482704 395 396 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_9 0x482708 397 398 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_10 0x48270C 399 400 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_11 0x482710 401 402 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_12 0x482714 403 404 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_13 0x482718 405 406 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_14 0x48271C 407 408 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_15 0x482720 409 410 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_0 0x482724 411 412 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_1 0x482728 413 414 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_2 0x48272C 415 416 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_3 0x482730 417 418 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_4 0x482734 419 420 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_5 0x482738 421 422 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_6 0x48273C 423 424 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_7 0x482740 425 426 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_8 0x482744 427 428 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_9 0x482748 429 430 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_10 0x48274C 431 432 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_11 0x482750 433 434 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_12 0x482754 435 436 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_13 0x482758 437 438 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_14 0x48275C 439 440 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_15 0x482760 441 442 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_0 0x482764 443 444 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_1 0x482768 445 446 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_2 0x48276C 447 448 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_3 0x482770 449 450 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_4 0x482774 451 452 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_5 0x482778 453 454 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_6 0x48277C 455 456 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_7 0x482780 457 458 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_8 0x482784 459 460 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_9 0x482788 461 462 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_10 0x48278C 463 464 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_11 0x482790 465 466 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_12 0x482794 467 468 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_13 0x482798 469 470 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_14 0x48279C 471 472 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_15 0x4827A0 473 474 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_0 0x4827A4 475 476 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_1 0x4827A8 477 478 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_2 0x4827AC 479 480 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_3 0x4827B0 481 482 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_4 0x4827B4 483 484 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_5 0x4827B8 485 486 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_6 0x4827BC 487 488 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_7 0x4827C0 489 490 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_8 0x4827C4 491 492 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_9 0x4827C8 493 494 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_10 0x4827CC 495 496 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_11 0x4827D0 497 498 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_12 0x4827D4 499 500 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_13 0x4827D8 501 502 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_14 0x4827DC 503 504 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_15 0x4827E0 505 506 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0 0x482824 507 508 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_1 0x482828 509 510 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_2 0x48282C 511 512 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_3 0x482830 513 514 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_4 0x482834 515 516 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_5 0x482838 517 518 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_6 0x48283C 519 520 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_7 0x482840 521 522 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_8 0x482844 523 524 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_9 0x482848 525 526 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_10 0x48284C 527 528 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_11 0x482850 529 530 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_12 0x482854 531 532 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_13 0x482858 533 534 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_14 0x48285C 535 536 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_15 0x482860 537 538 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0 0x482864 539 540 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_1 0x482868 541 542 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_2 0x48286C 543 544 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_3 0x482870 545 546 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_4 0x482874 547 548 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_5 0x482878 549 550 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_6 0x48287C 551 552 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_7 0x482880 553 554 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_8 0x482884 555 556 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_9 0x482888 557 558 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_10 0x48288C 559 560 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_11 0x482890 561 562 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_12 0x482894 563 564 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_13 0x482898 565 566 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_14 0x48289C 567 568 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_15 0x4828A0 569 570 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0 0x4828A4 571 572 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_1 0x4828A8 573 574 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_2 0x4828AC 575 576 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_3 0x4828B0 577 578 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_4 0x4828B4 579 580 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_5 0x4828B8 581 582 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_6 0x4828BC 583 584 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_7 0x4828C0 585 586 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_8 0x4828C4 587 588 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_9 0x4828C8 589 590 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_10 0x4828CC 591 592 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_11 0x4828D0 593 594 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_12 0x4828D4 595 596 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_13 0x4828D8 597 598 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_14 0x4828DC 599 600 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_15 0x4828E0 601 602 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0 0x4828E4 603 604 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_1 0x4828E8 605 606 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_2 0x4828EC 607 608 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_3 0x4828F0 609 610 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_4 0x4828F4 611 612 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_5 0x4828F8 613 614 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_6 0x4828FC 615 616 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_7 0x482900 617 618 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_8 0x482904 619 620 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_9 0x482908 621 622 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_10 0x48290C 623 624 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_11 0x482910 625 626 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_12 0x482914 627 628 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_13 0x482918 629 630 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_14 0x48291C 631 632 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_15 0x482920 633 634 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_0 0x482924 635 636 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_1 0x482928 637 638 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_2 0x48292C 639 640 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_3 0x482930 641 642 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_4 0x482934 643 644 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_5 0x482938 645 646 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_6 0x48293C 647 648 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_7 0x482940 649 650 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_8 0x482944 651 652 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_9 0x482948 653 654 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_10 0x48294C 655 656 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_11 0x482950 657 658 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_12 0x482954 659 660 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_13 0x482958 661 662 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_14 0x48295C 663 664 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_15 0x482960 665 666 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_0 0x482964 667 668 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_1 0x482968 669 670 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_2 0x48296C 671 672 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_3 0x482970 673 674 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_4 0x482974 675 676 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_5 0x482978 677 678 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_6 0x48297C 679 680 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_7 0x482980 681 682 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_8 0x482984 683 684 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_9 0x482988 685 686 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_10 0x48298C 687 688 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_11 0x482990 689 690 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_12 0x482994 691 692 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_13 0x482998 693 694 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_14 0x48299C 695 696 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_15 0x4829A0 697 698 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_0 0x4829A4 699 700 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_1 0x4829A8 701 702 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_2 0x4829AC 703 704 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_3 0x4829B0 705 706 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_4 0x4829B4 707 708 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_5 0x4829B8 709 710 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_6 0x4829BC 711 712 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_7 0x4829C0 713 714 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_8 0x4829C4 715 716 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_9 0x4829C8 717 718 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_10 0x4829CC 719 720 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_11 0x4829D0 721 722 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_12 0x4829D4 723 724 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_13 0x4829D8 725 726 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_14 0x4829DC 727 728 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_15 0x4829E0 729 730 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_0 0x4829E4 731 732 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_1 0x4829E8 733 734 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_2 0x4829EC 735 736 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_3 0x4829F0 737 738 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_4 0x4829F4 739 740 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_5 0x4829F8 741 742 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_6 0x4829FC 743 744 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_7 0x482A00 745 746 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_8 0x482A04 747 748 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_9 0x482A08 749 750 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_10 0x482A0C 751 752 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_11 0x482A10 753 754 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_12 0x482A14 755 756 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_13 0x482A18 757 758 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_14 0x482A1C 759 760 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_15 0x482A20 761 762 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_HIT_AW 0x482A64 763 764 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_HIT_AR 0x482A68 765 766 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_HIT_AW 0x482A6C 767 768 #define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_HIT_AR 0x482A70 769 770 #define mmDMA_IF_W_S_DOWN_CH1_RGL_CFG 0x482B64 771 772 #define mmDMA_IF_W_S_DOWN_CH1_RGL_SHIFT 0x482B68 773 774 #define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_0 0x482B6C 775 776 #define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_1 0x482B70 777 778 #define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_2 0x482B74 779 780 #define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_3 0x482B78 781 782 #define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_4 0x482B7C 783 784 #define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_5 0x482B80 785 786 #define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_6 0x482B84 787 788 #define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_7 0x482B88 789 790 #define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_0 0x482BAC 791 792 #define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_1 0x482BB0 793 794 #define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_2 0x482BB4 795 796 #define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_3 0x482BB8 797 798 #define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_4 0x482BBC 799 800 #define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_5 0x482BC0 801 802 #define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_6 0x482BC4 803 804 #define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_7 0x482BC8 805 806 #define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_0 0x482BEC 807 808 #define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_1 0x482BF0 809 810 #define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_2 0x482BF4 811 812 #define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_3 0x482BF8 813 814 #define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_4 0x482BFC 815 816 #define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_5 0x482C00 817 818 #define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_6 0x482C04 819 820 #define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_7 0x482C08 821 822 #define mmDMA_IF_W_S_DOWN_CH1_RGL_WDT 0x482C2C 823 824 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_WRAP 0x482C30 825 826 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_WRAP 0x482C34 827 828 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_WRAP 0x482C38 829 830 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_WRAP 0x482C3C 831 832 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_WRAP 0x482C40 833 834 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_WRAP 0x482C44 835 836 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_WRAP 0x482C48 837 838 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_WRAP 0x482C4C 839 840 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_CNT 0x482C50 841 842 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_CNT 0x482C54 843 844 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_CNT 0x482C58 845 846 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_CNT 0x482C5C 847 848 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_CNT 0x482C60 849 850 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_CNT 0x482C64 851 852 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_CNT 0x482C68 853 854 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_CNT 0x482C6C 855 856 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_WRAP 0x482C70 857 858 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_WRAP 0x482C74 859 860 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_WRAP 0x482C78 861 862 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_WRAP 0x482C7C 863 864 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_WRAP 0x482C80 865 866 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_WRAP 0x482C84 867 868 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_WRAP 0x482C88 869 870 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_WRAP 0x482C8C 871 872 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_CNT 0x482C90 873 874 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_CNT 0x482C94 875 876 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_CNT 0x482C98 877 878 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_CNT 0x482C9C 879 880 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_CNT 0x482CA0 881 882 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_CNT 0x482CA4 883 884 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_CNT 0x482CA8 885 886 #define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_CNT 0x482CAC 887 888 #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_PC_SEL_0 0x482CB0 889 890 #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_PC_SEL_1 0x482CB4 891 892 #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_PC_SEL_2 0x482CB8 893 894 #define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_PC_SEL_3 0x482CBC 895 896 #endif /* ASIC_REG_DMA_IF_W_S_DOWN_CH1_REGS_H_ */ 897