1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 #ifndef __DC_HWSS_DCN401_H__ 6 #define __DC_HWSS_DCN401_H__ 7 8 #include "inc/core_types.h" 9 #include "dc.h" 10 #include "dc_stream.h" 11 #include "hw_sequencer_private.h" 12 #include "dcn401/dcn401_dccg.h" 13 14 struct dc; 15 16 enum ips_ono_state { 17 ONO_ON = 0, 18 ONO_ON_IN_PROGRESS = 1, 19 ONO_OFF = 2, 20 ONO_OFF_IN_PROGRESS = 3 21 }; 22 23 struct ips_ono_region_state { 24 /** 25 * @desire_pwr_state: desired power state based on configured value 26 */ 27 uint32_t desire_pwr_state; 28 /** 29 * @current_pwr_state: current power gate status 30 */ 31 uint32_t current_pwr_state; 32 }; 33 34 void dcn401_program_gamut_remap(struct pipe_ctx *pipe_ctx); 35 36 void dcn401_init_hw(struct dc *dc); 37 38 bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx, 39 const struct dc_plane_state *plane_state); 40 bool dcn401_set_output_transfer_func(struct dc *dc, 41 struct pipe_ctx *pipe_ctx, 42 const struct dc_stream_state *stream); 43 void dcn401_trigger_3dlut_dma_load(struct dc *dc, 44 struct pipe_ctx *pipe_ctx); 45 void dcn401_calculate_dccg_tmds_div_value(struct pipe_ctx *pipe_ctx, 46 unsigned int *tmds_div); 47 enum dc_status dcn401_enable_stream_timing( 48 struct pipe_ctx *pipe_ctx, 49 struct dc_state *context, 50 struct dc *dc); 51 void dcn401_enable_stream(struct pipe_ctx *pipe_ctx); 52 void dcn401_populate_mcm_luts(struct dc *dc, 53 struct pipe_ctx *pipe_ctx, 54 struct dc_cm2_func_luts mcm_luts, 55 bool lut_bank_a); 56 void dcn401_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable); 57 58 void dcn401_disable_link_output(struct dc_link *link, 59 const struct link_resource *link_res, 60 enum signal_type signal); 61 62 void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx); 63 64 bool dcn401_apply_idle_power_optimizations(struct dc *dc, bool enable); 65 66 void dcn401_wait_for_dcc_meta_propagation(const struct dc *dc, 67 const struct pipe_ctx *top_pipe_to_program); 68 69 void dcn401_prepare_bandwidth(struct dc *dc, 70 struct dc_state *context); 71 72 void dcn401_optimize_bandwidth( 73 struct dc *dc, 74 struct dc_state *context); 75 76 void dcn401_fams2_global_control_lock(struct dc *dc, 77 struct dc_state *context, 78 bool lock); 79 void dcn401_fams2_update_config(struct dc *dc, struct dc_state *context, bool enable); 80 void dcn401_fams2_global_control_lock_fast(union block_sequence_params *params); 81 void dcn401_unblank_stream(struct pipe_ctx *pipe_ctx, struct dc_link_settings *link_settings); 82 void dcn401_hardware_release(struct dc *dc); 83 void dcn401_update_odm(struct dc *dc, struct dc_state *context, 84 struct pipe_ctx *otg_master); 85 void adjust_hotspot_between_slices_for_2x_magnify(uint32_t cursor_width, struct dc_cursor_position *pos_cpy); 86 void dcn401_wait_for_det_buffer_update_under_otg_master(struct dc *dc, struct dc_state *context, struct pipe_ctx *otg_master); 87 void dcn401_interdependent_update_lock(struct dc *dc, struct dc_state *context, bool lock); 88 void dcn401_program_outstanding_updates(struct dc *dc, struct dc_state *context); 89 void dcn401_reset_back_end_for_pipe( 90 struct dc *dc, 91 struct pipe_ctx *pipe_ctx, 92 struct dc_state *context); 93 void dcn401_reset_hw_ctx_wrap( 94 struct dc *dc, 95 struct dc_state *context); 96 void dcn401_perform_3dlut_wa_unlock(struct pipe_ctx *pipe_ctx); 97 void dcn401_program_front_end_for_ctx(struct dc *dc, struct dc_state *context); 98 void dcn401_post_unlock_program_front_end(struct dc *dc, struct dc_state *context); 99 bool dcn401_update_bandwidth(struct dc *dc, struct dc_state *context); 100 void dcn401_detect_pipe_changes( 101 struct dc_state *old_state, 102 struct dc_state *new_state, 103 struct pipe_ctx *old_pipe, 104 struct pipe_ctx *new_pipe); 105 #endif /* __DC_HWSS_DCN401_H__ */ 106