1 /* SPDX-License-Identifier: MIT */
2 /* Copyright 2025 Advanced Micro Devices, Inc. */
3
4 #include "dm_services.h"
5 #include "dc.h"
6
7 #include "dcn31/dcn31_init.h"
8 #include "dcn35/dcn35_init.h"
9 #include "dcn36/dcn36_resource.h"
10
11 #include "resource.h"
12 #include "include/irq_service_interface.h"
13 #include "basics/conversion.h"
14 #include "dcn36_resource.h"
15 #include "dml2_0/dml2_wrapper.h"
16
17 #include "dcn20/dcn20_resource.h"
18 #include "dcn30/dcn30_resource.h"
19 #include "dcn31/dcn31_resource.h"
20 #include "dcn32/dcn32_resource.h"
21 #include "dcn35/dcn35_resource.h"
22
23 #include "dcn10/dcn10_ipp.h"
24 #include "dcn30/dcn30_hubbub.h"
25 #include "dcn31/dcn31_hubbub.h"
26 #include "dcn35/dcn35_hubbub.h"
27 #include "dcn32/dcn32_mpc.h"
28 #include "dcn35/dcn35_hubp.h"
29 #include "irq/dcn36/irq_service_dcn36.h"
30 #include "dcn35/dcn35_dpp.h"
31 #include "dcn35/dcn35_optc.h"
32 #include "dcn20/dcn20_hwseq.h"
33 #include "dcn30/dcn30_hwseq.h"
34 #include "dce110/dce110_hwseq.h"
35 #include "dcn35/dcn35_opp.h"
36 #include "dcn35/dcn35_dsc.h"
37 #include "dcn30/dcn30_vpg.h"
38 #include "dcn30/dcn30_afmt.h"
39 #include "dcn31/dcn31_dio_link_encoder.h"
40 #include "dcn35/dcn35_dio_stream_encoder.h"
41 #include "dcn30/dcn30_hpo_frl_stream_encoder.h"
42 #include "dcn30/dcn30_hpo_frl_link_encoder.h"
43 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
44 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
45 #include "dcn32/dcn32_hpo_dp_link_encoder.h"
46 #include "link_service.h"
47 #include "dcn31/dcn31_apg.h"
48 #include "dcn32/dcn32_dio_link_encoder.h"
49 #include "dcn31/dcn31_vpg.h"
50 #include "dcn31/dcn31_afmt.h"
51 #include "dce/dce_clock_source.h"
52 #include "dce/dce_audio.h"
53 #include "dce/dce_hwseq.h"
54 #include "clk_mgr.h"
55 #include "dio/virtual/virtual_stream_encoder.h"
56 #include "dio/dcn10/dcn10_dio.h"
57 #include "dce110/dce110_resource.h"
58 #include "dml/display_mode_vba.h"
59 #include "dcn35/dcn35_dccg.h"
60 #include "dcn35/dcn35_pg_cntl.h"
61 #include "dcn10/dcn10_resource.h"
62 #include "dcn31/dcn31_panel_cntl.h"
63 #include "dcn35/dcn35_hwseq.h"
64 #include "dcn35/dcn35_dio_link_encoder.h"
65 #include "dml/dcn31/dcn31_fpu.h" /*todo*/
66 #include "dml/dcn35/dcn35_fpu.h"
67 #include "dcn35/dcn35_dwb.h"
68 #include "dcn35/dcn35_mmhubbub.h"
69
70 #include "dcn/dcn_3_6_0_offset.h"
71 #include "dcn/dcn_3_6_0_sh_mask.h"
72
73 #define regBIF_BX2_BIOS_SCRATCH_2 0x2ffc004e
74 #define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX 5
75
76 #define regBIF_BX2_BIOS_SCRATCH_3 0x2ffc004f
77 #define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX 5
78
79 #define regBIF_BX2_BIOS_SCRATCH_6 0x2ffc0052
80 #define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX 5
81
82 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0
83 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL
84
85 #include "reg_helper.h"
86 #include "dce/dmub_abm.h"
87 #include "dce/dmub_psr.h"
88 #include "dce/dmub_replay.h"
89 #include "dce/dce_aux.h"
90 #include "dce/dce_i2c.h"
91 #include "dml/dcn31/display_mode_vba_31.h" /*temp*/
92 #include "vm_helper.h"
93 #include "dcn20/dcn20_vmid.h"
94
95 #include "dc_state_priv.h"
96
97 #include "link_enc_cfg.h"
98 #define DC_LOGGER_INIT(logger)
99
100 enum dcn36_clk_src_array_id {
101 DCN36_CLK_SRC_PLL0,
102 DCN36_CLK_SRC_PLL1,
103 DCN36_CLK_SRC_PLL2,
104 DCN36_CLK_SRC_PLL3,
105 DCN36_CLK_SRC_PLL4,
106 DCN36_CLK_SRC_TOTAL
107 };
108
109 /* begin *********************
110 * macros to expend register list macro defined in HW object header file
111 */
112
113 /* DCN */
114 /* TODO awful hack. fixup dcn20_dwb.h */
115 #undef BASE_INNER
116 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
117
118 #define BASE(seg) BASE_INNER(seg)
119
120 #define SR(reg_name)\
121 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
122 reg ## reg_name
123
124 #define SR_ARR(reg_name, id) \
125 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
126
127 #define SR_ARR_INIT(reg_name, id, value) \
128 REG_STRUCT[id].reg_name = value
129
130 #define SRI(reg_name, block, id)\
131 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
132 reg ## block ## id ## _ ## reg_name
133
134 #define SRI_ARR(reg_name, block, id)\
135 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
136 reg ## block ## id ## _ ## reg_name
137
138 #define SR_ARR_I2C(reg_name, id) \
139 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
140
141 #define SRI_ARR_I2C(reg_name, block, id)\
142 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
143 reg ## block ## id ## _ ## reg_name
144
145 #define SRI_ARR_DME(reg_name, block, id, offset)\
146 REG_STRUCT[id - offset].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
147 reg ## block ## id ## _ ## reg_name
148
149 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\
150 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
151 reg ## block ## id ## _ ## reg_name
152
153 #define SRI2(reg_name, block, id)\
154 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
155 reg ## reg_name
156
157 #define SRI2_ARR(reg_name, block, id)\
158 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
159 reg ## reg_name
160
161 #define SRIR(var_name, reg_name, block, id)\
162 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
163 reg ## block ## id ## _ ## reg_name
164
165 #define SRII(reg_name, block, id)\
166 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
167 reg ## block ## id ## _ ## reg_name
168
169 #define SRII_ARR_2(reg_name, block, id, inst)\
170 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
171 reg ## block ## id ## _ ## reg_name
172
173 #define SRII_MPC_RMU(reg_name, block, id)\
174 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
175 reg ## block ## id ## _ ## reg_name
176
177 #define SRII_DWB(reg_name, temp_name, block, id)\
178 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
179 reg ## block ## id ## _ ## temp_name
180
181 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
182 .field_name = reg_name ## __ ## field_name ## post_fix
183
184 #define DCCG_SRII(reg_name, block, id)\
185 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
186 reg ## block ## id ## _ ## reg_name
187
188 #define VUPDATE_SRII(reg_name, block, id)\
189 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
190 reg ## reg_name ## _ ## block ## id
191
192 /* NBIO */
193 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
194
195 #define NBIO_BASE(seg) \
196 NBIO_BASE_INNER(seg)
197
198 #define NBIO_SR(reg_name)\
199 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
200 regBIF_BX2_ ## reg_name
201
202 #define NBIO_SR_ARR(reg_name, id)\
203 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
204 regBIF_BX2_ ## reg_name
205
206 #define bios_regs_init() \
207 ( \
208 NBIO_SR(BIOS_SCRATCH_3),\
209 NBIO_SR(BIOS_SCRATCH_6)\
210 )
211
212 static struct bios_registers bios_regs;
213
214 #define clk_src_regs_init(index, pllid)\
215 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)
216
217 static struct dce110_clk_src_regs clk_src_regs[5];
218
219 static const struct dce110_clk_src_shift cs_shift = {
220 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT)
221 };
222
223 static const struct dce110_clk_src_mask cs_mask = {
224 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK)
225 };
226
227 #define abm_regs_init(id)\
228 ABM_DCN32_REG_LIST_RI(id)
229
230 static struct dce_abm_registers abm_regs[4];
231
232 static const struct dce_abm_shift abm_shift = {
233 ABM_MASK_SH_LIST_DCN35(__SHIFT)
234 };
235
236 static const struct dce_abm_mask abm_mask = {
237 ABM_MASK_SH_LIST_DCN35(_MASK)
238 };
239
240 #define audio_regs_init(id)\
241 AUD_COMMON_REG_LIST_RI(id)
242
243 static struct dce_audio_registers audio_regs[7];
244
245
246 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
247 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
248 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
249 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
250
251 static const struct dce_audio_shift audio_shift = {
252 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
253 };
254
255 static const struct dce_audio_mask audio_mask = {
256 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
257 };
258
259 #define vpg_regs_init(id)\
260 VPG_DCN31_REG_LIST_RI(id)
261
262 static struct dcn31_vpg_registers vpg_regs[10];
263
264 static const struct dcn31_vpg_shift vpg_shift = {
265 DCN31_VPG_MASK_SH_LIST(__SHIFT)
266 };
267
268 static const struct dcn31_vpg_mask vpg_mask = {
269 DCN31_VPG_MASK_SH_LIST(_MASK)
270 };
271
272 #define afmt_regs_init(id)\
273 AFMT_DCN31_REG_LIST_RI(id)
274
275 static struct dcn31_afmt_registers afmt_regs[6];
276
277 static const struct dcn31_afmt_shift afmt_shift = {
278 DCN31_AFMT_MASK_SH_LIST(__SHIFT)
279 };
280
281 static const struct dcn31_afmt_mask afmt_mask = {
282 DCN31_AFMT_MASK_SH_LIST(_MASK)
283 };
284
285 #define apg_regs_init(id)\
286 APG_DCN31_REG_LIST_RI(id)
287
288 static struct dcn31_apg_registers apg_regs[4];
289
290 static const struct dcn31_apg_shift apg_shift = {
291 DCN31_APG_MASK_SH_LIST(__SHIFT)
292 };
293
294 static const struct dcn31_apg_mask apg_mask = {
295 DCN31_APG_MASK_SH_LIST(_MASK)
296 };
297
298 #define stream_enc_regs_init(id)\
299 SE_DCN35_REG_LIST_RI(id)
300
301 static struct dcn10_stream_enc_registers stream_enc_regs[5];
302
303 static const struct dcn10_stream_encoder_shift se_shift = {
304 SE_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
305 };
306
307 static const struct dcn10_stream_encoder_mask se_mask = {
308 SE_COMMON_MASK_SH_LIST_DCN35(_MASK)
309 };
310
311 #define aux_regs_init(id)\
312 DCN2_AUX_REG_LIST_RI(id)
313
314 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];
315
316 #define hpd_regs_init(id)\
317 HPD_REG_LIST_RI(id)
318
319 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];
320
321
322 static const struct dce110_aux_registers_shift aux_shift = {
323 DCN_AUX_MASK_SH_LIST(__SHIFT)
324 };
325
326 static const struct dce110_aux_registers_mask aux_mask = {
327 DCN_AUX_MASK_SH_LIST(_MASK)
328 };
329
330 #define link_regs_init(id, phyid)\
331 ( \
332 LE_DCN35_REG_LIST_RI(id), \
333 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\
334 )
335
336 static struct dcn10_link_enc_registers link_enc_regs[5];
337
338 static const struct dcn10_link_enc_shift le_shift = {
339 LINK_ENCODER_MASK_SH_LIST_DCN35(__SHIFT), \
340 //DPCS_DCN31_MASK_SH_LIST(__SHIFT)
341 };
342
343 static const struct dcn10_link_enc_mask le_mask = {
344 LINK_ENCODER_MASK_SH_LIST_DCN35(_MASK), \
345 //DPCS_DCN31_MASK_SH_LIST(_MASK)
346 };
347
348 #define hpo_frl_stream_encoder_dme_reg_list(id)\
349 DCN3_0_HPO_STREAM_ENC_DME_REG_LIST_RI(id, 6)
350
351 #define hpo_frl_stream_encoder_reg_list(id)\
352 DCN3_0_HPO_FRL_STREAM_ENC_REG_LIST_RI(id)
353
354 static struct dcn30_hpo_frl_stream_enc_registers hpo_frl_stream_enc_regs[2];
355
356 static const struct dcn30_hpo_frl_stream_encoder_shift hpo_se_shift = {
357 DCN3_0_HPO_STREAM_ENC_MASK_SH_LIST(__SHIFT)
358 };
359
360 static const struct dcn30_hpo_frl_stream_encoder_mask hpo_se_mask = {
361 DCN3_0_HPO_STREAM_ENC_MASK_SH_LIST(_MASK)
362 };
363
364 #define hpo_frl_link_encoder_reg_list(id)\
365 DCN3_0_HPO_FRL_LINK_ENC_REG_LIST_RI(id)
366
367 static struct dcn30_hpo_frl_link_encoder_registers hpo_frl_link_enc_regs[1];
368
369 static const struct dcn30_hpo_frl_link_encoder_shift hpo_le_shift = {
370 DCN3_0_HPO_FRL_LINK_ENC_MASK_SH_LIST(__SHIFT)
371 };
372
373 static const struct dcn30_hpo_frl_link_encoder_mask hpo_le_mask = {
374 DCN3_0_HPO_FRL_LINK_ENC_MASK_SH_LIST(_MASK)
375 };
376
377 #define hpo_dp_stream_encoder_reg_init(id)\
378 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
379
380 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];
381
382 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
383 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
384 };
385
386 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
387 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
388 };
389
390 #define hpo_dp_link_encoder_reg_init(id)\
391 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)
392
393 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2];
394
395 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
396 DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(__SHIFT)
397 };
398
399 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
400 DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(_MASK)
401 };
402
403 #define dpp_regs_init(id)\
404 DPP_REG_LIST_DCN35_RI(id)
405
406 static struct dcn3_dpp_registers dpp_regs[4];
407
408 static const struct dcn35_dpp_shift tf_shift = {
409 DPP_REG_LIST_SH_MASK_DCN35(__SHIFT)
410 };
411
412 static const struct dcn35_dpp_mask tf_mask = {
413 DPP_REG_LIST_SH_MASK_DCN35(_MASK)
414 };
415
416 #define opp_regs_init(id)\
417 OPP_REG_LIST_DCN35_RI(id)
418
419 static struct dcn35_opp_registers opp_regs[4];
420
421 static const struct dcn35_opp_shift opp_shift = {
422 OPP_MASK_SH_LIST_DCN35(__SHIFT)
423 };
424
425 static const struct dcn35_opp_mask opp_mask = {
426 OPP_MASK_SH_LIST_DCN35(_MASK)
427 };
428
429 #define aux_engine_regs_init(id)\
430 ( \
431 AUX_COMMON_REG_LIST0_RI(id), \
432 SR_ARR_INIT(AUXN_IMPCAL, id, 0), \
433 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \
434 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK) \
435 )
436
437 static struct dce110_aux_registers aux_engine_regs[5];
438
439 #define dwbc_regs_dcn3_init(id)\
440 DWBC_COMMON_REG_LIST_DCN30_RI(id)
441
442 static struct dcn30_dwbc_registers dwbc35_regs[1];
443
444 static const struct dcn35_dwbc_shift dwbc35_shift = {
445 DWBC_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
446 };
447
448 static const struct dcn35_dwbc_mask dwbc35_mask = {
449 DWBC_COMMON_MASK_SH_LIST_DCN35(_MASK)
450 };
451
452 #define mcif_wb_regs_dcn3_init(id)\
453 MCIF_WB_COMMON_REG_LIST_DCN3_5_RI(id)
454
455 static struct dcn35_mmhubbub_registers mcif_wb35_regs[1];
456
457 static const struct dcn35_mmhubbub_shift mcif_wb35_shift = {
458 MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)
459 };
460
461 static const struct dcn35_mmhubbub_mask mcif_wb35_mask = {
462 MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(_MASK)
463 };
464
465 #define dsc_regsDCN35_init(id)\
466 DSC_REG_LIST_DCN20_RI(id)
467
468 static struct dcn20_dsc_registers dsc_regs[4];
469
470 static const struct dcn35_dsc_shift dsc_shift = {
471 DSC_REG_LIST_SH_MASK_DCN35(__SHIFT)
472 };
473
474 static const struct dcn35_dsc_mask dsc_mask = {
475 DSC_REG_LIST_SH_MASK_DCN35(_MASK)
476 };
477
478 static struct dcn30_mpc_registers mpc_regs;
479
480 #define dcn_mpc_regs_init() \
481 MPC_REG_LIST_DCN3_2_RI(0),\
482 MPC_REG_LIST_DCN3_2_RI(1),\
483 MPC_REG_LIST_DCN3_2_RI(2),\
484 MPC_REG_LIST_DCN3_2_RI(3),\
485 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
486 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
487 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
488 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
489 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)
490
491 static const struct dcn30_mpc_shift mpc_shift = {
492 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
493 };
494
495 static const struct dcn30_mpc_mask mpc_mask = {
496 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)
497 };
498
499 #define optc_regs_init(id)\
500 OPTC_COMMON_REG_LIST_DCN3_5_RI(id),\
501 SRI_ARR(OTG_CRC0_DATA_R32, OTG_CRC32, id),\
502 SRI_ARR(OTG_CRC0_DATA_G32, OTG_CRC32, id),\
503 SRI_ARR(OTG_CRC0_DATA_B32, OTG_CRC32, id),\
504 SRI_ARR(OTG_CRC1_DATA_R32, OTG_CRC32, id),\
505 SRI_ARR(OTG_CRC1_DATA_G32, OTG_CRC32, id),\
506 SRI_ARR(OTG_CRC1_DATA_B32, OTG_CRC32, id)
507
508 static struct dcn_optc_registers optc_regs[4];
509
510 static const struct dcn_optc_shift optc_shift = {
511 OPTC_COMMON_MASK_SH_LIST_DCN3_6(__SHIFT)
512 };
513
514 static const struct dcn_optc_mask optc_mask = {
515 OPTC_COMMON_MASK_SH_LIST_DCN3_6(_MASK)
516 };
517
518 #define hubp_regs_init(id)\
519 HUBP_REG_LIST_DCN30_RI(id)
520
521 static struct dcn_hubp2_registers hubp_regs[4];
522
523
524 static const struct dcn35_hubp2_shift hubp_shift = {
525 HUBP_MASK_SH_LIST_DCN35(__SHIFT)
526 };
527
528 static const struct dcn35_hubp2_mask hubp_mask = {
529 HUBP_MASK_SH_LIST_DCN35(_MASK)
530 };
531
532 static struct dcn_hubbub_registers hubbub_reg;
533
534 #define hubbub_reg_init()\
535 HUBBUB_REG_LIST_DCN35(0)
536
537 static const struct dcn_hubbub_shift hubbub_shift = {
538 HUBBUB_MASK_SH_LIST_DCN35(__SHIFT)
539 };
540
541 static const struct dcn_hubbub_mask hubbub_mask = {
542 HUBBUB_MASK_SH_LIST_DCN35(_MASK)
543 };
544
545 static struct dccg_registers dccg_regs;
546
547 #define dccg_regs_init()\
548 DCCG_REG_LIST_DCN35()
549
550 static const struct dccg_shift dccg_shift = {
551 DCCG_MASK_SH_LIST_DCN35(__SHIFT)
552 };
553
554 static const struct dccg_mask dccg_mask = {
555 DCCG_MASK_SH_LIST_DCN35(_MASK)
556 };
557
558 static struct pg_cntl_registers pg_cntl_regs;
559
560 #define pg_cntl_dcn35_regs_init() \
561 PG_CNTL_REG_LIST_DCN35()
562
563 static const struct pg_cntl_shift pg_cntl_shift = {
564 PG_CNTL_MASK_SH_LIST_DCN35(__SHIFT)
565 };
566
567 static const struct pg_cntl_mask pg_cntl_mask = {
568 PG_CNTL_MASK_SH_LIST_DCN35(_MASK)
569 };
570
571 #define SRII2(reg_name_pre, reg_name_post, id)\
572 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
573 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
574 reg ## reg_name_pre ## id ## _ ## reg_name_post
575
576 static struct dce_hwseq_registers hwseq_reg;
577
578 #define hwseq_reg_init()\
579 HWSEQ_DCN36_REG_LIST()
580
581 #define HWSEQ_DCN36_MASK_SH_LIST(mask_sh)\
582 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
583 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
584 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
585 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
586 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
587 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
588 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
589 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
590 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
591 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
592 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
593 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
594 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
595 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
596 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
597 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
598 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
599 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
600 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
601 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
602 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
603 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
604 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
605 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
606 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
607 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
608 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
609 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
610 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
611 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
612 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
613 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
614 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
615 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
616 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
617 HWS_SF(, DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
618 HWS_SF(, DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
619 HWS_SF(, DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
620 HWS_SF(, DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
621 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
622 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
623 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
624 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
625 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
626 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
627 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh),\
628 HWS_SF(, DMU_CLK_CNTL, DISPCLK_R_DMU_GATE_DIS, mask_sh),\
629 HWS_SF(, DMU_CLK_CNTL, DISPCLK_G_RBBMIF_GATE_DIS, mask_sh),\
630 HWS_SF(, DMU_CLK_CNTL, RBBMIF_FGCG_REP_DIS, mask_sh),\
631 HWS_SF(, DMU_CLK_CNTL, DPREFCLK_ALLOW_DS_CLKSTOP, mask_sh),\
632 HWS_SF(, DMU_CLK_CNTL, DISPCLK_ALLOW_DS_CLKSTOP, mask_sh),\
633 HWS_SF(, DMU_CLK_CNTL, DPPCLK_ALLOW_DS_CLKSTOP, mask_sh),\
634 HWS_SF(, DMU_CLK_CNTL, DTBCLK_ALLOW_DS_CLKSTOP, mask_sh),\
635 HWS_SF(, DMU_CLK_CNTL, DCFCLK_ALLOW_DS_CLKSTOP, mask_sh),\
636 HWS_SF(, DMU_CLK_CNTL, DPIACLK_ALLOW_DS_CLKSTOP, mask_sh),\
637 HWS_SF(, DMU_CLK_CNTL, LONO_FGCG_REP_DIS, mask_sh),\
638 HWS_SF(, DMU_CLK_CNTL, LONO_DISPCLK_GATE_DISABLE, mask_sh),\
639 HWS_SF(, DMU_CLK_CNTL, LONO_SOCCLK_GATE_DISABLE, mask_sh),\
640 HWS_SF(, DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE, mask_sh),\
641 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh), \
642 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh), \
643 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh), \
644 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh), \
645 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_FE_GATE_DISABLE, mask_sh), \
646 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh), \
647 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh), \
648 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh), \
649 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh), \
650 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABLE, mask_sh), \
651 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_GATE_DISABLE, mask_sh), \
652 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh), \
653 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
654 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
655 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
656 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh),\
657 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\
658 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\
659 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\
660 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\
661 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\
662 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\
663 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\
664 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\
665 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK0_GATE_DISABLE, mask_sh),\
666 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK1_GATE_DISABLE, mask_sh),\
667 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK2_GATE_DISABLE, mask_sh),\
668 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK3_GATE_DISABLE, mask_sh)
669
670 static const struct dce_hwseq_shift hwseq_shift = {
671 HWSEQ_DCN36_MASK_SH_LIST(__SHIFT)
672 };
673
674 static const struct dce_hwseq_mask hwseq_mask = {
675 HWSEQ_DCN36_MASK_SH_LIST(_MASK)
676 };
677
678 #define vmid_regs_init(id)\
679 DCN20_VMID_REG_LIST_RI(id)
680
681 static struct dcn_vmid_registers vmid_regs[16];
682
683 static const struct dcn20_vmid_shift vmid_shifts = {
684 DCN20_VMID_MASK_SH_LIST(__SHIFT)
685 };
686
687 static const struct dcn20_vmid_mask vmid_masks = {
688 DCN20_VMID_MASK_SH_LIST(_MASK)
689 };
690
691 static struct dcn_dio_registers dio_regs;
692
693 #define DIO_MASK_SH_LIST(mask_sh)\
694 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh)
695
696 static const struct dcn_dio_shift dio_shift = {
697 DIO_MASK_SH_LIST(__SHIFT)
698 };
699
700 static const struct dcn_dio_mask dio_mask = {
701 DIO_MASK_SH_LIST(_MASK)
702 };
703
704 static const struct resource_caps res_cap_dcn36 = {
705 .num_timing_generator = 4,
706 .num_opp = 4,
707 .num_video_plane = 4,
708 .num_audio = 5,
709 .num_stream_encoder = 5,
710 .num_dig_link_enc = 5,
711 .num_hpo_frl = 1,
712 .num_hpo_dp_stream_encoder = 4,
713 .num_hpo_dp_link_encoder = 2,
714 .num_pll = 4,/*1 c10 edp, 3xc20 combo PHY*/
715 .num_dwb = 1,
716 .num_ddc = 5,
717 .num_vmid = 16,
718 .num_mpc_3dlut = 2,
719 .num_dsc = 4,
720 };
721
722 static const struct dc_plane_cap plane_cap = {
723 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
724 .per_pixel_alpha = true,
725
726 .pixel_format_support = {
727 .argb8888 = true,
728 .nv12 = true,
729 .fp16 = true,
730 .p010 = true,
731 .ayuv = false,
732 },
733
734 .max_upscale_factor = {
735 .argb8888 = 16000,
736 .nv12 = 16000,
737 .fp16 = 16000
738 },
739
740 // 6:1 downscaling ratio: 1000/6 = 166.666
741 .max_downscale_factor = {
742 .argb8888 = 250,
743 .nv12 = 167,
744 .fp16 = 167
745 },
746 64,
747 64
748 };
749
750 static const struct dc_debug_options debug_defaults_drv = {
751 .limit_ffe = 3,
752 .disable_dmcu = true,
753 .force_abm_enable = false,
754 .clock_trace = true,
755 .disable_pplib_clock_request = false,
756 .pipe_split_policy = MPC_SPLIT_AVOID,
757 .force_single_disp_pipe_split = false,
758 .disable_dcc = DCC_ENABLE,
759 .disable_dpp_power_gate = true,
760 .disable_hubp_power_gate = true,
761 .disable_optc_power_gate = true, /*should the same as above two*/
762 .disable_hpo_power_gate = true, /*dmubfw force domain25 on*/
763 .disable_clock_gate = false,
764 .disable_dsc_power_gate = true,
765 .vsr_support = true,
766 .performance_trace = false,
767 .max_downscale_src_width = 4096,/*upto true 4k*/
768 .disable_pplib_wm_range = false,
769 .scl_reset_length10 = true,
770 .sanity_checks = false,
771 .underflow_assert_delay_us = 0xFFFFFFFF,
772 .dwb_fi_phase = -1, // -1 = disable,
773 .dmub_command_table = true,
774 .pstate_enabled = true,
775 .use_max_lb = true,
776 .enable_mem_low_power = {
777 .bits = {
778 .vga = false,
779 .i2c = true,
780 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
781 .dscl = true,
782 .cm = true,
783 .mpc = true,
784 .optc = true,
785 .vpg = true,
786 .afmt = true,
787 }
788 },
789 .root_clock_optimization = {
790 .bits = {
791 .dpp = true,
792 .dsc = true,/*dscclk and dsc pg*/
793 .hdmistream = true,
794 .hdmichar = true,
795 .dpstream = true,
796 .symclk32_se = true,
797 .symclk32_le = true,
798 .symclk_fe = true,
799 .physymclk = false,
800 .dpiasymclk = true,
801 }
802 },
803 .seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT,
804 .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/
805 .minimum_z8_residency_time = 1, /* Always allow when other conditions are met */
806 .using_dml2 = true,
807 .support_eDP1_5 = true,
808 .enable_hpo_pg_support = false,
809 .enable_single_display_2to1_odm_policy = true,
810 .disable_idle_power_optimizations = false,
811 .disable_boot_optimizations = false,
812 .disable_unbounded_requesting = false,
813 .disable_mem_low_power = false,
814 //must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions
815 .enable_double_buffered_dsc_pg_support = true,
816 .enable_dp_dig_pixel_rate_div_policy = 1,
817 .disable_z10 = false,
818 .ignore_pg = true,
819 .psp_disabled_wa = true,
820 .ips2_eval_delay_us = 2000,
821 .ips2_entry_delay_us = 800,
822 .disable_dmub_reallow_idle = false,
823 .static_screen_wait_frames = 2,
824 .disable_timeout = true,
825 .min_disp_clk_khz = 50000,
826 };
827
828 static const struct dc_check_config config_defaults = {
829 .enable_legacy_fast_update = false,
830 };
831
832 static const struct dc_panel_config panel_config_defaults = {
833 .psr = {
834 .disable_psr = false,
835 .disallow_psrsu = false,
836 .disallow_replay = false,
837 },
838 .ilr = {
839 .optimize_edp_link_rate = true,
840 },
841 };
842
dcn35_dpp_destroy(struct dpp ** dpp)843 static void dcn35_dpp_destroy(struct dpp **dpp)
844 {
845 kfree(TO_DCN20_DPP(*dpp));
846 *dpp = NULL;
847 }
848
dcn35_dpp_create(struct dc_context * ctx,uint32_t inst)849 static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst)
850 {
851 struct dcn3_dpp *dpp = kzalloc_obj(struct dcn3_dpp);
852 bool success = (dpp != NULL);
853
854 if (!success)
855 return NULL;
856
857 #undef REG_STRUCT
858 #define REG_STRUCT dpp_regs
859 dpp_regs_init(0),
860 dpp_regs_init(1),
861 dpp_regs_init(2),
862 dpp_regs_init(3);
863
864 success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift,
865 &tf_mask);
866 if (success) {
867 dpp35_set_fgcg(
868 dpp,
869 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);
870 return &dpp->base;
871 }
872
873 BREAK_TO_DEBUGGER();
874 kfree(dpp);
875 return NULL;
876 }
877
dcn35_opp_create(struct dc_context * ctx,uint32_t inst)878 static struct output_pixel_processor *dcn35_opp_create(
879 struct dc_context *ctx, uint32_t inst)
880 {
881 struct dcn20_opp *opp =
882 kzalloc_obj(struct dcn20_opp);
883
884 if (!opp) {
885 BREAK_TO_DEBUGGER();
886 return NULL;
887 }
888
889 #undef REG_STRUCT
890 #define REG_STRUCT opp_regs
891 opp_regs_init(0),
892 opp_regs_init(1),
893 opp_regs_init(2),
894 opp_regs_init(3);
895
896 dcn35_opp_construct(opp, ctx, inst,
897 &opp_regs[inst], &opp_shift, &opp_mask);
898
899 dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp);
900
901 return &opp->base;
902 }
903
dcn31_aux_engine_create(struct dc_context * ctx,uint32_t inst)904 static struct dce_aux *dcn31_aux_engine_create(
905 struct dc_context *ctx,
906 uint32_t inst)
907 {
908 struct aux_engine_dce110 *aux_engine =
909 kzalloc_obj(struct aux_engine_dce110);
910
911 if (!aux_engine)
912 return NULL;
913
914 #undef REG_STRUCT
915 #define REG_STRUCT aux_engine_regs
916 aux_engine_regs_init(0),
917 aux_engine_regs_init(1),
918 aux_engine_regs_init(2),
919 aux_engine_regs_init(3),
920 aux_engine_regs_init(4);
921
922 dce110_aux_engine_construct(aux_engine, ctx, inst,
923 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
924 &aux_engine_regs[inst],
925 &aux_mask,
926 &aux_shift,
927 ctx->dc->caps.extended_aux_timeout_support);
928
929 return &aux_engine->base;
930 }
931
932 #define i2c_inst_regs_init(id)\
933 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
934
935 static struct dce_i2c_registers i2c_hw_regs[5];
936
937 static const struct dce_i2c_shift i2c_shifts = {
938 I2C_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
939 };
940
941 static const struct dce_i2c_mask i2c_masks = {
942 I2C_COMMON_MASK_SH_LIST_DCN35(_MASK)
943 };
944
945 /* ========================================================== */
946
947 /*
948 * DPIA index | Preferred Encoder | Host Router
949 * 0 | C | 0
950 * 1 | First Available | 0
951 * 2 | D | 1
952 * 3 | First Available | 1
953 */
954 /* ========================================================== */
955 static const enum engine_id dpia_to_preferred_enc_id_table[] = {
956 ENGINE_ID_DIGC,
957 ENGINE_ID_DIGC,
958 ENGINE_ID_DIGD,
959 ENGINE_ID_DIGD
960 };
961
dcn36_get_preferred_eng_id_dpia(unsigned int dpia_index)962 static enum engine_id dcn36_get_preferred_eng_id_dpia(unsigned int dpia_index)
963 {
964 return dpia_to_preferred_enc_id_table[dpia_index];
965 }
966
dcn31_i2c_hw_create(struct dc_context * ctx,uint32_t inst)967 static struct dce_i2c_hw *dcn31_i2c_hw_create(
968 struct dc_context *ctx,
969 uint32_t inst)
970 {
971 struct dce_i2c_hw *dce_i2c_hw =
972 kzalloc_obj(struct dce_i2c_hw);
973
974 if (!dce_i2c_hw)
975 return NULL;
976
977 #undef REG_STRUCT
978 #define REG_STRUCT i2c_hw_regs
979 i2c_inst_regs_init(1),
980 i2c_inst_regs_init(2),
981 i2c_inst_regs_init(3),
982 i2c_inst_regs_init(4),
983 i2c_inst_regs_init(5);
984
985 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
986 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
987
988 return dce_i2c_hw;
989 }
dcn35_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)990 static struct mpc *dcn35_mpc_create(
991 struct dc_context *ctx,
992 int num_mpcc,
993 int num_rmu)
994 {
995 struct dcn30_mpc *mpc30 = kzalloc_obj(struct dcn30_mpc);
996
997 if (!mpc30)
998 return NULL;
999
1000 #undef REG_STRUCT
1001 #define REG_STRUCT mpc_regs
1002 dcn_mpc_regs_init();
1003
1004 dcn32_mpc_construct(mpc30, ctx,
1005 &mpc_regs,
1006 &mpc_shift,
1007 &mpc_mask,
1008 num_mpcc,
1009 num_rmu);
1010
1011 return &mpc30->base;
1012 }
1013
dcn36_dio_create(struct dc_context * ctx)1014 static struct dio *dcn36_dio_create(struct dc_context *ctx)
1015 {
1016 struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio);
1017
1018 if (!dio10)
1019 return NULL;
1020
1021 #undef REG_STRUCT
1022 #define REG_STRUCT dio_regs
1023 DIO_REG_LIST_DCN10();
1024
1025 dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask);
1026
1027 return &dio10->base;
1028 }
1029
dcn35_hubbub_create(struct dc_context * ctx)1030 static struct hubbub *dcn35_hubbub_create(struct dc_context *ctx)
1031 {
1032 int i;
1033
1034 struct dcn20_hubbub *hubbub3 = kzalloc_obj(struct dcn20_hubbub);
1035
1036 if (!hubbub3)
1037 return NULL;
1038
1039 #undef REG_STRUCT
1040 #define REG_STRUCT hubbub_reg
1041 hubbub_reg_init();
1042
1043 #undef REG_STRUCT
1044 #define REG_STRUCT vmid_regs
1045 vmid_regs_init(0),
1046 vmid_regs_init(1),
1047 vmid_regs_init(2),
1048 vmid_regs_init(3),
1049 vmid_regs_init(4),
1050 vmid_regs_init(5),
1051 vmid_regs_init(6),
1052 vmid_regs_init(7),
1053 vmid_regs_init(8),
1054 vmid_regs_init(9),
1055 vmid_regs_init(10),
1056 vmid_regs_init(11),
1057 vmid_regs_init(12),
1058 vmid_regs_init(13),
1059 vmid_regs_init(14),
1060 vmid_regs_init(15);
1061
1062 hubbub35_construct(hubbub3, ctx,
1063 &hubbub_reg,
1064 &hubbub_shift,
1065 &hubbub_mask,
1066 384,/*ctx->dc->dml.ip.det_buffer_size_kbytes,*/
1067 8, /*ctx->dc->dml.ip.pixel_chunk_size_kbytes,*/
1068 1792 /*ctx->dc->dml.ip.config_return_buffer_size_in_kbytes*/);
1069
1070
1071 for (i = 0; i < res_cap_dcn36.num_vmid; i++) {
1072 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1073
1074 vmid->ctx = ctx;
1075
1076 vmid->regs = &vmid_regs[i];
1077 vmid->shifts = &vmid_shifts;
1078 vmid->masks = &vmid_masks;
1079 }
1080
1081 return &hubbub3->base;
1082 }
1083
dcn35_timing_generator_create(struct dc_context * ctx,uint32_t instance)1084 static struct timing_generator *dcn35_timing_generator_create(
1085 struct dc_context *ctx,
1086 uint32_t instance)
1087 {
1088 struct optc *tgn10 =
1089 kzalloc_obj(struct optc);
1090
1091 if (!tgn10)
1092 return NULL;
1093
1094 #undef REG_STRUCT
1095 #define REG_STRUCT optc_regs
1096 optc_regs_init(0),
1097 optc_regs_init(1),
1098 optc_regs_init(2),
1099 optc_regs_init(3);
1100
1101 tgn10->base.inst = instance;
1102 tgn10->base.ctx = ctx;
1103
1104 tgn10->tg_regs = &optc_regs[instance];
1105 tgn10->tg_shift = &optc_shift;
1106 tgn10->tg_mask = &optc_mask;
1107
1108 dcn35_timing_generator_init(tgn10);
1109
1110 return &tgn10->base;
1111 }
1112
1113 static const struct encoder_feature_support link_enc_feature = {
1114 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1115 .max_hdmi_pixel_clock = 600000,
1116 .hdmi_ycbcr420_supported = true,
1117 .dp_ycbcr420_supported = true,
1118 .fec_supported = true,
1119 .flags.bits.IS_HBR2_CAPABLE = true,
1120 .flags.bits.IS_HBR3_CAPABLE = true,
1121 .flags.bits.IS_TPS3_CAPABLE = true,
1122 .flags.bits.IS_TPS4_CAPABLE = true
1123 };
1124
dcn35_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1125 static struct link_encoder *dcn35_link_encoder_create(
1126 struct dc_context *ctx,
1127 const struct encoder_init_data *enc_init_data)
1128 {
1129 struct dcn20_link_encoder *enc20 =
1130 kzalloc_obj(struct dcn20_link_encoder);
1131
1132 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1133 return NULL;
1134
1135 #undef REG_STRUCT
1136 #define REG_STRUCT link_enc_aux_regs
1137 aux_regs_init(0),
1138 aux_regs_init(1),
1139 aux_regs_init(2),
1140 aux_regs_init(3),
1141 aux_regs_init(4);
1142
1143 #undef REG_STRUCT
1144 #define REG_STRUCT link_enc_hpd_regs
1145 hpd_regs_init(0),
1146 hpd_regs_init(1),
1147 hpd_regs_init(2),
1148 hpd_regs_init(3),
1149 hpd_regs_init(4);
1150
1151 #undef REG_STRUCT
1152 #define REG_STRUCT link_enc_regs
1153 link_regs_init(0, A),
1154 link_regs_init(1, B),
1155 link_regs_init(2, C),
1156 link_regs_init(3, D),
1157 link_regs_init(4, E);
1158
1159 dcn35_link_encoder_construct(enc20,
1160 enc_init_data,
1161 &link_enc_feature,
1162 &link_enc_regs[enc_init_data->transmitter],
1163 &link_enc_aux_regs[enc_init_data->channel - 1],
1164 &link_enc_hpd_regs[enc_init_data->hpd_source],
1165 &le_shift,
1166 &le_mask);
1167
1168 return &enc20->enc10.base;
1169 }
1170
1171 /* Create a minimal link encoder object not associated with a particular
1172 * physical connector.
1173 * resource_funcs.link_enc_create_minimal
1174 */
dcn31_link_enc_create_minimal(struct dc_context * ctx,enum engine_id eng_id)1175 static struct link_encoder *dcn31_link_enc_create_minimal(
1176 struct dc_context *ctx, enum engine_id eng_id)
1177 {
1178 struct dcn20_link_encoder *enc20;
1179
1180 if (((unsigned int)eng_id - ENGINE_ID_DIGA) >= ctx->dc->res_pool->res_cap->num_dig_link_enc)
1181 return NULL;
1182
1183 enc20 = kzalloc_obj(struct dcn20_link_encoder);
1184 if (!enc20)
1185 return NULL;
1186
1187 dcn31_link_encoder_construct_minimal(
1188 enc20,
1189 ctx,
1190 &link_enc_feature,
1191 &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1192 &le_shift,
1193 &le_mask,
1194 eng_id);
1195
1196 return &enc20->enc10.base;
1197 }
1198
dcn31_panel_cntl_create(const struct panel_cntl_init_data * init_data)1199 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1200 {
1201 struct dcn31_panel_cntl *panel_cntl =
1202 kzalloc_obj(struct dcn31_panel_cntl);
1203
1204 if (!panel_cntl)
1205 return NULL;
1206
1207 dcn31_panel_cntl_construct(panel_cntl, init_data);
1208
1209 return &panel_cntl->base;
1210 }
1211
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1212 static void read_dce_straps(
1213 struct dc_context *ctx,
1214 struct resource_straps *straps)
1215 {
1216 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1217 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1218
1219 }
1220
dcn31_create_audio(struct dc_context * ctx,unsigned int inst)1221 static struct audio *dcn31_create_audio(
1222 struct dc_context *ctx, unsigned int inst)
1223 {
1224
1225 #undef REG_STRUCT
1226 #define REG_STRUCT audio_regs
1227 audio_regs_init(0),
1228 audio_regs_init(1),
1229 audio_regs_init(2),
1230 audio_regs_init(3),
1231 audio_regs_init(4);
1232 audio_regs_init(5);
1233 audio_regs_init(6);
1234
1235 return dce_audio_create(ctx, inst,
1236 &audio_regs[inst], &audio_shift, &audio_mask);
1237 }
1238
dcn31_vpg_create(struct dc_context * ctx,uint32_t inst)1239 static struct vpg *dcn31_vpg_create(
1240 struct dc_context *ctx,
1241 uint32_t inst)
1242 {
1243 struct dcn31_vpg *vpg31 = kzalloc_obj(struct dcn31_vpg);
1244
1245 if (!vpg31)
1246 return NULL;
1247
1248 #undef REG_STRUCT
1249 #define REG_STRUCT vpg_regs
1250 vpg_regs_init(0),
1251 vpg_regs_init(1),
1252 vpg_regs_init(2),
1253 vpg_regs_init(3),
1254 vpg_regs_init(4),
1255 vpg_regs_init(5),
1256 vpg_regs_init(6),
1257 vpg_regs_init(7),
1258 vpg_regs_init(8),
1259 vpg_regs_init(9);
1260
1261 vpg31_construct(vpg31, ctx, inst,
1262 &vpg_regs[inst],
1263 &vpg_shift,
1264 &vpg_mask);
1265
1266 return &vpg31->base;
1267 }
1268
dcn31_afmt_create(struct dc_context * ctx,uint32_t inst)1269 static struct afmt *dcn31_afmt_create(
1270 struct dc_context *ctx,
1271 uint32_t inst)
1272 {
1273 struct dcn31_afmt *afmt31 = kzalloc_obj(struct dcn31_afmt);
1274
1275 if (!afmt31)
1276 return NULL;
1277
1278 #undef REG_STRUCT
1279 #define REG_STRUCT afmt_regs
1280 afmt_regs_init(0),
1281 afmt_regs_init(1),
1282 afmt_regs_init(2),
1283 afmt_regs_init(3),
1284 afmt_regs_init(4),
1285 afmt_regs_init(5);
1286
1287 afmt31_construct(afmt31, ctx, inst,
1288 &afmt_regs[inst],
1289 &afmt_shift,
1290 &afmt_mask);
1291
1292 // Light sleep by default, no need to power down here
1293
1294 return &afmt31->base;
1295 }
1296
dcn31_apg_create(struct dc_context * ctx,uint32_t inst)1297 static struct apg *dcn31_apg_create(
1298 struct dc_context *ctx,
1299 uint32_t inst)
1300 {
1301 struct dcn31_apg *apg31 = kzalloc_obj(struct dcn31_apg);
1302
1303 if (!apg31)
1304 return NULL;
1305
1306 #undef REG_STRUCT
1307 #define REG_STRUCT apg_regs
1308 apg_regs_init(0),
1309 apg_regs_init(1),
1310 apg_regs_init(2),
1311 apg_regs_init(3);
1312
1313 apg31_construct(apg31, ctx, inst,
1314 &apg_regs[inst],
1315 &apg_shift,
1316 &apg_mask);
1317
1318 return &apg31->base;
1319 }
1320
dcn35_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1321 static struct stream_encoder *dcn35_stream_encoder_create(
1322 enum engine_id eng_id,
1323 struct dc_context *ctx)
1324 {
1325 struct dcn10_stream_encoder *enc1;
1326 struct vpg *vpg;
1327 struct afmt *afmt;
1328 int vpg_inst;
1329 int afmt_inst;
1330
1331 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1332 if (eng_id <= ENGINE_ID_DIGF) {
1333 vpg_inst = eng_id;
1334 afmt_inst = eng_id;
1335 } else
1336 return NULL;
1337
1338 enc1 = kzalloc_obj(struct dcn10_stream_encoder);
1339 vpg = dcn31_vpg_create(ctx, vpg_inst);
1340 afmt = dcn31_afmt_create(ctx, afmt_inst);
1341
1342 if (!enc1 || !vpg || !afmt) {
1343 kfree(enc1);
1344 kfree(vpg);
1345 kfree(afmt);
1346 return NULL;
1347 }
1348
1349 #undef REG_STRUCT
1350 #define REG_STRUCT stream_enc_regs
1351 stream_enc_regs_init(0),
1352 stream_enc_regs_init(1),
1353 stream_enc_regs_init(2),
1354 stream_enc_regs_init(3),
1355 stream_enc_regs_init(4);
1356
1357 dcn35_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1358 eng_id, vpg, afmt,
1359 &stream_enc_regs[eng_id],
1360 &se_shift, &se_mask);
1361
1362 return &enc1->base;
1363 }
1364
dcn31_hpo_frl_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1365 static struct hpo_frl_stream_encoder *dcn31_hpo_frl_stream_encoder_create(
1366 enum engine_id eng_id,
1367 struct dc_context *ctx)
1368 {
1369 struct dcn30_hpo_frl_stream_encoder *hpo_enc3;
1370 struct vpg *vpg;
1371 struct afmt *afmt;
1372 int vpg_inst;
1373 int afmt_inst;
1374
1375 #undef REG_STRUCT
1376 #define REG_STRUCT hpo_frl_stream_enc_regs
1377 hpo_frl_stream_encoder_reg_list(0),
1378 hpo_frl_stream_encoder_dme_reg_list(6);
1379
1380 /* Mapping of VPG, AFMT, DME register blocks to HPO block instance */
1381 if (eng_id == ENGINE_ID_HPO_0) {
1382 vpg_inst = 5;
1383 afmt_inst = 5;
1384 } else
1385 return NULL;
1386
1387 /* allocate HPO stream encoder and create VPG, AFMT sub-blocks */
1388 hpo_enc3 = kzalloc_obj(struct dcn30_hpo_frl_stream_encoder);
1389 vpg = dcn31_vpg_create(ctx, vpg_inst);
1390 afmt = dcn31_afmt_create(ctx, afmt_inst);
1391
1392 if (!hpo_enc3 || !vpg || !afmt) {
1393 kfree(hpo_enc3);
1394 kfree(vpg);
1395 kfree(afmt);
1396 return NULL;
1397 }
1398
1399 dcn30_hpo_frl_stream_encoder_construct(hpo_enc3, ctx, ctx->dc_bios,
1400 eng_id, vpg, afmt,
1401 &hpo_frl_stream_enc_regs[eng_id-ENGINE_ID_HPO_0],
1402 &hpo_se_shift, &hpo_se_mask);
1403
1404 return &hpo_enc3->base;
1405 }
1406
dcn31_hpo_frl_link_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1407 static struct hpo_frl_link_encoder *dcn31_hpo_frl_link_encoder_create(
1408 enum engine_id eng_id,
1409 struct dc_context *ctx)
1410 {
1411 struct dcn30_hpo_frl_link_encoder *hpo_enc3;
1412
1413 ASSERT((eng_id == ENGINE_ID_HPO_0) || (eng_id == ENGINE_ID_HPO_1));
1414
1415 #undef REG_STRUCT
1416 #define REG_STRUCT hpo_frl_link_enc_regs
1417 hpo_frl_link_encoder_reg_list(0);
1418
1419 /* allocate HPO link encoder */
1420 hpo_enc3 = kzalloc_obj(struct dcn30_hpo_frl_link_encoder);
1421 if (!hpo_enc3)
1422 return NULL; /* out of memory */
1423
1424 hpo_frl_link_encoder3_construct(hpo_enc3, ctx, eng_id-ENGINE_ID_HPO_0,
1425 &hpo_frl_link_enc_regs[eng_id-ENGINE_ID_HPO_0],
1426 &hpo_le_shift, &hpo_le_mask);
1427
1428 return &hpo_enc3->base;
1429 }
1430
dcn31_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1431 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1432 enum engine_id eng_id,
1433 struct dc_context *ctx)
1434 {
1435 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1436 struct vpg *vpg;
1437 struct apg *apg;
1438 uint32_t hpo_dp_inst;
1439 uint32_t vpg_inst;
1440 uint32_t apg_inst;
1441
1442 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1443 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1444
1445 /* Mapping of VPG register blocks to HPO DP block instance:
1446 * VPG[6] -> HPO_DP[0]
1447 * VPG[7] -> HPO_DP[1]
1448 * VPG[8] -> HPO_DP[2]
1449 * VPG[9] -> HPO_DP[3]
1450 */
1451 vpg_inst = hpo_dp_inst + 6;
1452
1453 /* Mapping of APG register blocks to HPO DP block instance:
1454 * APG[0] -> HPO_DP[0]
1455 * APG[1] -> HPO_DP[1]
1456 * APG[2] -> HPO_DP[2]
1457 * APG[3] -> HPO_DP[3]
1458 */
1459 apg_inst = hpo_dp_inst;
1460
1461 /* allocate HPO stream encoder and create VPG sub-block */
1462 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_stream_encoder);
1463 vpg = dcn31_vpg_create(ctx, vpg_inst);
1464 apg = dcn31_apg_create(ctx, apg_inst);
1465
1466 if (!hpo_dp_enc31 || !vpg || !apg) {
1467 kfree(hpo_dp_enc31);
1468 kfree(vpg);
1469 kfree(apg);
1470 return NULL;
1471 }
1472
1473 #undef REG_STRUCT
1474 #define REG_STRUCT hpo_dp_stream_enc_regs
1475 hpo_dp_stream_encoder_reg_init(0),
1476 hpo_dp_stream_encoder_reg_init(1),
1477 hpo_dp_stream_encoder_reg_init(2),
1478 hpo_dp_stream_encoder_reg_init(3);
1479
1480 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1481 hpo_dp_inst, eng_id, vpg, apg,
1482 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1483 &hpo_dp_se_shift, &hpo_dp_se_mask);
1484
1485 return &hpo_dp_enc31->base;
1486 }
1487
dcn31_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1488 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1489 uint8_t inst,
1490 struct dc_context *ctx)
1491 {
1492 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1493
1494 /* allocate HPO link encoder */
1495 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_link_encoder);
1496 if (!hpo_dp_enc31)
1497 return NULL; /* out of memory */
1498
1499 #undef REG_STRUCT
1500 #define REG_STRUCT hpo_dp_link_enc_regs
1501 hpo_dp_link_encoder_reg_init(0),
1502 hpo_dp_link_encoder_reg_init(1);
1503
1504 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1505 &hpo_dp_link_enc_regs[inst],
1506 &hpo_dp_le_shift, &hpo_dp_le_mask);
1507
1508 return &hpo_dp_enc31->base;
1509 }
1510
dcn36_hwseq_create(struct dc_context * ctx)1511 static struct dce_hwseq *dcn36_hwseq_create(
1512 struct dc_context *ctx)
1513 {
1514 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
1515
1516 #undef REG_STRUCT
1517 #define REG_STRUCT hwseq_reg
1518 hwseq_reg_init();
1519
1520 if (hws) {
1521 hws->ctx = ctx;
1522 hws->regs = &hwseq_reg;
1523 hws->shifts = &hwseq_shift;
1524 hws->masks = &hwseq_mask;
1525 }
1526 return hws;
1527 }
1528 static const struct resource_create_funcs res_create_funcs = {
1529 .read_dce_straps = read_dce_straps,
1530 .create_audio = dcn31_create_audio,
1531 .create_stream_encoder = dcn35_stream_encoder_create,
1532 .create_hpo_frl_stream_encoder = dcn31_hpo_frl_stream_encoder_create,
1533 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1534 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1535 .create_hwseq = dcn36_hwseq_create,
1536 };
1537
dcn36_resource_destruct(struct dcn36_resource_pool * pool)1538 static void dcn36_resource_destruct(struct dcn36_resource_pool *pool)
1539 {
1540 unsigned int i;
1541
1542 for (i = 0; i < pool->base.stream_enc_count; i++) {
1543 if (pool->base.stream_enc[i] != NULL) {
1544 if (pool->base.stream_enc[i]->vpg != NULL) {
1545 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1546 pool->base.stream_enc[i]->vpg = NULL;
1547 }
1548 if (pool->base.stream_enc[i]->afmt != NULL) {
1549 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1550 pool->base.stream_enc[i]->afmt = NULL;
1551 }
1552 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1553 pool->base.stream_enc[i] = NULL;
1554 }
1555 }
1556
1557 for (i = 0; i < pool->base.hpo_frl_stream_enc_count; i++) {
1558 if (pool->base.hpo_frl_stream_enc[i] != NULL) {
1559 if (pool->base.hpo_frl_stream_enc[i]->vpg != NULL) {
1560 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_frl_stream_enc[i]->vpg));
1561 pool->base.hpo_frl_stream_enc[i]->vpg = NULL;
1562 }
1563 if (pool->base.hpo_frl_stream_enc[i]->afmt != NULL) {
1564 kfree(DCN30_AFMT_FROM_AFMT(pool->base.hpo_frl_stream_enc[i]->afmt));
1565 pool->base.hpo_frl_stream_enc[i]->afmt = NULL;
1566 }
1567 kfree(DCN30_HPO_FRL_STRENC_FROM_HPO_FRL_STRENC(pool->base.hpo_frl_stream_enc[i]));
1568 pool->base.hpo_frl_stream_enc[i] = NULL;
1569 }
1570 }
1571
1572 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1573 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1574 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1575 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1576 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1577 }
1578 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1579 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1580 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1581 }
1582 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1583 pool->base.hpo_dp_stream_enc[i] = NULL;
1584 }
1585 }
1586
1587 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1588 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1589 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1590 pool->base.hpo_dp_link_enc[i] = NULL;
1591 }
1592 }
1593
1594 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
1595 if (pool->base.dscs[i] != NULL)
1596 dcn20_dsc_destroy(&pool->base.dscs[i]);
1597 }
1598
1599 if (pool->base.mpc != NULL) {
1600 kfree(TO_DCN20_MPC(pool->base.mpc));
1601 pool->base.mpc = NULL;
1602 }
1603 if (pool->base.hubbub != NULL) {
1604 kfree(pool->base.hubbub);
1605 pool->base.hubbub = NULL;
1606 }
1607 for (i = 0; i < pool->base.pipe_count; i++) {
1608 if (pool->base.dpps[i] != NULL)
1609 dcn35_dpp_destroy(&pool->base.dpps[i]);
1610
1611 if (pool->base.ipps[i] != NULL)
1612 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1613
1614 if (pool->base.hubps[i] != NULL) {
1615 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1616 pool->base.hubps[i] = NULL;
1617 }
1618
1619 if (pool->base.irqs != NULL) {
1620 dal_irq_service_destroy(&pool->base.irqs);
1621 }
1622 }
1623
1624 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
1625 if (pool->base.engines[i] != NULL)
1626 dce110_engine_destroy(&pool->base.engines[i]);
1627 if (pool->base.hw_i2cs[i] != NULL) {
1628 kfree(pool->base.hw_i2cs[i]);
1629 pool->base.hw_i2cs[i] = NULL;
1630 }
1631 if (pool->base.sw_i2cs[i] != NULL) {
1632 kfree(pool->base.sw_i2cs[i]);
1633 pool->base.sw_i2cs[i] = NULL;
1634 }
1635 }
1636
1637 for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
1638 if (pool->base.opps[i] != NULL)
1639 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1640 }
1641
1642 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
1643 if (pool->base.timing_generators[i] != NULL) {
1644 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1645 pool->base.timing_generators[i] = NULL;
1646 }
1647 }
1648
1649 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
1650 if (pool->base.dwbc[i] != NULL) {
1651 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1652 pool->base.dwbc[i] = NULL;
1653 }
1654 if (pool->base.mcif_wb[i] != NULL) {
1655 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1656 pool->base.mcif_wb[i] = NULL;
1657 }
1658 }
1659
1660 for (i = 0; i < pool->base.audio_count; i++) {
1661 if (pool->base.audios[i])
1662 dce_aud_destroy(&pool->base.audios[i]);
1663 }
1664
1665 for (i = 0; i < pool->base.clk_src_count; i++) {
1666 if (pool->base.clock_sources[i] != NULL) {
1667 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1668 pool->base.clock_sources[i] = NULL;
1669 }
1670 }
1671
1672 for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
1673 if (pool->base.mpc_lut[i] != NULL) {
1674 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1675 pool->base.mpc_lut[i] = NULL;
1676 }
1677 if (pool->base.mpc_shaper[i] != NULL) {
1678 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1679 pool->base.mpc_shaper[i] = NULL;
1680 }
1681 }
1682
1683 if (pool->base.dp_clock_source != NULL) {
1684 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1685 pool->base.dp_clock_source = NULL;
1686 }
1687
1688 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
1689 if (pool->base.multiple_abms[i] != NULL)
1690 dce_abm_destroy(&pool->base.multiple_abms[i]);
1691 }
1692
1693 if (pool->base.psr != NULL)
1694 dmub_psr_destroy(&pool->base.psr);
1695
1696 if (pool->base.replay != NULL)
1697 dmub_replay_destroy(&pool->base.replay);
1698
1699 if (pool->base.pg_cntl != NULL)
1700 dcn_pg_cntl_destroy(&pool->base.pg_cntl);
1701
1702 if (pool->base.dccg != NULL)
1703 dcn_dccg_destroy(&pool->base.dccg);
1704
1705 if (pool->base.dio != NULL) {
1706 kfree(TO_DCN10_DIO(pool->base.dio));
1707 pool->base.dio = NULL;
1708 }
1709 }
1710
dcn35_hubp_create(struct dc_context * ctx,uint32_t inst)1711 static struct hubp *dcn35_hubp_create(
1712 struct dc_context *ctx,
1713 uint32_t inst)
1714 {
1715 struct dcn20_hubp *hubp2 =
1716 kzalloc_obj(struct dcn20_hubp);
1717
1718 if (!hubp2)
1719 return NULL;
1720
1721 #undef REG_STRUCT
1722 #define REG_STRUCT hubp_regs
1723 hubp_regs_init(0),
1724 hubp_regs_init(1),
1725 hubp_regs_init(2),
1726 hubp_regs_init(3);
1727
1728 if (hubp35_construct(hubp2, ctx, inst,
1729 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1730 return &hubp2->base;
1731
1732 BREAK_TO_DEBUGGER();
1733 kfree(hubp2);
1734 return NULL;
1735 }
1736
dcn35_dwbc_init(struct dcn30_dwbc * dwbc30,struct dc_context * ctx)1737 static void dcn35_dwbc_init(struct dcn30_dwbc *dwbc30, struct dc_context *ctx)
1738 {
1739 dcn35_dwbc_set_fgcg(
1740 dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb);
1741 }
1742
dcn35_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1743 static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1744 {
1745 unsigned int i;
1746 uint32_t pipe_count = pool->res_cap->num_dwb;
1747
1748 for (i = 0; i < pipe_count; i++) {
1749 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc);
1750
1751 if (!dwbc30) {
1752 dm_error("DC: failed to create dwbc30!\n");
1753 return false;
1754 }
1755
1756 #undef REG_STRUCT
1757 #define REG_STRUCT dwbc35_regs
1758 dwbc_regs_dcn3_init(0);
1759
1760 dcn35_dwbc_construct(dwbc30, ctx,
1761 &dwbc35_regs[i],
1762 &dwbc35_shift,
1763 &dwbc35_mask,
1764 i);
1765
1766 pool->dwbc[i] = &dwbc30->base;
1767
1768 dcn35_dwbc_init(dwbc30, ctx);
1769 }
1770 return true;
1771 }
1772
dcn35_mmhubbub_init(struct dcn30_mmhubbub * mcif_wb30,struct dc_context * ctx)1773 static void dcn35_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30,
1774 struct dc_context *ctx)
1775 {
1776 dcn35_mmhubbub_set_fgcg(
1777 mcif_wb30,
1778 ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub);
1779 }
1780
dcn35_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1781 static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1782 {
1783 unsigned int i;
1784 uint32_t pipe_count = pool->res_cap->num_dwb;
1785
1786 for (i = 0; i < pipe_count; i++) {
1787 struct dcn30_mmhubbub *mcif_wb30 = kzalloc_obj(struct dcn30_mmhubbub);
1788
1789 if (!mcif_wb30) {
1790 dm_error("DC: failed to create mcif_wb30!\n");
1791 return false;
1792 }
1793
1794 #undef REG_STRUCT
1795 #define REG_STRUCT mcif_wb35_regs
1796 mcif_wb_regs_dcn3_init(0);
1797
1798 dcn35_mmhubbub_construct(mcif_wb30, ctx,
1799 &mcif_wb35_regs[i],
1800 &mcif_wb35_shift,
1801 &mcif_wb35_mask,
1802 i);
1803
1804 dcn35_mmhubbub_init(mcif_wb30, ctx);
1805
1806 pool->mcif_wb[i] = &mcif_wb30->base;
1807 }
1808 return true;
1809 }
1810
dcn35_dsc_create(struct dc_context * ctx,uint32_t inst)1811 static struct display_stream_compressor *dcn35_dsc_create(
1812 struct dc_context *ctx, uint32_t inst)
1813 {
1814 struct dcn20_dsc *dsc =
1815 kzalloc_obj(struct dcn20_dsc);
1816
1817 if (!dsc) {
1818 BREAK_TO_DEBUGGER();
1819 return NULL;
1820 }
1821
1822 #undef REG_STRUCT
1823 #define REG_STRUCT dsc_regs
1824 dsc_regsDCN35_init(0),
1825 dsc_regsDCN35_init(1),
1826 dsc_regsDCN35_init(2),
1827 dsc_regsDCN35_init(3);
1828
1829 dsc35_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1830 dsc35_set_fgcg(dsc,
1831 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);
1832 return &dsc->base;
1833 }
1834
dcn36_destroy_resource_pool(struct resource_pool ** pool)1835 static void dcn36_destroy_resource_pool(struct resource_pool **pool)
1836 {
1837 struct dcn36_resource_pool *dcn36_pool = TO_DCN36_RES_POOL(*pool);
1838
1839 dcn36_resource_destruct(dcn36_pool);
1840 kfree(dcn36_pool);
1841 *pool = NULL;
1842 }
1843
dcn35_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1844 static struct clock_source *dcn35_clock_source_create(
1845 struct dc_context *ctx,
1846 struct dc_bios *bios,
1847 enum clock_source_id id,
1848 const struct dce110_clk_src_regs *regs,
1849 bool dp_clk_src)
1850 {
1851 struct dce110_clk_src *clk_src =
1852 kzalloc_obj(struct dce110_clk_src);
1853
1854 if (!clk_src)
1855 return NULL;
1856
1857 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1858 regs, &cs_shift, &cs_mask)) {
1859 clk_src->base.dp_clk_src = dp_clk_src;
1860 return &clk_src->base;
1861 }
1862
1863 kfree(clk_src);
1864 BREAK_TO_DEBUGGER();
1865 return NULL;
1866 }
1867
1868 static struct dc_cap_funcs cap_funcs = {
1869 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1870 };
1871
dcn35_get_panel_config_defaults(struct dc_panel_config * panel_config)1872 static void dcn35_get_panel_config_defaults(struct dc_panel_config *panel_config)
1873 {
1874 *panel_config = panel_config_defaults;
1875 }
1876
1877
dcn35_validate_bandwidth(struct dc * dc,struct dc_state * context,enum dc_validate_mode validate_mode)1878 static enum dc_status dcn35_validate_bandwidth(struct dc *dc,
1879 struct dc_state *context,
1880 enum dc_validate_mode validate_mode)
1881 {
1882 bool out = false;
1883
1884 DC_FP_START();
1885 out = dml2_validate(dc, context,
1886 context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1887 validate_mode);
1888 DC_FP_END();
1889
1890 if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING)
1891 return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1892
1893 DC_FP_START();
1894 dcn35_decide_zstate_support(dc, context);
1895 DC_FP_END();
1896
1897 return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1898 }
1899
1900
populate_dml_pipes_from_context_fpu(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,enum dc_validate_mode validate_mode)1901 static int populate_dml_pipes_from_context_fpu(struct dc *dc,
1902 struct dc_state *context,
1903 display_e2e_pipe_params_st *pipes,
1904 enum dc_validate_mode validate_mode)
1905 {
1906 int ret;
1907
1908 DC_FP_START();
1909 ret = dcn35_populate_dml_pipes_from_context_fpu(dc, context, pipes, validate_mode);
1910 DC_FP_END();
1911
1912 return ret;
1913 }
1914
1915 static struct resource_funcs dcn36_res_pool_funcs = {
1916 .destroy = dcn36_destroy_resource_pool,
1917 .link_enc_create = dcn35_link_encoder_create,
1918 .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1919 .link_encs_assign = link_enc_cfg_link_encs_assign,
1920 .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1921 .hpo_frl_link_enc_create = dcn31_hpo_frl_link_encoder_create,
1922 .panel_cntl_create = dcn31_panel_cntl_create,
1923 .validate_bandwidth = dcn35_validate_bandwidth,
1924 .calculate_wm_and_dlg = NULL,
1925 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1926 .populate_dml_pipes = populate_dml_pipes_from_context_fpu,
1927 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1928 .release_pipe = dcn20_release_pipe,
1929 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1930 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1931 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1932 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1933 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1934 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1935 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1936 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1937 .update_bw_bounding_box = dcn35_update_bw_bounding_box,
1938 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1939 .get_panel_config_defaults = dcn35_get_panel_config_defaults,
1940 .get_preferred_eng_id_dpia = dcn36_get_preferred_eng_id_dpia,
1941 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
1942 .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch,
1943 .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params,
1944 .get_default_tiling_info = dcn10_get_default_tiling_info,
1945 };
1946
dcn36_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn36_resource_pool * pool)1947 static bool dcn36_resource_construct(
1948 uint8_t num_virtual_links,
1949 struct dc *dc,
1950 struct dcn36_resource_pool *pool)
1951 {
1952 int i;
1953 struct dc_context *ctx = dc->ctx;
1954 struct irq_service_init_data init_data;
1955
1956 #undef REG_STRUCT
1957 #define REG_STRUCT bios_regs
1958 bios_regs_init();
1959
1960 #undef REG_STRUCT
1961 #define REG_STRUCT clk_src_regs
1962 clk_src_regs_init(0, A),
1963 clk_src_regs_init(1, B),
1964 clk_src_regs_init(2, C),
1965 clk_src_regs_init(3, D),
1966 clk_src_regs_init(4, E);
1967
1968 #undef REG_STRUCT
1969 #define REG_STRUCT abm_regs
1970 abm_regs_init(0),
1971 abm_regs_init(1),
1972 abm_regs_init(2),
1973 abm_regs_init(3);
1974
1975 #undef REG_STRUCT
1976 #define REG_STRUCT dccg_regs
1977 dccg_regs_init();
1978
1979 ctx->dc_bios->regs = &bios_regs;
1980
1981 pool->base.res_cap = &res_cap_dcn36;
1982
1983 pool->base.funcs = &dcn36_res_pool_funcs;
1984
1985 /*************************************************
1986 * Resource + asic cap harcoding *
1987 *************************************************/
1988 pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1989 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1990 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1991 dc->caps.max_downscale_ratio = 600;
1992 dc->caps.i2c_speed_in_khz = 100;
1993 dc->caps.i2c_speed_in_khz_hdcp = 100;
1994 dc->caps.max_cursor_size = 256;
1995 dc->caps.min_horizontal_blanking_period = 80;
1996 dc->caps.dmdata_alloc_size = 2048;
1997 dc->caps.max_slave_planes = 3;
1998 dc->caps.max_slave_yuv_planes = 3;
1999 dc->caps.max_slave_rgb_planes = 3;
2000 dc->caps.post_blend_color_processing = true;
2001 dc->caps.force_dp_tps4_for_cp2520 = true;
2002 if (dc->config.forceHBR2CP2520)
2003 dc->caps.force_dp_tps4_for_cp2520 = false;
2004 dc->caps.hdmi_hpo = true;
2005 dc->caps.dp_hpo = true;
2006 dc->caps.dp_hdmi21_pcon_support = true;
2007
2008 dc->caps.edp_dsc_support = true;
2009 dc->caps.extended_aux_timeout_support = true;
2010 dc->caps.dmcub_support = true;
2011 dc->caps.is_apu = true;
2012 dc->caps.seamless_odm = true;
2013
2014 dc->caps.zstate_support = true;
2015 dc->caps.ips_support = true;
2016 dc->caps.max_v_total = (1 << 15) - 1;
2017 dc->caps.vtotal_limited_by_fp2 = true;
2018
2019 /* Color pipeline capabilities */
2020 dc->caps.color.dpp.dcn_arch = 1;
2021 dc->caps.color.dpp.input_lut_shared = 0;
2022 dc->caps.color.dpp.icsc = 1;
2023 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2024 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2025 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2026 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2027 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2028 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2029 dc->caps.color.dpp.post_csc = 1;
2030 dc->caps.color.dpp.gamma_corr = 1;
2031 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
2032 dc->caps.color.dpp.upsp_pre_scaler = 0;
2033
2034 dc->caps.color.dpp.hw_3d_lut = 0;
2035 dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1
2036 // no OGAM ROM on DCN301
2037 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2038 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2039 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2040 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2041 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2042 dc->caps.color.dpp.ocsc = 0;
2043
2044 dc->caps.color.mpc.gamut_remap = 1;
2045 dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2
2046 dc->caps.color.mpc.ogam_ram = 1;
2047 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2048 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2049 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2050 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2051 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2052 dc->caps.color.mpc.ocsc = 1;
2053 dc->caps.color.mpc.preblend = true;
2054 dc->caps.color.mpc.max_gamut_remap_coeff = dc_fixpt_from_fraction(S3D12_MAX, DIVIDER);
2055
2056 dc->caps.num_of_host_routers = 2;
2057 dc->caps.num_of_dpias_per_host_router = 2;
2058
2059 /* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order
2060 * to provide some margin.
2061 * It's expected for furture ASIC to have equal or higher value, in order to
2062 * have determinstic power improvement from generate to genration.
2063 * (i.e., we should not expect new ASIC generation with lower vmin rate)
2064 */
2065 dc->caps.max_disp_clock_khz_at_vmin = 650000;
2066
2067 /* Sequential ONO is based on ASIC. */
2068 if (dc->ctx->asic_id.hw_internal_rev >= 0x40)
2069 dc->caps.sequential_ono = true;
2070
2071 /* Use pipe context based otg sync logic */
2072 dc->config.use_pipe_ctx_sync_logic = true;
2073
2074 dc->config.disable_hbr_audio_dp2 = true;
2075 /* read VBIOS LTTPR caps */
2076 {
2077 if (ctx->dc_bios->funcs->get_lttpr_caps) {
2078 enum bp_result bp_query_result;
2079 uint8_t is_vbios_lttpr_enable = 0;
2080
2081 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
2082 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
2083 }
2084
2085 /* interop bit is implicit */
2086 {
2087 dc->caps.vbios_lttpr_aware = true;
2088 }
2089 }
2090 dc->check_config = config_defaults;
2091
2092 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2093 dc->debug = debug_defaults_drv;
2094
2095 /*HW default is to have all the FGCG enabled, SW no need to program them*/
2096 dc->debug.enable_fine_grain_clock_gating.u32All = 0xFFFF;
2097 // Init the vm_helper
2098 if (dc->vm_helper)
2099 vm_helper_init(dc->vm_helper, 16);
2100
2101 /*************************************************
2102 * Create resources *
2103 *************************************************/
2104
2105 /* Clock Sources for Pixel Clock*/
2106 pool->base.clock_sources[DCN36_CLK_SRC_PLL0] =
2107 dcn35_clock_source_create(ctx, ctx->dc_bios,
2108 CLOCK_SOURCE_COMBO_PHY_PLL0,
2109 &clk_src_regs[0], false);
2110 pool->base.clock_sources[DCN36_CLK_SRC_PLL1] =
2111 dcn35_clock_source_create(ctx, ctx->dc_bios,
2112 CLOCK_SOURCE_COMBO_PHY_PLL1,
2113 &clk_src_regs[1], false);
2114 pool->base.clock_sources[DCN36_CLK_SRC_PLL2] =
2115 dcn35_clock_source_create(ctx, ctx->dc_bios,
2116 CLOCK_SOURCE_COMBO_PHY_PLL2,
2117 &clk_src_regs[2], false);
2118 pool->base.clock_sources[DCN36_CLK_SRC_PLL3] =
2119 dcn35_clock_source_create(ctx, ctx->dc_bios,
2120 CLOCK_SOURCE_COMBO_PHY_PLL3,
2121 &clk_src_regs[3], false);
2122 pool->base.clock_sources[DCN36_CLK_SRC_PLL4] =
2123 dcn35_clock_source_create(ctx, ctx->dc_bios,
2124 CLOCK_SOURCE_COMBO_PHY_PLL4,
2125 &clk_src_regs[4], false);
2126
2127 pool->base.clk_src_count = DCN36_CLK_SRC_TOTAL;
2128
2129 /* todo: not reuse phy_pll registers */
2130 pool->base.dp_clock_source =
2131 dcn35_clock_source_create(ctx, ctx->dc_bios,
2132 CLOCK_SOURCE_ID_DP_DTO,
2133 &clk_src_regs[0], true);
2134
2135 for (i = 0; i < (int)pool->base.clk_src_count; i++) {
2136 if (pool->base.clock_sources[i] == NULL) {
2137 dm_error("DC: failed to create clock sources!\n");
2138 BREAK_TO_DEBUGGER();
2139 goto create_fail;
2140 }
2141 }
2142 /*temp till dml2 fully work without dml1*/
2143 dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip, DML_PROJECT_DCN31);
2144
2145 /* TODO: DCCG */
2146 pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2147 if (pool->base.dccg == NULL) {
2148 dm_error("DC: failed to create dccg!\n");
2149 BREAK_TO_DEBUGGER();
2150 goto create_fail;
2151 }
2152
2153 #undef REG_STRUCT
2154 #define REG_STRUCT pg_cntl_regs
2155 pg_cntl_dcn35_regs_init();
2156
2157 pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);
2158 if (pool->base.pg_cntl == NULL) {
2159 dm_error("DC: failed to create power gate control!\n");
2160 BREAK_TO_DEBUGGER();
2161 goto create_fail;
2162 }
2163
2164 /* TODO: IRQ */
2165 init_data.ctx = dc->ctx;
2166 pool->base.irqs = dal_irq_service_dcn36_create(&init_data);
2167 if (!pool->base.irqs)
2168 goto create_fail;
2169
2170 /* HUBBUB */
2171 pool->base.hubbub = dcn35_hubbub_create(ctx);
2172 if (pool->base.hubbub == NULL) {
2173 BREAK_TO_DEBUGGER();
2174 dm_error("DC: failed to create hubbub!\n");
2175 goto create_fail;
2176 }
2177
2178 /* DIO */
2179 pool->base.dio = dcn36_dio_create(ctx);
2180 if (pool->base.dio == NULL) {
2181 BREAK_TO_DEBUGGER();
2182 dm_error("DC: failed to create dio!\n");
2183 goto create_fail;
2184 }
2185
2186 /* HUBPs, DPPs, OPPs and TGs */
2187 for (i = 0; i < (int)pool->base.pipe_count; i++) {
2188 pool->base.hubps[i] = dcn35_hubp_create(ctx, i);
2189 if (pool->base.hubps[i] == NULL) {
2190 BREAK_TO_DEBUGGER();
2191 dm_error(
2192 "DC: failed to create hubps!\n");
2193 goto create_fail;
2194 }
2195
2196 pool->base.dpps[i] = dcn35_dpp_create(ctx, i);
2197 if (pool->base.dpps[i] == NULL) {
2198 BREAK_TO_DEBUGGER();
2199 dm_error(
2200 "DC: failed to create dpps!\n");
2201 goto create_fail;
2202 }
2203 }
2204
2205 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2206 pool->base.opps[i] = dcn35_opp_create(ctx, i);
2207 if (pool->base.opps[i] == NULL) {
2208 BREAK_TO_DEBUGGER();
2209 dm_error(
2210 "DC: failed to create output pixel processor!\n");
2211 goto create_fail;
2212 }
2213 }
2214
2215 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2216 pool->base.timing_generators[i] = dcn35_timing_generator_create(
2217 ctx, i);
2218 if (pool->base.timing_generators[i] == NULL) {
2219 BREAK_TO_DEBUGGER();
2220 dm_error("DC: failed to create tg!\n");
2221 goto create_fail;
2222 }
2223 }
2224 pool->base.timing_generator_count = i;
2225
2226 /* PSR */
2227 pool->base.psr = dmub_psr_create(ctx);
2228 if (pool->base.psr == NULL) {
2229 dm_error("DC: failed to create psr obj!\n");
2230 BREAK_TO_DEBUGGER();
2231 goto create_fail;
2232 }
2233
2234 /* Replay */
2235 pool->base.replay = dmub_replay_create(ctx);
2236 if (pool->base.replay == NULL) {
2237 dm_error("DC: failed to create replay obj!\n");
2238 BREAK_TO_DEBUGGER();
2239 goto create_fail;
2240 }
2241
2242 /* ABM */
2243 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2244 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2245 &abm_regs[i],
2246 &abm_shift,
2247 &abm_mask);
2248 if (pool->base.multiple_abms[i] == NULL) {
2249 dm_error("DC: failed to create abm for pipe %d!\n", i);
2250 BREAK_TO_DEBUGGER();
2251 goto create_fail;
2252 }
2253 }
2254
2255 /* MPC and DSC */
2256 pool->base.mpc = dcn35_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2257 if (pool->base.mpc == NULL) {
2258 BREAK_TO_DEBUGGER();
2259 dm_error("DC: failed to create mpc!\n");
2260 goto create_fail;
2261 }
2262
2263 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2264 pool->base.dscs[i] = dcn35_dsc_create(ctx, i);
2265 if (pool->base.dscs[i] == NULL) {
2266 BREAK_TO_DEBUGGER();
2267 dm_error("DC: failed to create display stream compressor %d!\n", i);
2268 goto create_fail;
2269 }
2270 }
2271
2272 /* DWB and MMHUBBUB */
2273 if (!dcn35_dwbc_create(ctx, &pool->base)) {
2274 BREAK_TO_DEBUGGER();
2275 dm_error("DC: failed to create dwbc!\n");
2276 goto create_fail;
2277 }
2278
2279 if (!dcn35_mmhubbub_create(ctx, &pool->base)) {
2280 BREAK_TO_DEBUGGER();
2281 dm_error("DC: failed to create mcif_wb!\n");
2282 goto create_fail;
2283 }
2284
2285 /* AUX and I2C */
2286 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2287 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2288 if (pool->base.engines[i] == NULL) {
2289 BREAK_TO_DEBUGGER();
2290 dm_error(
2291 "DC:failed to create aux engine!!\n");
2292 goto create_fail;
2293 }
2294 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2295 if (pool->base.hw_i2cs[i] == NULL) {
2296 BREAK_TO_DEBUGGER();
2297 dm_error(
2298 "DC:failed to create hw i2c!!\n");
2299 goto create_fail;
2300 }
2301 pool->base.sw_i2cs[i] = NULL;
2302 }
2303
2304 /* DCN3.5 has 6 DPIA */
2305 pool->base.usb4_dpia_count = 4;
2306 if (dc->debug.dpia_debug.bits.disable_dpia)
2307 pool->base.usb4_dpia_count = 0;
2308
2309 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2310 if (!resource_construct(num_virtual_links, dc, &pool->base,
2311 &res_create_funcs))
2312 goto create_fail;
2313
2314 /* HW Sequencer and Plane caps */
2315 dcn35_hw_sequencer_construct(dc);
2316
2317 dc->caps.max_planes = pool->base.pipe_count;
2318
2319 for (i = 0; i < (int)dc->caps.max_planes; ++i)
2320 dc->caps.planes[i] = plane_cap;
2321
2322 dc->caps.max_odm_combine_factor = 4;
2323
2324 dc->cap_funcs = cap_funcs;
2325
2326 dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
2327
2328 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
2329 dc->dml2_options.use_native_soc_bb_construction = true;
2330 dc->dml2_options.minimize_dispclk_using_odm = false;
2331 if (dc->config.EnableMinDispClkODM)
2332 dc->dml2_options.minimize_dispclk_using_odm = true;
2333 dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm;
2334
2335 resource_init_common_dml2_callbacks(dc, &dc->dml2_options);
2336 dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
2337
2338 dc->dml2_options.max_segments_per_hubp = 24;
2339 dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/
2340 dc->dml2_options.override_det_buffer_size_kbytes = true;
2341
2342 if (dc->config.sdpif_request_limit_words_per_umc == 0)
2343 dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/
2344
2345 return true;
2346
2347 create_fail:
2348
2349 dcn36_resource_destruct(pool);
2350
2351 return false;
2352 }
2353
dcn36_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2354 struct resource_pool *dcn36_create_resource_pool(
2355 const struct dc_init_data *init_data,
2356 struct dc *dc)
2357 {
2358 struct dcn36_resource_pool *pool =
2359 kzalloc_obj(struct dcn36_resource_pool);
2360
2361 if (!pool)
2362 return NULL;
2363
2364 if (dcn36_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
2365 return &pool->base;
2366
2367 BREAK_TO_DEBUGGER();
2368 kfree(pool);
2369 return NULL;
2370 }
2371