xref: /linux/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_vpg.h (revision db5d28c0bfe566908719bec8e25443aabecbb802)
1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #ifndef __DAL_DCN31_VPG_H__
27 #define __DAL_DCN31_VPG_H__
28 
29 #include "vpg.h"
30 
31 #define DCN31_VPG_FROM_VPG(vpg)\
32 	container_of(vpg, struct dcn31_vpg, base)
33 
34 #define VPG_DCN31_REG_LIST(id) \
35 	SRI(VPG_GENERIC_STATUS, VPG, id), \
36 	SRI(VPG_GENERIC_PACKET_ACCESS_CTRL, VPG, id), \
37 	SRI(VPG_GENERIC_PACKET_DATA, VPG, id), \
38 	SRI(VPG_GSP_FRAME_UPDATE_CTRL, VPG, id), \
39 	SRI(VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG, id), \
40 	SRI(VPG_MEM_PWR, VPG, id)
41 
42 struct dcn31_vpg_registers {
43 	uint32_t VPG_GENERIC_STATUS;
44 	uint32_t VPG_GENERIC_PACKET_ACCESS_CTRL;
45 	uint32_t VPG_GENERIC_PACKET_DATA;
46 	uint32_t VPG_GSP_FRAME_UPDATE_CTRL;
47 	uint32_t VPG_GSP_IMMEDIATE_UPDATE_CTRL;
48 	uint32_t VPG_MEM_PWR;
49 };
50 
51 #define DCN31_VPG_MASK_SH_LIST(mask_sh)\
52 	SE_SF(VPG0_VPG_GENERIC_STATUS, VPG_GENERIC_CONFLICT_OCCURED, mask_sh),\
53 	SE_SF(VPG0_VPG_GENERIC_STATUS, VPG_GENERIC_CONFLICT_CLR, mask_sh),\
54 	SE_SF(VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL, VPG_GENERIC_DATA_INDEX, mask_sh),\
55 	SE_SF(VPG0_VPG_GENERIC_PACKET_DATA, VPG_GENERIC_DATA_BYTE0, mask_sh),\
56 	SE_SF(VPG0_VPG_GENERIC_PACKET_DATA, VPG_GENERIC_DATA_BYTE1, mask_sh),\
57 	SE_SF(VPG0_VPG_GENERIC_PACKET_DATA, VPG_GENERIC_DATA_BYTE2, mask_sh),\
58 	SE_SF(VPG0_VPG_GENERIC_PACKET_DATA, VPG_GENERIC_DATA_BYTE3, mask_sh),\
59 	SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC0_FRAME_UPDATE, mask_sh),\
60 	SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC1_FRAME_UPDATE, mask_sh),\
61 	SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC2_FRAME_UPDATE, mask_sh),\
62 	SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC3_FRAME_UPDATE, mask_sh),\
63 	SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC4_FRAME_UPDATE, mask_sh),\
64 	SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC5_FRAME_UPDATE, mask_sh),\
65 	SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC6_FRAME_UPDATE, mask_sh),\
66 	SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC7_FRAME_UPDATE, mask_sh),\
67 	SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC8_FRAME_UPDATE, mask_sh),\
68 	SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC9_FRAME_UPDATE, mask_sh),\
69 	SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC10_FRAME_UPDATE, mask_sh),\
70 	SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC11_FRAME_UPDATE, mask_sh),\
71 	SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC12_FRAME_UPDATE, mask_sh),\
72 	SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC13_FRAME_UPDATE, mask_sh),\
73 	SE_SF(VPG0_VPG_GSP_FRAME_UPDATE_CTRL, VPG_GENERIC14_FRAME_UPDATE, mask_sh),\
74 	SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC0_IMMEDIATE_UPDATE, mask_sh),\
75 	SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC1_IMMEDIATE_UPDATE, mask_sh),\
76 	SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC2_IMMEDIATE_UPDATE, mask_sh),\
77 	SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC3_IMMEDIATE_UPDATE, mask_sh),\
78 	SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC4_IMMEDIATE_UPDATE, mask_sh),\
79 	SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC5_IMMEDIATE_UPDATE, mask_sh),\
80 	SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC6_IMMEDIATE_UPDATE, mask_sh),\
81 	SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC7_IMMEDIATE_UPDATE, mask_sh),\
82 	SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC8_IMMEDIATE_UPDATE, mask_sh),\
83 	SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC9_IMMEDIATE_UPDATE, mask_sh),\
84 	SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC10_IMMEDIATE_UPDATE, mask_sh),\
85 	SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC11_IMMEDIATE_UPDATE, mask_sh),\
86 	SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC12_IMMEDIATE_UPDATE, mask_sh),\
87 	SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC13_IMMEDIATE_UPDATE, mask_sh),\
88 	SE_SF(VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG_GENERIC14_IMMEDIATE_UPDATE, mask_sh),\
89 	SE_SF(VPG0_VPG_MEM_PWR, VPG_GSP_MEM_LIGHT_SLEEP_DIS, mask_sh),\
90 	SE_SF(VPG0_VPG_MEM_PWR, VPG_GSP_LIGHT_SLEEP_FORCE, mask_sh),\
91 	SE_SF(VPG0_VPG_MEM_PWR, VPG_GSP_MEM_PWR_STATE, mask_sh)
92 
93 #define VPG_DCN31_REG_FIELD_LIST(type) \
94 	type VPG_GENERIC_CONFLICT_OCCURED;\
95 	type VPG_GENERIC_CONFLICT_CLR;\
96 	type VPG_GENERIC_DATA_INDEX;\
97 	type VPG_GENERIC_DATA_BYTE0;\
98 	type VPG_GENERIC_DATA_BYTE1;\
99 	type VPG_GENERIC_DATA_BYTE2;\
100 	type VPG_GENERIC_DATA_BYTE3;\
101 	type VPG_GENERIC0_FRAME_UPDATE;\
102 	type VPG_GENERIC1_FRAME_UPDATE;\
103 	type VPG_GENERIC2_FRAME_UPDATE;\
104 	type VPG_GENERIC3_FRAME_UPDATE;\
105 	type VPG_GENERIC4_FRAME_UPDATE;\
106 	type VPG_GENERIC5_FRAME_UPDATE;\
107 	type VPG_GENERIC6_FRAME_UPDATE;\
108 	type VPG_GENERIC7_FRAME_UPDATE;\
109 	type VPG_GENERIC8_FRAME_UPDATE;\
110 	type VPG_GENERIC9_FRAME_UPDATE;\
111 	type VPG_GENERIC10_FRAME_UPDATE;\
112 	type VPG_GENERIC11_FRAME_UPDATE;\
113 	type VPG_GENERIC12_FRAME_UPDATE;\
114 	type VPG_GENERIC13_FRAME_UPDATE;\
115 	type VPG_GENERIC14_FRAME_UPDATE;\
116 	type VPG_GENERIC0_IMMEDIATE_UPDATE;\
117 	type VPG_GENERIC1_IMMEDIATE_UPDATE;\
118 	type VPG_GENERIC2_IMMEDIATE_UPDATE;\
119 	type VPG_GENERIC3_IMMEDIATE_UPDATE;\
120 	type VPG_GENERIC4_IMMEDIATE_UPDATE;\
121 	type VPG_GENERIC5_IMMEDIATE_UPDATE;\
122 	type VPG_GENERIC6_IMMEDIATE_UPDATE;\
123 	type VPG_GENERIC7_IMMEDIATE_UPDATE;\
124 	type VPG_GENERIC8_IMMEDIATE_UPDATE;\
125 	type VPG_GENERIC9_IMMEDIATE_UPDATE;\
126 	type VPG_GENERIC10_IMMEDIATE_UPDATE;\
127 	type VPG_GENERIC11_IMMEDIATE_UPDATE;\
128 	type VPG_GENERIC12_IMMEDIATE_UPDATE;\
129 	type VPG_GENERIC13_IMMEDIATE_UPDATE;\
130 	type VPG_GENERIC14_IMMEDIATE_UPDATE;\
131 	type VPG_GSP_MEM_LIGHT_SLEEP_DIS;\
132 	type VPG_GSP_LIGHT_SLEEP_FORCE;\
133 	type VPG_GSP_MEM_PWR_STATE
134 
135 struct dcn31_vpg_shift {
136 	VPG_DCN31_REG_FIELD_LIST(uint8_t);
137 };
138 
139 struct dcn31_vpg_mask {
140 	VPG_DCN31_REG_FIELD_LIST(uint32_t);
141 };
142 
143 struct dcn31_vpg {
144 	struct vpg base;
145 	const struct dcn31_vpg_registers *regs;
146 	const struct dcn31_vpg_shift *vpg_shift;
147 	const struct dcn31_vpg_mask *vpg_mask;
148 };
149 
150 void vpg31_poweron(
151 		struct vpg *vpg);
152 
153 void vpg31_powerdown(
154 		struct vpg *vpg);
155 
156 void vpg31_construct(struct dcn31_vpg *vpg31,
157 	struct dc_context *ctx,
158 	uint32_t inst,
159 	const struct dcn31_vpg_registers *vpg_regs,
160 	const struct dcn31_vpg_shift *vpg_shift,
161 	const struct dcn31_vpg_mask *vpg_mask);
162 
163 #endif
164