1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 #ifndef _dcn_4_1_0_OFFSET_HEADER 6 #define _dcn_4_1_0_OFFSET_HEADER 7 8 9 10 // addressBlock: dcn_dcec_dccg_dccg_dfs_dispdec 11 // base address: 0x0 12 #define regDENTIST_DISPCLK_CNTL 0x0064 13 #define regDENTIST_DISPCLK_CNTL_BASE_IDX 1 14 15 16 // addressBlock: dcn_dcec_dccg_dccg_dispdec 17 // base address: 0x0 18 #define regPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040 19 #define regPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1 20 #define regPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041 21 #define regPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1 22 #define regPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042 23 #define regPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1 24 #define regPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043 25 #define regPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1 26 #define regDP_DTO_DBUF_EN 0x0044 27 #define regDP_DTO_DBUF_EN_BASE_IDX 1 28 #define regDSCCLK3_DTO_PARAM 0x0045 29 #define regDSCCLK3_DTO_PARAM_BASE_IDX 1 30 #define regDSCCLK4_DTO_PARAM 0x0046 31 #define regDSCCLK4_DTO_PARAM_BASE_IDX 1 32 #define regDSCCLK5_DTO_PARAM 0x0047 33 #define regDSCCLK5_DTO_PARAM_BASE_IDX 1 34 #define regDPREFCLK_CGTT_BLK_CTRL_REG 0x0048 35 #define regDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 36 #define regDCCG_GATE_DISABLE_CNTL4 0x0049 37 #define regDCCG_GATE_DISABLE_CNTL4_BASE_IDX 1 38 #define regDPSTREAMCLK_CNTL 0x004a 39 #define regDPSTREAMCLK_CNTL_BASE_IDX 1 40 #define regREFCLK_CGTT_BLK_CTRL_REG 0x004b 41 #define regREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 42 #define regPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c 43 #define regPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1 1 44 #define regDCCG_GLOBAL_FGCG_REP_CNTL 0x0050 45 #define regDCCG_GLOBAL_FGCG_REP_CNTL_BASE_IDX 1 46 #define regSYMCLKG_CLOCK_ENABLE 0x0057 47 #define regSYMCLKG_CLOCK_ENABLE_BASE_IDX 1 48 #define regDPREFCLK_CNTL 0x0058 49 #define regDPREFCLK_CNTL_BASE_IDX 1 50 #define regAOMCLK0_CNTL 0x0059 51 #define regAOMCLK0_CNTL_BASE_IDX 1 52 #define regAOMCLK1_CNTL 0x005a 53 #define regAOMCLK1_CNTL_BASE_IDX 1 54 #define regAOMCLK2_CNTL 0x005b 55 #define regAOMCLK2_CNTL_BASE_IDX 1 56 #define regDCCG_AUDIO_DTO2_PHASE 0x005c 57 #define regDCCG_AUDIO_DTO2_PHASE_BASE_IDX 1 58 #define regDCCG_AUDIO_DTO2_MODULO 0x005d 59 #define regDCCG_AUDIO_DTO2_MODULO_BASE_IDX 1 60 #define regDCE_VERSION 0x005e 61 #define regDCE_VERSION_BASE_IDX 1 62 #define regPHYPLLG_PIXCLK_RESYNC_CNTL 0x005f 63 #define regPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX 1 64 #define regSYMCLK32_SE_CNTL 0x0065 65 #define regSYMCLK32_SE_CNTL_BASE_IDX 1 66 #define regSYMCLK32_LE_CNTL 0x0066 67 #define regSYMCLK32_LE_CNTL_BASE_IDX 1 68 #define regDTBCLK_P_CNTL 0x0068 69 #define regDTBCLK_P_CNTL_BASE_IDX 1 70 #define regDCCG_GATE_DISABLE_CNTL5 0x0069 71 #define regDCCG_GATE_DISABLE_CNTL5_BASE_IDX 1 72 #define regDSCCLK0_DTO_PARAM 0x006c 73 #define regDSCCLK0_DTO_PARAM_BASE_IDX 1 74 #define regDSCCLK1_DTO_PARAM 0x006d 75 #define regDSCCLK1_DTO_PARAM_BASE_IDX 1 76 #define regDSCCLK2_DTO_PARAM 0x006e 77 #define regDSCCLK2_DTO_PARAM_BASE_IDX 1 78 #define regOTG_PIXEL_RATE_DIV 0x006f 79 #define regOTG_PIXEL_RATE_DIV_BASE_IDX 1 80 #define regMILLISECOND_TIME_BASE_DIV 0x0070 81 #define regMILLISECOND_TIME_BASE_DIV_BASE_IDX 1 82 #define regDISPCLK_FREQ_CHANGE_CNTL 0x0071 83 #define regDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1 84 #define regDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072 85 #define regDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1 86 #define regDCCG_GATE_DISABLE_CNTL 0x0074 87 #define regDCCG_GATE_DISABLE_CNTL_BASE_IDX 1 88 #define regDISPCLK_CGTT_BLK_CTRL_REG 0x0075 89 #define regDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 90 #define regSOCCLK_CGTT_BLK_CTRL_REG 0x0076 91 #define regSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 92 #define regDCCG_CAC_STATUS 0x0077 93 #define regDCCG_CAC_STATUS_BASE_IDX 1 94 #define regPIXCLK1_RESYNC_CNTL 0x0078 95 #define regPIXCLK1_RESYNC_CNTL_BASE_IDX 1 96 #define regPIXCLK2_RESYNC_CNTL 0x0079 97 #define regPIXCLK2_RESYNC_CNTL_BASE_IDX 1 98 #define regPIXCLK0_RESYNC_CNTL 0x007a 99 #define regPIXCLK0_RESYNC_CNTL_BASE_IDX 1 100 #define regMICROSECOND_TIME_BASE_DIV 0x007b 101 #define regMICROSECOND_TIME_BASE_DIV_BASE_IDX 1 102 #define regDCCG_GATE_DISABLE_CNTL2 0x007c 103 #define regDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1 104 #define regSYMCLK_CGTT_BLK_CTRL_REG 0x007d 105 #define regSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 106 #define regPHYPLLF_PIXCLK_RESYNC_CNTL 0x007e 107 #define regPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1 108 #define regDCCG_DISP_CNTL_REG 0x007f 109 #define regDCCG_DISP_CNTL_REG_BASE_IDX 1 110 #define regOTG0_PIXEL_RATE_CNTL 0x0080 111 #define regOTG0_PIXEL_RATE_CNTL_BASE_IDX 1 112 #define regDP_DTO0_PHASE 0x0081 113 #define regDP_DTO0_PHASE_BASE_IDX 1 114 #define regDP_DTO0_MODULO 0x0082 115 #define regDP_DTO0_MODULO_BASE_IDX 1 116 #define regOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083 117 #define regOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 118 #define regOTG1_PIXEL_RATE_CNTL 0x0084 119 #define regOTG1_PIXEL_RATE_CNTL_BASE_IDX 1 120 #define regDP_DTO1_PHASE 0x0085 121 #define regDP_DTO1_PHASE_BASE_IDX 1 122 #define regDP_DTO1_MODULO 0x0086 123 #define regDP_DTO1_MODULO_BASE_IDX 1 124 #define regOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087 125 #define regOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 126 #define regOTG2_PIXEL_RATE_CNTL 0x0088 127 #define regOTG2_PIXEL_RATE_CNTL_BASE_IDX 1 128 #define regDP_DTO2_PHASE 0x0089 129 #define regDP_DTO2_PHASE_BASE_IDX 1 130 #define regDP_DTO2_MODULO 0x008a 131 #define regDP_DTO2_MODULO_BASE_IDX 1 132 #define regOTG2_PHYPLL_PIXEL_RATE_CNTL 0x008b 133 #define regOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 134 #define regOTG3_PIXEL_RATE_CNTL 0x008c 135 #define regOTG3_PIXEL_RATE_CNTL_BASE_IDX 1 136 #define regDP_DTO3_PHASE 0x008d 137 #define regDP_DTO3_PHASE_BASE_IDX 1 138 #define regDP_DTO3_MODULO 0x008e 139 #define regDP_DTO3_MODULO_BASE_IDX 1 140 #define regOTG3_PHYPLL_PIXEL_RATE_CNTL 0x008f 141 #define regOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 142 #define regOTG4_PIXEL_RATE_CNTL 0x0090 143 #define regOTG4_PIXEL_RATE_CNTL_BASE_IDX 1 144 #define regDP_DTO4_PHASE 0x0091 145 #define regDP_DTO4_PHASE_BASE_IDX 1 146 #define regDP_DTO4_MODULO 0x0092 147 #define regDP_DTO4_MODULO_BASE_IDX 1 148 #define regOTG4_PHYPLL_PIXEL_RATE_CNTL 0x0093 149 #define regOTG4_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 150 #define regOTG5_PIXEL_RATE_CNTL 0x0094 151 #define regOTG5_PIXEL_RATE_CNTL_BASE_IDX 1 152 #define regDP_DTO5_PHASE 0x0095 153 #define regDP_DTO5_PHASE_BASE_IDX 1 154 #define regDP_DTO5_MODULO 0x0096 155 #define regDP_DTO5_MODULO_BASE_IDX 1 156 #define regOTG5_PHYPLL_PIXEL_RATE_CNTL 0x0097 157 #define regOTG5_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 158 #define regDPPCLK_CGTT_BLK_CTRL_REG 0x0098 159 #define regDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 160 #define regDPPCLK0_DTO_PARAM 0x0099 161 #define regDPPCLK0_DTO_PARAM_BASE_IDX 1 162 #define regDPPCLK1_DTO_PARAM 0x009a 163 #define regDPPCLK1_DTO_PARAM_BASE_IDX 1 164 #define regDPPCLK2_DTO_PARAM 0x009b 165 #define regDPPCLK2_DTO_PARAM_BASE_IDX 1 166 #define regDPPCLK3_DTO_PARAM 0x009c 167 #define regDPPCLK3_DTO_PARAM_BASE_IDX 1 168 #define regDPPCLK4_DTO_PARAM 0x009d 169 #define regDPPCLK4_DTO_PARAM_BASE_IDX 1 170 #define regDPPCLK5_DTO_PARAM 0x009e 171 #define regDPPCLK5_DTO_PARAM_BASE_IDX 1 172 #define regDCCG_CAC_STATUS2 0x009f 173 #define regDCCG_CAC_STATUS2_BASE_IDX 1 174 #define regSYMCLKA_CLOCK_ENABLE 0x00a0 175 #define regSYMCLKA_CLOCK_ENABLE_BASE_IDX 1 176 #define regSYMCLKB_CLOCK_ENABLE 0x00a1 177 #define regSYMCLKB_CLOCK_ENABLE_BASE_IDX 1 178 #define regSYMCLKC_CLOCK_ENABLE 0x00a2 179 #define regSYMCLKC_CLOCK_ENABLE_BASE_IDX 1 180 #define regSYMCLKD_CLOCK_ENABLE 0x00a3 181 #define regSYMCLKD_CLOCK_ENABLE_BASE_IDX 1 182 #define regSYMCLKE_CLOCK_ENABLE 0x00a4 183 #define regSYMCLKE_CLOCK_ENABLE_BASE_IDX 1 184 #define regSYMCLKF_CLOCK_ENABLE 0x00a5 185 #define regSYMCLKF_CLOCK_ENABLE_BASE_IDX 1 186 #define regDCCG_SOFT_RESET 0x00a6 187 #define regDCCG_SOFT_RESET_BASE_IDX 1 188 #define regDSCCLK_DTO_CTRL 0x00a7 189 #define regDSCCLK_DTO_CTRL_BASE_IDX 1 190 #define regDPPCLK_CTRL 0x00a8 191 #define regDPPCLK_CTRL_BASE_IDX 1 192 #define regDCCG_GATE_DISABLE_CNTL6 0x00a9 193 #define regDCCG_GATE_DISABLE_CNTL6_BASE_IDX 1 194 #define regSYMCLK_PSP_CNTL 0x00aa 195 #define regSYMCLK_PSP_CNTL_BASE_IDX 1 196 #define regDCCG_AUDIO_DTO_SOURCE 0x00ab 197 #define regDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1 198 #define regDCCG_AUDIO_DTO0_PHASE 0x00ac 199 #define regDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1 200 #define regDCCG_AUDIO_DTO0_MODULE 0x00ad 201 #define regDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1 202 #define regDCCG_AUDIO_DTO1_PHASE 0x00ae 203 #define regDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1 204 #define regDCCG_AUDIO_DTO1_MODULE 0x00af 205 #define regDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1 206 #define regDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0 207 #define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1 208 #define regDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1 209 #define regDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1 210 #define regDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2 211 #define regDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1 212 #define regDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3 213 #define regDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1 214 #define regDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4 215 #define regDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1 216 #define regDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5 217 #define regDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1 218 #define regDPPCLK_DTO_CTRL 0x00b6 219 #define regDPPCLK_DTO_CTRL_BASE_IDX 1 220 #define regDCCG_VSYNC_CNT_CTRL 0x00b8 221 #define regDCCG_VSYNC_CNT_CTRL_BASE_IDX 1 222 #define regDCCG_VSYNC_CNT_INT_CTRL 0x00b9 223 #define regDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1 224 #define regFORCE_SYMCLK_DISABLE 0x00ba 225 #define regFORCE_SYMCLK_DISABLE_BASE_IDX 1 226 #define regDCCG_TEST_CLK_SEL 0x00be 227 #define regDCCG_TEST_CLK_SEL_BASE_IDX 1 228 #define regHDMICHARCLK0_CLOCK_CNTL 0x004a 229 #define regHDMICHARCLK0_CLOCK_CNTL_BASE_IDX 2 230 #define regHDMICHARCLK1_CLOCK_CNTL 0x004b 231 #define regHDMICHARCLK1_CLOCK_CNTL_BASE_IDX 2 232 #define regHDMICHARCLK2_CLOCK_CNTL 0x004c 233 #define regHDMICHARCLK2_CLOCK_CNTL_BASE_IDX 2 234 #define regHDMICHARCLK3_CLOCK_CNTL 0x004d 235 #define regHDMICHARCLK3_CLOCK_CNTL_BASE_IDX 2 236 #define regHDMICHARCLK4_CLOCK_CNTL 0x004e 237 #define regHDMICHARCLK4_CLOCK_CNTL_BASE_IDX 2 238 #define regHDMICHARCLK5_CLOCK_CNTL 0x004f 239 #define regHDMICHARCLK5_CLOCK_CNTL_BASE_IDX 2 240 #define regPHYASYMCLK_CLOCK_CNTL 0x0052 241 #define regPHYASYMCLK_CLOCK_CNTL_BASE_IDX 2 242 #define regPHYBSYMCLK_CLOCK_CNTL 0x0053 243 #define regPHYBSYMCLK_CLOCK_CNTL_BASE_IDX 2 244 #define regPHYCSYMCLK_CLOCK_CNTL 0x0054 245 #define regPHYCSYMCLK_CLOCK_CNTL_BASE_IDX 2 246 #define regPHYDSYMCLK_CLOCK_CNTL 0x0055 247 #define regPHYDSYMCLK_CLOCK_CNTL_BASE_IDX 2 248 #define regPHYESYMCLK_CLOCK_CNTL 0x0056 249 #define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX 2 250 #define regPHYFSYMCLK_CLOCK_CNTL 0x0057 251 #define regPHYFSYMCLK_CLOCK_CNTL_BASE_IDX 2 252 #define regPHYGSYMCLK_CLOCK_CNTL 0x0058 253 #define regPHYGSYMCLK_CLOCK_CNTL_BASE_IDX 2 254 #define regHDMISTREAMCLK_CNTL 0x0059 255 #define regHDMISTREAMCLK_CNTL_BASE_IDX 2 256 #define regDCCG_GATE_DISABLE_CNTL3 0x005a 257 #define regDCCG_GATE_DISABLE_CNTL3_BASE_IDX 2 258 #define regHDMISTREAMCLK0_DTO_PARAM 0x005b 259 #define regHDMISTREAMCLK0_DTO_PARAM_BASE_IDX 2 260 261 // base address: 0x0 262 263 264 // base address: 0x30 265 266 267 // addressBlock: dcn_dcec_dmu_fgsec_dispdec 268 // base address: 0x0 269 #define regDMCUB_RBBMIF_SEC_CNTL 0x017a 270 #define regDMCUB_RBBMIF_SEC_CNTL_BASE_IDX 2 271 272 // addressBlock: dcn_dcec_dmu_rbbmif_dispdec 273 // base address: 0x0 274 #define regRBBMIF_TIMEOUT 0x017f 275 #define regRBBMIF_TIMEOUT_BASE_IDX 2 276 #define regRBBMIF_STATUS 0x0180 277 #define regRBBMIF_STATUS_BASE_IDX 2 278 #define regRBBMIF_STATUS_2 0x0181 279 #define regRBBMIF_STATUS_2_BASE_IDX 2 280 #define regRBBMIF_INT_STATUS 0x0182 281 #define regRBBMIF_INT_STATUS_BASE_IDX 2 282 #define regRBBMIF_TIMEOUT_DIS 0x0183 283 #define regRBBMIF_TIMEOUT_DIS_BASE_IDX 2 284 #define regRBBMIF_TIMEOUT_DIS_2 0x0184 285 #define regRBBMIF_TIMEOUT_DIS_2_BASE_IDX 2 286 #define regRBBMIF_STATUS_FLAG 0x0185 287 #define regRBBMIF_STATUS_FLAG_BASE_IDX 2 288 289 // addressBlock: dcn_dcec_dmu_ihc_dispdec 290 // base address: 0x0 291 #define regDC_GPU_TIMER_START_POSITION_V_UPDATE 0x0126 292 #define regDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2 293 #define regDC_GPU_TIMER_START_POSITION_VSTARTUP 0x0127 294 #define regDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX 2 295 #define regDC_GPU_TIMER_READ 0x0128 296 #define regDC_GPU_TIMER_READ_BASE_IDX 2 297 #define regDC_GPU_TIMER_READ_CNTL 0x0129 298 #define regDC_GPU_TIMER_READ_CNTL_BASE_IDX 2 299 #define regDISP_INTERRUPT_STATUS 0x012a 300 #define regDISP_INTERRUPT_STATUS_BASE_IDX 2 301 #define regDISP_INTERRUPT_STATUS_CONTINUE 0x012b 302 #define regDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 303 #define regDISP_INTERRUPT_STATUS_CONTINUE2 0x012c 304 #define regDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2 305 #define regDISP_INTERRUPT_STATUS_CONTINUE3 0x012d 306 #define regDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2 307 #define regDISP_INTERRUPT_STATUS_CONTINUE4 0x012e 308 #define regDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2 309 #define regDISP_INTERRUPT_STATUS_CONTINUE5 0x012f 310 #define regDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2 311 #define regDISP_INTERRUPT_STATUS_CONTINUE6 0x0130 312 #define regDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2 313 #define regDISP_INTERRUPT_STATUS_CONTINUE7 0x0131 314 #define regDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2 315 #define regDISP_INTERRUPT_STATUS_CONTINUE8 0x0132 316 #define regDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2 317 #define regDISP_INTERRUPT_STATUS_CONTINUE9 0x0133 318 #define regDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2 319 #define regDISP_INTERRUPT_STATUS_CONTINUE10 0x0134 320 #define regDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2 321 #define regDISP_INTERRUPT_STATUS_CONTINUE11 0x0135 322 #define regDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2 323 #define regDISP_INTERRUPT_STATUS_CONTINUE12 0x0136 324 #define regDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX 2 325 #define regDISP_INTERRUPT_STATUS_CONTINUE13 0x0137 326 #define regDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX 2 327 #define regDISP_INTERRUPT_STATUS_CONTINUE14 0x0138 328 #define regDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX 2 329 #define regDISP_INTERRUPT_STATUS_CONTINUE15 0x0139 330 #define regDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX 2 331 #define regDISP_INTERRUPT_STATUS_CONTINUE16 0x013a 332 #define regDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX 2 333 #define regDISP_INTERRUPT_STATUS_CONTINUE17 0x013b 334 #define regDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX 2 335 #define regDISP_INTERRUPT_STATUS_CONTINUE18 0x013c 336 #define regDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX 2 337 #define regDISP_INTERRUPT_STATUS_CONTINUE19 0x013d 338 #define regDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX 2 339 #define regDISP_INTERRUPT_STATUS_CONTINUE20 0x013e 340 #define regDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX 2 341 #define regDISP_INTERRUPT_STATUS_CONTINUE21 0x013f 342 #define regDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX 2 343 #define regDISP_INTERRUPT_STATUS_CONTINUE22 0x0140 344 #define regDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX 2 345 #define regDC_GPU_TIMER_START_POSITION_VREADY 0x0141 346 #define regDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX 2 347 #define regDC_GPU_TIMER_START_POSITION_FLIP 0x0142 348 #define regDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX 2 349 #define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0x0143 350 #define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX 2 351 #define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0x0144 352 #define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX 2 353 #define regDISP_INTERRUPT_STATUS_CONTINUE23 0x0145 354 #define regDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX 2 355 #define regDISP_INTERRUPT_STATUS_CONTINUE24 0x0146 356 #define regDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX 2 357 #define regDISP_INTERRUPT_STATUS_CONTINUE25 0x0147 358 #define regDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX 2 359 #define regDCCG_INTERRUPT_DEST 0x0148 360 #define regDCCG_INTERRUPT_DEST_BASE_IDX 2 361 #define regDMU_INTERRUPT_DEST 0x0149 362 #define regDMU_INTERRUPT_DEST_BASE_IDX 2 363 #define regDMU_INTERRUPT_DEST2 0x014a 364 #define regDMU_INTERRUPT_DEST2_BASE_IDX 2 365 #define regDCPG_INTERRUPT_DEST 0x014b 366 #define regDCPG_INTERRUPT_DEST_BASE_IDX 2 367 #define regDCPG_INTERRUPT_DEST2 0x014c 368 #define regDCPG_INTERRUPT_DEST2_BASE_IDX 2 369 #define regMMHUBBUB_INTERRUPT_DEST 0x014d 370 #define regMMHUBBUB_INTERRUPT_DEST_BASE_IDX 2 371 #define regWB_INTERRUPT_DEST 0x014e 372 #define regWB_INTERRUPT_DEST_BASE_IDX 2 373 #define regDCHUB_INTERRUPT_DEST 0x014f 374 #define regDCHUB_INTERRUPT_DEST_BASE_IDX 2 375 #define regDCHUB_PERFCOUNTER_INTERRUPT_DEST 0x0150 376 #define regDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 377 #define regDCHUB_INTERRUPT_DEST2 0x0151 378 #define regDCHUB_INTERRUPT_DEST2_BASE_IDX 2 379 #define regDPP_PERFCOUNTER_INTERRUPT_DEST 0x0152 380 #define regDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 381 #define regMPC_INTERRUPT_DEST 0x0153 382 #define regMPC_INTERRUPT_DEST_BASE_IDX 2 383 #define regOPP_INTERRUPT_DEST 0x0154 384 #define regOPP_INTERRUPT_DEST_BASE_IDX 2 385 #define regOPTC_INTERRUPT_DEST 0x0155 386 #define regOPTC_INTERRUPT_DEST_BASE_IDX 2 387 #define regOTG0_INTERRUPT_DEST 0x0156 388 #define regOTG0_INTERRUPT_DEST_BASE_IDX 2 389 #define regOTG1_INTERRUPT_DEST 0x0157 390 #define regOTG1_INTERRUPT_DEST_BASE_IDX 2 391 #define regOTG2_INTERRUPT_DEST 0x0158 392 #define regOTG2_INTERRUPT_DEST_BASE_IDX 2 393 #define regOTG3_INTERRUPT_DEST 0x0159 394 #define regOTG3_INTERRUPT_DEST_BASE_IDX 2 395 #define regOTG4_INTERRUPT_DEST 0x015a 396 #define regOTG4_INTERRUPT_DEST_BASE_IDX 2 397 #define regOTG5_INTERRUPT_DEST 0x015b 398 #define regOTG5_INTERRUPT_DEST_BASE_IDX 2 399 #define regDIG_INTERRUPT_DEST 0x015c 400 #define regDIG_INTERRUPT_DEST_BASE_IDX 2 401 #define regI2C_DDC_HPD_INTERRUPT_DEST 0x015d 402 #define regI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX 2 403 #define regHDCP_INTERRUPT_DEST 0x015e 404 #define regHDCP_INTERRUPT_DEST_BASE_IDX 2 405 #define regDIO_INTERRUPT_DEST 0x015f 406 #define regDIO_INTERRUPT_DEST_BASE_IDX 2 407 #define regDCIO_INTERRUPT_DEST 0x0160 408 #define regDCIO_INTERRUPT_DEST_BASE_IDX 2 409 #define regHPD_INTERRUPT_DEST 0x0161 410 #define regHPD_INTERRUPT_DEST_BASE_IDX 2 411 #define regAZ_INTERRUPT_DEST 0x0162 412 #define regAZ_INTERRUPT_DEST_BASE_IDX 2 413 #define regAUX_INTERRUPT_DEST 0x0163 414 #define regAUX_INTERRUPT_DEST_BASE_IDX 2 415 #define regDSC_INTERRUPT_DEST 0x0164 416 #define regDSC_INTERRUPT_DEST_BASE_IDX 2 417 #define regHPO_INTERRUPT_DEST 0x0165 418 #define regHPO_INTERRUPT_DEST_BASE_IDX 2 419 420 421 // addressBlock: dcn_dcec_dmu_dmu_misc_dispdec 422 // base address: 0x0 423 #define regCC_DC_PIPE_DIS 0x00ca 424 #define regCC_DC_PIPE_DIS_BASE_IDX 2 425 #define regDMU_CLK_CNTL 0x00cb 426 #define regDMU_CLK_CNTL_BASE_IDX 2 427 #define regDMCUB_SMU_INTERRUPT_CNTL 0x00cd 428 #define regDMCUB_SMU_INTERRUPT_CNTL_BASE_IDX 2 429 #define regSMU_INTERRUPT_CONTROL 0x00ce 430 #define regSMU_INTERRUPT_CONTROL_BASE_IDX 2 431 #define regDMU_MISC_ALLOW_DS_FORCE 0x00d6 432 #define regDMU_MISC_ALLOW_DS_FORCE_BASE_IDX 2 433 #define regDMU_DISPCLK_CGTT_BLK_CTRL_REG 0x00d8 434 #define regDMU_DISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 2 435 #define regDMU_SOCCLK_CGTT_BLK_CTRL_REG 0x00d9 436 #define regDMU_SOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 2 437 438 439 // addressBlock: dcn_dcec_dmu_dc_pg_dispdec 440 // base address: 0x0 441 #define regDOMAIN0_PG_CONFIG 0x0080 442 #define regDOMAIN0_PG_CONFIG_BASE_IDX 2 443 #define regDOMAIN0_PG_STATUS 0x0081 444 #define regDOMAIN0_PG_STATUS_BASE_IDX 2 445 #define regDOMAIN1_PG_CONFIG 0x0082 446 #define regDOMAIN1_PG_CONFIG_BASE_IDX 2 447 #define regDOMAIN1_PG_STATUS 0x0083 448 #define regDOMAIN1_PG_STATUS_BASE_IDX 2 449 #define regDOMAIN2_PG_CONFIG 0x0084 450 #define regDOMAIN2_PG_CONFIG_BASE_IDX 2 451 #define regDOMAIN2_PG_STATUS 0x0085 452 #define regDOMAIN2_PG_STATUS_BASE_IDX 2 453 #define regDOMAIN3_PG_CONFIG 0x0086 454 #define regDOMAIN3_PG_CONFIG_BASE_IDX 2 455 #define regDOMAIN3_PG_STATUS 0x0087 456 #define regDOMAIN3_PG_STATUS_BASE_IDX 2 457 #define regDOMAIN16_PG_CONFIG 0x0089 458 #define regDOMAIN16_PG_CONFIG_BASE_IDX 2 459 #define regDOMAIN16_PG_STATUS 0x008a 460 #define regDOMAIN16_PG_STATUS_BASE_IDX 2 461 #define regDOMAIN17_PG_CONFIG 0x008b 462 #define regDOMAIN17_PG_CONFIG_BASE_IDX 2 463 #define regDOMAIN17_PG_STATUS 0x008c 464 #define regDOMAIN17_PG_STATUS_BASE_IDX 2 465 #define regDOMAIN18_PG_CONFIG 0x008d 466 #define regDOMAIN18_PG_CONFIG_BASE_IDX 2 467 #define regDOMAIN18_PG_STATUS 0x008e 468 #define regDOMAIN18_PG_STATUS_BASE_IDX 2 469 #define regDOMAIN19_PG_CONFIG 0x008f 470 #define regDOMAIN19_PG_CONFIG_BASE_IDX 2 471 #define regDOMAIN19_PG_STATUS 0x0090 472 #define regDOMAIN19_PG_STATUS_BASE_IDX 2 473 #define regDOMAIN22_PG_CONFIG 0x0092 474 #define regDOMAIN22_PG_CONFIG_BASE_IDX 2 475 #define regDOMAIN22_PG_STATUS 0x0093 476 #define regDOMAIN22_PG_STATUS_BASE_IDX 2 477 #define regDOMAIN23_PG_CONFIG 0x0094 478 #define regDOMAIN23_PG_CONFIG_BASE_IDX 2 479 #define regDOMAIN23_PG_STATUS 0x0095 480 #define regDOMAIN23_PG_STATUS_BASE_IDX 2 481 #define regDOMAIN24_PG_CONFIG 0x0096 482 #define regDOMAIN24_PG_CONFIG_BASE_IDX 2 483 #define regDOMAIN24_PG_STATUS 0x0097 484 #define regDOMAIN24_PG_STATUS_BASE_IDX 2 485 #define regDOMAIN25_PG_CONFIG 0x0098 486 #define regDOMAIN25_PG_CONFIG_BASE_IDX 2 487 #define regDOMAIN25_PG_STATUS 0x0099 488 #define regDOMAIN25_PG_STATUS_BASE_IDX 2 489 #define regDCPG_INTERRUPT_STATUS 0x009a 490 #define regDCPG_INTERRUPT_STATUS_BASE_IDX 2 491 #define regDCPG_INTERRUPT_STATUS_2 0x009b 492 #define regDCPG_INTERRUPT_STATUS_2_BASE_IDX 2 493 #define regDCPG_INTERRUPT_STATUS_3 0x009c 494 #define regDCPG_INTERRUPT_STATUS_3_BASE_IDX 2 495 #define regDCPG_INTERRUPT_CONTROL_1 0x009d 496 #define regDCPG_INTERRUPT_CONTROL_1_BASE_IDX 2 497 #define regDCPG_INTERRUPT_CONTROL_2 0x009e 498 #define regDCPG_INTERRUPT_CONTROL_2_BASE_IDX 2 499 #define regDCPG_INTERRUPT_CONTROL_3 0x009f 500 #define regDCPG_INTERRUPT_CONTROL_3_BASE_IDX 2 501 #define regDC_IP_REQUEST_CNTL 0x00a0 502 #define regDC_IP_REQUEST_CNTL_BASE_IDX 2 503 #define regDC_PGCNTL_STATUS_REG 0x00a1 504 #define regDC_PGCNTL_STATUS_REG_BASE_IDX 2 505 #define regLONO_MEM_PWR_REQ_CNTL 0x00a4 506 #define regLONO_MEM_PWR_REQ_CNTL_BASE_IDX 2 507 508 509 // addressBlock: dcn_dcec_dmu_dmcub_dispdec 510 // base address: 0x0 511 #define regDMCUB_REGION0_OFFSET 0x018e 512 #define regDMCUB_REGION0_OFFSET_BASE_IDX 2 513 #define regDMCUB_REGION0_OFFSET_HIGH 0x018f 514 #define regDMCUB_REGION0_OFFSET_HIGH_BASE_IDX 2 515 #define regDMCUB_REGION1_OFFSET 0x0190 516 #define regDMCUB_REGION1_OFFSET_BASE_IDX 2 517 #define regDMCUB_REGION1_OFFSET_HIGH 0x0191 518 #define regDMCUB_REGION1_OFFSET_HIGH_BASE_IDX 2 519 #define regDMCUB_REGION2_OFFSET 0x0192 520 #define regDMCUB_REGION2_OFFSET_BASE_IDX 2 521 #define regDMCUB_REGION2_OFFSET_HIGH 0x0193 522 #define regDMCUB_REGION2_OFFSET_HIGH_BASE_IDX 2 523 #define regDMCUB_REGION4_OFFSET 0x0196 524 #define regDMCUB_REGION4_OFFSET_BASE_IDX 2 525 #define regDMCUB_REGION4_OFFSET_HIGH 0x0197 526 #define regDMCUB_REGION4_OFFSET_HIGH_BASE_IDX 2 527 #define regDMCUB_REGION5_OFFSET 0x0198 528 #define regDMCUB_REGION5_OFFSET_BASE_IDX 2 529 #define regDMCUB_REGION5_OFFSET_HIGH 0x0199 530 #define regDMCUB_REGION5_OFFSET_HIGH_BASE_IDX 2 531 #define regDMCUB_REGION6_OFFSET 0x019a 532 #define regDMCUB_REGION6_OFFSET_BASE_IDX 2 533 #define regDMCUB_REGION6_OFFSET_HIGH 0x019b 534 #define regDMCUB_REGION6_OFFSET_HIGH_BASE_IDX 2 535 #define regDMCUB_REGION7_OFFSET 0x019c 536 #define regDMCUB_REGION7_OFFSET_BASE_IDX 2 537 #define regDMCUB_REGION7_OFFSET_HIGH 0x019d 538 #define regDMCUB_REGION7_OFFSET_HIGH_BASE_IDX 2 539 #define regDMCUB_REGION0_TOP_ADDRESS 0x019e 540 #define regDMCUB_REGION0_TOP_ADDRESS_BASE_IDX 2 541 #define regDMCUB_REGION1_TOP_ADDRESS 0x019f 542 #define regDMCUB_REGION1_TOP_ADDRESS_BASE_IDX 2 543 #define regDMCUB_REGION2_TOP_ADDRESS 0x01a0 544 #define regDMCUB_REGION2_TOP_ADDRESS_BASE_IDX 2 545 #define regDMCUB_REGION4_TOP_ADDRESS 0x01a1 546 #define regDMCUB_REGION4_TOP_ADDRESS_BASE_IDX 2 547 #define regDMCUB_REGION5_TOP_ADDRESS 0x01a2 548 #define regDMCUB_REGION5_TOP_ADDRESS_BASE_IDX 2 549 #define regDMCUB_REGION6_TOP_ADDRESS 0x01a3 550 #define regDMCUB_REGION6_TOP_ADDRESS_BASE_IDX 2 551 #define regDMCUB_REGION7_TOP_ADDRESS 0x01a4 552 #define regDMCUB_REGION7_TOP_ADDRESS_BASE_IDX 2 553 #define regDMCUB_REGION3_CW0_BASE_ADDRESS 0x01a5 554 #define regDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX 2 555 #define regDMCUB_REGION3_CW1_BASE_ADDRESS 0x01a6 556 #define regDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX 2 557 #define regDMCUB_REGION3_CW2_BASE_ADDRESS 0x01a7 558 #define regDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX 2 559 #define regDMCUB_REGION3_CW3_BASE_ADDRESS 0x01a8 560 #define regDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX 2 561 #define regDMCUB_REGION3_CW4_BASE_ADDRESS 0x01a9 562 #define regDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX 2 563 #define regDMCUB_REGION3_CW5_BASE_ADDRESS 0x01aa 564 #define regDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX 2 565 #define regDMCUB_REGION3_CW6_BASE_ADDRESS 0x01ab 566 #define regDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX 2 567 #define regDMCUB_REGION3_CW7_BASE_ADDRESS 0x01ac 568 #define regDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX 2 569 #define regDMCUB_REGION3_CW0_TOP_ADDRESS 0x01ad 570 #define regDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX 2 571 #define regDMCUB_REGION3_CW1_TOP_ADDRESS 0x01ae 572 #define regDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX 2 573 #define regDMCUB_REGION3_CW2_TOP_ADDRESS 0x01af 574 #define regDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX 2 575 #define regDMCUB_REGION3_CW3_TOP_ADDRESS 0x01b0 576 #define regDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX 2 577 #define regDMCUB_REGION3_CW4_TOP_ADDRESS 0x01b1 578 #define regDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX 2 579 #define regDMCUB_REGION3_CW5_TOP_ADDRESS 0x01b2 580 #define regDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX 2 581 #define regDMCUB_REGION3_CW6_TOP_ADDRESS 0x01b3 582 #define regDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX 2 583 #define regDMCUB_REGION3_CW7_TOP_ADDRESS 0x01b4 584 #define regDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX 2 585 #define regDMCUB_REGION3_CW0_OFFSET 0x01b5 586 #define regDMCUB_REGION3_CW0_OFFSET_BASE_IDX 2 587 #define regDMCUB_REGION3_CW0_OFFSET_HIGH 0x01b6 588 #define regDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX 2 589 #define regDMCUB_REGION3_CW1_OFFSET 0x01b7 590 #define regDMCUB_REGION3_CW1_OFFSET_BASE_IDX 2 591 #define regDMCUB_REGION3_CW1_OFFSET_HIGH 0x01b8 592 #define regDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX 2 593 #define regDMCUB_REGION3_CW2_OFFSET 0x01b9 594 #define regDMCUB_REGION3_CW2_OFFSET_BASE_IDX 2 595 #define regDMCUB_REGION3_CW2_OFFSET_HIGH 0x01ba 596 #define regDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX 2 597 #define regDMCUB_REGION3_CW3_OFFSET 0x01bb 598 #define regDMCUB_REGION3_CW3_OFFSET_BASE_IDX 2 599 #define regDMCUB_REGION3_CW3_OFFSET_HIGH 0x01bc 600 #define regDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX 2 601 #define regDMCUB_REGION3_CW4_OFFSET 0x01bd 602 #define regDMCUB_REGION3_CW4_OFFSET_BASE_IDX 2 603 #define regDMCUB_REGION3_CW4_OFFSET_HIGH 0x01be 604 #define regDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX 2 605 #define regDMCUB_REGION3_CW5_OFFSET 0x01bf 606 #define regDMCUB_REGION3_CW5_OFFSET_BASE_IDX 2 607 #define regDMCUB_REGION3_CW5_OFFSET_HIGH 0x01c0 608 #define regDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX 2 609 #define regDMCUB_REGION3_CW6_OFFSET 0x01c1 610 #define regDMCUB_REGION3_CW6_OFFSET_BASE_IDX 2 611 #define regDMCUB_REGION3_CW6_OFFSET_HIGH 0x01c2 612 #define regDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX 2 613 #define regDMCUB_REGION3_CW7_OFFSET 0x01c3 614 #define regDMCUB_REGION3_CW7_OFFSET_BASE_IDX 2 615 #define regDMCUB_REGION3_CW7_OFFSET_HIGH 0x01c4 616 #define regDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX 2 617 #define regDMCUB_INTERRUPT_ENABLE 0x01c5 618 #define regDMCUB_INTERRUPT_ENABLE_BASE_IDX 2 619 #define regDMCUB_INTERRUPT_ACK 0x01c6 620 #define regDMCUB_INTERRUPT_ACK_BASE_IDX 2 621 #define regDMCUB_INTERRUPT_STATUS 0x01c7 622 #define regDMCUB_INTERRUPT_STATUS_BASE_IDX 2 623 #define regDMCUB_INTERRUPT_TYPE 0x01c8 624 #define regDMCUB_INTERRUPT_TYPE_BASE_IDX 2 625 #define regDMCUB_EXT_INTERRUPT_STATUS 0x01c9 626 #define regDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX 2 627 #define regDMCUB_EXT_INTERRUPT_CTXID 0x01ca 628 #define regDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX 2 629 #define regDMCUB_EXT_INTERRUPT_ACK 0x01cb 630 #define regDMCUB_EXT_INTERRUPT_ACK_BASE_IDX 2 631 #define regDMCUB_INST_FETCH_FAULT_ADDR 0x01cc 632 #define regDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX 2 633 #define regDMCUB_DATA_WRITE_FAULT_ADDR 0x01cd 634 #define regDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX 2 635 #define regDMCUB_SEC_CNTL 0x01ce 636 #define regDMCUB_SEC_CNTL_BASE_IDX 2 637 #define regDMCUB_MEM_CNTL 0x01cf 638 #define regDMCUB_MEM_CNTL_BASE_IDX 2 639 #define regDMCUB_INBOX0_BASE_ADDRESS 0x01d0 640 #define regDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX 2 641 #define regDMCUB_INBOX0_SIZE 0x01d1 642 #define regDMCUB_INBOX0_SIZE_BASE_IDX 2 643 #define regDMCUB_INBOX0_WPTR 0x01d2 644 #define regDMCUB_INBOX0_WPTR_BASE_IDX 2 645 #define regDMCUB_INBOX0_RPTR 0x01d3 646 #define regDMCUB_INBOX0_RPTR_BASE_IDX 2 647 #define regDMCUB_INBOX1_BASE_ADDRESS 0x01d4 648 #define regDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX 2 649 #define regDMCUB_INBOX1_SIZE 0x01d5 650 #define regDMCUB_INBOX1_SIZE_BASE_IDX 2 651 #define regDMCUB_INBOX1_WPTR 0x01d6 652 #define regDMCUB_INBOX1_WPTR_BASE_IDX 2 653 #define regDMCUB_INBOX1_RPTR 0x01d7 654 #define regDMCUB_INBOX1_RPTR_BASE_IDX 2 655 #define regDMCUB_OUTBOX0_BASE_ADDRESS 0x01d8 656 #define regDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX 2 657 #define regDMCUB_OUTBOX0_SIZE 0x01d9 658 #define regDMCUB_OUTBOX0_SIZE_BASE_IDX 2 659 #define regDMCUB_OUTBOX0_WPTR 0x01da 660 #define regDMCUB_OUTBOX0_WPTR_BASE_IDX 2 661 #define regDMCUB_OUTBOX0_RPTR 0x01db 662 #define regDMCUB_OUTBOX0_RPTR_BASE_IDX 2 663 #define regDMCUB_OUTBOX1_BASE_ADDRESS 0x01dc 664 #define regDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX 2 665 #define regDMCUB_OUTBOX1_SIZE 0x01dd 666 #define regDMCUB_OUTBOX1_SIZE_BASE_IDX 2 667 #define regDMCUB_OUTBOX1_WPTR 0x01de 668 #define regDMCUB_OUTBOX1_WPTR_BASE_IDX 2 669 #define regDMCUB_OUTBOX1_RPTR 0x01df 670 #define regDMCUB_OUTBOX1_RPTR_BASE_IDX 2 671 #define regDMCUB_TIMER_TRIGGER0 0x01e0 672 #define regDMCUB_TIMER_TRIGGER0_BASE_IDX 2 673 #define regDMCUB_TIMER_TRIGGER1 0x01e1 674 #define regDMCUB_TIMER_TRIGGER1_BASE_IDX 2 675 #define regDMCUB_TIMER_WINDOW 0x01e2 676 #define regDMCUB_TIMER_WINDOW_BASE_IDX 2 677 #define regDMCUB_SCRATCH0 0x01e3 678 #define regDMCUB_SCRATCH0_BASE_IDX 2 679 #define regDMCUB_SCRATCH1 0x01e4 680 #define regDMCUB_SCRATCH1_BASE_IDX 2 681 #define regDMCUB_SCRATCH2 0x01e5 682 #define regDMCUB_SCRATCH2_BASE_IDX 2 683 #define regDMCUB_SCRATCH3 0x01e6 684 #define regDMCUB_SCRATCH3_BASE_IDX 2 685 #define regDMCUB_SCRATCH4 0x01e7 686 #define regDMCUB_SCRATCH4_BASE_IDX 2 687 #define regDMCUB_SCRATCH5 0x01e8 688 #define regDMCUB_SCRATCH5_BASE_IDX 2 689 #define regDMCUB_SCRATCH6 0x01e9 690 #define regDMCUB_SCRATCH6_BASE_IDX 2 691 #define regDMCUB_SCRATCH7 0x01ea 692 #define regDMCUB_SCRATCH7_BASE_IDX 2 693 #define regDMCUB_SCRATCH8 0x01eb 694 #define regDMCUB_SCRATCH8_BASE_IDX 2 695 #define regDMCUB_SCRATCH9 0x01ec 696 #define regDMCUB_SCRATCH9_BASE_IDX 2 697 #define regDMCUB_SCRATCH10 0x01ed 698 #define regDMCUB_SCRATCH10_BASE_IDX 2 699 #define regDMCUB_SCRATCH11 0x01ee 700 #define regDMCUB_SCRATCH11_BASE_IDX 2 701 #define regDMCUB_SCRATCH12 0x01ef 702 #define regDMCUB_SCRATCH12_BASE_IDX 2 703 #define regDMCUB_SCRATCH13 0x01f0 704 #define regDMCUB_SCRATCH13_BASE_IDX 2 705 #define regDMCUB_SCRATCH14 0x01f1 706 #define regDMCUB_SCRATCH14_BASE_IDX 2 707 #define regDMCUB_SCRATCH15 0x01f2 708 #define regDMCUB_SCRATCH15_BASE_IDX 2 709 #define regDMCUB_SCRATCH16 0x01f3 710 #define regDMCUB_SCRATCH16_BASE_IDX 2 711 #define regDMCUB_SCRATCH17 0x01f4 712 #define regDMCUB_SCRATCH17_BASE_IDX 2 713 #define regDMCUB_SCRATCH18 0x01f5 714 #define regDMCUB_SCRATCH18_BASE_IDX 2 715 #define regDMCUB_CNTL 0x01f6 716 #define regDMCUB_CNTL_BASE_IDX 2 717 #define regDMCUB_GPINT_DATAIN0 0x01f7 718 #define regDMCUB_GPINT_DATAIN0_BASE_IDX 2 719 #define regDMCUB_GPINT_DATAIN1 0x01f8 720 #define regDMCUB_GPINT_DATAIN1_BASE_IDX 2 721 #define regDMCUB_GPINT_DATAOUT 0x01f9 722 #define regDMCUB_GPINT_DATAOUT_BASE_IDX 2 723 #define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR 0x01fa 724 #define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX 2 725 #define regDMCUB_LS_WAKE_INT_ENABLE 0x01fb 726 #define regDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX 2 727 #define regDMCUB_MEM_PWR_CNTL 0x01fc 728 #define regDMCUB_MEM_PWR_CNTL_BASE_IDX 2 729 #define regDMCUB_TIMER_CURRENT 0x01fd 730 #define regDMCUB_TIMER_CURRENT_BASE_IDX 2 731 #define regDMCUB_PROC_ID 0x01ff 732 #define regDMCUB_PROC_ID_BASE_IDX 2 733 #define regDMCUB_CNTL2 0x0200 734 #define regDMCUB_CNTL2_BASE_IDX 2 735 #define regDMCUB_GPINT_DATAIN2 0x0215 736 #define regDMCUB_GPINT_DATAIN2_BASE_IDX 2 737 #define regDMCUB_GPINT_DATAIN3 0x0216 738 #define regDMCUB_GPINT_DATAIN3_BASE_IDX 2 739 #define regDMCUB_GPINT_DATAIN4 0x0217 740 #define regDMCUB_GPINT_DATAIN4_BASE_IDX 2 741 #define regDMCUB_GPINT_DATAIN5 0x0218 742 #define regDMCUB_GPINT_DATAIN5_BASE_IDX 2 743 #define regDMCUB_GPINT_DATAIN6 0x0219 744 #define regDMCUB_GPINT_DATAIN6_BASE_IDX 2 745 #define regDMCUB_REGION3_TMR_AXI_SPACE 0x021a 746 #define regDMCUB_REGION3_TMR_AXI_SPACE_BASE_IDX 2 747 #define regDMCUB_SCRATCH19 0x021b 748 #define regDMCUB_SCRATCH19_BASE_IDX 2 749 #define regDMCUB_SCRATCH20 0x021c 750 #define regDMCUB_SCRATCH20_BASE_IDX 2 751 #define regDMCUB_SCRATCH21 0x021d 752 #define regDMCUB_SCRATCH21_BASE_IDX 2 753 #define regDMCUB_SCRATCH22 0x021e 754 #define regDMCUB_SCRATCH22_BASE_IDX 2 755 #define regDMCUB_SCRATCH23 0x021f 756 #define regDMCUB_SCRATCH23_BASE_IDX 2 757 #define regHOST_INTERRUPT_CSR 0x0222 758 #define regHOST_INTERRUPT_CSR_BASE_IDX 2 759 #define regDMCUB_REG_INBOX0_RDY 0x0223 760 #define regDMCUB_REG_INBOX0_RDY_BASE_IDX 2 761 #define regDMCUB_REG_INBOX0_MSG0 0x0224 762 #define regDMCUB_REG_INBOX0_MSG0_BASE_IDX 2 763 #define regDMCUB_REG_INBOX0_MSG1 0x0225 764 #define regDMCUB_REG_INBOX0_MSG1_BASE_IDX 2 765 #define regDMCUB_REG_INBOX0_MSG2 0x0226 766 #define regDMCUB_REG_INBOX0_MSG2_BASE_IDX 2 767 #define regDMCUB_REG_INBOX0_MSG3 0x0227 768 #define regDMCUB_REG_INBOX0_MSG3_BASE_IDX 2 769 #define regDMCUB_REG_INBOX0_MSG4 0x0228 770 #define regDMCUB_REG_INBOX0_MSG4_BASE_IDX 2 771 #define regDMCUB_REG_INBOX0_MSG5 0x0229 772 #define regDMCUB_REG_INBOX0_MSG5_BASE_IDX 2 773 #define regDMCUB_REG_INBOX0_MSG6 0x022a 774 #define regDMCUB_REG_INBOX0_MSG6_BASE_IDX 2 775 #define regDMCUB_REG_INBOX0_MSG7 0x022b 776 #define regDMCUB_REG_INBOX0_MSG7_BASE_IDX 2 777 #define regDMCUB_REG_INBOX0_MSG8 0x022c 778 #define regDMCUB_REG_INBOX0_MSG8_BASE_IDX 2 779 #define regDMCUB_REG_INBOX0_MSG9 0x022d 780 #define regDMCUB_REG_INBOX0_MSG9_BASE_IDX 2 781 #define regDMCUB_REG_INBOX0_MSG10 0x022e 782 #define regDMCUB_REG_INBOX0_MSG10_BASE_IDX 2 783 #define regDMCUB_REG_INBOX0_MSG11 0x022f 784 #define regDMCUB_REG_INBOX0_MSG11_BASE_IDX 2 785 #define regDMCUB_REG_INBOX0_MSG12 0x0230 786 #define regDMCUB_REG_INBOX0_MSG12_BASE_IDX 2 787 #define regDMCUB_REG_INBOX0_MSG13 0x0231 788 #define regDMCUB_REG_INBOX0_MSG13_BASE_IDX 2 789 #define regDMCUB_REG_INBOX0_MSG14 0x0232 790 #define regDMCUB_REG_INBOX0_MSG14_BASE_IDX 2 791 #define regDMCUB_REG_INBOX0_RSP 0x0233 792 #define regDMCUB_REG_INBOX0_RSP_BASE_IDX 2 793 #define regDMCUB_REG_OUTBOX0_RDY 0x0234 794 #define regDMCUB_REG_OUTBOX0_RDY_BASE_IDX 2 795 #define regDMCUB_REG_OUTBOX0_MSG0 0x0235 796 #define regDMCUB_REG_OUTBOX0_MSG0_BASE_IDX 2 797 #define regDMCUB_REG_OUTBOX0_RSP 0x0236 798 #define regDMCUB_REG_OUTBOX0_RSP_BASE_IDX 2 799 #define regDMCUB_REG_INBOX1_RDY 0x0237 800 #define regDMCUB_REG_INBOX1_RDY_BASE_IDX 2 801 #define regDMCUB_REG_INBOX1_MSG0 0x0238 802 #define regDMCUB_REG_INBOX1_MSG0_BASE_IDX 2 803 #define regDMCUB_REG_INBOX1_MSG1 0x0239 804 #define regDMCUB_REG_INBOX1_MSG1_BASE_IDX 2 805 #define regDMCUB_REG_INBOX1_RSP 0x023a 806 #define regDMCUB_REG_INBOX1_RSP_BASE_IDX 2 807 #define regDMCUB_REG_INBOX2_RDY 0x023b 808 #define regDMCUB_REG_INBOX2_RDY_BASE_IDX 2 809 #define regDMCUB_REG_INBOX2_MSG0 0x023c 810 #define regDMCUB_REG_INBOX2_MSG0_BASE_IDX 2 811 #define regDMCUB_REG_INBOX2_MSG1 0x023d 812 #define regDMCUB_REG_INBOX2_MSG1_BASE_IDX 2 813 #define regDMCUB_REG_INBOX2_RSP 0x023e 814 #define regDMCUB_REG_INBOX2_RSP_BASE_IDX 2 815 #define regDMCUB_REG_INBOX3_RDY 0x023f 816 #define regDMCUB_REG_INBOX3_RDY_BASE_IDX 2 817 #define regDMCUB_REG_INBOX3_MSG0 0x0240 818 #define regDMCUB_REG_INBOX3_MSG0_BASE_IDX 2 819 #define regDMCUB_REG_INBOX3_MSG1 0x0241 820 #define regDMCUB_REG_INBOX3_MSG1_BASE_IDX 2 821 #define regDMCUB_REG_INBOX3_RSP 0x0242 822 #define regDMCUB_REG_INBOX3_RSP_BASE_IDX 2 823 #define regDMCUB_REG_INBOX4_RDY 0x0243 824 #define regDMCUB_REG_INBOX4_RDY_BASE_IDX 2 825 #define regDMCUB_REG_INBOX4_MSG0 0x0244 826 #define regDMCUB_REG_INBOX4_MSG0_BASE_IDX 2 827 #define regDMCUB_REG_INBOX4_MSG1 0x0245 828 #define regDMCUB_REG_INBOX4_MSG1_BASE_IDX 2 829 #define regDMCUB_REG_INBOX4_RSP 0x0246 830 #define regDMCUB_REG_INBOX4_RSP_BASE_IDX 2 831 832 833 // addressBlock: dcn_dcec_wb0_dispdec_dwb_top_dispdec 834 // base address: 0x0 835 #define regDWB_ENABLE_CLK_CTRL 0x3228 836 #define regDWB_ENABLE_CLK_CTRL_BASE_IDX 2 837 #define regDWB_MEM_PWR_CTRL 0x3229 838 #define regDWB_MEM_PWR_CTRL_BASE_IDX 2 839 #define regFC_MODE_CTRL 0x322a 840 #define regFC_MODE_CTRL_BASE_IDX 2 841 #define regFC_FLOW_CTRL 0x322b 842 #define regFC_FLOW_CTRL_BASE_IDX 2 843 #define regFC_WINDOW_START 0x322c 844 #define regFC_WINDOW_START_BASE_IDX 2 845 #define regFC_WINDOW_SIZE 0x322d 846 #define regFC_WINDOW_SIZE_BASE_IDX 2 847 #define regFC_SOURCE_SIZE 0x322e 848 #define regFC_SOURCE_SIZE_BASE_IDX 2 849 #define regDWB_UPDATE_CTRL 0x322f 850 #define regDWB_UPDATE_CTRL_BASE_IDX 2 851 #define regDWB_CRC_CTRL 0x3230 852 #define regDWB_CRC_CTRL_BASE_IDX 2 853 #define regDWB_CRC_MASK_R_G 0x3231 854 #define regDWB_CRC_MASK_R_G_BASE_IDX 2 855 #define regDWB_CRC_MASK_B_A 0x3232 856 #define regDWB_CRC_MASK_B_A_BASE_IDX 2 857 #define regDWB_CRC_VAL_R_G 0x3233 858 #define regDWB_CRC_VAL_R_G_BASE_IDX 2 859 #define regDWB_CRC_VAL_B_A 0x3234 860 #define regDWB_CRC_VAL_B_A_BASE_IDX 2 861 #define regDWB_OUT_CTRL 0x3235 862 #define regDWB_OUT_CTRL_BASE_IDX 2 863 #define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN 0x3236 864 #define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX 2 865 #define regDWB_MMHUBBUB_BACKPRESSURE_CNT 0x3237 866 #define regDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX 2 867 #define regDWB_HOST_READ_CONTROL 0x3238 868 #define regDWB_HOST_READ_CONTROL_BASE_IDX 2 869 #define regDWB_OVERFLOW_STATUS 0x3239 870 #define regDWB_OVERFLOW_STATUS_BASE_IDX 2 871 #define regDWB_OVERFLOW_COUNTER 0x323a 872 #define regDWB_OVERFLOW_COUNTER_BASE_IDX 2 873 #define regDWB_SOFT_RESET 0x323b 874 #define regDWB_SOFT_RESET_BASE_IDX 2 875 #define regDWB_DEBUG_CTRL 0x323c 876 #define regDWB_DEBUG_CTRL_BASE_IDX 2 877 #define regDWB_DEBUG 0x323d 878 #define regDWB_DEBUG_BASE_IDX 2 879 880 881 // addressBlock: dcn_dcec_wb0_dispdec_dwbcp_dispdec 882 // base address: 0x0 883 #define regDWB_HDR_MULT_COEF 0x3294 884 #define regDWB_HDR_MULT_COEF_BASE_IDX 2 885 #define regDWB_GAMUT_REMAP_MODE 0x3295 886 #define regDWB_GAMUT_REMAP_MODE_BASE_IDX 2 887 #define regDWB_GAMUT_REMAP_COEF_FORMAT 0x3296 888 #define regDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 2 889 #define regDWB_GAMUT_REMAPA_C11_C12 0x3297 890 #define regDWB_GAMUT_REMAPA_C11_C12_BASE_IDX 2 891 #define regDWB_GAMUT_REMAPA_C13_C14 0x3298 892 #define regDWB_GAMUT_REMAPA_C13_C14_BASE_IDX 2 893 #define regDWB_GAMUT_REMAPA_C21_C22 0x3299 894 #define regDWB_GAMUT_REMAPA_C21_C22_BASE_IDX 2 895 #define regDWB_GAMUT_REMAPA_C23_C24 0x329a 896 #define regDWB_GAMUT_REMAPA_C23_C24_BASE_IDX 2 897 #define regDWB_GAMUT_REMAPA_C31_C32 0x329b 898 #define regDWB_GAMUT_REMAPA_C31_C32_BASE_IDX 2 899 #define regDWB_GAMUT_REMAPA_C33_C34 0x329c 900 #define regDWB_GAMUT_REMAPA_C33_C34_BASE_IDX 2 901 #define regDWB_GAMUT_REMAPB_C11_C12 0x329d 902 #define regDWB_GAMUT_REMAPB_C11_C12_BASE_IDX 2 903 #define regDWB_GAMUT_REMAPB_C13_C14 0x329e 904 #define regDWB_GAMUT_REMAPB_C13_C14_BASE_IDX 2 905 #define regDWB_GAMUT_REMAPB_C21_C22 0x329f 906 #define regDWB_GAMUT_REMAPB_C21_C22_BASE_IDX 2 907 #define regDWB_GAMUT_REMAPB_C23_C24 0x32a0 908 #define regDWB_GAMUT_REMAPB_C23_C24_BASE_IDX 2 909 #define regDWB_GAMUT_REMAPB_C31_C32 0x32a1 910 #define regDWB_GAMUT_REMAPB_C31_C32_BASE_IDX 2 911 #define regDWB_GAMUT_REMAPB_C33_C34 0x32a2 912 #define regDWB_GAMUT_REMAPB_C33_C34_BASE_IDX 2 913 #define regDWB_OGAM_CONTROL 0x32a3 914 #define regDWB_OGAM_CONTROL_BASE_IDX 2 915 #define regDWB_OGAM_LUT_INDEX 0x32a4 916 #define regDWB_OGAM_LUT_INDEX_BASE_IDX 2 917 #define regDWB_OGAM_LUT_DATA 0x32a5 918 #define regDWB_OGAM_LUT_DATA_BASE_IDX 2 919 #define regDWB_OGAM_LUT_CONTROL 0x32a6 920 #define regDWB_OGAM_LUT_CONTROL_BASE_IDX 2 921 #define regDWB_OGAM_RAMA_START_CNTL_B 0x32a7 922 #define regDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 923 #define regDWB_OGAM_RAMA_START_CNTL_G 0x32a8 924 #define regDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 925 #define regDWB_OGAM_RAMA_START_CNTL_R 0x32a9 926 #define regDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 927 #define regDWB_OGAM_RAMA_START_BASE_CNTL_B 0x32aa 928 #define regDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 929 #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B 0x32ab 930 #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 931 #define regDWB_OGAM_RAMA_START_BASE_CNTL_G 0x32ac 932 #define regDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 933 #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G 0x32ad 934 #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 935 #define regDWB_OGAM_RAMA_START_BASE_CNTL_R 0x32ae 936 #define regDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 937 #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R 0x32af 938 #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 939 #define regDWB_OGAM_RAMA_END_CNTL1_B 0x32b0 940 #define regDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 941 #define regDWB_OGAM_RAMA_END_CNTL2_B 0x32b1 942 #define regDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 943 #define regDWB_OGAM_RAMA_END_CNTL1_G 0x32b2 944 #define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 945 #define regDWB_OGAM_RAMA_END_CNTL2_G 0x32b3 946 #define regDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 947 #define regDWB_OGAM_RAMA_END_CNTL1_R 0x32b4 948 #define regDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 949 #define regDWB_OGAM_RAMA_END_CNTL2_R 0x32b5 950 #define regDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 951 #define regDWB_OGAM_RAMA_OFFSET_B 0x32b6 952 #define regDWB_OGAM_RAMA_OFFSET_B_BASE_IDX 2 953 #define regDWB_OGAM_RAMA_OFFSET_G 0x32b7 954 #define regDWB_OGAM_RAMA_OFFSET_G_BASE_IDX 2 955 #define regDWB_OGAM_RAMA_OFFSET_R 0x32b8 956 #define regDWB_OGAM_RAMA_OFFSET_R_BASE_IDX 2 957 #define regDWB_OGAM_RAMA_REGION_0_1 0x32b9 958 #define regDWB_OGAM_RAMA_REGION_0_1_BASE_IDX 2 959 #define regDWB_OGAM_RAMA_REGION_2_3 0x32ba 960 #define regDWB_OGAM_RAMA_REGION_2_3_BASE_IDX 2 961 #define regDWB_OGAM_RAMA_REGION_4_5 0x32bb 962 #define regDWB_OGAM_RAMA_REGION_4_5_BASE_IDX 2 963 #define regDWB_OGAM_RAMA_REGION_6_7 0x32bc 964 #define regDWB_OGAM_RAMA_REGION_6_7_BASE_IDX 2 965 #define regDWB_OGAM_RAMA_REGION_8_9 0x32bd 966 #define regDWB_OGAM_RAMA_REGION_8_9_BASE_IDX 2 967 #define regDWB_OGAM_RAMA_REGION_10_11 0x32be 968 #define regDWB_OGAM_RAMA_REGION_10_11_BASE_IDX 2 969 #define regDWB_OGAM_RAMA_REGION_12_13 0x32bf 970 #define regDWB_OGAM_RAMA_REGION_12_13_BASE_IDX 2 971 #define regDWB_OGAM_RAMA_REGION_14_15 0x32c0 972 #define regDWB_OGAM_RAMA_REGION_14_15_BASE_IDX 2 973 #define regDWB_OGAM_RAMA_REGION_16_17 0x32c1 974 #define regDWB_OGAM_RAMA_REGION_16_17_BASE_IDX 2 975 #define regDWB_OGAM_RAMA_REGION_18_19 0x32c2 976 #define regDWB_OGAM_RAMA_REGION_18_19_BASE_IDX 2 977 #define regDWB_OGAM_RAMA_REGION_20_21 0x32c3 978 #define regDWB_OGAM_RAMA_REGION_20_21_BASE_IDX 2 979 #define regDWB_OGAM_RAMA_REGION_22_23 0x32c4 980 #define regDWB_OGAM_RAMA_REGION_22_23_BASE_IDX 2 981 #define regDWB_OGAM_RAMA_REGION_24_25 0x32c5 982 #define regDWB_OGAM_RAMA_REGION_24_25_BASE_IDX 2 983 #define regDWB_OGAM_RAMA_REGION_26_27 0x32c6 984 #define regDWB_OGAM_RAMA_REGION_26_27_BASE_IDX 2 985 #define regDWB_OGAM_RAMA_REGION_28_29 0x32c7 986 #define regDWB_OGAM_RAMA_REGION_28_29_BASE_IDX 2 987 #define regDWB_OGAM_RAMA_REGION_30_31 0x32c8 988 #define regDWB_OGAM_RAMA_REGION_30_31_BASE_IDX 2 989 #define regDWB_OGAM_RAMA_REGION_32_33 0x32c9 990 #define regDWB_OGAM_RAMA_REGION_32_33_BASE_IDX 2 991 #define regDWB_OGAM_RAMB_START_CNTL_B 0x32ca 992 #define regDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 993 #define regDWB_OGAM_RAMB_START_CNTL_G 0x32cb 994 #define regDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 995 #define regDWB_OGAM_RAMB_START_CNTL_R 0x32cc 996 #define regDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 997 #define regDWB_OGAM_RAMB_START_BASE_CNTL_B 0x32cd 998 #define regDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 999 #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B 0x32ce 1000 #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 1001 #define regDWB_OGAM_RAMB_START_BASE_CNTL_G 0x32cf 1002 #define regDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 1003 #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G 0x32d0 1004 #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 1005 #define regDWB_OGAM_RAMB_START_BASE_CNTL_R 0x32d1 1006 #define regDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 1007 #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R 0x32d2 1008 #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 1009 #define regDWB_OGAM_RAMB_END_CNTL1_B 0x32d3 1010 #define regDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 1011 #define regDWB_OGAM_RAMB_END_CNTL2_B 0x32d4 1012 #define regDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 1013 #define regDWB_OGAM_RAMB_END_CNTL1_G 0x32d5 1014 #define regDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 1015 #define regDWB_OGAM_RAMB_END_CNTL2_G 0x32d6 1016 #define regDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 1017 #define regDWB_OGAM_RAMB_END_CNTL1_R 0x32d7 1018 #define regDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 1019 #define regDWB_OGAM_RAMB_END_CNTL2_R 0x32d8 1020 #define regDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 1021 #define regDWB_OGAM_RAMB_OFFSET_B 0x32d9 1022 #define regDWB_OGAM_RAMB_OFFSET_B_BASE_IDX 2 1023 #define regDWB_OGAM_RAMB_OFFSET_G 0x32da 1024 #define regDWB_OGAM_RAMB_OFFSET_G_BASE_IDX 2 1025 #define regDWB_OGAM_RAMB_OFFSET_R 0x32db 1026 #define regDWB_OGAM_RAMB_OFFSET_R_BASE_IDX 2 1027 #define regDWB_OGAM_RAMB_REGION_0_1 0x32dc 1028 #define regDWB_OGAM_RAMB_REGION_0_1_BASE_IDX 2 1029 #define regDWB_OGAM_RAMB_REGION_2_3 0x32dd 1030 #define regDWB_OGAM_RAMB_REGION_2_3_BASE_IDX 2 1031 #define regDWB_OGAM_RAMB_REGION_4_5 0x32de 1032 #define regDWB_OGAM_RAMB_REGION_4_5_BASE_IDX 2 1033 #define regDWB_OGAM_RAMB_REGION_6_7 0x32df 1034 #define regDWB_OGAM_RAMB_REGION_6_7_BASE_IDX 2 1035 #define regDWB_OGAM_RAMB_REGION_8_9 0x32e0 1036 #define regDWB_OGAM_RAMB_REGION_8_9_BASE_IDX 2 1037 #define regDWB_OGAM_RAMB_REGION_10_11 0x32e1 1038 #define regDWB_OGAM_RAMB_REGION_10_11_BASE_IDX 2 1039 #define regDWB_OGAM_RAMB_REGION_12_13 0x32e2 1040 #define regDWB_OGAM_RAMB_REGION_12_13_BASE_IDX 2 1041 #define regDWB_OGAM_RAMB_REGION_14_15 0x32e3 1042 #define regDWB_OGAM_RAMB_REGION_14_15_BASE_IDX 2 1043 #define regDWB_OGAM_RAMB_REGION_16_17 0x32e4 1044 #define regDWB_OGAM_RAMB_REGION_16_17_BASE_IDX 2 1045 #define regDWB_OGAM_RAMB_REGION_18_19 0x32e5 1046 #define regDWB_OGAM_RAMB_REGION_18_19_BASE_IDX 2 1047 #define regDWB_OGAM_RAMB_REGION_20_21 0x32e6 1048 #define regDWB_OGAM_RAMB_REGION_20_21_BASE_IDX 2 1049 #define regDWB_OGAM_RAMB_REGION_22_23 0x32e7 1050 #define regDWB_OGAM_RAMB_REGION_22_23_BASE_IDX 2 1051 #define regDWB_OGAM_RAMB_REGION_24_25 0x32e8 1052 #define regDWB_OGAM_RAMB_REGION_24_25_BASE_IDX 2 1053 #define regDWB_OGAM_RAMB_REGION_26_27 0x32e9 1054 #define regDWB_OGAM_RAMB_REGION_26_27_BASE_IDX 2 1055 #define regDWB_OGAM_RAMB_REGION_28_29 0x32ea 1056 #define regDWB_OGAM_RAMB_REGION_28_29_BASE_IDX 2 1057 #define regDWB_OGAM_RAMB_REGION_30_31 0x32eb 1058 #define regDWB_OGAM_RAMB_REGION_30_31_BASE_IDX 2 1059 #define regDWB_OGAM_RAMB_REGION_32_33 0x32ec 1060 #define regDWB_OGAM_RAMB_REGION_32_33_BASE_IDX 2 1061 1062 1063 // addressBlock: dcn_dcec_mmhubbub_mcif_wb0_dispdec 1064 // base address: 0x0 1065 #define regMCIF_WB_BUFMGR_SW_CONTROL 0x0272 1066 #define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 1067 #define regMCIF_WB_BUFMGR_STATUS 0x0274 1068 #define regMCIF_WB_BUFMGR_STATUS_BASE_IDX 2 1069 #define regMCIF_WB_BUF_PITCH 0x0275 1070 #define regMCIF_WB_BUF_PITCH_BASE_IDX 2 1071 #define regMCIF_WB_BUF_1_STATUS 0x0276 1072 #define regMCIF_WB_BUF_1_STATUS_BASE_IDX 2 1073 #define regMCIF_WB_BUF_1_STATUS2 0x0277 1074 #define regMCIF_WB_BUF_1_STATUS2_BASE_IDX 2 1075 #define regMCIF_WB_BUF_2_STATUS 0x0278 1076 #define regMCIF_WB_BUF_2_STATUS_BASE_IDX 2 1077 #define regMCIF_WB_BUF_2_STATUS2 0x0279 1078 #define regMCIF_WB_BUF_2_STATUS2_BASE_IDX 2 1079 #define regMCIF_WB_BUF_3_STATUS 0x027a 1080 #define regMCIF_WB_BUF_3_STATUS_BASE_IDX 2 1081 #define regMCIF_WB_BUF_3_STATUS2 0x027b 1082 #define regMCIF_WB_BUF_3_STATUS2_BASE_IDX 2 1083 #define regMCIF_WB_BUF_4_STATUS 0x027c 1084 #define regMCIF_WB_BUF_4_STATUS_BASE_IDX 2 1085 #define regMCIF_WB_BUF_4_STATUS2 0x027d 1086 #define regMCIF_WB_BUF_4_STATUS2_BASE_IDX 2 1087 #define regMCIF_WB_ARBITRATION_CONTROL 0x027e 1088 #define regMCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 1089 #define regMCIF_WB_SCLK_CHANGE 0x027f 1090 #define regMCIF_WB_SCLK_CHANGE_BASE_IDX 2 1091 #define regMCIF_WB_TEST_DEBUG_INDEX 0x0280 1092 #define regMCIF_WB_TEST_DEBUG_INDEX_BASE_IDX 2 1093 #define regMCIF_WB_TEST_DEBUG_DATA 0x0281 1094 #define regMCIF_WB_TEST_DEBUG_DATA_BASE_IDX 2 1095 #define regMCIF_WB_BUF_1_ADDR_Y 0x0282 1096 #define regMCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 1097 #define regMCIF_WB_BUF_1_ADDR_C 0x0284 1098 #define regMCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 1099 #define regMCIF_WB_BUF_2_ADDR_Y 0x0286 1100 #define regMCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 1101 #define regMCIF_WB_BUF_2_ADDR_C 0x0288 1102 #define regMCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 1103 #define regMCIF_WB_BUF_3_ADDR_Y 0x028a 1104 #define regMCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 1105 #define regMCIF_WB_BUF_3_ADDR_C 0x028c 1106 #define regMCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 1107 #define regMCIF_WB_BUF_4_ADDR_Y 0x028e 1108 #define regMCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 1109 #define regMCIF_WB_BUF_4_ADDR_C 0x0290 1110 #define regMCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 1111 #define regMCIF_WB_BUFMGR_VCE_CONTROL 0x0292 1112 #define regMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 1113 #define regMCIF_WB_NB_PSTATE_CONTROL 0x0293 1114 #define regMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 1115 #define regMCIF_WB_CLOCK_GATER_CONTROL 0x0294 1116 #define regMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 1117 #define regMCIF_WB_SELF_REFRESH_CONTROL 0x0296 1118 #define regMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 1119 #define regMULTI_LEVEL_QOS_CTRL 0x0297 1120 #define regMULTI_LEVEL_QOS_CTRL_BASE_IDX 2 1121 #define regMCIF_WB_SECURITY_LEVEL 0x0298 1122 #define regMCIF_WB_SECURITY_LEVEL_BASE_IDX 2 1123 #define regMCIF_WB_BUF_LUMA_SIZE 0x0299 1124 #define regMCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 1125 #define regMCIF_WB_BUF_CHROMA_SIZE 0x029a 1126 #define regMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 1127 #define regMCIF_WB_BUF_1_ADDR_Y_HIGH 0x029b 1128 #define regMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2 1129 #define regMCIF_WB_BUF_1_ADDR_C_HIGH 0x029c 1130 #define regMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2 1131 #define regMCIF_WB_BUF_2_ADDR_Y_HIGH 0x029d 1132 #define regMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2 1133 #define regMCIF_WB_BUF_2_ADDR_C_HIGH 0x029e 1134 #define regMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2 1135 #define regMCIF_WB_BUF_3_ADDR_Y_HIGH 0x029f 1136 #define regMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2 1137 #define regMCIF_WB_BUF_3_ADDR_C_HIGH 0x02a0 1138 #define regMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2 1139 #define regMCIF_WB_BUF_4_ADDR_Y_HIGH 0x02a1 1140 #define regMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2 1141 #define regMCIF_WB_BUF_4_ADDR_C_HIGH 0x02a2 1142 #define regMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2 1143 #define regMCIF_WB_BUF_1_RESOLUTION 0x02a3 1144 #define regMCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2 1145 #define regMCIF_WB_BUF_2_RESOLUTION 0x02a4 1146 #define regMCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2 1147 #define regMCIF_WB_BUF_3_RESOLUTION 0x02a5 1148 #define regMCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2 1149 #define regMCIF_WB_BUF_4_RESOLUTION 0x02a6 1150 #define regMCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2 1151 #define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI 0x02a7 1152 #define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI_BASE_IDX 2 1153 #define regMCIF_WB_VMID_CONTROL 0x02a8 1154 #define regMCIF_WB_VMID_CONTROL_BASE_IDX 2 1155 #define regMCIF_WB_MIN_TTO 0x02a9 1156 #define regMCIF_WB_MIN_TTO_BASE_IDX 2 1157 1158 // addressBlock: dcn_dcec_mmhubbub_mmhubbub_dispdec 1159 // base address: 0x0 1160 #define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02aa 1161 #define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 1162 #define regMCIF_WB_WATERMARK 0x02ab 1163 #define regMCIF_WB_WATERMARK_BASE_IDX 2 1164 #define regMMHUBBUB_WARMUP_CONFIG 0x02ac 1165 #define regMMHUBBUB_WARMUP_CONFIG_BASE_IDX 2 1166 #define regMMHUBBUB_WARMUP_CONTROL_STATUS 0x02ad 1167 #define regMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX 2 1168 #define regMMHUBBUB_WARMUP_BASE_ADDR_LOW 0x02ae 1169 #define regMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX 2 1170 #define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH 0x02af 1171 #define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX 2 1172 #define regMMHUBBUB_WARMUP_ADDR_REGION 0x02b0 1173 #define regMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX 2 1174 #define regMMHUBBUB_MIN_TTO 0x02b1 1175 #define regMMHUBBUB_MIN_TTO_BASE_IDX 2 1176 #define regMMHUBBUB_CTRL 0x0333 1177 #define regMMHUBBUB_CTRL_BASE_IDX 2 1178 #define regWBIF_SMU_WM_CONTROL 0x0334 1179 #define regWBIF_SMU_WM_CONTROL_BASE_IDX 2 1180 #define regWBIF0_MISC_CTRL 0x0335 1181 #define regWBIF0_MISC_CTRL_BASE_IDX 2 1182 #define regWBIF0_PHASE0_OUTSTANDING_COUNTER 0x0336 1183 #define regWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 1184 #define regWBIF0_PHASE1_OUTSTANDING_COUNTER 0x0337 1185 #define regWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 1186 #define regMMHUBBUB_MEM_PWR_STATUS 0x033e 1187 #define regMMHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 1188 #define regMMHUBBUB_MEM_PWR_CNTL 0x033f 1189 #define regMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 2 1190 #define regMMHUBBUB_CLOCK_CNTL 0x0340 1191 #define regMMHUBBUB_CLOCK_CNTL_BASE_IDX 2 1192 #define regMMHUBBUB_SOFT_RESET 0x0341 1193 #define regMMHUBBUB_SOFT_RESET_BASE_IDX 2 1194 #define regDMU_IF_ERR_STATUS 0x0345 1195 #define regDMU_IF_ERR_STATUS_BASE_IDX 2 1196 #define regMMHUBBUB_CLIENT_UNIT_ID 0x0346 1197 #define regMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX 2 1198 #define regMMHUBBUB_WARMUP_VMID_CONTROL 0x0348 1199 #define regMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX 2 1200 1201 1202 // addressBlock: dcn_dcec_hda_azf0controller_dispdec 1203 // base address: 0x0 1204 #define regAZALIA_CONTROLLER_CLOCK_GATING 0x03c2 1205 #define regAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2 1206 #define regAZALIA_AUDIO_DTO 0x03c3 1207 #define regAZALIA_AUDIO_DTO_BASE_IDX 2 1208 #define regAZALIA_AUDIO_DTO_CONTROL 0x03c4 1209 #define regAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2 1210 #define regAZALIA_SOCCLK_CONTROL 0x03c5 1211 #define regAZALIA_SOCCLK_CONTROL_BASE_IDX 2 1212 #define regAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6 1213 #define regAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2 1214 #define regAZALIA_DATA_DMA_CONTROL 0x03c7 1215 #define regAZALIA_DATA_DMA_CONTROL_BASE_IDX 2 1216 #define regAZALIA_BDL_DMA_CONTROL 0x03c8 1217 #define regAZALIA_BDL_DMA_CONTROL_BASE_IDX 2 1218 #define regAZALIA_RIRB_AND_DP_CONTROL 0x03c9 1219 #define regAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2 1220 #define regAZALIA_CORB_DMA_CONTROL 0x03ca 1221 #define regAZALIA_CORB_DMA_CONTROL_BASE_IDX 2 1222 #define regAZALIA_GLOBAL_CAPABILITIES 0x03d3 1223 #define regAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2 1224 #define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x03d4 1225 #define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 1226 #define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5 1227 #define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2 1228 #define regAZALIA_INPUT_PAYLOAD_CAPABILITY 0x03d6 1229 #define regAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 1230 #define regAZALIA_INPUT_CRC0_CONTROL0 0x03d9 1231 #define regAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2 1232 #define regAZALIA_INPUT_CRC0_CONTROL1 0x03da 1233 #define regAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2 1234 #define regAZALIA_INPUT_CRC0_CONTROL2 0x03db 1235 #define regAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2 1236 #define regAZALIA_INPUT_CRC0_CONTROL3 0x03dc 1237 #define regAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2 1238 #define regAZALIA_INPUT_CRC0_RESULT 0x03dd 1239 #define regAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2 1240 #define regAZALIA_INPUT_CRC1_CONTROL0 0x03de 1241 #define regAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2 1242 #define regAZALIA_INPUT_CRC1_CONTROL1 0x03df 1243 #define regAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2 1244 #define regAZALIA_INPUT_CRC1_CONTROL2 0x03e0 1245 #define regAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2 1246 #define regAZALIA_INPUT_CRC1_CONTROL3 0x03e1 1247 #define regAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2 1248 #define regAZALIA_INPUT_CRC1_RESULT 0x03e2 1249 #define regAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2 1250 #define regAZALIA_CRC0_CONTROL0 0x03e3 1251 #define regAZALIA_CRC0_CONTROL0_BASE_IDX 2 1252 #define regAZALIA_CRC0_CONTROL1 0x03e4 1253 #define regAZALIA_CRC0_CONTROL1_BASE_IDX 2 1254 #define regAZALIA_CRC0_CONTROL2 0x03e5 1255 #define regAZALIA_CRC0_CONTROL2_BASE_IDX 2 1256 #define regAZALIA_CRC0_CONTROL3 0x03e6 1257 #define regAZALIA_CRC0_CONTROL3_BASE_IDX 2 1258 #define regAZALIA_CRC0_RESULT 0x03e7 1259 #define regAZALIA_CRC0_RESULT_BASE_IDX 2 1260 #define regAZALIA_CRC1_CONTROL0 0x03e8 1261 #define regAZALIA_CRC1_CONTROL0_BASE_IDX 2 1262 #define regAZALIA_CRC1_CONTROL1 0x03e9 1263 #define regAZALIA_CRC1_CONTROL1_BASE_IDX 2 1264 #define regAZALIA_CRC1_CONTROL2 0x03ea 1265 #define regAZALIA_CRC1_CONTROL2_BASE_IDX 2 1266 #define regAZALIA_CRC1_CONTROL3 0x03eb 1267 #define regAZALIA_CRC1_CONTROL3_BASE_IDX 2 1268 #define regAZALIA_CRC1_RESULT 0x03ec 1269 #define regAZALIA_CRC1_RESULT_BASE_IDX 2 1270 #define regAZALIA_SOFT_RESET 0x03ed 1271 #define regAZALIA_SOFT_RESET_BASE_IDX 2 1272 #define regAZALIA_MEM_PWR_CTRL 0x03ee 1273 #define regAZALIA_MEM_PWR_CTRL_BASE_IDX 2 1274 #define regAZALIA_MEM_PWR_STATUS 0x03ef 1275 #define regAZALIA_MEM_PWR_STATUS_BASE_IDX 2 1276 1277 1278 // addressBlock: dcn_dcec_hda_azf0root_dispdec 1279 // base address: 0x0 1280 #define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406 1281 #define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2 1282 #define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407 1283 #define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2 1284 #define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408 1285 #define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2 1286 #define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409 1287 #define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2 1288 #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a 1289 #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2 1290 #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b 1291 #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2 1292 #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c 1293 #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2 1294 #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d 1295 #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2 1296 #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e 1297 #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2 1298 #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f 1299 #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2 1300 #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410 1301 #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2 1302 #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411 1303 #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2 1304 #define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x0412 1305 #define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 1306 #define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0413 1307 #define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 1308 #define regREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c 1309 #define regREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 1310 #define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d 1311 #define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 1312 1313 1314 // addressBlock: dcn_dcec_hda_az_misc_dispdec 1315 // base address: 0x0 1316 #define regAZ_CLOCK_CNTL 0x0372 1317 #define regAZ_CLOCK_CNTL_BASE_IDX 2 1318 #define regAZ_MEM_GLOBAL_PWR_REQ_CNTL 0x0373 1319 #define regAZ_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 2 1320 #define regAZ_STRAPS 0x0374 1321 #define regAZ_STRAPS_BASE_IDX 2 1322 1323 1324 // addressBlock: dcn_dcec_hda_azf0stream0_dispdec 1325 // base address: 0x0 1326 #define regAZF0STREAM0_AZALIA_STREAM_INDEX 0x035e 1327 #define regAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2 1328 #define regAZF0STREAM0_AZALIA_STREAM_DATA 0x035f 1329 #define regAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2 1330 1331 1332 // addressBlock: dcn_dcec_hda_azf0stream1_dispdec 1333 // base address: 0x8 1334 #define regAZF0STREAM1_AZALIA_STREAM_INDEX 0x0360 1335 #define regAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2 1336 #define regAZF0STREAM1_AZALIA_STREAM_DATA 0x0361 1337 #define regAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2 1338 1339 1340 // addressBlock: dcn_dcec_hda_azf0stream2_dispdec 1341 // base address: 0x10 1342 #define regAZF0STREAM2_AZALIA_STREAM_INDEX 0x0362 1343 #define regAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2 1344 #define regAZF0STREAM2_AZALIA_STREAM_DATA 0x0363 1345 #define regAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2 1346 1347 1348 // addressBlock: dcn_dcec_hda_azf0stream3_dispdec 1349 // base address: 0x18 1350 #define regAZF0STREAM3_AZALIA_STREAM_INDEX 0x0364 1351 #define regAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2 1352 #define regAZF0STREAM3_AZALIA_STREAM_DATA 0x0365 1353 #define regAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2 1354 1355 1356 // addressBlock: dcn_dcec_hda_azf0stream4_dispdec 1357 // base address: 0x20 1358 #define regAZF0STREAM4_AZALIA_STREAM_INDEX 0x0366 1359 #define regAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2 1360 #define regAZF0STREAM4_AZALIA_STREAM_DATA 0x0367 1361 #define regAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2 1362 1363 1364 // addressBlock: dcn_dcec_hda_azf0stream5_dispdec 1365 // base address: 0x28 1366 #define regAZF0STREAM5_AZALIA_STREAM_INDEX 0x0368 1367 #define regAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2 1368 #define regAZF0STREAM5_AZALIA_STREAM_DATA 0x0369 1369 #define regAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2 1370 1371 1372 // addressBlock: dcn_dcec_hda_azf0stream6_dispdec 1373 // base address: 0x30 1374 #define regAZF0STREAM6_AZALIA_STREAM_INDEX 0x036a 1375 #define regAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2 1376 #define regAZF0STREAM6_AZALIA_STREAM_DATA 0x036b 1377 #define regAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2 1378 1379 1380 // addressBlock: dcn_dcec_hda_azf0stream7_dispdec 1381 // base address: 0x38 1382 #define regAZF0STREAM7_AZALIA_STREAM_INDEX 0x036c 1383 #define regAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2 1384 #define regAZF0STREAM7_AZALIA_STREAM_DATA 0x036d 1385 #define regAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2 1386 1387 1388 // addressBlock: dcn_dcec_hda_azf0stream8_dispdec 1389 // base address: 0x320 1390 #define regAZF0STREAM8_AZALIA_STREAM_INDEX 0x0426 1391 #define regAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2 1392 #define regAZF0STREAM8_AZALIA_STREAM_DATA 0x0427 1393 #define regAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2 1394 1395 1396 // addressBlock: dcn_dcec_hda_azf0stream9_dispdec 1397 // base address: 0x328 1398 #define regAZF0STREAM9_AZALIA_STREAM_INDEX 0x0428 1399 #define regAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2 1400 #define regAZF0STREAM9_AZALIA_STREAM_DATA 0x0429 1401 #define regAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2 1402 1403 1404 // addressBlock: dcn_dcec_hda_azf0stream10_dispdec 1405 // base address: 0x330 1406 #define regAZF0STREAM10_AZALIA_STREAM_INDEX 0x042a 1407 #define regAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2 1408 #define regAZF0STREAM10_AZALIA_STREAM_DATA 0x042b 1409 #define regAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2 1410 1411 1412 // addressBlock: dcn_dcec_hda_azf0stream11_dispdec 1413 // base address: 0x338 1414 #define regAZF0STREAM11_AZALIA_STREAM_INDEX 0x042c 1415 #define regAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2 1416 #define regAZF0STREAM11_AZALIA_STREAM_DATA 0x042d 1417 #define regAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2 1418 1419 1420 // addressBlock: dcn_dcec_hda_azf0stream12_dispdec 1421 // base address: 0x340 1422 #define regAZF0STREAM12_AZALIA_STREAM_INDEX 0x042e 1423 #define regAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2 1424 #define regAZF0STREAM12_AZALIA_STREAM_DATA 0x042f 1425 #define regAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2 1426 1427 1428 // addressBlock: dcn_dcec_hda_azf0stream13_dispdec 1429 // base address: 0x348 1430 #define regAZF0STREAM13_AZALIA_STREAM_INDEX 0x0430 1431 #define regAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2 1432 #define regAZF0STREAM13_AZALIA_STREAM_DATA 0x0431 1433 #define regAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2 1434 1435 1436 // addressBlock: dcn_dcec_hda_azf0stream14_dispdec 1437 // base address: 0x350 1438 #define regAZF0STREAM14_AZALIA_STREAM_INDEX 0x0432 1439 #define regAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2 1440 #define regAZF0STREAM14_AZALIA_STREAM_DATA 0x0433 1441 #define regAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2 1442 1443 1444 // addressBlock: dcn_dcec_hda_azf0stream15_dispdec 1445 // base address: 0x358 1446 #define regAZF0STREAM15_AZALIA_STREAM_INDEX 0x0434 1447 #define regAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2 1448 #define regAZF0STREAM15_AZALIA_STREAM_DATA 0x0435 1449 #define regAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2 1450 1451 1452 // addressBlock: dcn_dcec_hda_azf0endpoint0_dispdec 1453 // base address: 0x0 1454 #define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386 1455 #define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1456 #define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387 1457 #define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1458 1459 1460 // addressBlock: dcn_dcec_hda_azf0endpoint1_dispdec 1461 // base address: 0x18 1462 #define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c 1463 #define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1464 #define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d 1465 #define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1466 1467 1468 // addressBlock: dcn_dcec_hda_azf0endpoint2_dispdec 1469 // base address: 0x30 1470 #define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0392 1471 #define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1472 #define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0393 1473 #define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1474 1475 1476 // addressBlock: dcn_dcec_hda_azf0endpoint3_dispdec 1477 // base address: 0x48 1478 #define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0398 1479 #define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1480 #define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0399 1481 #define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1482 1483 1484 // addressBlock: dcn_dcec_hda_azf0endpoint4_dispdec 1485 // base address: 0x60 1486 #define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x039e 1487 #define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1488 #define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x039f 1489 #define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1490 1491 1492 // addressBlock: dcn_dcec_hda_azf0endpoint5_dispdec 1493 // base address: 0x78 1494 #define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03a4 1495 #define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1496 #define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03a5 1497 #define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1498 1499 1500 // addressBlock: dcn_dcec_hda_azf0endpoint6_dispdec 1501 // base address: 0x90 1502 #define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03aa 1503 #define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1504 #define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03ab 1505 #define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1506 1507 1508 // addressBlock: dcn_dcec_hda_azf0endpoint7_dispdec 1509 // base address: 0xa8 1510 #define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03b0 1511 #define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1512 #define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03b1 1513 #define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1514 1515 1516 // addressBlock: dcn_dcec_hda_azf0inputendpoint0_dispdec 1517 // base address: 0x0 1518 #define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a 1519 #define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1520 #define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b 1521 #define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1522 1523 1524 // addressBlock: dcn_dcec_hda_azf0inputendpoint1_dispdec 1525 // base address: 0x10 1526 #define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e 1527 #define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1528 #define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f 1529 #define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1530 1531 1532 // addressBlock: dcn_dcec_hda_azf0inputendpoint2_dispdec 1533 // base address: 0x20 1534 #define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0442 1535 #define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1536 #define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0443 1537 #define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1538 1539 1540 // addressBlock: dcn_dcec_hda_azf0inputendpoint3_dispdec 1541 // base address: 0x30 1542 #define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0446 1543 #define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1544 #define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0447 1545 #define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1546 1547 1548 // addressBlock: dcn_dcec_hda_azf0inputendpoint4_dispdec 1549 // base address: 0x40 1550 #define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044a 1551 #define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1552 #define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044b 1553 #define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1554 1555 1556 // addressBlock: dcn_dcec_hda_azf0inputendpoint5_dispdec 1557 // base address: 0x50 1558 #define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044e 1559 #define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1560 #define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044f 1561 #define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1562 1563 1564 // addressBlock: dcn_dcec_hda_azf0inputendpoint6_dispdec 1565 // base address: 0x60 1566 #define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0452 1567 #define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1568 #define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0453 1569 #define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1570 1571 1572 // addressBlock: dcn_dcec_hda_azf0inputendpoint7_dispdec 1573 // base address: 0x70 1574 #define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0456 1575 #define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1576 #define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0457 1577 #define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1578 1579 1580 // addressBlock: dcn_dcec_dchubbubl_hubbub_dispdec 1581 // base address: 0x0 1582 #define regDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x04f9 1583 #define regDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2 1584 #define regDCHUBBUB_ARB_SAT_LEVEL 0x04fa 1585 #define regDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2 1586 #define regDCHUBBUB_ARB_QOS_FORCE 0x04fb 1587 #define regDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2 1588 #define regDCHUBBUB_ARB_DRAM_STATE_CNTL 0x04fc 1589 #define regDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2 1590 #define regDCHUBBUB_ARB_USR_RETRAINING_CNTL 0x04fd 1591 #define regDCHUBBUB_ARB_USR_RETRAINING_CNTL_BASE_IDX 2 1592 #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x04fe 1593 #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2 1594 #define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A 0x04ff 1595 #define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A_BASE_IDX 2 1596 #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A 0x0500 1597 #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX 2 1598 #define regDCHUBBUB_ARB_REFCYC_PER_META_TRIP_A 0x0501 1599 #define regDCHUBBUB_ARB_REFCYC_PER_META_TRIP_A_BASE_IDX 2 1600 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0x0502 1601 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX 2 1602 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0x0503 1603 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX 2 1604 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A 0x0504 1605 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A_BASE_IDX 2 1606 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A 0x0505 1607 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A_BASE_IDX 2 1608 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A 0x0506 1609 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A_BASE_IDX 2 1610 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A 0x0507 1611 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A_BASE_IDX 2 1612 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A 0x0508 1613 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A_BASE_IDX 2 1614 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A 0x0509 1615 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A_BASE_IDX 2 1616 #define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A 0x050a 1617 #define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX 2 1618 #define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A 0x050b 1619 #define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A_BASE_IDX 2 1620 #define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A 0x050c 1621 #define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX 2 1622 #define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A 0x050d 1623 #define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A_BASE_IDX 2 1624 #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A 0x050e 1625 #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX 2 1626 #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A 0x050f 1627 #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX 2 1628 #define regDCHUBBUB_ARB_FRAC_URG_BW_MALL_A 0x0510 1629 #define regDCHUBBUB_ARB_FRAC_URG_BW_MALL_A_BASE_IDX 2 1630 #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x0511 1631 #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2 1632 #define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B 0x0512 1633 #define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B_BASE_IDX 2 1634 #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B 0x0513 1635 #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX 2 1636 #define regDCHUBBUB_ARB_REFCYC_PER_META_TRIP_B 0x0514 1637 #define regDCHUBBUB_ARB_REFCYC_PER_META_TRIP_B_BASE_IDX 2 1638 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0x0515 1639 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX 2 1640 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0x0516 1641 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX 2 1642 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B 0x0517 1643 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B_BASE_IDX 2 1644 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B 0x0518 1645 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B_BASE_IDX 2 1646 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B 0x0519 1647 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B_BASE_IDX 2 1648 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B 0x051a 1649 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B_BASE_IDX 2 1650 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B 0x051b 1651 #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B_BASE_IDX 2 1652 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B 0x051c 1653 #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B_BASE_IDX 2 1654 #define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B 0x051d 1655 #define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX 2 1656 #define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B 0x051e 1657 #define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B_BASE_IDX 2 1658 #define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B 0x051f 1659 #define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX 2 1660 #define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B 0x0520 1661 #define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B_BASE_IDX 2 1662 #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B 0x0521 1663 #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX 2 1664 #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B 0x0522 1665 #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX 2 1666 #define regDCHUBBUB_ARB_FRAC_URG_BW_MALL_B 0x0523 1667 #define regDCHUBBUB_ARB_FRAC_URG_BW_MALL_B_BASE_IDX 2 1668 #define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x0524 1669 #define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2 1670 #define regDCHUBBUB_ARB_MALL_CNTL 0x0525 1671 #define regDCHUBBUB_ARB_MALL_CNTL_BASE_IDX 2 1672 #define regDCHUBBUB_ARB_TIMEOUT_ENABLE 0x0526 1673 #define regDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2 1674 #define regDCHUBBUB_GLOBAL_TIMER_CNTL 0x0527 1675 #define regDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2 1676 #define regSURFACE_CHECK0_ADDRESS_LSB 0x0528 1677 #define regSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX 2 1678 #define regSURFACE_CHECK0_ADDRESS_MSB 0x0529 1679 #define regSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX 2 1680 #define regSURFACE_CHECK1_ADDRESS_LSB 0x052a 1681 #define regSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX 2 1682 #define regSURFACE_CHECK1_ADDRESS_MSB 0x052b 1683 #define regSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX 2 1684 #define regSURFACE_CHECK2_ADDRESS_LSB 0x052c 1685 #define regSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX 2 1686 #define regSURFACE_CHECK2_ADDRESS_MSB 0x052d 1687 #define regSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX 2 1688 #define regSURFACE_CHECK3_ADDRESS_LSB 0x052e 1689 #define regSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX 2 1690 #define regSURFACE_CHECK3_ADDRESS_MSB 0x052f 1691 #define regSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX 2 1692 #define regVTG0_CONTROL 0x0530 1693 #define regVTG0_CONTROL_BASE_IDX 2 1694 #define regVTG1_CONTROL 0x0531 1695 #define regVTG1_CONTROL_BASE_IDX 2 1696 #define regVTG2_CONTROL 0x0532 1697 #define regVTG2_CONTROL_BASE_IDX 2 1698 #define regVTG3_CONTROL 0x0533 1699 #define regVTG3_CONTROL_BASE_IDX 2 1700 #define regDCHUBBUB_SOFT_RESET 0x0534 1701 #define regDCHUBBUB_SOFT_RESET_BASE_IDX 2 1702 #define regDCHUBBUB_CLOCK_CNTL 0x0535 1703 #define regDCHUBBUB_CLOCK_CNTL_BASE_IDX 2 1704 #define regDCFCLK_CNTL 0x0536 1705 #define regDCFCLK_CNTL_BASE_IDX 2 1706 #define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0x0537 1707 #define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX 2 1708 #define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0x0538 1709 #define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX 2 1710 #define regDCHUBBUB_VLINE_SNAPSHOT 0x0539 1711 #define regDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2 1712 #define regDCHUBBUB_CTRL_STATUS 0x053a 1713 #define regDCHUBBUB_CTRL_STATUS_BASE_IDX 2 1714 #define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1 0x0540 1715 #define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX 2 1716 #define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2 0x0541 1717 #define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX 2 1718 #define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS 0x0542 1719 #define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX 2 1720 #define regFMON_CTRL 0x0543 1721 #define regFMON_CTRL_BASE_IDX 2 1722 #define regDCHUBBUB_TEST_DEBUG_INDEX 0x0544 1723 #define regDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX 2 1724 #define regDCHUBBUB_TEST_DEBUG_DATA 0x0545 1725 #define regDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX 2 1726 1727 1728 // addressBlock: dcn_dcec_dchubbubl_hubbub_sdpif_dispdec 1729 // base address: 0x0 1730 #define regDCHUBBUB_SDPIF_CFG0 0x046f 1731 #define regDCHUBBUB_SDPIF_CFG0_BASE_IDX 2 1732 #define regDCHUBBUB_SDPIF_CFG1 0x0470 1733 #define regDCHUBBUB_SDPIF_CFG1_BASE_IDX 2 1734 #define regDCHUBBUB_SDPIF_CFG2 0x0471 1735 #define regDCHUBBUB_SDPIF_CFG2_BASE_IDX 2 1736 #define regVM_REQUEST_PHYSICAL 0x0472 1737 #define regVM_REQUEST_PHYSICAL_BASE_IDX 2 1738 #define regDCHUBBUB_FORCE_IO_STATUS_0 0x0473 1739 #define regDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX 2 1740 #define regDCHUBBUB_FORCE_IO_STATUS_1 0x0474 1741 #define regDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX 2 1742 #define regDCN_VM_FB_LOCATION_BASE 0x0475 1743 #define regDCN_VM_FB_LOCATION_BASE_BASE_IDX 2 1744 #define regDCN_VM_FB_LOCATION_TOP 0x0476 1745 #define regDCN_VM_FB_LOCATION_TOP_BASE_IDX 2 1746 #define regDCN_VM_FB_OFFSET 0x0477 1747 #define regDCN_VM_FB_OFFSET_BASE_IDX 2 1748 #define regDCN_VM_AGP_BOT 0x0478 1749 #define regDCN_VM_AGP_BOT_BASE_IDX 2 1750 #define regDCN_VM_AGP_TOP 0x0479 1751 #define regDCN_VM_AGP_TOP_BASE_IDX 2 1752 #define regDCN_VM_AGP_BASE 0x047a 1753 #define regDCN_VM_AGP_BASE_BASE_IDX 2 1754 #define regDCN_VM_LOCAL_HBM_ADDRESS_START 0x047b 1755 #define regDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 2 1756 #define regDCN_VM_LOCAL_HBM_ADDRESS_END 0x047c 1757 #define regDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 2 1758 #define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x047d 1759 #define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 2 1760 #define regDCHUBBUB_SDPIF_PIPE_SEC_LVL 0x047e 1761 #define regDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX 2 1762 #define regDCHUBBUB_SDPIF_PIPE_NOALLOC 0x047f 1763 #define regDCHUBBUB_SDPIF_PIPE_NOALLOC_BASE_IDX 2 1764 #define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL 0x0480 1765 #define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL_BASE_IDX 2 1766 #define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL 0x0481 1767 #define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL_BASE_IDX 2 1768 #define regDCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL 0x0482 1769 #define regDCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL_BASE_IDX 2 1770 #define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL 0x0483 1771 #define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL_BASE_IDX 2 1772 #define regDCHUBBUB_SDPIF_PIPE_DATAFETCH 0x0484 1773 #define regDCHUBBUB_SDPIF_PIPE_DATAFETCH_BASE_IDX 2 1774 #define regSDPIF_REQUEST_RATE_LIMIT 0x0485 1775 #define regSDPIF_REQUEST_RATE_LIMIT_BASE_IDX 2 1776 #define regDCHUBBUB_SDPIF_MEM_PWR_CTRL 0x0486 1777 #define regDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX 2 1778 #define regDCHUBBUB_SDPIF_MEM_PWR_STATUS 0x0487 1779 #define regDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX 2 1780 #define regDCHUBBUB_SDPIF_MCACHE_INVALIDATION_CTL 0x0488 1781 #define regDCHUBBUB_SDPIF_MCACHE_INVALIDATION_CTL_BASE_IDX 2 1782 1783 1784 // addressBlock: dcn_dcec_dchubbubl_hubbub_ret_path_dispdec 1785 // base address: 0x0 1786 #define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04af 1787 #define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2 1788 #define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04b0 1789 #define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2 1790 #define regDCHUBBUB_CRC_CTRL 0x04b1 1791 #define regDCHUBBUB_CRC_CTRL_BASE_IDX 2 1792 #define regDCHUBBUB_CRC0_VAL_R_G 0x04b2 1793 #define regDCHUBBUB_CRC0_VAL_R_G_BASE_IDX 2 1794 #define regDCHUBBUB_CRC0_VAL_B_A 0x04b3 1795 #define regDCHUBBUB_CRC0_VAL_B_A_BASE_IDX 2 1796 #define regDCHUBBUB_CRC1_VAL_R_G 0x04b4 1797 #define regDCHUBBUB_CRC1_VAL_R_G_BASE_IDX 2 1798 #define regDCHUBBUB_CRC1_VAL_B_A 0x04b5 1799 #define regDCHUBBUB_CRC1_VAL_B_A_BASE_IDX 2 1800 #define regDCHUBBUB_DCC_STAT_CNTL 0x04b6 1801 #define regDCHUBBUB_DCC_STAT_CNTL_BASE_IDX 2 1802 #define regDCHUBBUB_DCC_STAT0 0x04b7 1803 #define regDCHUBBUB_DCC_STAT0_BASE_IDX 2 1804 #define regDCHUBBUB_DCC_STAT1 0x04b8 1805 #define regDCHUBBUB_DCC_STAT1_BASE_IDX 2 1806 #define regDCHUBBUB_DCC_STAT2 0x04b9 1807 #define regDCHUBBUB_DCC_STAT2_BASE_IDX 2 1808 #define regDCHUBBUB_COMPBUF_CTRL 0x04ba 1809 #define regDCHUBBUB_COMPBUF_CTRL_BASE_IDX 2 1810 #define regDCHUBBUB_DET0_CTRL 0x04bb 1811 #define regDCHUBBUB_DET0_CTRL_BASE_IDX 2 1812 #define regDCHUBBUB_DET1_CTRL 0x04bc 1813 #define regDCHUBBUB_DET1_CTRL_BASE_IDX 2 1814 #define regDCHUBBUB_DET2_CTRL 0x04bd 1815 #define regDCHUBBUB_DET2_CTRL_BASE_IDX 2 1816 #define regDCHUBBUB_DET3_CTRL 0x04be 1817 #define regDCHUBBUB_DET3_CTRL_BASE_IDX 2 1818 #define regDCHUBBUB_STAT 0x04bf 1819 #define regDCHUBBUB_STAT_BASE_IDX 2 1820 #define regDCHUBBUB_MEM_PWR_MODE_CTRL 0x04c0 1821 #define regDCHUBBUB_MEM_PWR_MODE_CTRL_BASE_IDX 2 1822 #define regCOMPBUF_MEM_PWR_CTRL_1 0x04c1 1823 #define regCOMPBUF_MEM_PWR_CTRL_1_BASE_IDX 2 1824 #define regCOMPBUF_MEM_PWR_CTRL_2 0x04c2 1825 #define regCOMPBUF_MEM_PWR_CTRL_2_BASE_IDX 2 1826 #define regDCHUBBUB_MEM_PWR_STATUS 0x04c3 1827 #define regDCHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 1828 #define regCOMPBUF_RESERVED_SPACE 0x04c4 1829 #define regCOMPBUF_RESERVED_SPACE_BASE_IDX 2 1830 #define regDCN_DECOMP_STATUS 0x04c5 1831 #define regDCN_DECOMP_STATUS_BASE_IDX 2 1832 #define regDCHUBBUB_DEBUG_CTRL_0 0x04c6 1833 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2 1834 #define regDCHUBBUB_DEBUG_CTRL_1 0x04c7 1835 #define regDCHUBBUB_DEBUG_CTRL_1_BASE_IDX 2 1836 #define regDCHUBBUB_DEBUG_CTRL_2 0x04c8 1837 #define regDCHUBBUB_DEBUG_CTRL_2_BASE_IDX 2 1838 #define regDCHUBBUB_RET_PATH_TEST_DEBUG_INDEX 0x04c9 1839 #define regDCHUBBUB_RET_PATH_TEST_DEBUG_INDEX_BASE_IDX 2 1840 #define regDCHUBBUB_RET_PATH_TEST_DEBUG_DATA 0x04ca 1841 #define regDCHUBBUB_RET_PATH_TEST_DEBUG_DATA_BASE_IDX 2 1842 1843 1844 // addressBlock: dcn_dcec_dchubbubl_hubbub_vmrq_if_dispdec 1845 // base address: 0x0 1846 #define regDCN_VM_CONTEXT0_CNTL 0x0559 1847 #define regDCN_VM_CONTEXT0_CNTL_BASE_IDX 2 1848 #define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x055a 1849 #define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1850 #define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x055b 1851 #define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1852 #define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x055c 1853 #define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1854 #define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x055d 1855 #define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1856 #define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x055e 1857 #define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1858 #define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x055f 1859 #define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1860 #define regDCN_VM_CONTEXT1_CNTL 0x0560 1861 #define regDCN_VM_CONTEXT1_CNTL_BASE_IDX 2 1862 #define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0561 1863 #define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1864 #define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0562 1865 #define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1866 #define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0563 1867 #define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1868 #define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0564 1869 #define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1870 #define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0565 1871 #define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1872 #define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0566 1873 #define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1874 #define regDCN_VM_CONTEXT2_CNTL 0x0567 1875 #define regDCN_VM_CONTEXT2_CNTL_BASE_IDX 2 1876 #define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0568 1877 #define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1878 #define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0569 1879 #define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1880 #define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x056a 1881 #define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1882 #define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x056b 1883 #define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1884 #define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x056c 1885 #define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1886 #define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x056d 1887 #define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1888 #define regDCN_VM_CONTEXT3_CNTL 0x056e 1889 #define regDCN_VM_CONTEXT3_CNTL_BASE_IDX 2 1890 #define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x056f 1891 #define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1892 #define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0570 1893 #define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1894 #define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0571 1895 #define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1896 #define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0572 1897 #define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1898 #define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0573 1899 #define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1900 #define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0574 1901 #define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1902 #define regDCN_VM_CONTEXT4_CNTL 0x0575 1903 #define regDCN_VM_CONTEXT4_CNTL_BASE_IDX 2 1904 #define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0576 1905 #define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1906 #define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0577 1907 #define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1908 #define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0578 1909 #define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1910 #define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0579 1911 #define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1912 #define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x057a 1913 #define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1914 #define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x057b 1915 #define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1916 #define regDCN_VM_CONTEXT5_CNTL 0x057c 1917 #define regDCN_VM_CONTEXT5_CNTL_BASE_IDX 2 1918 #define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x057d 1919 #define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1920 #define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x057e 1921 #define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1922 #define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x057f 1923 #define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1924 #define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0580 1925 #define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1926 #define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0581 1927 #define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1928 #define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0582 1929 #define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1930 #define regDCN_VM_CONTEXT6_CNTL 0x0583 1931 #define regDCN_VM_CONTEXT6_CNTL_BASE_IDX 2 1932 #define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0584 1933 #define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1934 #define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0585 1935 #define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1936 #define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0586 1937 #define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1938 #define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0587 1939 #define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1940 #define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0588 1941 #define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1942 #define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0589 1943 #define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1944 #define regDCN_VM_CONTEXT7_CNTL 0x058a 1945 #define regDCN_VM_CONTEXT7_CNTL_BASE_IDX 2 1946 #define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x058b 1947 #define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1948 #define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x058c 1949 #define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1950 #define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x058d 1951 #define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1952 #define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x058e 1953 #define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1954 #define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x058f 1955 #define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1956 #define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0590 1957 #define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1958 #define regDCN_VM_CONTEXT8_CNTL 0x0591 1959 #define regDCN_VM_CONTEXT8_CNTL_BASE_IDX 2 1960 #define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0592 1961 #define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1962 #define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0593 1963 #define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1964 #define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0594 1965 #define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1966 #define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0595 1967 #define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1968 #define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0596 1969 #define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1970 #define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0597 1971 #define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1972 #define regDCN_VM_CONTEXT9_CNTL 0x0598 1973 #define regDCN_VM_CONTEXT9_CNTL_BASE_IDX 2 1974 #define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0599 1975 #define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1976 #define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x059a 1977 #define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1978 #define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x059b 1979 #define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1980 #define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x059c 1981 #define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1982 #define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x059d 1983 #define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1984 #define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x059e 1985 #define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1986 #define regDCN_VM_CONTEXT10_CNTL 0x059f 1987 #define regDCN_VM_CONTEXT10_CNTL_BASE_IDX 2 1988 #define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x05a0 1989 #define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1990 #define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x05a1 1991 #define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1992 #define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x05a2 1993 #define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1994 #define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x05a3 1995 #define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1996 #define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x05a4 1997 #define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1998 #define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x05a5 1999 #define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2000 #define regDCN_VM_CONTEXT11_CNTL 0x05a6 2001 #define regDCN_VM_CONTEXT11_CNTL_BASE_IDX 2 2002 #define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x05a7 2003 #define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2004 #define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x05a8 2005 #define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2006 #define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x05a9 2007 #define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2008 #define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x05aa 2009 #define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2010 #define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x05ab 2011 #define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2012 #define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x05ac 2013 #define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2014 #define regDCN_VM_CONTEXT12_CNTL 0x05ad 2015 #define regDCN_VM_CONTEXT12_CNTL_BASE_IDX 2 2016 #define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x05ae 2017 #define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2018 #define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x05af 2019 #define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2020 #define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x05b0 2021 #define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2022 #define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x05b1 2023 #define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2024 #define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x05b2 2025 #define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2026 #define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x05b3 2027 #define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2028 #define regDCN_VM_CONTEXT13_CNTL 0x05b4 2029 #define regDCN_VM_CONTEXT13_CNTL_BASE_IDX 2 2030 #define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x05b5 2031 #define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2032 #define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x05b6 2033 #define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2034 #define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x05b7 2035 #define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2036 #define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x05b8 2037 #define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2038 #define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x05b9 2039 #define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2040 #define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x05ba 2041 #define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2042 #define regDCN_VM_CONTEXT14_CNTL 0x05bb 2043 #define regDCN_VM_CONTEXT14_CNTL_BASE_IDX 2 2044 #define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x05bc 2045 #define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2046 #define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x05bd 2047 #define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2048 #define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x05be 2049 #define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2050 #define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x05bf 2051 #define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2052 #define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x05c0 2053 #define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2054 #define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x05c1 2055 #define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2056 #define regDCN_VM_CONTEXT15_CNTL 0x05c2 2057 #define regDCN_VM_CONTEXT15_CNTL_BASE_IDX 2 2058 #define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x05c3 2059 #define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2060 #define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x05c4 2061 #define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2062 #define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x05c5 2063 #define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2064 #define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x05c6 2065 #define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2066 #define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x05c7 2067 #define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2068 #define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x05c8 2069 #define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2070 #define regDCN_VM_DEFAULT_ADDR_MSB 0x05c9 2071 #define regDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX 2 2072 #define regDCN_VM_DEFAULT_ADDR_LSB 0x05ca 2073 #define regDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX 2 2074 #define regDCN_VM_FAULT_CNTL 0x05cb 2075 #define regDCN_VM_FAULT_CNTL_BASE_IDX 2 2076 #define regDCN_VM_FAULT_STATUS 0x05cc 2077 #define regDCN_VM_FAULT_STATUS_BASE_IDX 2 2078 #define regDCN_VM_FAULT_ADDR_MSB 0x05cd 2079 #define regDCN_VM_FAULT_ADDR_MSB_BASE_IDX 2 2080 #define regDCN_VM_FAULT_ADDR_LSB 0x05ce 2081 #define regDCN_VM_FAULT_ADDR_LSB_BASE_IDX 2 2082 2083 2084 // addressBlock: dcn_dcec_dcbubp0_dispdec_hubp_dispdec 2085 // base address: 0x0 2086 #define regHUBP0_DCSURF_SURFACE_CONFIG 0x05e5 2087 #define regHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2 2088 #define regHUBP0_DCSURF_ADDR_CONFIG 0x05e6 2089 #define regHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2 2090 #define regHUBP0_DCSURF_TILING_CONFIG 0x05e7 2091 #define regHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2 2092 #define regHUBP0_DCSURF_PRI_VIEWPORT_START 0x05e9 2093 #define regHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 2094 #define regHUBP0_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE 0x05ea 2095 #define regHUBP0_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE_BASE_IDX 2 2096 #define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x05eb 2097 #define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 2098 #define regHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x05ec 2099 #define regHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 2100 #define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x05ed 2101 #define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 2102 #define regHUBP0_DCSURF_SEC_VIEWPORT_START 0x05ee 2103 #define regHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 2104 #define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x05ef 2105 #define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 2106 #define regHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x05f0 2107 #define regHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 2108 #define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x05f1 2109 #define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 2110 #define regHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x05f2 2111 #define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 2112 #define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x05f3 2113 #define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 2114 #define regHUBP0_DCHUBP_CNTL 0x05f4 2115 #define regHUBP0_DCHUBP_CNTL_BASE_IDX 2 2116 #define regHUBP0_HUBP_CLK_CNTL 0x05f5 2117 #define regHUBP0_HUBP_CLK_CNTL_BASE_IDX 2 2118 #define regHUBP0_DCHUBP_VMPG_CONFIG 0x05f6 2119 #define regHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2 2120 #define regHUBP0_DCHUBP_MALL_CONFIG 0x05f7 2121 #define regHUBP0_DCHUBP_MALL_CONFIG_BASE_IDX 2 2122 #define regHUBP0_DCHUBP_MALL_SUB_VP0 0x05f8 2123 #define regHUBP0_DCHUBP_MALL_SUB_VP0_BASE_IDX 2 2124 #define regHUBP0_DCHUBP_MALL_SUB_VP1 0x05f9 2125 #define regHUBP0_DCHUBP_MALL_SUB_VP1_BASE_IDX 2 2126 #define regHUBP0_DCHUBP_MALL_SUB_VP2 0x05fa 2127 #define regHUBP0_DCHUBP_MALL_SUB_VP2_BASE_IDX 2 2128 #define regHUBP0_DCHUBP_MCACHEID_CONFIG 0x05fb 2129 #define regHUBP0_DCHUBP_MCACHEID_CONFIG_BASE_IDX 2 2130 #define regHUBP0_HUBPREQ_DEBUG_DB 0x05fc 2131 #define regHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2 2132 #define regHUBP0_HUBPREQ_DEBUG 0x05fd 2133 #define regHUBP0_HUBPREQ_DEBUG_BASE_IDX 2 2134 #define regHUBP0_HUBP_DEBUG_CTRL 0x05fe 2135 #define regHUBP0_HUBP_DEBUG_CTRL_BASE_IDX 2 2136 #define regHUBP0_HUBP_DEBUG_MUX_DCFCLK 0x05ff 2137 #define regHUBP0_HUBP_DEBUG_MUX_DCFCLK_BASE_IDX 2 2138 #define regHUBP0_HUBP_DEBUG_MUX_DPPCLK 0x0600 2139 #define regHUBP0_HUBP_DEBUG_MUX_DPPCLK_BASE_IDX 2 2140 #define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x0601 2141 #define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 2142 #define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0602 2143 #define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 2144 #define regHUBP0_HUBP_MALL_STATUS 0x0603 2145 #define regHUBP0_HUBP_MALL_STATUS_BASE_IDX 2 2146 2147 2148 // addressBlock: dcn_dcec_dcbubp0_dispdec_hubpreq_dispdec 2149 // base address: 0x0 2150 #define regHUBPREQ0_DCSURF_SURFACE_PITCH 0x0607 2151 #define regHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2 2152 #define regHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x0608 2153 #define regHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 2154 #define regHUBPREQ0_VMID_SETTINGS_0 0x0609 2155 #define regHUBPREQ0_VMID_SETTINGS_0_BASE_IDX 2 2156 #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x060a 2157 #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 2158 #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x060b 2159 #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2160 #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x060c 2161 #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 2162 #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x060d 2163 #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2164 #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x060e 2165 #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 2166 #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x060f 2167 #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2168 #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0610 2169 #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 2170 #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0611 2171 #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2172 #define regHUBPREQ0_DCSURF_SURFACE_CONTROL 0x0612 2173 #define regHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2 2174 #define regHUBPREQ0_DCSURF_FLIP_CONTROL 0x0613 2175 #define regHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2 2176 #define regHUBPREQ0_DCSURF_FLIP_CONTROL2 0x0614 2177 #define regHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2 2178 #define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x0617 2179 #define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 2180 #define regHUBPREQ0_DCSURF_SURFACE_INUSE 0x0618 2181 #define regHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2 2182 #define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0619 2183 #define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 2184 #define regHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x061a 2185 #define regHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 2186 #define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x061b 2187 #define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 2188 #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x061c 2189 #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 2190 #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x061d 2191 #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 2192 #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x061e 2193 #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 2194 #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x061f 2195 #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 2196 #define regHUBPREQ0_DCN_EXPANSION_MODE 0x0620 2197 #define regHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2 2198 #define regHUBPREQ0_DCN_TTU_QOS_WM 0x0621 2199 #define regHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2 2200 #define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x0622 2201 #define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 2202 #define regHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x0623 2203 #define regHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 2204 #define regHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x0624 2205 #define regHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 2206 #define regHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x0625 2207 #define regHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 2208 #define regHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x0626 2209 #define regHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 2210 #define regHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x0627 2211 #define regHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 2212 #define regHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x0628 2213 #define regHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 2214 #define regHUBPREQ0_DCN_CUR1_TTU_CNTL0 0x0629 2215 #define regHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 2216 #define regHUBPREQ0_DCN_CUR1_TTU_CNTL1 0x062a 2217 #define regHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 2218 #define regHUBPREQ0_DCN_DMDATA_VM_CNTL 0x062b 2219 #define regHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX 2 2220 #define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x062c 2221 #define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 2222 #define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x062d 2223 #define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 2224 #define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0x063a 2225 #define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 2226 #define regHUBPREQ0_BLANK_OFFSET_0 0x063b 2227 #define regHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2 2228 #define regHUBPREQ0_BLANK_OFFSET_1 0x063c 2229 #define regHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2 2230 #define regHUBPREQ0_DST_DIMENSIONS 0x063d 2231 #define regHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2 2232 #define regHUBPREQ0_DST_AFTER_SCALER 0x063e 2233 #define regHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2 2234 #define regHUBPREQ0_PREFETCH_SETTINGS 0x063f 2235 #define regHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX 2 2236 #define regHUBPREQ0_PREFETCH_SETTINGS_C 0x0640 2237 #define regHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX 2 2238 #define regHUBPREQ0_VBLANK_PARAMETERS_0 0x0641 2239 #define regHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2 2240 #define regHUBPREQ0_VBLANK_PARAMETERS_1 0x0642 2241 #define regHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2 2242 #define regHUBPREQ0_VBLANK_PARAMETERS_2 0x0643 2243 #define regHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2 2244 #define regHUBPREQ0_VBLANK_PARAMETERS_3 0x0644 2245 #define regHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2 2246 #define regHUBPREQ0_VBLANK_PARAMETERS_4 0x0645 2247 #define regHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2 2248 #define regHUBPREQ0_FLIP_PARAMETERS_0 0x0646 2249 #define regHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX 2 2250 #define regHUBPREQ0_FLIP_PARAMETERS_1 0x0647 2251 #define regHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX 2 2252 #define regHUBPREQ0_FLIP_PARAMETERS_2 0x0648 2253 #define regHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX 2 2254 #define regHUBPREQ0_NOM_PARAMETERS_0 0x0649 2255 #define regHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX 2 2256 #define regHUBPREQ0_NOM_PARAMETERS_1 0x064a 2257 #define regHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX 2 2258 #define regHUBPREQ0_NOM_PARAMETERS_2 0x064b 2259 #define regHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX 2 2260 #define regHUBPREQ0_NOM_PARAMETERS_3 0x064c 2261 #define regHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX 2 2262 #define regHUBPREQ0_NOM_PARAMETERS_4 0x064d 2263 #define regHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2 2264 #define regHUBPREQ0_NOM_PARAMETERS_5 0x064e 2265 #define regHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2 2266 #define regHUBPREQ0_NOM_PARAMETERS_6 0x064f 2267 #define regHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2 2268 #define regHUBPREQ0_NOM_PARAMETERS_7 0x0650 2269 #define regHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2 2270 #define regHUBPREQ0_PER_LINE_DELIVERY_PRE 0x0651 2271 #define regHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2 2272 #define regHUBPREQ0_PER_LINE_DELIVERY 0x0652 2273 #define regHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2 2274 #define regHUBPREQ0_CURSOR_SETTINGS 0x0653 2275 #define regHUBPREQ0_CURSOR_SETTINGS_BASE_IDX 2 2276 #define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x0654 2277 #define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 2278 #define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT 0x0655 2279 #define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 2280 #define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x0656 2281 #define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 2282 #define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x0657 2283 #define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 2284 #define regHUBPREQ0_VBLANK_PARAMETERS_5 0x065a 2285 #define regHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX 2 2286 #define regHUBPREQ0_VBLANK_PARAMETERS_6 0x065b 2287 #define regHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX 2 2288 #define regHUBPREQ0_FLIP_PARAMETERS_3 0x065c 2289 #define regHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX 2 2290 #define regHUBPREQ0_FLIP_PARAMETERS_4 0x065d 2291 #define regHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX 2 2292 #define regHUBPREQ0_FLIP_PARAMETERS_5 0x065e 2293 #define regHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX 2 2294 #define regHUBPREQ0_FLIP_PARAMETERS_6 0x065f 2295 #define regHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX 2 2296 #define regHUBPREQ0_UCLK_PSTATE_FORCE 0x0660 2297 #define regHUBPREQ0_UCLK_PSTATE_FORCE_BASE_IDX 2 2298 #define regHUBPREQ0_HUBPREQ_STATUS_REG0 0x0661 2299 #define regHUBPREQ0_HUBPREQ_STATUS_REG0_BASE_IDX 2 2300 #define regHUBPREQ0_HUBPREQ_STATUS_REG1 0x0662 2301 #define regHUBPREQ0_HUBPREQ_STATUS_REG1_BASE_IDX 2 2302 #define regHUBPREQ0_HUBPREQ_STATUS_REG2 0x0663 2303 #define regHUBPREQ0_HUBPREQ_STATUS_REG2_BASE_IDX 2 2304 #define regHUBPREQ0_HUBPREQ_STATUS_REG3 0x0664 2305 #define regHUBPREQ0_HUBPREQ_STATUS_REG3_BASE_IDX 2 2306 2307 2308 // addressBlock: dcn_dcec_dcbubp0_dispdec_hubpret_dispdec 2309 // base address: 0x0 2310 #define regHUBPRET0_HUBPRET_CONTROL 0x066d 2311 #define regHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2 2312 #define regHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x066e 2313 #define regHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 2314 #define regHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x066f 2315 #define regHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 2316 #define regHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x0670 2317 #define regHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 2318 #define regHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x0671 2319 #define regHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 2320 #define regHUBPRET0_HUBPRET_READ_LINE0 0x0672 2321 #define regHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2 2322 #define regHUBPRET0_HUBPRET_READ_LINE1 0x0673 2323 #define regHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2 2324 #define regHUBPRET0_HUBPRET_INTERRUPT 0x0674 2325 #define regHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2 2326 #define regHUBPRET0_HUBPRET_READ_LINE_VALUE 0x0675 2327 #define regHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 2328 #define regHUBPRET0_HUBPRET_READ_LINE_STATUS 0x0676 2329 #define regHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 2330 2331 2332 // addressBlock: dcn_dcec_dcbubp0_dispdec_cursor0_dispdec 2333 // base address: 0x0 2334 #define regCURSOR0_0_CURSOR_CONTROL 0x0679 2335 #define regCURSOR0_0_CURSOR_CONTROL_BASE_IDX 2 2336 #define regCURSOR0_0_CURSOR_SURFACE_ADDRESS 0x067a 2337 #define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 2338 #define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH 0x067b 2339 #define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2340 #define regCURSOR0_0_CURSOR_SIZE 0x067c 2341 #define regCURSOR0_0_CURSOR_SIZE_BASE_IDX 2 2342 #define regCURSOR0_0_CURSOR_POSITION 0x067d 2343 #define regCURSOR0_0_CURSOR_POSITION_BASE_IDX 2 2344 #define regCURSOR0_0_CURSOR_HOT_SPOT 0x067e 2345 #define regCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX 2 2346 #define regCURSOR0_0_CURSOR_STEREO_CONTROL 0x067f 2347 #define regCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX 2 2348 #define regCURSOR0_0_CURSOR_DST_OFFSET 0x0680 2349 #define regCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX 2 2350 #define regCURSOR0_0_CURSOR_MEM_PWR_CTRL 0x0681 2351 #define regCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 2352 #define regCURSOR0_0_CURSOR_MEM_PWR_STATUS 0x0682 2353 #define regCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 2354 #define regCURSOR0_0_DMDATA_ADDRESS_HIGH 0x0683 2355 #define regCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX 2 2356 #define regCURSOR0_0_DMDATA_ADDRESS_LOW 0x0684 2357 #define regCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX 2 2358 #define regCURSOR0_0_DMDATA_CNTL 0x0685 2359 #define regCURSOR0_0_DMDATA_CNTL_BASE_IDX 2 2360 #define regCURSOR0_0_DMDATA_QOS_CNTL 0x0686 2361 #define regCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX 2 2362 #define regCURSOR0_0_DMDATA_STATUS 0x0687 2363 #define regCURSOR0_0_DMDATA_STATUS_BASE_IDX 2 2364 #define regCURSOR0_0_DMDATA_SW_CNTL 0x0688 2365 #define regCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX 2 2366 #define regCURSOR0_0_DMDATA_SW_DATA 0x0689 2367 #define regCURSOR0_0_DMDATA_SW_DATA_BASE_IDX 2 2368 #define regCURSOR0_0_HUBP_3DLUT_CONTROL 0x068a 2369 #define regCURSOR0_0_HUBP_3DLUT_CONTROL_BASE_IDX 2 2370 #define regCURSOR0_0_HUBP_3DLUT_ADDRESS_LOW 0x068b 2371 #define regCURSOR0_0_HUBP_3DLUT_ADDRESS_LOW_BASE_IDX 2 2372 #define regCURSOR0_0_HUBP_3DLUT_ADDRESS_HIGH 0x068c 2373 #define regCURSOR0_0_HUBP_3DLUT_ADDRESS_HIGH_BASE_IDX 2 2374 #define regCURSOR0_0_HUBP_3DLUT_DLG_PARAM 0x068d 2375 #define regCURSOR0_0_HUBP_3DLUT_DLG_PARAM_BASE_IDX 2 2376 2377 // addressBlock: dcn_dcec_dcbubp1_dispdec_hubp_dispdec 2378 // base address: 0x370 2379 #define regHUBP1_DCSURF_SURFACE_CONFIG 0x06c1 2380 #define regHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2 2381 #define regHUBP1_DCSURF_ADDR_CONFIG 0x06c2 2382 #define regHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2 2383 #define regHUBP1_DCSURF_TILING_CONFIG 0x06c3 2384 #define regHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2 2385 #define regHUBP1_DCSURF_PRI_VIEWPORT_START 0x06c5 2386 #define regHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 2387 #define regHUBP1_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE 0x06c6 2388 #define regHUBP1_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE_BASE_IDX 2 2389 #define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x06c7 2390 #define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 2391 #define regHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x06c8 2392 #define regHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 2393 #define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06c9 2394 #define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 2395 #define regHUBP1_DCSURF_SEC_VIEWPORT_START 0x06ca 2396 #define regHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 2397 #define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x06cb 2398 #define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 2399 #define regHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x06cc 2400 #define regHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 2401 #define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06cd 2402 #define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 2403 #define regHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x06ce 2404 #define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 2405 #define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x06cf 2406 #define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 2407 #define regHUBP1_DCHUBP_CNTL 0x06d0 2408 #define regHUBP1_DCHUBP_CNTL_BASE_IDX 2 2409 #define regHUBP1_HUBP_CLK_CNTL 0x06d1 2410 #define regHUBP1_HUBP_CLK_CNTL_BASE_IDX 2 2411 #define regHUBP1_DCHUBP_VMPG_CONFIG 0x06d2 2412 #define regHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2 2413 #define regHUBP1_DCHUBP_MALL_CONFIG 0x06d3 2414 #define regHUBP1_DCHUBP_MALL_CONFIG_BASE_IDX 2 2415 #define regHUBP1_DCHUBP_MALL_SUB_VP0 0x06d4 2416 #define regHUBP1_DCHUBP_MALL_SUB_VP0_BASE_IDX 2 2417 #define regHUBP1_DCHUBP_MALL_SUB_VP1 0x06d5 2418 #define regHUBP1_DCHUBP_MALL_SUB_VP1_BASE_IDX 2 2419 #define regHUBP1_DCHUBP_MALL_SUB_VP2 0x06d6 2420 #define regHUBP1_DCHUBP_MALL_SUB_VP2_BASE_IDX 2 2421 #define regHUBP1_DCHUBP_MCACHEID_CONFIG 0x06d7 2422 #define regHUBP1_DCHUBP_MCACHEID_CONFIG_BASE_IDX 2 2423 #define regHUBP1_HUBPREQ_DEBUG_DB 0x06d8 2424 #define regHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2 2425 #define regHUBP1_HUBPREQ_DEBUG 0x06d9 2426 #define regHUBP1_HUBPREQ_DEBUG_BASE_IDX 2 2427 #define regHUBP1_HUBP_DEBUG_CTRL 0x06da 2428 #define regHUBP1_HUBP_DEBUG_CTRL_BASE_IDX 2 2429 #define regHUBP1_HUBP_DEBUG_MUX_DCFCLK 0x06db 2430 #define regHUBP1_HUBP_DEBUG_MUX_DCFCLK_BASE_IDX 2 2431 #define regHUBP1_HUBP_DEBUG_MUX_DPPCLK 0x06dc 2432 #define regHUBP1_HUBP_DEBUG_MUX_DPPCLK_BASE_IDX 2 2433 #define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06dd 2434 #define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 2435 #define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06de 2436 #define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 2437 #define regHUBP1_HUBP_MALL_STATUS 0x06df 2438 #define regHUBP1_HUBP_MALL_STATUS_BASE_IDX 2 2439 2440 2441 // addressBlock: dcn_dcec_dcbubp1_dispdec_hubpreq_dispdec 2442 // base address: 0x370 2443 #define regHUBPREQ1_DCSURF_SURFACE_PITCH 0x06e3 2444 #define regHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2 2445 #define regHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x06e4 2446 #define regHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 2447 #define regHUBPREQ1_VMID_SETTINGS_0 0x06e5 2448 #define regHUBPREQ1_VMID_SETTINGS_0_BASE_IDX 2 2449 #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x06e6 2450 #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 2451 #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x06e7 2452 #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2453 #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x06e8 2454 #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 2455 #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x06e9 2456 #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2457 #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x06ea 2458 #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 2459 #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x06eb 2460 #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2461 #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x06ec 2462 #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 2463 #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x06ed 2464 #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2465 #define regHUBPREQ1_DCSURF_SURFACE_CONTROL 0x06ee 2466 #define regHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2 2467 #define regHUBPREQ1_DCSURF_FLIP_CONTROL 0x06ef 2468 #define regHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2 2469 #define regHUBPREQ1_DCSURF_FLIP_CONTROL2 0x06f0 2470 #define regHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2 2471 #define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x06f3 2472 #define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 2473 #define regHUBPREQ1_DCSURF_SURFACE_INUSE 0x06f4 2474 #define regHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2 2475 #define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x06f5 2476 #define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 2477 #define regHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x06f6 2478 #define regHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 2479 #define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x06f7 2480 #define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 2481 #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x06f8 2482 #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 2483 #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x06f9 2484 #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 2485 #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x06fa 2486 #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 2487 #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x06fb 2488 #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 2489 #define regHUBPREQ1_DCN_EXPANSION_MODE 0x06fc 2490 #define regHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2 2491 #define regHUBPREQ1_DCN_TTU_QOS_WM 0x06fd 2492 #define regHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2 2493 #define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x06fe 2494 #define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 2495 #define regHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x06ff 2496 #define regHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 2497 #define regHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x0700 2498 #define regHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 2499 #define regHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x0701 2500 #define regHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 2501 #define regHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x0702 2502 #define regHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 2503 #define regHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x0703 2504 #define regHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 2505 #define regHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x0704 2506 #define regHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 2507 #define regHUBPREQ1_DCN_CUR1_TTU_CNTL0 0x0705 2508 #define regHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 2509 #define regHUBPREQ1_DCN_CUR1_TTU_CNTL1 0x0706 2510 #define regHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 2511 #define regHUBPREQ1_DCN_DMDATA_VM_CNTL 0x0707 2512 #define regHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX 2 2513 #define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0708 2514 #define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 2515 #define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0709 2516 #define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 2517 #define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0x0716 2518 #define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 2519 #define regHUBPREQ1_BLANK_OFFSET_0 0x0717 2520 #define regHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2 2521 #define regHUBPREQ1_BLANK_OFFSET_1 0x0718 2522 #define regHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2 2523 #define regHUBPREQ1_DST_DIMENSIONS 0x0719 2524 #define regHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2 2525 #define regHUBPREQ1_DST_AFTER_SCALER 0x071a 2526 #define regHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2 2527 #define regHUBPREQ1_PREFETCH_SETTINGS 0x071b 2528 #define regHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX 2 2529 #define regHUBPREQ1_PREFETCH_SETTINGS_C 0x071c 2530 #define regHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX 2 2531 #define regHUBPREQ1_VBLANK_PARAMETERS_0 0x071d 2532 #define regHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2 2533 #define regHUBPREQ1_VBLANK_PARAMETERS_1 0x071e 2534 #define regHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2 2535 #define regHUBPREQ1_VBLANK_PARAMETERS_2 0x071f 2536 #define regHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2 2537 #define regHUBPREQ1_VBLANK_PARAMETERS_3 0x0720 2538 #define regHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2 2539 #define regHUBPREQ1_VBLANK_PARAMETERS_4 0x0721 2540 #define regHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2 2541 #define regHUBPREQ1_FLIP_PARAMETERS_0 0x0722 2542 #define regHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX 2 2543 #define regHUBPREQ1_FLIP_PARAMETERS_1 0x0723 2544 #define regHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX 2 2545 #define regHUBPREQ1_FLIP_PARAMETERS_2 0x0724 2546 #define regHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX 2 2547 #define regHUBPREQ1_NOM_PARAMETERS_0 0x0725 2548 #define regHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX 2 2549 #define regHUBPREQ1_NOM_PARAMETERS_1 0x0726 2550 #define regHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX 2 2551 #define regHUBPREQ1_NOM_PARAMETERS_2 0x0727 2552 #define regHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX 2 2553 #define regHUBPREQ1_NOM_PARAMETERS_3 0x0728 2554 #define regHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX 2 2555 #define regHUBPREQ1_NOM_PARAMETERS_4 0x0729 2556 #define regHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2 2557 #define regHUBPREQ1_NOM_PARAMETERS_5 0x072a 2558 #define regHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2 2559 #define regHUBPREQ1_NOM_PARAMETERS_6 0x072b 2560 #define regHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2 2561 #define regHUBPREQ1_NOM_PARAMETERS_7 0x072c 2562 #define regHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2 2563 #define regHUBPREQ1_PER_LINE_DELIVERY_PRE 0x072d 2564 #define regHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2 2565 #define regHUBPREQ1_PER_LINE_DELIVERY 0x072e 2566 #define regHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2 2567 #define regHUBPREQ1_CURSOR_SETTINGS 0x072f 2568 #define regHUBPREQ1_CURSOR_SETTINGS_BASE_IDX 2 2569 #define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x0730 2570 #define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 2571 #define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT 0x0731 2572 #define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 2573 #define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x0732 2574 #define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 2575 #define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x0733 2576 #define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 2577 #define regHUBPREQ1_VBLANK_PARAMETERS_5 0x0736 2578 #define regHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX 2 2579 #define regHUBPREQ1_VBLANK_PARAMETERS_6 0x0737 2580 #define regHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX 2 2581 #define regHUBPREQ1_FLIP_PARAMETERS_3 0x0738 2582 #define regHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX 2 2583 #define regHUBPREQ1_FLIP_PARAMETERS_4 0x0739 2584 #define regHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX 2 2585 #define regHUBPREQ1_FLIP_PARAMETERS_5 0x073a 2586 #define regHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX 2 2587 #define regHUBPREQ1_FLIP_PARAMETERS_6 0x073b 2588 #define regHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX 2 2589 #define regHUBPREQ1_UCLK_PSTATE_FORCE 0x073c 2590 #define regHUBPREQ1_UCLK_PSTATE_FORCE_BASE_IDX 2 2591 #define regHUBPREQ1_HUBPREQ_STATUS_REG0 0x073d 2592 #define regHUBPREQ1_HUBPREQ_STATUS_REG0_BASE_IDX 2 2593 #define regHUBPREQ1_HUBPREQ_STATUS_REG1 0x073e 2594 #define regHUBPREQ1_HUBPREQ_STATUS_REG1_BASE_IDX 2 2595 #define regHUBPREQ1_HUBPREQ_STATUS_REG2 0x073f 2596 #define regHUBPREQ1_HUBPREQ_STATUS_REG2_BASE_IDX 2 2597 #define regHUBPREQ1_HUBPREQ_STATUS_REG3 0x0740 2598 #define regHUBPREQ1_HUBPREQ_STATUS_REG3_BASE_IDX 2 2599 2600 2601 // addressBlock: dcn_dcec_dcbubp1_dispdec_hubpret_dispdec 2602 // base address: 0x370 2603 #define regHUBPRET1_HUBPRET_CONTROL 0x0749 2604 #define regHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2 2605 #define regHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x074a 2606 #define regHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 2607 #define regHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x074b 2608 #define regHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 2609 #define regHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x074c 2610 #define regHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 2611 #define regHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x074d 2612 #define regHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 2613 #define regHUBPRET1_HUBPRET_READ_LINE0 0x074e 2614 #define regHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2 2615 #define regHUBPRET1_HUBPRET_READ_LINE1 0x074f 2616 #define regHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2 2617 #define regHUBPRET1_HUBPRET_INTERRUPT 0x0750 2618 #define regHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2 2619 #define regHUBPRET1_HUBPRET_READ_LINE_VALUE 0x0751 2620 #define regHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 2621 #define regHUBPRET1_HUBPRET_READ_LINE_STATUS 0x0752 2622 #define regHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 2623 2624 2625 // addressBlock: dcn_dcec_dcbubp1_dispdec_cursor0_dispdec 2626 // base address: 0x370 2627 #define regCURSOR0_1_CURSOR_CONTROL 0x0755 2628 #define regCURSOR0_1_CURSOR_CONTROL_BASE_IDX 2 2629 #define regCURSOR0_1_CURSOR_SURFACE_ADDRESS 0x0756 2630 #define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 2631 #define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH 0x0757 2632 #define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2633 #define regCURSOR0_1_CURSOR_SIZE 0x0758 2634 #define regCURSOR0_1_CURSOR_SIZE_BASE_IDX 2 2635 #define regCURSOR0_1_CURSOR_POSITION 0x0759 2636 #define regCURSOR0_1_CURSOR_POSITION_BASE_IDX 2 2637 #define regCURSOR0_1_CURSOR_HOT_SPOT 0x075a 2638 #define regCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX 2 2639 #define regCURSOR0_1_CURSOR_STEREO_CONTROL 0x075b 2640 #define regCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX 2 2641 #define regCURSOR0_1_CURSOR_DST_OFFSET 0x075c 2642 #define regCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX 2 2643 #define regCURSOR0_1_CURSOR_MEM_PWR_CTRL 0x075d 2644 #define regCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 2645 #define regCURSOR0_1_CURSOR_MEM_PWR_STATUS 0x075e 2646 #define regCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 2647 #define regCURSOR0_1_DMDATA_ADDRESS_HIGH 0x075f 2648 #define regCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX 2 2649 #define regCURSOR0_1_DMDATA_ADDRESS_LOW 0x0760 2650 #define regCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX 2 2651 #define regCURSOR0_1_DMDATA_CNTL 0x0761 2652 #define regCURSOR0_1_DMDATA_CNTL_BASE_IDX 2 2653 #define regCURSOR0_1_DMDATA_QOS_CNTL 0x0762 2654 #define regCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX 2 2655 #define regCURSOR0_1_DMDATA_STATUS 0x0763 2656 #define regCURSOR0_1_DMDATA_STATUS_BASE_IDX 2 2657 #define regCURSOR0_1_DMDATA_SW_CNTL 0x0764 2658 #define regCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX 2 2659 #define regCURSOR0_1_DMDATA_SW_DATA 0x0765 2660 #define regCURSOR0_1_DMDATA_SW_DATA_BASE_IDX 2 2661 #define regCURSOR0_1_HUBP_3DLUT_CONTROL 0x0766 2662 #define regCURSOR0_1_HUBP_3DLUT_CONTROL_BASE_IDX 2 2663 #define regCURSOR0_1_HUBP_3DLUT_ADDRESS_LOW 0x0767 2664 #define regCURSOR0_1_HUBP_3DLUT_ADDRESS_LOW_BASE_IDX 2 2665 #define regCURSOR0_1_HUBP_3DLUT_ADDRESS_HIGH 0x0768 2666 #define regCURSOR0_1_HUBP_3DLUT_ADDRESS_HIGH_BASE_IDX 2 2667 #define regCURSOR0_1_HUBP_3DLUT_DLG_PARAM 0x0769 2668 #define regCURSOR0_1_HUBP_3DLUT_DLG_PARAM_BASE_IDX 2 2669 2670 // addressBlock: dcn_dcec_dcbubp2_dispdec_hubp_dispdec 2671 // base address: 0x6e0 2672 #define regHUBP2_DCSURF_SURFACE_CONFIG 0x079d 2673 #define regHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX 2 2674 #define regHUBP2_DCSURF_ADDR_CONFIG 0x079e 2675 #define regHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX 2 2676 #define regHUBP2_DCSURF_TILING_CONFIG 0x079f 2677 #define regHUBP2_DCSURF_TILING_CONFIG_BASE_IDX 2 2678 #define regHUBP2_DCSURF_PRI_VIEWPORT_START 0x07a1 2679 #define regHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 2680 #define regHUBP2_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE 0x07a2 2681 #define regHUBP2_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE_BASE_IDX 2 2682 #define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0x07a3 2683 #define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 2684 #define regHUBP2_DCSURF_PRI_VIEWPORT_START_C 0x07a4 2685 #define regHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 2686 #define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x07a5 2687 #define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 2688 #define regHUBP2_DCSURF_SEC_VIEWPORT_START 0x07a6 2689 #define regHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 2690 #define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0x07a7 2691 #define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 2692 #define regHUBP2_DCSURF_SEC_VIEWPORT_START_C 0x07a8 2693 #define regHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 2694 #define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x07a9 2695 #define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 2696 #define regHUBP2_DCHUBP_REQ_SIZE_CONFIG 0x07aa 2697 #define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 2698 #define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0x07ab 2699 #define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 2700 #define regHUBP2_DCHUBP_CNTL 0x07ac 2701 #define regHUBP2_DCHUBP_CNTL_BASE_IDX 2 2702 #define regHUBP2_HUBP_CLK_CNTL 0x07ad 2703 #define regHUBP2_HUBP_CLK_CNTL_BASE_IDX 2 2704 #define regHUBP2_DCHUBP_VMPG_CONFIG 0x07ae 2705 #define regHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX 2 2706 #define regHUBP2_DCHUBP_MALL_CONFIG 0x07af 2707 #define regHUBP2_DCHUBP_MALL_CONFIG_BASE_IDX 2 2708 #define regHUBP2_DCHUBP_MALL_SUB_VP0 0x07b0 2709 #define regHUBP2_DCHUBP_MALL_SUB_VP0_BASE_IDX 2 2710 #define regHUBP2_DCHUBP_MALL_SUB_VP1 0x07b1 2711 #define regHUBP2_DCHUBP_MALL_SUB_VP1_BASE_IDX 2 2712 #define regHUBP2_DCHUBP_MALL_SUB_VP2 0x07b2 2713 #define regHUBP2_DCHUBP_MALL_SUB_VP2_BASE_IDX 2 2714 #define regHUBP2_DCHUBP_MCACHEID_CONFIG 0x07b3 2715 #define regHUBP2_DCHUBP_MCACHEID_CONFIG_BASE_IDX 2 2716 #define regHUBP2_HUBPREQ_DEBUG_DB 0x07b4 2717 #define regHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2 2718 #define regHUBP2_HUBPREQ_DEBUG 0x07b5 2719 #define regHUBP2_HUBPREQ_DEBUG_BASE_IDX 2 2720 #define regHUBP2_HUBP_DEBUG_CTRL 0x07b6 2721 #define regHUBP2_HUBP_DEBUG_CTRL_BASE_IDX 2 2722 #define regHUBP2_HUBP_DEBUG_MUX_DCFCLK 0x07b7 2723 #define regHUBP2_HUBP_DEBUG_MUX_DCFCLK_BASE_IDX 2 2724 #define regHUBP2_HUBP_DEBUG_MUX_DPPCLK 0x07b8 2725 #define regHUBP2_HUBP_DEBUG_MUX_DPPCLK_BASE_IDX 2 2726 #define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x07b9 2727 #define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 2728 #define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x07ba 2729 #define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 2730 #define regHUBP2_HUBP_MALL_STATUS 0x07bb 2731 #define regHUBP2_HUBP_MALL_STATUS_BASE_IDX 2 2732 2733 2734 // addressBlock: dcn_dcec_dcbubp2_dispdec_hubpreq_dispdec 2735 // base address: 0x6e0 2736 #define regHUBPREQ2_DCSURF_SURFACE_PITCH 0x07bf 2737 #define regHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX 2 2738 #define regHUBPREQ2_DCSURF_SURFACE_PITCH_C 0x07c0 2739 #define regHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 2740 #define regHUBPREQ2_VMID_SETTINGS_0 0x07c1 2741 #define regHUBPREQ2_VMID_SETTINGS_0_BASE_IDX 2 2742 #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0x07c2 2743 #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 2744 #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x07c3 2745 #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2746 #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x07c4 2747 #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 2748 #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x07c5 2749 #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2750 #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0x07c6 2751 #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 2752 #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x07c7 2753 #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2754 #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x07c8 2755 #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 2756 #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x07c9 2757 #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2758 #define regHUBPREQ2_DCSURF_SURFACE_CONTROL 0x07ca 2759 #define regHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX 2 2760 #define regHUBPREQ2_DCSURF_FLIP_CONTROL 0x07cb 2761 #define regHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX 2 2762 #define regHUBPREQ2_DCSURF_FLIP_CONTROL2 0x07cc 2763 #define regHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX 2 2764 #define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0x07cf 2765 #define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 2766 #define regHUBPREQ2_DCSURF_SURFACE_INUSE 0x07d0 2767 #define regHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX 2 2768 #define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0x07d1 2769 #define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 2770 #define regHUBPREQ2_DCSURF_SURFACE_INUSE_C 0x07d2 2771 #define regHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 2772 #define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0x07d3 2773 #define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 2774 #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0x07d4 2775 #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 2776 #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x07d5 2777 #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 2778 #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0x07d6 2779 #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 2780 #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x07d7 2781 #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 2782 #define regHUBPREQ2_DCN_EXPANSION_MODE 0x07d8 2783 #define regHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX 2 2784 #define regHUBPREQ2_DCN_TTU_QOS_WM 0x07d9 2785 #define regHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX 2 2786 #define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0x07da 2787 #define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 2788 #define regHUBPREQ2_DCN_SURF0_TTU_CNTL0 0x07db 2789 #define regHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 2790 #define regHUBPREQ2_DCN_SURF0_TTU_CNTL1 0x07dc 2791 #define regHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 2792 #define regHUBPREQ2_DCN_SURF1_TTU_CNTL0 0x07dd 2793 #define regHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 2794 #define regHUBPREQ2_DCN_SURF1_TTU_CNTL1 0x07de 2795 #define regHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 2796 #define regHUBPREQ2_DCN_CUR0_TTU_CNTL0 0x07df 2797 #define regHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 2798 #define regHUBPREQ2_DCN_CUR0_TTU_CNTL1 0x07e0 2799 #define regHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 2800 #define regHUBPREQ2_DCN_CUR1_TTU_CNTL0 0x07e1 2801 #define regHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 2802 #define regHUBPREQ2_DCN_CUR1_TTU_CNTL1 0x07e2 2803 #define regHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 2804 #define regHUBPREQ2_DCN_DMDATA_VM_CNTL 0x07e3 2805 #define regHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX 2 2806 #define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x07e4 2807 #define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 2808 #define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x07e5 2809 #define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 2810 #define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL 0x07f2 2811 #define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 2812 #define regHUBPREQ2_BLANK_OFFSET_0 0x07f3 2813 #define regHUBPREQ2_BLANK_OFFSET_0_BASE_IDX 2 2814 #define regHUBPREQ2_BLANK_OFFSET_1 0x07f4 2815 #define regHUBPREQ2_BLANK_OFFSET_1_BASE_IDX 2 2816 #define regHUBPREQ2_DST_DIMENSIONS 0x07f5 2817 #define regHUBPREQ2_DST_DIMENSIONS_BASE_IDX 2 2818 #define regHUBPREQ2_DST_AFTER_SCALER 0x07f6 2819 #define regHUBPREQ2_DST_AFTER_SCALER_BASE_IDX 2 2820 #define regHUBPREQ2_PREFETCH_SETTINGS 0x07f7 2821 #define regHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX 2 2822 #define regHUBPREQ2_PREFETCH_SETTINGS_C 0x07f8 2823 #define regHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX 2 2824 #define regHUBPREQ2_VBLANK_PARAMETERS_0 0x07f9 2825 #define regHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX 2 2826 #define regHUBPREQ2_VBLANK_PARAMETERS_1 0x07fa 2827 #define regHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX 2 2828 #define regHUBPREQ2_VBLANK_PARAMETERS_2 0x07fb 2829 #define regHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX 2 2830 #define regHUBPREQ2_VBLANK_PARAMETERS_3 0x07fc 2831 #define regHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX 2 2832 #define regHUBPREQ2_VBLANK_PARAMETERS_4 0x07fd 2833 #define regHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX 2 2834 #define regHUBPREQ2_FLIP_PARAMETERS_0 0x07fe 2835 #define regHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX 2 2836 #define regHUBPREQ2_FLIP_PARAMETERS_1 0x07ff 2837 #define regHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX 2 2838 #define regHUBPREQ2_FLIP_PARAMETERS_2 0x0800 2839 #define regHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX 2 2840 #define regHUBPREQ2_NOM_PARAMETERS_0 0x0801 2841 #define regHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX 2 2842 #define regHUBPREQ2_NOM_PARAMETERS_1 0x0802 2843 #define regHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX 2 2844 #define regHUBPREQ2_NOM_PARAMETERS_2 0x0803 2845 #define regHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX 2 2846 #define regHUBPREQ2_NOM_PARAMETERS_3 0x0804 2847 #define regHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX 2 2848 #define regHUBPREQ2_NOM_PARAMETERS_4 0x0805 2849 #define regHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX 2 2850 #define regHUBPREQ2_NOM_PARAMETERS_5 0x0806 2851 #define regHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX 2 2852 #define regHUBPREQ2_NOM_PARAMETERS_6 0x0807 2853 #define regHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX 2 2854 #define regHUBPREQ2_NOM_PARAMETERS_7 0x0808 2855 #define regHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX 2 2856 #define regHUBPREQ2_PER_LINE_DELIVERY_PRE 0x0809 2857 #define regHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX 2 2858 #define regHUBPREQ2_PER_LINE_DELIVERY 0x080a 2859 #define regHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX 2 2860 #define regHUBPREQ2_CURSOR_SETTINGS 0x080b 2861 #define regHUBPREQ2_CURSOR_SETTINGS_BASE_IDX 2 2862 #define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0x080c 2863 #define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 2864 #define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT 0x080d 2865 #define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 2866 #define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0x080e 2867 #define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 2868 #define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0x080f 2869 #define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 2870 #define regHUBPREQ2_VBLANK_PARAMETERS_5 0x0812 2871 #define regHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX 2 2872 #define regHUBPREQ2_VBLANK_PARAMETERS_6 0x0813 2873 #define regHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX 2 2874 #define regHUBPREQ2_FLIP_PARAMETERS_3 0x0814 2875 #define regHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX 2 2876 #define regHUBPREQ2_FLIP_PARAMETERS_4 0x0815 2877 #define regHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX 2 2878 #define regHUBPREQ2_FLIP_PARAMETERS_5 0x0816 2879 #define regHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX 2 2880 #define regHUBPREQ2_FLIP_PARAMETERS_6 0x0817 2881 #define regHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX 2 2882 #define regHUBPREQ2_UCLK_PSTATE_FORCE 0x0818 2883 #define regHUBPREQ2_UCLK_PSTATE_FORCE_BASE_IDX 2 2884 #define regHUBPREQ2_HUBPREQ_STATUS_REG0 0x0819 2885 #define regHUBPREQ2_HUBPREQ_STATUS_REG0_BASE_IDX 2 2886 #define regHUBPREQ2_HUBPREQ_STATUS_REG1 0x081a 2887 #define regHUBPREQ2_HUBPREQ_STATUS_REG1_BASE_IDX 2 2888 #define regHUBPREQ2_HUBPREQ_STATUS_REG2 0x081b 2889 #define regHUBPREQ2_HUBPREQ_STATUS_REG2_BASE_IDX 2 2890 #define regHUBPREQ2_HUBPREQ_STATUS_REG3 0x081c 2891 #define regHUBPREQ2_HUBPREQ_STATUS_REG3_BASE_IDX 2 2892 2893 2894 // addressBlock: dcn_dcec_dcbubp2_dispdec_hubpret_dispdec 2895 // base address: 0x6e0 2896 #define regHUBPRET2_HUBPRET_CONTROL 0x0825 2897 #define regHUBPRET2_HUBPRET_CONTROL_BASE_IDX 2 2898 #define regHUBPRET2_HUBPRET_MEM_PWR_CTRL 0x0826 2899 #define regHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 2900 #define regHUBPRET2_HUBPRET_MEM_PWR_STATUS 0x0827 2901 #define regHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 2902 #define regHUBPRET2_HUBPRET_READ_LINE_CTRL0 0x0828 2903 #define regHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 2904 #define regHUBPRET2_HUBPRET_READ_LINE_CTRL1 0x0829 2905 #define regHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 2906 #define regHUBPRET2_HUBPRET_READ_LINE0 0x082a 2907 #define regHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX 2 2908 #define regHUBPRET2_HUBPRET_READ_LINE1 0x082b 2909 #define regHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX 2 2910 #define regHUBPRET2_HUBPRET_INTERRUPT 0x082c 2911 #define regHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX 2 2912 #define regHUBPRET2_HUBPRET_READ_LINE_VALUE 0x082d 2913 #define regHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 2914 #define regHUBPRET2_HUBPRET_READ_LINE_STATUS 0x082e 2915 #define regHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 2916 2917 2918 // addressBlock: dcn_dcec_dcbubp2_dispdec_cursor0_dispdec 2919 // base address: 0x6e0 2920 #define regCURSOR0_2_CURSOR_CONTROL 0x0831 2921 #define regCURSOR0_2_CURSOR_CONTROL_BASE_IDX 2 2922 #define regCURSOR0_2_CURSOR_SURFACE_ADDRESS 0x0832 2923 #define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 2924 #define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH 0x0833 2925 #define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2926 #define regCURSOR0_2_CURSOR_SIZE 0x0834 2927 #define regCURSOR0_2_CURSOR_SIZE_BASE_IDX 2 2928 #define regCURSOR0_2_CURSOR_POSITION 0x0835 2929 #define regCURSOR0_2_CURSOR_POSITION_BASE_IDX 2 2930 #define regCURSOR0_2_CURSOR_HOT_SPOT 0x0836 2931 #define regCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX 2 2932 #define regCURSOR0_2_CURSOR_STEREO_CONTROL 0x0837 2933 #define regCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX 2 2934 #define regCURSOR0_2_CURSOR_DST_OFFSET 0x0838 2935 #define regCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX 2 2936 #define regCURSOR0_2_CURSOR_MEM_PWR_CTRL 0x0839 2937 #define regCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 2938 #define regCURSOR0_2_CURSOR_MEM_PWR_STATUS 0x083a 2939 #define regCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 2940 #define regCURSOR0_2_DMDATA_ADDRESS_HIGH 0x083b 2941 #define regCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX 2 2942 #define regCURSOR0_2_DMDATA_ADDRESS_LOW 0x083c 2943 #define regCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX 2 2944 #define regCURSOR0_2_DMDATA_CNTL 0x083d 2945 #define regCURSOR0_2_DMDATA_CNTL_BASE_IDX 2 2946 #define regCURSOR0_2_DMDATA_QOS_CNTL 0x083e 2947 #define regCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX 2 2948 #define regCURSOR0_2_DMDATA_STATUS 0x083f 2949 #define regCURSOR0_2_DMDATA_STATUS_BASE_IDX 2 2950 #define regCURSOR0_2_DMDATA_SW_CNTL 0x0840 2951 #define regCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX 2 2952 #define regCURSOR0_2_DMDATA_SW_DATA 0x0841 2953 #define regCURSOR0_2_DMDATA_SW_DATA_BASE_IDX 2 2954 #define regCURSOR0_2_HUBP_3DLUT_CONTROL 0x0842 2955 #define regCURSOR0_2_HUBP_3DLUT_CONTROL_BASE_IDX 2 2956 #define regCURSOR0_2_HUBP_3DLUT_ADDRESS_LOW 0x0843 2957 #define regCURSOR0_2_HUBP_3DLUT_ADDRESS_LOW_BASE_IDX 2 2958 #define regCURSOR0_2_HUBP_3DLUT_ADDRESS_HIGH 0x0844 2959 #define regCURSOR0_2_HUBP_3DLUT_ADDRESS_HIGH_BASE_IDX 2 2960 #define regCURSOR0_2_HUBP_3DLUT_DLG_PARAM 0x0845 2961 #define regCURSOR0_2_HUBP_3DLUT_DLG_PARAM_BASE_IDX 2 2962 2963 2964 // addressBlock: dcn_dcec_dcbubp3_dispdec_hubp_dispdec 2965 // base address: 0xa50 2966 #define regHUBP3_DCSURF_SURFACE_CONFIG 0x0879 2967 #define regHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX 2 2968 #define regHUBP3_DCSURF_ADDR_CONFIG 0x087a 2969 #define regHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX 2 2970 #define regHUBP3_DCSURF_TILING_CONFIG 0x087b 2971 #define regHUBP3_DCSURF_TILING_CONFIG_BASE_IDX 2 2972 #define regHUBP3_DCSURF_PRI_VIEWPORT_START 0x087d 2973 #define regHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 2974 #define regHUBP3_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE 0x087e 2975 #define regHUBP3_DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE_BASE_IDX 2 2976 #define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0x087f 2977 #define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 2978 #define regHUBP3_DCSURF_PRI_VIEWPORT_START_C 0x0880 2979 #define regHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 2980 #define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0881 2981 #define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 2982 #define regHUBP3_DCSURF_SEC_VIEWPORT_START 0x0882 2983 #define regHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 2984 #define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0x0883 2985 #define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 2986 #define regHUBP3_DCSURF_SEC_VIEWPORT_START_C 0x0884 2987 #define regHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 2988 #define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0885 2989 #define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 2990 #define regHUBP3_DCHUBP_REQ_SIZE_CONFIG 0x0886 2991 #define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 2992 #define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0x0887 2993 #define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 2994 #define regHUBP3_DCHUBP_CNTL 0x0888 2995 #define regHUBP3_DCHUBP_CNTL_BASE_IDX 2 2996 #define regHUBP3_HUBP_CLK_CNTL 0x0889 2997 #define regHUBP3_HUBP_CLK_CNTL_BASE_IDX 2 2998 #define regHUBP3_DCHUBP_VMPG_CONFIG 0x088a 2999 #define regHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX 2 3000 #define regHUBP3_DCHUBP_MALL_CONFIG 0x088b 3001 #define regHUBP3_DCHUBP_MALL_CONFIG_BASE_IDX 2 3002 #define regHUBP3_DCHUBP_MALL_SUB_VP0 0x088c 3003 #define regHUBP3_DCHUBP_MALL_SUB_VP0_BASE_IDX 2 3004 #define regHUBP3_DCHUBP_MALL_SUB_VP1 0x088d 3005 #define regHUBP3_DCHUBP_MALL_SUB_VP1_BASE_IDX 2 3006 #define regHUBP3_DCHUBP_MALL_SUB_VP2 0x088e 3007 #define regHUBP3_DCHUBP_MALL_SUB_VP2_BASE_IDX 2 3008 #define regHUBP3_DCHUBP_MCACHEID_CONFIG 0x088f 3009 #define regHUBP3_DCHUBP_MCACHEID_CONFIG_BASE_IDX 2 3010 #define regHUBP3_HUBPREQ_DEBUG_DB 0x0890 3011 #define regHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2 3012 #define regHUBP3_HUBPREQ_DEBUG 0x0891 3013 #define regHUBP3_HUBPREQ_DEBUG_BASE_IDX 2 3014 #define regHUBP3_HUBP_DEBUG_CTRL 0x0892 3015 #define regHUBP3_HUBP_DEBUG_CTRL_BASE_IDX 2 3016 #define regHUBP3_HUBP_DEBUG_MUX_DCFCLK 0x0893 3017 #define regHUBP3_HUBP_DEBUG_MUX_DCFCLK_BASE_IDX 2 3018 #define regHUBP3_HUBP_DEBUG_MUX_DPPCLK 0x0894 3019 #define regHUBP3_HUBP_DEBUG_MUX_DPPCLK_BASE_IDX 2 3020 #define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x0895 3021 #define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 3022 #define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0896 3023 #define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 3024 #define regHUBP3_HUBP_MALL_STATUS 0x0897 3025 #define regHUBP3_HUBP_MALL_STATUS_BASE_IDX 2 3026 3027 3028 // addressBlock: dcn_dcec_dcbubp3_dispdec_hubpreq_dispdec 3029 // base address: 0xa50 3030 #define regHUBPREQ3_DCSURF_SURFACE_PITCH 0x089b 3031 #define regHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX 2 3032 #define regHUBPREQ3_DCSURF_SURFACE_PITCH_C 0x089c 3033 #define regHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 3034 #define regHUBPREQ3_VMID_SETTINGS_0 0x089d 3035 #define regHUBPREQ3_VMID_SETTINGS_0_BASE_IDX 2 3036 #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0x089e 3037 #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 3038 #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x089f 3039 #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3040 #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x08a0 3041 #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 3042 #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x08a1 3043 #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3044 #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0x08a2 3045 #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 3046 #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x08a3 3047 #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3048 #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x08a4 3049 #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 3050 #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x08a5 3051 #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3052 #define regHUBPREQ3_DCSURF_SURFACE_CONTROL 0x08a6 3053 #define regHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX 2 3054 #define regHUBPREQ3_DCSURF_FLIP_CONTROL 0x08a7 3055 #define regHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX 2 3056 #define regHUBPREQ3_DCSURF_FLIP_CONTROL2 0x08a8 3057 #define regHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX 2 3058 #define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0x08ab 3059 #define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 3060 #define regHUBPREQ3_DCSURF_SURFACE_INUSE 0x08ac 3061 #define regHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX 2 3062 #define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0x08ad 3063 #define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 3064 #define regHUBPREQ3_DCSURF_SURFACE_INUSE_C 0x08ae 3065 #define regHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 3066 #define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0x08af 3067 #define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 3068 #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0x08b0 3069 #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 3070 #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x08b1 3071 #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 3072 #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0x08b2 3073 #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 3074 #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x08b3 3075 #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 3076 #define regHUBPREQ3_DCN_EXPANSION_MODE 0x08b4 3077 #define regHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX 2 3078 #define regHUBPREQ3_DCN_TTU_QOS_WM 0x08b5 3079 #define regHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX 2 3080 #define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0x08b6 3081 #define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 3082 #define regHUBPREQ3_DCN_SURF0_TTU_CNTL0 0x08b7 3083 #define regHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 3084 #define regHUBPREQ3_DCN_SURF0_TTU_CNTL1 0x08b8 3085 #define regHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 3086 #define regHUBPREQ3_DCN_SURF1_TTU_CNTL0 0x08b9 3087 #define regHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 3088 #define regHUBPREQ3_DCN_SURF1_TTU_CNTL1 0x08ba 3089 #define regHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 3090 #define regHUBPREQ3_DCN_CUR0_TTU_CNTL0 0x08bb 3091 #define regHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 3092 #define regHUBPREQ3_DCN_CUR0_TTU_CNTL1 0x08bc 3093 #define regHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 3094 #define regHUBPREQ3_DCN_CUR1_TTU_CNTL0 0x08bd 3095 #define regHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 3096 #define regHUBPREQ3_DCN_CUR1_TTU_CNTL1 0x08be 3097 #define regHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 3098 #define regHUBPREQ3_DCN_DMDATA_VM_CNTL 0x08bf 3099 #define regHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX 2 3100 #define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x08c0 3101 #define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 3102 #define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x08c1 3103 #define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 3104 #define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL 0x08ce 3105 #define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 3106 #define regHUBPREQ3_BLANK_OFFSET_0 0x08cf 3107 #define regHUBPREQ3_BLANK_OFFSET_0_BASE_IDX 2 3108 #define regHUBPREQ3_BLANK_OFFSET_1 0x08d0 3109 #define regHUBPREQ3_BLANK_OFFSET_1_BASE_IDX 2 3110 #define regHUBPREQ3_DST_DIMENSIONS 0x08d1 3111 #define regHUBPREQ3_DST_DIMENSIONS_BASE_IDX 2 3112 #define regHUBPREQ3_DST_AFTER_SCALER 0x08d2 3113 #define regHUBPREQ3_DST_AFTER_SCALER_BASE_IDX 2 3114 #define regHUBPREQ3_PREFETCH_SETTINGS 0x08d3 3115 #define regHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX 2 3116 #define regHUBPREQ3_PREFETCH_SETTINGS_C 0x08d4 3117 #define regHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX 2 3118 #define regHUBPREQ3_VBLANK_PARAMETERS_0 0x08d5 3119 #define regHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX 2 3120 #define regHUBPREQ3_VBLANK_PARAMETERS_1 0x08d6 3121 #define regHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX 2 3122 #define regHUBPREQ3_VBLANK_PARAMETERS_2 0x08d7 3123 #define regHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX 2 3124 #define regHUBPREQ3_VBLANK_PARAMETERS_3 0x08d8 3125 #define regHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX 2 3126 #define regHUBPREQ3_VBLANK_PARAMETERS_4 0x08d9 3127 #define regHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX 2 3128 #define regHUBPREQ3_FLIP_PARAMETERS_0 0x08da 3129 #define regHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX 2 3130 #define regHUBPREQ3_FLIP_PARAMETERS_1 0x08db 3131 #define regHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX 2 3132 #define regHUBPREQ3_FLIP_PARAMETERS_2 0x08dc 3133 #define regHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX 2 3134 #define regHUBPREQ3_NOM_PARAMETERS_0 0x08dd 3135 #define regHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX 2 3136 #define regHUBPREQ3_NOM_PARAMETERS_1 0x08de 3137 #define regHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX 2 3138 #define regHUBPREQ3_NOM_PARAMETERS_2 0x08df 3139 #define regHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX 2 3140 #define regHUBPREQ3_NOM_PARAMETERS_3 0x08e0 3141 #define regHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX 2 3142 #define regHUBPREQ3_NOM_PARAMETERS_4 0x08e1 3143 #define regHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX 2 3144 #define regHUBPREQ3_NOM_PARAMETERS_5 0x08e2 3145 #define regHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX 2 3146 #define regHUBPREQ3_NOM_PARAMETERS_6 0x08e3 3147 #define regHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX 2 3148 #define regHUBPREQ3_NOM_PARAMETERS_7 0x08e4 3149 #define regHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX 2 3150 #define regHUBPREQ3_PER_LINE_DELIVERY_PRE 0x08e5 3151 #define regHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX 2 3152 #define regHUBPREQ3_PER_LINE_DELIVERY 0x08e6 3153 #define regHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX 2 3154 #define regHUBPREQ3_CURSOR_SETTINGS 0x08e7 3155 #define regHUBPREQ3_CURSOR_SETTINGS_BASE_IDX 2 3156 #define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0x08e8 3157 #define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 3158 #define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT 0x08e9 3159 #define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 3160 #define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0x08ea 3161 #define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 3162 #define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0x08eb 3163 #define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 3164 #define regHUBPREQ3_VBLANK_PARAMETERS_5 0x08ee 3165 #define regHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX 2 3166 #define regHUBPREQ3_VBLANK_PARAMETERS_6 0x08ef 3167 #define regHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX 2 3168 #define regHUBPREQ3_FLIP_PARAMETERS_3 0x08f0 3169 #define regHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX 2 3170 #define regHUBPREQ3_FLIP_PARAMETERS_4 0x08f1 3171 #define regHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX 2 3172 #define regHUBPREQ3_FLIP_PARAMETERS_5 0x08f2 3173 #define regHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX 2 3174 #define regHUBPREQ3_FLIP_PARAMETERS_6 0x08f3 3175 #define regHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX 2 3176 #define regHUBPREQ3_UCLK_PSTATE_FORCE 0x08f4 3177 #define regHUBPREQ3_UCLK_PSTATE_FORCE_BASE_IDX 2 3178 #define regHUBPREQ3_HUBPREQ_STATUS_REG0 0x08f5 3179 #define regHUBPREQ3_HUBPREQ_STATUS_REG0_BASE_IDX 2 3180 #define regHUBPREQ3_HUBPREQ_STATUS_REG1 0x08f6 3181 #define regHUBPREQ3_HUBPREQ_STATUS_REG1_BASE_IDX 2 3182 #define regHUBPREQ3_HUBPREQ_STATUS_REG2 0x08f7 3183 #define regHUBPREQ3_HUBPREQ_STATUS_REG2_BASE_IDX 2 3184 #define regHUBPREQ3_HUBPREQ_STATUS_REG3 0x08f8 3185 #define regHUBPREQ3_HUBPREQ_STATUS_REG3_BASE_IDX 2 3186 3187 3188 // addressBlock: dcn_dcec_dcbubp3_dispdec_hubpret_dispdec 3189 // base address: 0xa50 3190 #define regHUBPRET3_HUBPRET_CONTROL 0x0901 3191 #define regHUBPRET3_HUBPRET_CONTROL_BASE_IDX 2 3192 #define regHUBPRET3_HUBPRET_MEM_PWR_CTRL 0x0902 3193 #define regHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 3194 #define regHUBPRET3_HUBPRET_MEM_PWR_STATUS 0x0903 3195 #define regHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 3196 #define regHUBPRET3_HUBPRET_READ_LINE_CTRL0 0x0904 3197 #define regHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 3198 #define regHUBPRET3_HUBPRET_READ_LINE_CTRL1 0x0905 3199 #define regHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 3200 #define regHUBPRET3_HUBPRET_READ_LINE0 0x0906 3201 #define regHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX 2 3202 #define regHUBPRET3_HUBPRET_READ_LINE1 0x0907 3203 #define regHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX 2 3204 #define regHUBPRET3_HUBPRET_INTERRUPT 0x0908 3205 #define regHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX 2 3206 #define regHUBPRET3_HUBPRET_READ_LINE_VALUE 0x0909 3207 #define regHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 3208 #define regHUBPRET3_HUBPRET_READ_LINE_STATUS 0x090a 3209 #define regHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 3210 3211 3212 // addressBlock: dcn_dcec_dcbubp3_dispdec_cursor0_dispdec 3213 // base address: 0xa50 3214 #define regCURSOR0_3_CURSOR_CONTROL 0x090d 3215 #define regCURSOR0_3_CURSOR_CONTROL_BASE_IDX 2 3216 #define regCURSOR0_3_CURSOR_SURFACE_ADDRESS 0x090e 3217 #define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 3218 #define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH 0x090f 3219 #define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3220 #define regCURSOR0_3_CURSOR_SIZE 0x0910 3221 #define regCURSOR0_3_CURSOR_SIZE_BASE_IDX 2 3222 #define regCURSOR0_3_CURSOR_POSITION 0x0911 3223 #define regCURSOR0_3_CURSOR_POSITION_BASE_IDX 2 3224 #define regCURSOR0_3_CURSOR_HOT_SPOT 0x0912 3225 #define regCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX 2 3226 #define regCURSOR0_3_CURSOR_STEREO_CONTROL 0x0913 3227 #define regCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX 2 3228 #define regCURSOR0_3_CURSOR_DST_OFFSET 0x0914 3229 #define regCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX 2 3230 #define regCURSOR0_3_CURSOR_MEM_PWR_CTRL 0x0915 3231 #define regCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 3232 #define regCURSOR0_3_CURSOR_MEM_PWR_STATUS 0x0916 3233 #define regCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 3234 #define regCURSOR0_3_DMDATA_ADDRESS_HIGH 0x0917 3235 #define regCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX 2 3236 #define regCURSOR0_3_DMDATA_ADDRESS_LOW 0x0918 3237 #define regCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX 2 3238 #define regCURSOR0_3_DMDATA_CNTL 0x0919 3239 #define regCURSOR0_3_DMDATA_CNTL_BASE_IDX 2 3240 #define regCURSOR0_3_DMDATA_QOS_CNTL 0x091a 3241 #define regCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX 2 3242 #define regCURSOR0_3_DMDATA_STATUS 0x091b 3243 #define regCURSOR0_3_DMDATA_STATUS_BASE_IDX 2 3244 #define regCURSOR0_3_DMDATA_SW_CNTL 0x091c 3245 #define regCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX 2 3246 #define regCURSOR0_3_DMDATA_SW_DATA 0x091d 3247 #define regCURSOR0_3_DMDATA_SW_DATA_BASE_IDX 2 3248 #define regCURSOR0_3_HUBP_3DLUT_CONTROL 0x091e 3249 #define regCURSOR0_3_HUBP_3DLUT_CONTROL_BASE_IDX 2 3250 #define regCURSOR0_3_HUBP_3DLUT_ADDRESS_LOW 0x091f 3251 #define regCURSOR0_3_HUBP_3DLUT_ADDRESS_LOW_BASE_IDX 2 3252 #define regCURSOR0_3_HUBP_3DLUT_ADDRESS_HIGH 0x0920 3253 #define regCURSOR0_3_HUBP_3DLUT_ADDRESS_HIGH_BASE_IDX 2 3254 #define regCURSOR0_3_HUBP_3DLUT_DLG_PARAM 0x0921 3255 #define regCURSOR0_3_HUBP_3DLUT_DLG_PARAM_BASE_IDX 2 3256 3257 3258 // addressBlock: dcn_dcec_dpp0_dispdec_cnvc_cfg_dispdec 3259 // base address: 0x0 3260 #define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0ccf 3261 #define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 3262 #define regCNVC_CFG0_FORMAT_CONTROL 0x0cd0 3263 #define regCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2 3264 #define regCNVC_CFG0_FCNV_FP_BIAS_R 0x0cd1 3265 #define regCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX 2 3266 #define regCNVC_CFG0_FCNV_FP_BIAS_G 0x0cd2 3267 #define regCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX 2 3268 #define regCNVC_CFG0_FCNV_FP_BIAS_B 0x0cd3 3269 #define regCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX 2 3270 #define regCNVC_CFG0_FCNV_FP_SCALE_R 0x0cd4 3271 #define regCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX 2 3272 #define regCNVC_CFG0_FCNV_FP_SCALE_G 0x0cd5 3273 #define regCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX 2 3274 #define regCNVC_CFG0_FCNV_FP_SCALE_B 0x0cd6 3275 #define regCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX 2 3276 #define regCNVC_CFG0_COLOR_KEYER_CONTROL 0x0cd7 3277 #define regCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2 3278 #define regCNVC_CFG0_COLOR_KEYER_ALPHA 0x0cd8 3279 #define regCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2 3280 #define regCNVC_CFG0_COLOR_KEYER_RED 0x0cd9 3281 #define regCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2 3282 #define regCNVC_CFG0_COLOR_KEYER_GREEN 0x0cda 3283 #define regCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2 3284 #define regCNVC_CFG0_COLOR_KEYER_BLUE 0x0cdb 3285 #define regCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2 3286 #define regCNVC_CFG0_ALPHA_2BIT_LUT 0x0cdd 3287 #define regCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX 2 3288 #define regCNVC_CFG0_PRE_DEALPHA 0x0cde 3289 #define regCNVC_CFG0_PRE_DEALPHA_BASE_IDX 2 3290 #define regCNVC_CFG0_PRE_CSC_MODE 0x0cdf 3291 #define regCNVC_CFG0_PRE_CSC_MODE_BASE_IDX 2 3292 #define regCNVC_CFG0_PRE_CSC_C11_C12 0x0ce0 3293 #define regCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX 2 3294 #define regCNVC_CFG0_PRE_CSC_C13_C14 0x0ce1 3295 #define regCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX 2 3296 #define regCNVC_CFG0_PRE_CSC_C21_C22 0x0ce2 3297 #define regCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX 2 3298 #define regCNVC_CFG0_PRE_CSC_C23_C24 0x0ce3 3299 #define regCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX 2 3300 #define regCNVC_CFG0_PRE_CSC_C31_C32 0x0ce4 3301 #define regCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX 2 3302 #define regCNVC_CFG0_PRE_CSC_C33_C34 0x0ce5 3303 #define regCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX 2 3304 #define regCNVC_CFG0_PRE_CSC_B_C11_C12 0x0ce6 3305 #define regCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX 2 3306 #define regCNVC_CFG0_PRE_CSC_B_C13_C14 0x0ce7 3307 #define regCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX 2 3308 #define regCNVC_CFG0_PRE_CSC_B_C21_C22 0x0ce8 3309 #define regCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX 2 3310 #define regCNVC_CFG0_PRE_CSC_B_C23_C24 0x0ce9 3311 #define regCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX 2 3312 #define regCNVC_CFG0_PRE_CSC_B_C31_C32 0x0cea 3313 #define regCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX 2 3314 #define regCNVC_CFG0_PRE_CSC_B_C33_C34 0x0ceb 3315 #define regCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX 2 3316 #define regCNVC_CFG0_CNVC_COEF_FORMAT 0x0cec 3317 #define regCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX 2 3318 #define regCNVC_CFG0_PRE_DEGAM 0x0ced 3319 #define regCNVC_CFG0_PRE_DEGAM_BASE_IDX 2 3320 #define regCNVC_CFG0_PRE_REALPHA 0x0cee 3321 #define regCNVC_CFG0_PRE_REALPHA_BASE_IDX 2 3322 3323 3324 // addressBlock: dcn_dcec_dpp0_dispdec_cm_cur_dispdec 3325 // base address: 0x0 3326 #define regCM_CUR0_CURSOR0_CONTROL 0x0cf1 3327 #define regCM_CUR0_CURSOR0_CONTROL_BASE_IDX 2 3328 #define regCM_CUR0_CURSOR0_COLOR0 0x0cf2 3329 #define regCM_CUR0_CURSOR0_COLOR0_BASE_IDX 2 3330 #define regCM_CUR0_CURSOR0_COLOR1 0x0cf3 3331 #define regCM_CUR0_CURSOR0_COLOR1_BASE_IDX 2 3332 #define regCM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y 0x0cf4 3333 #define regCM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y_BASE_IDX 2 3334 #define regCM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB 0x0cf5 3335 #define regCM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB_BASE_IDX 2 3336 #define regCM_CUR0_CUR0_MATRIX_MODE 0x0cf6 3337 #define regCM_CUR0_CUR0_MATRIX_MODE_BASE_IDX 2 3338 #define regCM_CUR0_CUR0_MATRIX_C11_C12_A 0x0cf7 3339 #define regCM_CUR0_CUR0_MATRIX_C11_C12_A_BASE_IDX 2 3340 #define regCM_CUR0_CUR0_MATRIX_C13_C14_A 0x0cf8 3341 #define regCM_CUR0_CUR0_MATRIX_C13_C14_A_BASE_IDX 2 3342 #define regCM_CUR0_CUR0_MATRIX_C21_C22_A 0x0cf9 3343 #define regCM_CUR0_CUR0_MATRIX_C21_C22_A_BASE_IDX 2 3344 #define regCM_CUR0_CUR0_MATRIX_C23_C24_A 0x0cfa 3345 #define regCM_CUR0_CUR0_MATRIX_C23_C24_A_BASE_IDX 2 3346 #define regCM_CUR0_CUR0_MATRIX_C31_C32_A 0x0cfb 3347 #define regCM_CUR0_CUR0_MATRIX_C31_C32_A_BASE_IDX 2 3348 #define regCM_CUR0_CUR0_MATRIX_C33_C34_A 0x0cfc 3349 #define regCM_CUR0_CUR0_MATRIX_C33_C34_A_BASE_IDX 2 3350 #define regCM_CUR0_CUR0_MATRIX_C11_C12_B 0x0cfd 3351 #define regCM_CUR0_CUR0_MATRIX_C11_C12_B_BASE_IDX 2 3352 #define regCM_CUR0_CUR0_MATRIX_C13_C14_B 0x0cfe 3353 #define regCM_CUR0_CUR0_MATRIX_C13_C14_B_BASE_IDX 2 3354 #define regCM_CUR0_CUR0_MATRIX_C21_C22_B 0x0cff 3355 #define regCM_CUR0_CUR0_MATRIX_C21_C22_B_BASE_IDX 2 3356 #define regCM_CUR0_CUR0_MATRIX_C23_C24_B 0x0d00 3357 #define regCM_CUR0_CUR0_MATRIX_C23_C24_B_BASE_IDX 2 3358 #define regCM_CUR0_CUR0_MATRIX_C31_C32_B 0x0d01 3359 #define regCM_CUR0_CUR0_MATRIX_C31_C32_B_BASE_IDX 2 3360 #define regCM_CUR0_CUR0_MATRIX_C33_C34_B 0x0d02 3361 #define regCM_CUR0_CUR0_MATRIX_C33_C34_B_BASE_IDX 2 3362 3363 3364 // addressBlock: dcn_dcec_dpp0_dispdec_dscl_dispdec 3365 // base address: 0x0 3366 #define regDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0d06 3367 #define regDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 3368 #define regDSCL0_SCL_COEF_RAM_TAP_DATA 0x0d07 3369 #define regDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 3370 #define regDSCL0_SCL_MODE 0x0d08 3371 #define regDSCL0_SCL_MODE_BASE_IDX 2 3372 #define regDSCL0_SCL_TAP_CONTROL 0x0d09 3373 #define regDSCL0_SCL_TAP_CONTROL_BASE_IDX 2 3374 #define regDSCL0_DSCL_CONTROL 0x0d0a 3375 #define regDSCL0_DSCL_CONTROL_BASE_IDX 2 3376 #define regDSCL0_DSCL_2TAP_CONTROL 0x0d0b 3377 #define regDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2 3378 #define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0d0c 3379 #define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 3380 #define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0d0d 3381 #define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 3382 #define regDSCL0_SCL_HORZ_FILTER_INIT 0x0d0e 3383 #define regDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2 3384 #define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0d0f 3385 #define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 3386 #define regDSCL0_SCL_HORZ_FILTER_INIT_C 0x0d10 3387 #define regDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 3388 #define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0d11 3389 #define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 3390 #define regDSCL0_SCL_VERT_FILTER_INIT 0x0d12 3391 #define regDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2 3392 #define regDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0d13 3393 #define regDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 3394 #define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0d14 3395 #define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 3396 #define regDSCL0_SCL_VERT_FILTER_INIT_C 0x0d15 3397 #define regDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 3398 #define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0d16 3399 #define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 3400 #define regDSCL0_SCL_BLACK_COLOR 0x0d17 3401 #define regDSCL0_SCL_BLACK_COLOR_BASE_IDX 2 3402 #define regDSCL0_DSCL_UPDATE 0x0d18 3403 #define regDSCL0_DSCL_UPDATE_BASE_IDX 2 3404 #define regDSCL0_DSCL_AUTOCAL 0x0d19 3405 #define regDSCL0_DSCL_AUTOCAL_BASE_IDX 2 3406 #define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0d1a 3407 #define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 3408 #define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0d1b 3409 #define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 3410 #define regDSCL0_OTG_H_BLANK 0x0d1c 3411 #define regDSCL0_OTG_H_BLANK_BASE_IDX 2 3412 #define regDSCL0_OTG_V_BLANK 0x0d1d 3413 #define regDSCL0_OTG_V_BLANK_BASE_IDX 2 3414 #define regDSCL0_RECOUT_START 0x0d1e 3415 #define regDSCL0_RECOUT_START_BASE_IDX 2 3416 #define regDSCL0_RECOUT_SIZE 0x0d1f 3417 #define regDSCL0_RECOUT_SIZE_BASE_IDX 2 3418 #define regDSCL0_MPC_SIZE 0x0d20 3419 #define regDSCL0_MPC_SIZE_BASE_IDX 2 3420 #define regDSCL0_LB_DATA_FORMAT 0x0d21 3421 #define regDSCL0_LB_DATA_FORMAT_BASE_IDX 2 3422 #define regDSCL0_LB_MEMORY_CTRL 0x0d22 3423 #define regDSCL0_LB_MEMORY_CTRL_BASE_IDX 2 3424 #define regDSCL0_LB_V_COUNTER 0x0d23 3425 #define regDSCL0_LB_V_COUNTER_BASE_IDX 2 3426 #define regDSCL0_DSCL_MEM_PWR_CTRL 0x0d24 3427 #define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2 3428 #define regDSCL0_DSCL_MEM_PWR_STATUS 0x0d25 3429 #define regDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2 3430 #define regDSCL0_OBUF_CONTROL 0x0d26 3431 #define regDSCL0_OBUF_CONTROL_BASE_IDX 2 3432 #define regDSCL0_OBUF_MEM_PWR_CTRL 0x0d27 3433 #define regDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2 3434 #define regDSCL0_DSCL_EASF_H_MODE 0x0d28 3435 #define regDSCL0_DSCL_EASF_H_MODE_BASE_IDX 2 3436 #define regDSCL0_DSCL_EASF_V_MODE 0x0d29 3437 #define regDSCL0_DSCL_EASF_V_MODE_BASE_IDX 2 3438 #define regDSCL0_DSCL_SC_MODE 0x0d2a 3439 #define regDSCL0_DSCL_SC_MODE_BASE_IDX 2 3440 #define regDSCL0_DSCL_SC_MATRIX_C0C1 0x0d2b 3441 #define regDSCL0_DSCL_SC_MATRIX_C0C1_BASE_IDX 2 3442 #define regDSCL0_DSCL_SC_MATRIX_C2C3 0x0d2c 3443 #define regDSCL0_DSCL_SC_MATRIX_C2C3_BASE_IDX 2 3444 #define regDSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN 0x0d2d 3445 #define regDSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN_BASE_IDX 2 3446 #define regDSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE 0x0d2e 3447 #define regDSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE_BASE_IDX 2 3448 #define regDSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN 0x0d2f 3449 #define regDSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN_BASE_IDX 2 3450 #define regDSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE 0x0d30 3451 #define regDSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE_BASE_IDX 2 3452 #define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1 0x0d31 3453 #define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1_BASE_IDX 2 3454 #define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2 0x0d32 3455 #define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2_BASE_IDX 2 3456 #define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3 0x0d33 3457 #define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3_BASE_IDX 2 3458 #define regDSCL0_DSCL_EASF_RINGEST_FORCE 0x0d34 3459 #define regDSCL0_DSCL_EASF_RINGEST_FORCE_BASE_IDX 2 3460 #define regDSCL0_DSCL_EASF_H_BF_CNTL 0x0d35 3461 #define regDSCL0_DSCL_EASF_H_BF_CNTL_BASE_IDX 2 3462 #define regDSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN 0x0d36 3463 #define regDSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN_BASE_IDX 2 3464 #define regDSCL0_DSCL_EASF_V_BF_CNTL 0x0d37 3465 #define regDSCL0_DSCL_EASF_V_BF_CNTL_BASE_IDX 2 3466 #define regDSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN 0x0d38 3467 #define regDSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN_BASE_IDX 2 3468 #define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG0 0x0d39 3469 #define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG0_BASE_IDX 2 3470 #define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG1 0x0d3a 3471 #define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG1_BASE_IDX 2 3472 #define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG2 0x0d3b 3473 #define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG2_BASE_IDX 2 3474 #define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG3 0x0d3c 3475 #define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG3_BASE_IDX 2 3476 #define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG4 0x0d3d 3477 #define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG4_BASE_IDX 2 3478 #define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG5 0x0d3e 3479 #define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG5_BASE_IDX 2 3480 #define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG6 0x0d3f 3481 #define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG6_BASE_IDX 2 3482 #define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG7 0x0d40 3483 #define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG7_BASE_IDX 2 3484 #define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG0 0x0d41 3485 #define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG0_BASE_IDX 2 3486 #define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG1 0x0d42 3487 #define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG1_BASE_IDX 2 3488 #define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG2 0x0d43 3489 #define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG2_BASE_IDX 2 3490 #define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG3 0x0d44 3491 #define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG3_BASE_IDX 2 3492 #define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG4 0x0d45 3493 #define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG4_BASE_IDX 2 3494 #define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG5 0x0d46 3495 #define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG5_BASE_IDX 2 3496 #define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG6 0x0d47 3497 #define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG6_BASE_IDX 2 3498 #define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG7 0x0d48 3499 #define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG7_BASE_IDX 2 3500 #define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG0 0x0d49 3501 #define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG0_BASE_IDX 2 3502 #define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG1 0x0d4a 3503 #define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG1_BASE_IDX 2 3504 #define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG2 0x0d4b 3505 #define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG2_BASE_IDX 2 3506 #define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG3 0x0d4c 3507 #define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG3_BASE_IDX 2 3508 #define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG4 0x0d4d 3509 #define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG4_BASE_IDX 2 3510 #define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG5 0x0d4e 3511 #define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG5_BASE_IDX 2 3512 #define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG0 0x0d4f 3513 #define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG0_BASE_IDX 2 3514 #define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG1 0x0d50 3515 #define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG1_BASE_IDX 2 3516 #define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG2 0x0d51 3517 #define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG2_BASE_IDX 2 3518 #define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG3 0x0d52 3519 #define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG3_BASE_IDX 2 3520 #define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG4 0x0d53 3521 #define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG4_BASE_IDX 2 3522 #define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG5 0x0d54 3523 #define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG5_BASE_IDX 2 3524 #define regDSCL0_ISHARP_MODE 0x0d55 3525 #define regDSCL0_ISHARP_MODE_BASE_IDX 2 3526 #define regDSCL0_ISHARP_DELTA_CTRL 0x0d56 3527 #define regDSCL0_ISHARP_DELTA_CTRL_BASE_IDX 2 3528 #define regDSCL0_ISHARP_DELTA_INDEX 0x0d57 3529 #define regDSCL0_ISHARP_DELTA_INDEX_BASE_IDX 2 3530 #define regDSCL0_ISHARP_DELTA_DATA 0x0d58 3531 #define regDSCL0_ISHARP_DELTA_DATA_BASE_IDX 2 3532 #define regDSCL0_ISHARP_NLDELTA_SOFT_CLIP 0x0d59 3533 #define regDSCL0_ISHARP_NLDELTA_SOFT_CLIP_BASE_IDX 2 3534 #define regDSCL0_ISHARP_NOISEDET_THRESHOLD 0x0d5a 3535 #define regDSCL0_ISHARP_NOISEDET_THRESHOLD_BASE_IDX 2 3536 #define regDSCL0_ISHARP_NOISE_GAIN_PWL 0x0d5b 3537 #define regDSCL0_ISHARP_NOISE_GAIN_PWL_BASE_IDX 2 3538 #define regDSCL0_ISHARP_LBA_PWL_SEG0 0x0d5c 3539 #define regDSCL0_ISHARP_LBA_PWL_SEG0_BASE_IDX 2 3540 #define regDSCL0_ISHARP_LBA_PWL_SEG1 0x0d5d 3541 #define regDSCL0_ISHARP_LBA_PWL_SEG1_BASE_IDX 2 3542 #define regDSCL0_ISHARP_LBA_PWL_SEG2 0x0d5e 3543 #define regDSCL0_ISHARP_LBA_PWL_SEG2_BASE_IDX 2 3544 #define regDSCL0_ISHARP_LBA_PWL_SEG3 0x0d5f 3545 #define regDSCL0_ISHARP_LBA_PWL_SEG3_BASE_IDX 2 3546 #define regDSCL0_ISHARP_LBA_PWL_SEG4 0x0d60 3547 #define regDSCL0_ISHARP_LBA_PWL_SEG4_BASE_IDX 2 3548 #define regDSCL0_ISHARP_LBA_PWL_SEG5 0x0d61 3549 #define regDSCL0_ISHARP_LBA_PWL_SEG5_BASE_IDX 2 3550 #define regDSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL 0x0d62 3551 #define regDSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL_BASE_IDX 2 3552 3553 3554 // addressBlock: dcn_dcec_dpp0_dispdec_cm_dispdec 3555 // base address: 0x0 3556 #define regCM0_CM_CONTROL 0x0d67 3557 #define regCM0_CM_CONTROL_BASE_IDX 2 3558 #define regCM0_CM_POST_CSC_CONTROL 0x0d68 3559 #define regCM0_CM_POST_CSC_CONTROL_BASE_IDX 2 3560 #define regCM0_CM_POST_CSC_C11_C12 0x0d69 3561 #define regCM0_CM_POST_CSC_C11_C12_BASE_IDX 2 3562 #define regCM0_CM_POST_CSC_C13_C14 0x0d6a 3563 #define regCM0_CM_POST_CSC_C13_C14_BASE_IDX 2 3564 #define regCM0_CM_POST_CSC_C21_C22 0x0d6b 3565 #define regCM0_CM_POST_CSC_C21_C22_BASE_IDX 2 3566 #define regCM0_CM_POST_CSC_C23_C24 0x0d6c 3567 #define regCM0_CM_POST_CSC_C23_C24_BASE_IDX 2 3568 #define regCM0_CM_POST_CSC_C31_C32 0x0d6d 3569 #define regCM0_CM_POST_CSC_C31_C32_BASE_IDX 2 3570 #define regCM0_CM_POST_CSC_C33_C34 0x0d6e 3571 #define regCM0_CM_POST_CSC_C33_C34_BASE_IDX 2 3572 #define regCM0_CM_POST_CSC_B_C11_C12 0x0d6f 3573 #define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX 2 3574 #define regCM0_CM_POST_CSC_B_C13_C14 0x0d70 3575 #define regCM0_CM_POST_CSC_B_C13_C14_BASE_IDX 2 3576 #define regCM0_CM_POST_CSC_B_C21_C22 0x0d71 3577 #define regCM0_CM_POST_CSC_B_C21_C22_BASE_IDX 2 3578 #define regCM0_CM_POST_CSC_B_C23_C24 0x0d72 3579 #define regCM0_CM_POST_CSC_B_C23_C24_BASE_IDX 2 3580 #define regCM0_CM_POST_CSC_B_C31_C32 0x0d73 3581 #define regCM0_CM_POST_CSC_B_C31_C32_BASE_IDX 2 3582 #define regCM0_CM_POST_CSC_B_C33_C34 0x0d74 3583 #define regCM0_CM_POST_CSC_B_C33_C34_BASE_IDX 2 3584 #define regCM0_CM_BIAS_CR_R 0x0d75 3585 #define regCM0_CM_BIAS_CR_R_BASE_IDX 2 3586 #define regCM0_CM_BIAS_Y_G_CB_B 0x0d76 3587 #define regCM0_CM_BIAS_Y_G_CB_B_BASE_IDX 2 3588 #define regCM0_CM_GAMCOR_CONTROL 0x0d77 3589 #define regCM0_CM_GAMCOR_CONTROL_BASE_IDX 2 3590 #define regCM0_CM_GAMCOR_LUT_INDEX 0x0d78 3591 #define regCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 3592 #define regCM0_CM_GAMCOR_LUT_DATA 0x0d79 3593 #define regCM0_CM_GAMCOR_LUT_DATA_BASE_IDX 2 3594 #define regCM0_CM_GAMCOR_LUT_CONTROL 0x0d7a 3595 #define regCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 3596 #define regCM0_CM_GAMCOR_RAMA_START_CNTL_B 0x0d7b 3597 #define regCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 3598 #define regCM0_CM_GAMCOR_RAMA_START_CNTL_G 0x0d7c 3599 #define regCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 3600 #define regCM0_CM_GAMCOR_RAMA_START_CNTL_R 0x0d7d 3601 #define regCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 3602 #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0d7e 3603 #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 3604 #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0d7f 3605 #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 3606 #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0d80 3607 #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 3608 #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0d81 3609 #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 3610 #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0d82 3611 #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 3612 #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0d83 3613 #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 3614 #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B 0x0d84 3615 #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 3616 #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B 0x0d85 3617 #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 3618 #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G 0x0d86 3619 #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 3620 #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G 0x0d87 3621 #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 3622 #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R 0x0d88 3623 #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 3624 #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R 0x0d89 3625 #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 3626 #define regCM0_CM_GAMCOR_RAMA_OFFSET_B 0x0d8a 3627 #define regCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 3628 #define regCM0_CM_GAMCOR_RAMA_OFFSET_G 0x0d8b 3629 #define regCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 3630 #define regCM0_CM_GAMCOR_RAMA_OFFSET_R 0x0d8c 3631 #define regCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 3632 #define regCM0_CM_GAMCOR_RAMA_REGION_0_1 0x0d8d 3633 #define regCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 3634 #define regCM0_CM_GAMCOR_RAMA_REGION_2_3 0x0d8e 3635 #define regCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 3636 #define regCM0_CM_GAMCOR_RAMA_REGION_4_5 0x0d8f 3637 #define regCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 3638 #define regCM0_CM_GAMCOR_RAMA_REGION_6_7 0x0d90 3639 #define regCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 3640 #define regCM0_CM_GAMCOR_RAMA_REGION_8_9 0x0d91 3641 #define regCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 3642 #define regCM0_CM_GAMCOR_RAMA_REGION_10_11 0x0d92 3643 #define regCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 3644 #define regCM0_CM_GAMCOR_RAMA_REGION_12_13 0x0d93 3645 #define regCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 3646 #define regCM0_CM_GAMCOR_RAMA_REGION_14_15 0x0d94 3647 #define regCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 3648 #define regCM0_CM_GAMCOR_RAMA_REGION_16_17 0x0d95 3649 #define regCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 3650 #define regCM0_CM_GAMCOR_RAMA_REGION_18_19 0x0d96 3651 #define regCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 3652 #define regCM0_CM_GAMCOR_RAMA_REGION_20_21 0x0d97 3653 #define regCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 3654 #define regCM0_CM_GAMCOR_RAMA_REGION_22_23 0x0d98 3655 #define regCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 3656 #define regCM0_CM_GAMCOR_RAMA_REGION_24_25 0x0d99 3657 #define regCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 3658 #define regCM0_CM_GAMCOR_RAMA_REGION_26_27 0x0d9a 3659 #define regCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 3660 #define regCM0_CM_GAMCOR_RAMA_REGION_28_29 0x0d9b 3661 #define regCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 3662 #define regCM0_CM_GAMCOR_RAMA_REGION_30_31 0x0d9c 3663 #define regCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 3664 #define regCM0_CM_GAMCOR_RAMA_REGION_32_33 0x0d9d 3665 #define regCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 3666 #define regCM0_CM_GAMCOR_RAMB_START_CNTL_B 0x0d9e 3667 #define regCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 3668 #define regCM0_CM_GAMCOR_RAMB_START_CNTL_G 0x0d9f 3669 #define regCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 3670 #define regCM0_CM_GAMCOR_RAMB_START_CNTL_R 0x0da0 3671 #define regCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 3672 #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0da1 3673 #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 3674 #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0da2 3675 #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 3676 #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0da3 3677 #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 3678 #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0da4 3679 #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 3680 #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0da5 3681 #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 3682 #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0da6 3683 #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 3684 #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B 0x0da7 3685 #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 3686 #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B 0x0da8 3687 #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 3688 #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G 0x0da9 3689 #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 3690 #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G 0x0daa 3691 #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 3692 #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R 0x0dab 3693 #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 3694 #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R 0x0dac 3695 #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 3696 #define regCM0_CM_GAMCOR_RAMB_OFFSET_B 0x0dad 3697 #define regCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 3698 #define regCM0_CM_GAMCOR_RAMB_OFFSET_G 0x0dae 3699 #define regCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 3700 #define regCM0_CM_GAMCOR_RAMB_OFFSET_R 0x0daf 3701 #define regCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 3702 #define regCM0_CM_GAMCOR_RAMB_REGION_0_1 0x0db0 3703 #define regCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 3704 #define regCM0_CM_GAMCOR_RAMB_REGION_2_3 0x0db1 3705 #define regCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 3706 #define regCM0_CM_GAMCOR_RAMB_REGION_4_5 0x0db2 3707 #define regCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 3708 #define regCM0_CM_GAMCOR_RAMB_REGION_6_7 0x0db3 3709 #define regCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 3710 #define regCM0_CM_GAMCOR_RAMB_REGION_8_9 0x0db4 3711 #define regCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 3712 #define regCM0_CM_GAMCOR_RAMB_REGION_10_11 0x0db5 3713 #define regCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 3714 #define regCM0_CM_GAMCOR_RAMB_REGION_12_13 0x0db6 3715 #define regCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 3716 #define regCM0_CM_GAMCOR_RAMB_REGION_14_15 0x0db7 3717 #define regCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 3718 #define regCM0_CM_GAMCOR_RAMB_REGION_16_17 0x0db8 3719 #define regCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 3720 #define regCM0_CM_GAMCOR_RAMB_REGION_18_19 0x0db9 3721 #define regCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 3722 #define regCM0_CM_GAMCOR_RAMB_REGION_20_21 0x0dba 3723 #define regCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 3724 #define regCM0_CM_GAMCOR_RAMB_REGION_22_23 0x0dbb 3725 #define regCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 3726 #define regCM0_CM_GAMCOR_RAMB_REGION_24_25 0x0dbc 3727 #define regCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 3728 #define regCM0_CM_GAMCOR_RAMB_REGION_26_27 0x0dbd 3729 #define regCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 3730 #define regCM0_CM_GAMCOR_RAMB_REGION_28_29 0x0dbe 3731 #define regCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 3732 #define regCM0_CM_GAMCOR_RAMB_REGION_30_31 0x0dbf 3733 #define regCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 3734 #define regCM0_CM_GAMCOR_RAMB_REGION_32_33 0x0dc0 3735 #define regCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 3736 #define regCM0_CM_HDR_MULT_COEF 0x0dc1 3737 #define regCM0_CM_HDR_MULT_COEF_BASE_IDX 2 3738 #define regCM0_CM_MEM_PWR_CTRL 0x0dc2 3739 #define regCM0_CM_MEM_PWR_CTRL_BASE_IDX 2 3740 #define regCM0_CM_MEM_PWR_STATUS 0x0dc3 3741 #define regCM0_CM_MEM_PWR_STATUS_BASE_IDX 2 3742 #define regCM0_CM_DEALPHA 0x0dc5 3743 #define regCM0_CM_DEALPHA_BASE_IDX 2 3744 #define regCM0_CM_COEF_FORMAT 0x0dc6 3745 #define regCM0_CM_COEF_FORMAT_BASE_IDX 2 3746 #define regCM0_CM_TEST_DEBUG_INDEX 0x0dc7 3747 #define regCM0_CM_TEST_DEBUG_INDEX_BASE_IDX 2 3748 #define regCM0_CM_TEST_DEBUG_DATA 0x0dc8 3749 #define regCM0_CM_TEST_DEBUG_DATA_BASE_IDX 2 3750 3751 3752 // addressBlock: dcn_dcec_dpp0_dispdec_dpp_top_dispdec 3753 // base address: 0x0 3754 #define regDPP_TOP0_DPP_CONTROL 0x0cc5 3755 #define regDPP_TOP0_DPP_CONTROL_BASE_IDX 2 3756 #define regDPP_TOP0_DPP_SOFT_RESET 0x0cc6 3757 #define regDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2 3758 #define regDPP_TOP0_DPP_CRC_VAL_R_G 0x0cc7 3759 #define regDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX 2 3760 #define regDPP_TOP0_DPP_CRC_VAL_B_A 0x0cc8 3761 #define regDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX 2 3762 #define regDPP_TOP0_DPP_CRC_CTRL 0x0cc9 3763 #define regDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2 3764 #define regDPP_TOP0_HOST_READ_CONTROL 0x0cca 3765 #define regDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2 3766 3767 // addressBlock: dcn_dcec_dpp1_dispdec_cnvc_cfg_dispdec 3768 // base address: 0x5ac 3769 #define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0e3a 3770 #define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 3771 #define regCNVC_CFG1_FORMAT_CONTROL 0x0e3b 3772 #define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2 3773 #define regCNVC_CFG1_FCNV_FP_BIAS_R 0x0e3c 3774 #define regCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX 2 3775 #define regCNVC_CFG1_FCNV_FP_BIAS_G 0x0e3d 3776 #define regCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX 2 3777 #define regCNVC_CFG1_FCNV_FP_BIAS_B 0x0e3e 3778 #define regCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX 2 3779 #define regCNVC_CFG1_FCNV_FP_SCALE_R 0x0e3f 3780 #define regCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX 2 3781 #define regCNVC_CFG1_FCNV_FP_SCALE_G 0x0e40 3782 #define regCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX 2 3783 #define regCNVC_CFG1_FCNV_FP_SCALE_B 0x0e41 3784 #define regCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX 2 3785 #define regCNVC_CFG1_COLOR_KEYER_CONTROL 0x0e42 3786 #define regCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2 3787 #define regCNVC_CFG1_COLOR_KEYER_ALPHA 0x0e43 3788 #define regCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2 3789 #define regCNVC_CFG1_COLOR_KEYER_RED 0x0e44 3790 #define regCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2 3791 #define regCNVC_CFG1_COLOR_KEYER_GREEN 0x0e45 3792 #define regCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2 3793 #define regCNVC_CFG1_COLOR_KEYER_BLUE 0x0e46 3794 #define regCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2 3795 #define regCNVC_CFG1_ALPHA_2BIT_LUT 0x0e48 3796 #define regCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX 2 3797 #define regCNVC_CFG1_PRE_DEALPHA 0x0e49 3798 #define regCNVC_CFG1_PRE_DEALPHA_BASE_IDX 2 3799 #define regCNVC_CFG1_PRE_CSC_MODE 0x0e4a 3800 #define regCNVC_CFG1_PRE_CSC_MODE_BASE_IDX 2 3801 #define regCNVC_CFG1_PRE_CSC_C11_C12 0x0e4b 3802 #define regCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX 2 3803 #define regCNVC_CFG1_PRE_CSC_C13_C14 0x0e4c 3804 #define regCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX 2 3805 #define regCNVC_CFG1_PRE_CSC_C21_C22 0x0e4d 3806 #define regCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX 2 3807 #define regCNVC_CFG1_PRE_CSC_C23_C24 0x0e4e 3808 #define regCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX 2 3809 #define regCNVC_CFG1_PRE_CSC_C31_C32 0x0e4f 3810 #define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX 2 3811 #define regCNVC_CFG1_PRE_CSC_C33_C34 0x0e50 3812 #define regCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX 2 3813 #define regCNVC_CFG1_PRE_CSC_B_C11_C12 0x0e51 3814 #define regCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX 2 3815 #define regCNVC_CFG1_PRE_CSC_B_C13_C14 0x0e52 3816 #define regCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX 2 3817 #define regCNVC_CFG1_PRE_CSC_B_C21_C22 0x0e53 3818 #define regCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX 2 3819 #define regCNVC_CFG1_PRE_CSC_B_C23_C24 0x0e54 3820 #define regCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX 2 3821 #define regCNVC_CFG1_PRE_CSC_B_C31_C32 0x0e55 3822 #define regCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX 2 3823 #define regCNVC_CFG1_PRE_CSC_B_C33_C34 0x0e56 3824 #define regCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX 2 3825 #define regCNVC_CFG1_CNVC_COEF_FORMAT 0x0e57 3826 #define regCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX 2 3827 #define regCNVC_CFG1_PRE_DEGAM 0x0e58 3828 #define regCNVC_CFG1_PRE_DEGAM_BASE_IDX 2 3829 #define regCNVC_CFG1_PRE_REALPHA 0x0e59 3830 #define regCNVC_CFG1_PRE_REALPHA_BASE_IDX 2 3831 3832 3833 // addressBlock: dcn_dcec_dpp1_dispdec_cm_cur_dispdec 3834 // base address: 0x5ac 3835 #define regCM_CUR1_CURSOR0_CONTROL 0x0e5c 3836 #define regCM_CUR1_CURSOR0_CONTROL_BASE_IDX 2 3837 #define regCM_CUR1_CURSOR0_COLOR0 0x0e5d 3838 #define regCM_CUR1_CURSOR0_COLOR0_BASE_IDX 2 3839 #define regCM_CUR1_CURSOR0_COLOR1 0x0e5e 3840 #define regCM_CUR1_CURSOR0_COLOR1_BASE_IDX 2 3841 #define regCM_CUR1_CURSOR0_FP_SCALE_BIAS_G_Y 0x0e5f 3842 #define regCM_CUR1_CURSOR0_FP_SCALE_BIAS_G_Y_BASE_IDX 2 3843 #define regCM_CUR1_CURSOR0_FP_SCALE_BIAS_RB_CRCB 0x0e60 3844 #define regCM_CUR1_CURSOR0_FP_SCALE_BIAS_RB_CRCB_BASE_IDX 2 3845 #define regCM_CUR1_CUR0_MATRIX_MODE 0x0e61 3846 #define regCM_CUR1_CUR0_MATRIX_MODE_BASE_IDX 2 3847 #define regCM_CUR1_CUR0_MATRIX_C11_C12_A 0x0e62 3848 #define regCM_CUR1_CUR0_MATRIX_C11_C12_A_BASE_IDX 2 3849 #define regCM_CUR1_CUR0_MATRIX_C13_C14_A 0x0e63 3850 #define regCM_CUR1_CUR0_MATRIX_C13_C14_A_BASE_IDX 2 3851 #define regCM_CUR1_CUR0_MATRIX_C21_C22_A 0x0e64 3852 #define regCM_CUR1_CUR0_MATRIX_C21_C22_A_BASE_IDX 2 3853 #define regCM_CUR1_CUR0_MATRIX_C23_C24_A 0x0e65 3854 #define regCM_CUR1_CUR0_MATRIX_C23_C24_A_BASE_IDX 2 3855 #define regCM_CUR1_CUR0_MATRIX_C31_C32_A 0x0e66 3856 #define regCM_CUR1_CUR0_MATRIX_C31_C32_A_BASE_IDX 2 3857 #define regCM_CUR1_CUR0_MATRIX_C33_C34_A 0x0e67 3858 #define regCM_CUR1_CUR0_MATRIX_C33_C34_A_BASE_IDX 2 3859 #define regCM_CUR1_CUR0_MATRIX_C11_C12_B 0x0e68 3860 #define regCM_CUR1_CUR0_MATRIX_C11_C12_B_BASE_IDX 2 3861 #define regCM_CUR1_CUR0_MATRIX_C13_C14_B 0x0e69 3862 #define regCM_CUR1_CUR0_MATRIX_C13_C14_B_BASE_IDX 2 3863 #define regCM_CUR1_CUR0_MATRIX_C21_C22_B 0x0e6a 3864 #define regCM_CUR1_CUR0_MATRIX_C21_C22_B_BASE_IDX 2 3865 #define regCM_CUR1_CUR0_MATRIX_C23_C24_B 0x0e6b 3866 #define regCM_CUR1_CUR0_MATRIX_C23_C24_B_BASE_IDX 2 3867 #define regCM_CUR1_CUR0_MATRIX_C31_C32_B 0x0e6c 3868 #define regCM_CUR1_CUR0_MATRIX_C31_C32_B_BASE_IDX 2 3869 #define regCM_CUR1_CUR0_MATRIX_C33_C34_B 0x0e6d 3870 #define regCM_CUR1_CUR0_MATRIX_C33_C34_B_BASE_IDX 2 3871 3872 3873 // addressBlock: dcn_dcec_dpp1_dispdec_dscl_dispdec 3874 // base address: 0x5ac 3875 #define regDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0e71 3876 #define regDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 3877 #define regDSCL1_SCL_COEF_RAM_TAP_DATA 0x0e72 3878 #define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 3879 #define regDSCL1_SCL_MODE 0x0e73 3880 #define regDSCL1_SCL_MODE_BASE_IDX 2 3881 #define regDSCL1_SCL_TAP_CONTROL 0x0e74 3882 #define regDSCL1_SCL_TAP_CONTROL_BASE_IDX 2 3883 #define regDSCL1_DSCL_CONTROL 0x0e75 3884 #define regDSCL1_DSCL_CONTROL_BASE_IDX 2 3885 #define regDSCL1_DSCL_2TAP_CONTROL 0x0e76 3886 #define regDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2 3887 #define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0e77 3888 #define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 3889 #define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0e78 3890 #define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 3891 #define regDSCL1_SCL_HORZ_FILTER_INIT 0x0e79 3892 #define regDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2 3893 #define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0e7a 3894 #define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 3895 #define regDSCL1_SCL_HORZ_FILTER_INIT_C 0x0e7b 3896 #define regDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 3897 #define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0e7c 3898 #define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 3899 #define regDSCL1_SCL_VERT_FILTER_INIT 0x0e7d 3900 #define regDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2 3901 #define regDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0e7e 3902 #define regDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 3903 #define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0e7f 3904 #define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 3905 #define regDSCL1_SCL_VERT_FILTER_INIT_C 0x0e80 3906 #define regDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 3907 #define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0e81 3908 #define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 3909 #define regDSCL1_SCL_BLACK_COLOR 0x0e82 3910 #define regDSCL1_SCL_BLACK_COLOR_BASE_IDX 2 3911 #define regDSCL1_DSCL_UPDATE 0x0e83 3912 #define regDSCL1_DSCL_UPDATE_BASE_IDX 2 3913 #define regDSCL1_DSCL_AUTOCAL 0x0e84 3914 #define regDSCL1_DSCL_AUTOCAL_BASE_IDX 2 3915 #define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0e85 3916 #define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 3917 #define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0e86 3918 #define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 3919 #define regDSCL1_OTG_H_BLANK 0x0e87 3920 #define regDSCL1_OTG_H_BLANK_BASE_IDX 2 3921 #define regDSCL1_OTG_V_BLANK 0x0e88 3922 #define regDSCL1_OTG_V_BLANK_BASE_IDX 2 3923 #define regDSCL1_RECOUT_START 0x0e89 3924 #define regDSCL1_RECOUT_START_BASE_IDX 2 3925 #define regDSCL1_RECOUT_SIZE 0x0e8a 3926 #define regDSCL1_RECOUT_SIZE_BASE_IDX 2 3927 #define regDSCL1_MPC_SIZE 0x0e8b 3928 #define regDSCL1_MPC_SIZE_BASE_IDX 2 3929 #define regDSCL1_LB_DATA_FORMAT 0x0e8c 3930 #define regDSCL1_LB_DATA_FORMAT_BASE_IDX 2 3931 #define regDSCL1_LB_MEMORY_CTRL 0x0e8d 3932 #define regDSCL1_LB_MEMORY_CTRL_BASE_IDX 2 3933 #define regDSCL1_LB_V_COUNTER 0x0e8e 3934 #define regDSCL1_LB_V_COUNTER_BASE_IDX 2 3935 #define regDSCL1_DSCL_MEM_PWR_CTRL 0x0e8f 3936 #define regDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2 3937 #define regDSCL1_DSCL_MEM_PWR_STATUS 0x0e90 3938 #define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2 3939 #define regDSCL1_OBUF_CONTROL 0x0e91 3940 #define regDSCL1_OBUF_CONTROL_BASE_IDX 2 3941 #define regDSCL1_OBUF_MEM_PWR_CTRL 0x0e92 3942 #define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2 3943 #define regDSCL1_DSCL_EASF_H_MODE 0x0e93 3944 #define regDSCL1_DSCL_EASF_H_MODE_BASE_IDX 2 3945 #define regDSCL1_DSCL_EASF_V_MODE 0x0e94 3946 #define regDSCL1_DSCL_EASF_V_MODE_BASE_IDX 2 3947 #define regDSCL1_DSCL_SC_MODE 0x0e95 3948 #define regDSCL1_DSCL_SC_MODE_BASE_IDX 2 3949 #define regDSCL1_DSCL_SC_MATRIX_C0C1 0x0e96 3950 #define regDSCL1_DSCL_SC_MATRIX_C0C1_BASE_IDX 2 3951 #define regDSCL1_DSCL_SC_MATRIX_C2C3 0x0e97 3952 #define regDSCL1_DSCL_SC_MATRIX_C2C3_BASE_IDX 2 3953 #define regDSCL1_DSCL_EASF_H_RINGEST_EVENTAP_GAIN 0x0e98 3954 #define regDSCL1_DSCL_EASF_H_RINGEST_EVENTAP_GAIN_BASE_IDX 2 3955 #define regDSCL1_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE 0x0e99 3956 #define regDSCL1_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE_BASE_IDX 2 3957 #define regDSCL1_DSCL_EASF_V_RINGEST_EVENTAP_GAIN 0x0e9a 3958 #define regDSCL1_DSCL_EASF_V_RINGEST_EVENTAP_GAIN_BASE_IDX 2 3959 #define regDSCL1_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE 0x0e9b 3960 #define regDSCL1_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE_BASE_IDX 2 3961 #define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL1 0x0e9c 3962 #define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL1_BASE_IDX 2 3963 #define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL2 0x0e9d 3964 #define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL2_BASE_IDX 2 3965 #define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL3 0x0e9e 3966 #define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL3_BASE_IDX 2 3967 #define regDSCL1_DSCL_EASF_RINGEST_FORCE 0x0e9f 3968 #define regDSCL1_DSCL_EASF_RINGEST_FORCE_BASE_IDX 2 3969 #define regDSCL1_DSCL_EASF_H_BF_CNTL 0x0ea0 3970 #define regDSCL1_DSCL_EASF_H_BF_CNTL_BASE_IDX 2 3971 #define regDSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN 0x0ea1 3972 #define regDSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN_BASE_IDX 2 3973 #define regDSCL1_DSCL_EASF_V_BF_CNTL 0x0ea2 3974 #define regDSCL1_DSCL_EASF_V_BF_CNTL_BASE_IDX 2 3975 #define regDSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN 0x0ea3 3976 #define regDSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN_BASE_IDX 2 3977 #define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG0 0x0ea4 3978 #define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG0_BASE_IDX 2 3979 #define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG1 0x0ea5 3980 #define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG1_BASE_IDX 2 3981 #define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG2 0x0ea6 3982 #define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG2_BASE_IDX 2 3983 #define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG3 0x0ea7 3984 #define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG3_BASE_IDX 2 3985 #define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG4 0x0ea8 3986 #define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG4_BASE_IDX 2 3987 #define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG5 0x0ea9 3988 #define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG5_BASE_IDX 2 3989 #define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG6 0x0eaa 3990 #define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG6_BASE_IDX 2 3991 #define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG7 0x0eab 3992 #define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG7_BASE_IDX 2 3993 #define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG0 0x0eac 3994 #define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG0_BASE_IDX 2 3995 #define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG1 0x0ead 3996 #define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG1_BASE_IDX 2 3997 #define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG2 0x0eae 3998 #define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG2_BASE_IDX 2 3999 #define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG3 0x0eaf 4000 #define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG3_BASE_IDX 2 4001 #define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG4 0x0eb0 4002 #define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG4_BASE_IDX 2 4003 #define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG5 0x0eb1 4004 #define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG5_BASE_IDX 2 4005 #define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG6 0x0eb2 4006 #define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG6_BASE_IDX 2 4007 #define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG7 0x0eb3 4008 #define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG7_BASE_IDX 2 4009 #define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG0 0x0eb4 4010 #define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG0_BASE_IDX 2 4011 #define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG1 0x0eb5 4012 #define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG1_BASE_IDX 2 4013 #define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG2 0x0eb6 4014 #define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG2_BASE_IDX 2 4015 #define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG3 0x0eb7 4016 #define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG3_BASE_IDX 2 4017 #define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG4 0x0eb8 4018 #define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG4_BASE_IDX 2 4019 #define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG5 0x0eb9 4020 #define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG5_BASE_IDX 2 4021 #define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG0 0x0eba 4022 #define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG0_BASE_IDX 2 4023 #define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG1 0x0ebb 4024 #define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG1_BASE_IDX 2 4025 #define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG2 0x0ebc 4026 #define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG2_BASE_IDX 2 4027 #define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG3 0x0ebd 4028 #define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG3_BASE_IDX 2 4029 #define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG4 0x0ebe 4030 #define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG4_BASE_IDX 2 4031 #define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG5 0x0ebf 4032 #define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG5_BASE_IDX 2 4033 #define regDSCL1_ISHARP_MODE 0x0ec0 4034 #define regDSCL1_ISHARP_MODE_BASE_IDX 2 4035 #define regDSCL1_ISHARP_DELTA_CTRL 0x0ec1 4036 #define regDSCL1_ISHARP_DELTA_CTRL_BASE_IDX 2 4037 #define regDSCL1_ISHARP_DELTA_INDEX 0x0ec2 4038 #define regDSCL1_ISHARP_DELTA_INDEX_BASE_IDX 2 4039 #define regDSCL1_ISHARP_DELTA_DATA 0x0ec3 4040 #define regDSCL1_ISHARP_DELTA_DATA_BASE_IDX 2 4041 #define regDSCL1_ISHARP_NLDELTA_SOFT_CLIP 0x0ec4 4042 #define regDSCL1_ISHARP_NLDELTA_SOFT_CLIP_BASE_IDX 2 4043 #define regDSCL1_ISHARP_NOISEDET_THRESHOLD 0x0ec5 4044 #define regDSCL1_ISHARP_NOISEDET_THRESHOLD_BASE_IDX 2 4045 #define regDSCL1_ISHARP_NOISE_GAIN_PWL 0x0ec6 4046 #define regDSCL1_ISHARP_NOISE_GAIN_PWL_BASE_IDX 2 4047 #define regDSCL1_ISHARP_LBA_PWL_SEG0 0x0ec7 4048 #define regDSCL1_ISHARP_LBA_PWL_SEG0_BASE_IDX 2 4049 #define regDSCL1_ISHARP_LBA_PWL_SEG1 0x0ec8 4050 #define regDSCL1_ISHARP_LBA_PWL_SEG1_BASE_IDX 2 4051 #define regDSCL1_ISHARP_LBA_PWL_SEG2 0x0ec9 4052 #define regDSCL1_ISHARP_LBA_PWL_SEG2_BASE_IDX 2 4053 #define regDSCL1_ISHARP_LBA_PWL_SEG3 0x0eca 4054 #define regDSCL1_ISHARP_LBA_PWL_SEG3_BASE_IDX 2 4055 #define regDSCL1_ISHARP_LBA_PWL_SEG4 0x0ecb 4056 #define regDSCL1_ISHARP_LBA_PWL_SEG4_BASE_IDX 2 4057 #define regDSCL1_ISHARP_LBA_PWL_SEG5 0x0ecc 4058 #define regDSCL1_ISHARP_LBA_PWL_SEG5_BASE_IDX 2 4059 #define regDSCL1_ISHARP_DELTA_LUT_MEM_PWR_CTRL 0x0ecd 4060 #define regDSCL1_ISHARP_DELTA_LUT_MEM_PWR_CTRL_BASE_IDX 2 4061 4062 4063 // addressBlock: dcn_dcec_dpp1_dispdec_cm_dispdec 4064 // base address: 0x5ac 4065 #define regCM1_CM_CONTROL 0x0ed2 4066 #define regCM1_CM_CONTROL_BASE_IDX 2 4067 #define regCM1_CM_POST_CSC_CONTROL 0x0ed3 4068 #define regCM1_CM_POST_CSC_CONTROL_BASE_IDX 2 4069 #define regCM1_CM_POST_CSC_C11_C12 0x0ed4 4070 #define regCM1_CM_POST_CSC_C11_C12_BASE_IDX 2 4071 #define regCM1_CM_POST_CSC_C13_C14 0x0ed5 4072 #define regCM1_CM_POST_CSC_C13_C14_BASE_IDX 2 4073 #define regCM1_CM_POST_CSC_C21_C22 0x0ed6 4074 #define regCM1_CM_POST_CSC_C21_C22_BASE_IDX 2 4075 #define regCM1_CM_POST_CSC_C23_C24 0x0ed7 4076 #define regCM1_CM_POST_CSC_C23_C24_BASE_IDX 2 4077 #define regCM1_CM_POST_CSC_C31_C32 0x0ed8 4078 #define regCM1_CM_POST_CSC_C31_C32_BASE_IDX 2 4079 #define regCM1_CM_POST_CSC_C33_C34 0x0ed9 4080 #define regCM1_CM_POST_CSC_C33_C34_BASE_IDX 2 4081 #define regCM1_CM_POST_CSC_B_C11_C12 0x0eda 4082 #define regCM1_CM_POST_CSC_B_C11_C12_BASE_IDX 2 4083 #define regCM1_CM_POST_CSC_B_C13_C14 0x0edb 4084 #define regCM1_CM_POST_CSC_B_C13_C14_BASE_IDX 2 4085 #define regCM1_CM_POST_CSC_B_C21_C22 0x0edc 4086 #define regCM1_CM_POST_CSC_B_C21_C22_BASE_IDX 2 4087 #define regCM1_CM_POST_CSC_B_C23_C24 0x0edd 4088 #define regCM1_CM_POST_CSC_B_C23_C24_BASE_IDX 2 4089 #define regCM1_CM_POST_CSC_B_C31_C32 0x0ede 4090 #define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX 2 4091 #define regCM1_CM_POST_CSC_B_C33_C34 0x0edf 4092 #define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX 2 4093 #define regCM1_CM_BIAS_CR_R 0x0ee0 4094 #define regCM1_CM_BIAS_CR_R_BASE_IDX 2 4095 #define regCM1_CM_BIAS_Y_G_CB_B 0x0ee1 4096 #define regCM1_CM_BIAS_Y_G_CB_B_BASE_IDX 2 4097 #define regCM1_CM_GAMCOR_CONTROL 0x0ee2 4098 #define regCM1_CM_GAMCOR_CONTROL_BASE_IDX 2 4099 #define regCM1_CM_GAMCOR_LUT_INDEX 0x0ee3 4100 #define regCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 4101 #define regCM1_CM_GAMCOR_LUT_DATA 0x0ee4 4102 #define regCM1_CM_GAMCOR_LUT_DATA_BASE_IDX 2 4103 #define regCM1_CM_GAMCOR_LUT_CONTROL 0x0ee5 4104 #define regCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 4105 #define regCM1_CM_GAMCOR_RAMA_START_CNTL_B 0x0ee6 4106 #define regCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 4107 #define regCM1_CM_GAMCOR_RAMA_START_CNTL_G 0x0ee7 4108 #define regCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 4109 #define regCM1_CM_GAMCOR_RAMA_START_CNTL_R 0x0ee8 4110 #define regCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 4111 #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0ee9 4112 #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 4113 #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0eea 4114 #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 4115 #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0eeb 4116 #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 4117 #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0eec 4118 #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 4119 #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0eed 4120 #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 4121 #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0eee 4122 #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 4123 #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B 0x0eef 4124 #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 4125 #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B 0x0ef0 4126 #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 4127 #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G 0x0ef1 4128 #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 4129 #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G 0x0ef2 4130 #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 4131 #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R 0x0ef3 4132 #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 4133 #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R 0x0ef4 4134 #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 4135 #define regCM1_CM_GAMCOR_RAMA_OFFSET_B 0x0ef5 4136 #define regCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 4137 #define regCM1_CM_GAMCOR_RAMA_OFFSET_G 0x0ef6 4138 #define regCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 4139 #define regCM1_CM_GAMCOR_RAMA_OFFSET_R 0x0ef7 4140 #define regCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 4141 #define regCM1_CM_GAMCOR_RAMA_REGION_0_1 0x0ef8 4142 #define regCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 4143 #define regCM1_CM_GAMCOR_RAMA_REGION_2_3 0x0ef9 4144 #define regCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 4145 #define regCM1_CM_GAMCOR_RAMA_REGION_4_5 0x0efa 4146 #define regCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 4147 #define regCM1_CM_GAMCOR_RAMA_REGION_6_7 0x0efb 4148 #define regCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 4149 #define regCM1_CM_GAMCOR_RAMA_REGION_8_9 0x0efc 4150 #define regCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 4151 #define regCM1_CM_GAMCOR_RAMA_REGION_10_11 0x0efd 4152 #define regCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 4153 #define regCM1_CM_GAMCOR_RAMA_REGION_12_13 0x0efe 4154 #define regCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 4155 #define regCM1_CM_GAMCOR_RAMA_REGION_14_15 0x0eff 4156 #define regCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 4157 #define regCM1_CM_GAMCOR_RAMA_REGION_16_17 0x0f00 4158 #define regCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 4159 #define regCM1_CM_GAMCOR_RAMA_REGION_18_19 0x0f01 4160 #define regCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 4161 #define regCM1_CM_GAMCOR_RAMA_REGION_20_21 0x0f02 4162 #define regCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 4163 #define regCM1_CM_GAMCOR_RAMA_REGION_22_23 0x0f03 4164 #define regCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 4165 #define regCM1_CM_GAMCOR_RAMA_REGION_24_25 0x0f04 4166 #define regCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 4167 #define regCM1_CM_GAMCOR_RAMA_REGION_26_27 0x0f05 4168 #define regCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 4169 #define regCM1_CM_GAMCOR_RAMA_REGION_28_29 0x0f06 4170 #define regCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 4171 #define regCM1_CM_GAMCOR_RAMA_REGION_30_31 0x0f07 4172 #define regCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 4173 #define regCM1_CM_GAMCOR_RAMA_REGION_32_33 0x0f08 4174 #define regCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 4175 #define regCM1_CM_GAMCOR_RAMB_START_CNTL_B 0x0f09 4176 #define regCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 4177 #define regCM1_CM_GAMCOR_RAMB_START_CNTL_G 0x0f0a 4178 #define regCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 4179 #define regCM1_CM_GAMCOR_RAMB_START_CNTL_R 0x0f0b 4180 #define regCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 4181 #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0f0c 4182 #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 4183 #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0f0d 4184 #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 4185 #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0f0e 4186 #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 4187 #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0f0f 4188 #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 4189 #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0f10 4190 #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 4191 #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0f11 4192 #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 4193 #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B 0x0f12 4194 #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 4195 #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B 0x0f13 4196 #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 4197 #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G 0x0f14 4198 #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 4199 #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G 0x0f15 4200 #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 4201 #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R 0x0f16 4202 #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 4203 #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R 0x0f17 4204 #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 4205 #define regCM1_CM_GAMCOR_RAMB_OFFSET_B 0x0f18 4206 #define regCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 4207 #define regCM1_CM_GAMCOR_RAMB_OFFSET_G 0x0f19 4208 #define regCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 4209 #define regCM1_CM_GAMCOR_RAMB_OFFSET_R 0x0f1a 4210 #define regCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 4211 #define regCM1_CM_GAMCOR_RAMB_REGION_0_1 0x0f1b 4212 #define regCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 4213 #define regCM1_CM_GAMCOR_RAMB_REGION_2_3 0x0f1c 4214 #define regCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 4215 #define regCM1_CM_GAMCOR_RAMB_REGION_4_5 0x0f1d 4216 #define regCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 4217 #define regCM1_CM_GAMCOR_RAMB_REGION_6_7 0x0f1e 4218 #define regCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 4219 #define regCM1_CM_GAMCOR_RAMB_REGION_8_9 0x0f1f 4220 #define regCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 4221 #define regCM1_CM_GAMCOR_RAMB_REGION_10_11 0x0f20 4222 #define regCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 4223 #define regCM1_CM_GAMCOR_RAMB_REGION_12_13 0x0f21 4224 #define regCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 4225 #define regCM1_CM_GAMCOR_RAMB_REGION_14_15 0x0f22 4226 #define regCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 4227 #define regCM1_CM_GAMCOR_RAMB_REGION_16_17 0x0f23 4228 #define regCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 4229 #define regCM1_CM_GAMCOR_RAMB_REGION_18_19 0x0f24 4230 #define regCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 4231 #define regCM1_CM_GAMCOR_RAMB_REGION_20_21 0x0f25 4232 #define regCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 4233 #define regCM1_CM_GAMCOR_RAMB_REGION_22_23 0x0f26 4234 #define regCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 4235 #define regCM1_CM_GAMCOR_RAMB_REGION_24_25 0x0f27 4236 #define regCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 4237 #define regCM1_CM_GAMCOR_RAMB_REGION_26_27 0x0f28 4238 #define regCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 4239 #define regCM1_CM_GAMCOR_RAMB_REGION_28_29 0x0f29 4240 #define regCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 4241 #define regCM1_CM_GAMCOR_RAMB_REGION_30_31 0x0f2a 4242 #define regCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 4243 #define regCM1_CM_GAMCOR_RAMB_REGION_32_33 0x0f2b 4244 #define regCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 4245 #define regCM1_CM_HDR_MULT_COEF 0x0f2c 4246 #define regCM1_CM_HDR_MULT_COEF_BASE_IDX 2 4247 #define regCM1_CM_MEM_PWR_CTRL 0x0f2d 4248 #define regCM1_CM_MEM_PWR_CTRL_BASE_IDX 2 4249 #define regCM1_CM_MEM_PWR_STATUS 0x0f2e 4250 #define regCM1_CM_MEM_PWR_STATUS_BASE_IDX 2 4251 #define regCM1_CM_DEALPHA 0x0f30 4252 #define regCM1_CM_DEALPHA_BASE_IDX 2 4253 #define regCM1_CM_COEF_FORMAT 0x0f31 4254 #define regCM1_CM_COEF_FORMAT_BASE_IDX 2 4255 #define regCM1_CM_TEST_DEBUG_INDEX 0x0f32 4256 #define regCM1_CM_TEST_DEBUG_INDEX_BASE_IDX 2 4257 #define regCM1_CM_TEST_DEBUG_DATA 0x0f33 4258 #define regCM1_CM_TEST_DEBUG_DATA_BASE_IDX 2 4259 4260 4261 // addressBlock: dcn_dcec_dpp1_dispdec_dpp_top_dispdec 4262 // base address: 0x5ac 4263 #define regDPP_TOP1_DPP_CONTROL 0x0e30 4264 #define regDPP_TOP1_DPP_CONTROL_BASE_IDX 2 4265 #define regDPP_TOP1_DPP_SOFT_RESET 0x0e31 4266 #define regDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2 4267 #define regDPP_TOP1_DPP_CRC_VAL_R_G 0x0e32 4268 #define regDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX 2 4269 #define regDPP_TOP1_DPP_CRC_VAL_B_A 0x0e33 4270 #define regDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX 2 4271 #define regDPP_TOP1_DPP_CRC_CTRL 0x0e34 4272 #define regDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2 4273 #define regDPP_TOP1_HOST_READ_CONTROL 0x0e35 4274 #define regDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2 4275 4276 4277 // addressBlock: dcn_dcec_dpp2_dispdec_cnvc_cfg_dispdec 4278 // base address: 0xb58 4279 #define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0x0fa5 4280 #define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 4281 #define regCNVC_CFG2_FORMAT_CONTROL 0x0fa6 4282 #define regCNVC_CFG2_FORMAT_CONTROL_BASE_IDX 2 4283 #define regCNVC_CFG2_FCNV_FP_BIAS_R 0x0fa7 4284 #define regCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX 2 4285 #define regCNVC_CFG2_FCNV_FP_BIAS_G 0x0fa8 4286 #define regCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX 2 4287 #define regCNVC_CFG2_FCNV_FP_BIAS_B 0x0fa9 4288 #define regCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX 2 4289 #define regCNVC_CFG2_FCNV_FP_SCALE_R 0x0faa 4290 #define regCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX 2 4291 #define regCNVC_CFG2_FCNV_FP_SCALE_G 0x0fab 4292 #define regCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX 2 4293 #define regCNVC_CFG2_FCNV_FP_SCALE_B 0x0fac 4294 #define regCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX 2 4295 #define regCNVC_CFG2_COLOR_KEYER_CONTROL 0x0fad 4296 #define regCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX 2 4297 #define regCNVC_CFG2_COLOR_KEYER_ALPHA 0x0fae 4298 #define regCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX 2 4299 #define regCNVC_CFG2_COLOR_KEYER_RED 0x0faf 4300 #define regCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX 2 4301 #define regCNVC_CFG2_COLOR_KEYER_GREEN 0x0fb0 4302 #define regCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX 2 4303 #define regCNVC_CFG2_COLOR_KEYER_BLUE 0x0fb1 4304 #define regCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX 2 4305 #define regCNVC_CFG2_ALPHA_2BIT_LUT 0x0fb3 4306 #define regCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX 2 4307 #define regCNVC_CFG2_PRE_DEALPHA 0x0fb4 4308 #define regCNVC_CFG2_PRE_DEALPHA_BASE_IDX 2 4309 #define regCNVC_CFG2_PRE_CSC_MODE 0x0fb5 4310 #define regCNVC_CFG2_PRE_CSC_MODE_BASE_IDX 2 4311 #define regCNVC_CFG2_PRE_CSC_C11_C12 0x0fb6 4312 #define regCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX 2 4313 #define regCNVC_CFG2_PRE_CSC_C13_C14 0x0fb7 4314 #define regCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX 2 4315 #define regCNVC_CFG2_PRE_CSC_C21_C22 0x0fb8 4316 #define regCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX 2 4317 #define regCNVC_CFG2_PRE_CSC_C23_C24 0x0fb9 4318 #define regCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX 2 4319 #define regCNVC_CFG2_PRE_CSC_C31_C32 0x0fba 4320 #define regCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX 2 4321 #define regCNVC_CFG2_PRE_CSC_C33_C34 0x0fbb 4322 #define regCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX 2 4323 #define regCNVC_CFG2_PRE_CSC_B_C11_C12 0x0fbc 4324 #define regCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX 2 4325 #define regCNVC_CFG2_PRE_CSC_B_C13_C14 0x0fbd 4326 #define regCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX 2 4327 #define regCNVC_CFG2_PRE_CSC_B_C21_C22 0x0fbe 4328 #define regCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX 2 4329 #define regCNVC_CFG2_PRE_CSC_B_C23_C24 0x0fbf 4330 #define regCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX 2 4331 #define regCNVC_CFG2_PRE_CSC_B_C31_C32 0x0fc0 4332 #define regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX 2 4333 #define regCNVC_CFG2_PRE_CSC_B_C33_C34 0x0fc1 4334 #define regCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX 2 4335 #define regCNVC_CFG2_CNVC_COEF_FORMAT 0x0fc2 4336 #define regCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX 2 4337 #define regCNVC_CFG2_PRE_DEGAM 0x0fc3 4338 #define regCNVC_CFG2_PRE_DEGAM_BASE_IDX 2 4339 #define regCNVC_CFG2_PRE_REALPHA 0x0fc4 4340 #define regCNVC_CFG2_PRE_REALPHA_BASE_IDX 2 4341 4342 4343 // addressBlock: dcn_dcec_dpp2_dispdec_cm_cur_dispdec 4344 // base address: 0xb58 4345 #define regCM_CUR2_CURSOR0_CONTROL 0x0fc7 4346 #define regCM_CUR2_CURSOR0_CONTROL_BASE_IDX 2 4347 #define regCM_CUR2_CURSOR0_COLOR0 0x0fc8 4348 #define regCM_CUR2_CURSOR0_COLOR0_BASE_IDX 2 4349 #define regCM_CUR2_CURSOR0_COLOR1 0x0fc9 4350 #define regCM_CUR2_CURSOR0_COLOR1_BASE_IDX 2 4351 #define regCM_CUR2_CURSOR0_FP_SCALE_BIAS_G_Y 0x0fca 4352 #define regCM_CUR2_CURSOR0_FP_SCALE_BIAS_G_Y_BASE_IDX 2 4353 #define regCM_CUR2_CURSOR0_FP_SCALE_BIAS_RB_CRCB 0x0fcb 4354 #define regCM_CUR2_CURSOR0_FP_SCALE_BIAS_RB_CRCB_BASE_IDX 2 4355 #define regCM_CUR2_CUR0_MATRIX_MODE 0x0fcc 4356 #define regCM_CUR2_CUR0_MATRIX_MODE_BASE_IDX 2 4357 #define regCM_CUR2_CUR0_MATRIX_C11_C12_A 0x0fcd 4358 #define regCM_CUR2_CUR0_MATRIX_C11_C12_A_BASE_IDX 2 4359 #define regCM_CUR2_CUR0_MATRIX_C13_C14_A 0x0fce 4360 #define regCM_CUR2_CUR0_MATRIX_C13_C14_A_BASE_IDX 2 4361 #define regCM_CUR2_CUR0_MATRIX_C21_C22_A 0x0fcf 4362 #define regCM_CUR2_CUR0_MATRIX_C21_C22_A_BASE_IDX 2 4363 #define regCM_CUR2_CUR0_MATRIX_C23_C24_A 0x0fd0 4364 #define regCM_CUR2_CUR0_MATRIX_C23_C24_A_BASE_IDX 2 4365 #define regCM_CUR2_CUR0_MATRIX_C31_C32_A 0x0fd1 4366 #define regCM_CUR2_CUR0_MATRIX_C31_C32_A_BASE_IDX 2 4367 #define regCM_CUR2_CUR0_MATRIX_C33_C34_A 0x0fd2 4368 #define regCM_CUR2_CUR0_MATRIX_C33_C34_A_BASE_IDX 2 4369 #define regCM_CUR2_CUR0_MATRIX_C11_C12_B 0x0fd3 4370 #define regCM_CUR2_CUR0_MATRIX_C11_C12_B_BASE_IDX 2 4371 #define regCM_CUR2_CUR0_MATRIX_C13_C14_B 0x0fd4 4372 #define regCM_CUR2_CUR0_MATRIX_C13_C14_B_BASE_IDX 2 4373 #define regCM_CUR2_CUR0_MATRIX_C21_C22_B 0x0fd5 4374 #define regCM_CUR2_CUR0_MATRIX_C21_C22_B_BASE_IDX 2 4375 #define regCM_CUR2_CUR0_MATRIX_C23_C24_B 0x0fd6 4376 #define regCM_CUR2_CUR0_MATRIX_C23_C24_B_BASE_IDX 2 4377 #define regCM_CUR2_CUR0_MATRIX_C31_C32_B 0x0fd7 4378 #define regCM_CUR2_CUR0_MATRIX_C31_C32_B_BASE_IDX 2 4379 #define regCM_CUR2_CUR0_MATRIX_C33_C34_B 0x0fd8 4380 #define regCM_CUR2_CUR0_MATRIX_C33_C34_B_BASE_IDX 2 4381 4382 4383 // addressBlock: dcn_dcec_dpp2_dispdec_dscl_dispdec 4384 // base address: 0xb58 4385 #define regDSCL2_SCL_COEF_RAM_TAP_SELECT 0x0fdc 4386 #define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 4387 #define regDSCL2_SCL_COEF_RAM_TAP_DATA 0x0fdd 4388 #define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 4389 #define regDSCL2_SCL_MODE 0x0fde 4390 #define regDSCL2_SCL_MODE_BASE_IDX 2 4391 #define regDSCL2_SCL_TAP_CONTROL 0x0fdf 4392 #define regDSCL2_SCL_TAP_CONTROL_BASE_IDX 2 4393 #define regDSCL2_DSCL_CONTROL 0x0fe0 4394 #define regDSCL2_DSCL_CONTROL_BASE_IDX 2 4395 #define regDSCL2_DSCL_2TAP_CONTROL 0x0fe1 4396 #define regDSCL2_DSCL_2TAP_CONTROL_BASE_IDX 2 4397 #define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0fe2 4398 #define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 4399 #define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0fe3 4400 #define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 4401 #define regDSCL2_SCL_HORZ_FILTER_INIT 0x0fe4 4402 #define regDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2 4403 #define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0fe5 4404 #define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 4405 #define regDSCL2_SCL_HORZ_FILTER_INIT_C 0x0fe6 4406 #define regDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 4407 #define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0fe7 4408 #define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 4409 #define regDSCL2_SCL_VERT_FILTER_INIT 0x0fe8 4410 #define regDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2 4411 #define regDSCL2_SCL_VERT_FILTER_INIT_BOT 0x0fe9 4412 #define regDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 4413 #define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0x0fea 4414 #define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 4415 #define regDSCL2_SCL_VERT_FILTER_INIT_C 0x0feb 4416 #define regDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 4417 #define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0x0fec 4418 #define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 4419 #define regDSCL2_SCL_BLACK_COLOR 0x0fed 4420 #define regDSCL2_SCL_BLACK_COLOR_BASE_IDX 2 4421 #define regDSCL2_DSCL_UPDATE 0x0fee 4422 #define regDSCL2_DSCL_UPDATE_BASE_IDX 2 4423 #define regDSCL2_DSCL_AUTOCAL 0x0fef 4424 #define regDSCL2_DSCL_AUTOCAL_BASE_IDX 2 4425 #define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0ff0 4426 #define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 4427 #define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0ff1 4428 #define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 4429 #define regDSCL2_OTG_H_BLANK 0x0ff2 4430 #define regDSCL2_OTG_H_BLANK_BASE_IDX 2 4431 #define regDSCL2_OTG_V_BLANK 0x0ff3 4432 #define regDSCL2_OTG_V_BLANK_BASE_IDX 2 4433 #define regDSCL2_RECOUT_START 0x0ff4 4434 #define regDSCL2_RECOUT_START_BASE_IDX 2 4435 #define regDSCL2_RECOUT_SIZE 0x0ff5 4436 #define regDSCL2_RECOUT_SIZE_BASE_IDX 2 4437 #define regDSCL2_MPC_SIZE 0x0ff6 4438 #define regDSCL2_MPC_SIZE_BASE_IDX 2 4439 #define regDSCL2_LB_DATA_FORMAT 0x0ff7 4440 #define regDSCL2_LB_DATA_FORMAT_BASE_IDX 2 4441 #define regDSCL2_LB_MEMORY_CTRL 0x0ff8 4442 #define regDSCL2_LB_MEMORY_CTRL_BASE_IDX 2 4443 #define regDSCL2_LB_V_COUNTER 0x0ff9 4444 #define regDSCL2_LB_V_COUNTER_BASE_IDX 2 4445 #define regDSCL2_DSCL_MEM_PWR_CTRL 0x0ffa 4446 #define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX 2 4447 #define regDSCL2_DSCL_MEM_PWR_STATUS 0x0ffb 4448 #define regDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 2 4449 #define regDSCL2_OBUF_CONTROL 0x0ffc 4450 #define regDSCL2_OBUF_CONTROL_BASE_IDX 2 4451 #define regDSCL2_OBUF_MEM_PWR_CTRL 0x0ffd 4452 #define regDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX 2 4453 #define regDSCL2_DSCL_EASF_H_MODE 0x0ffe 4454 #define regDSCL2_DSCL_EASF_H_MODE_BASE_IDX 2 4455 #define regDSCL2_DSCL_EASF_V_MODE 0x0fff 4456 #define regDSCL2_DSCL_EASF_V_MODE_BASE_IDX 2 4457 #define regDSCL2_DSCL_SC_MODE 0x1000 4458 #define regDSCL2_DSCL_SC_MODE_BASE_IDX 2 4459 #define regDSCL2_DSCL_SC_MATRIX_C0C1 0x1001 4460 #define regDSCL2_DSCL_SC_MATRIX_C0C1_BASE_IDX 2 4461 #define regDSCL2_DSCL_SC_MATRIX_C2C3 0x1002 4462 #define regDSCL2_DSCL_SC_MATRIX_C2C3_BASE_IDX 2 4463 #define regDSCL2_DSCL_EASF_H_RINGEST_EVENTAP_GAIN 0x1003 4464 #define regDSCL2_DSCL_EASF_H_RINGEST_EVENTAP_GAIN_BASE_IDX 2 4465 #define regDSCL2_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE 0x1004 4466 #define regDSCL2_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE_BASE_IDX 2 4467 #define regDSCL2_DSCL_EASF_V_RINGEST_EVENTAP_GAIN 0x1005 4468 #define regDSCL2_DSCL_EASF_V_RINGEST_EVENTAP_GAIN_BASE_IDX 2 4469 #define regDSCL2_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE 0x1006 4470 #define regDSCL2_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE_BASE_IDX 2 4471 #define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL1 0x1007 4472 #define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL1_BASE_IDX 2 4473 #define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL2 0x1008 4474 #define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL2_BASE_IDX 2 4475 #define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL3 0x1009 4476 #define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL3_BASE_IDX 2 4477 #define regDSCL2_DSCL_EASF_RINGEST_FORCE 0x100a 4478 #define regDSCL2_DSCL_EASF_RINGEST_FORCE_BASE_IDX 2 4479 #define regDSCL2_DSCL_EASF_H_BF_CNTL 0x100b 4480 #define regDSCL2_DSCL_EASF_H_BF_CNTL_BASE_IDX 2 4481 #define regDSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN 0x100c 4482 #define regDSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN_BASE_IDX 2 4483 #define regDSCL2_DSCL_EASF_V_BF_CNTL 0x100d 4484 #define regDSCL2_DSCL_EASF_V_BF_CNTL_BASE_IDX 2 4485 #define regDSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN 0x100e 4486 #define regDSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN_BASE_IDX 2 4487 #define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG0 0x100f 4488 #define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG0_BASE_IDX 2 4489 #define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG1 0x1010 4490 #define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG1_BASE_IDX 2 4491 #define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG2 0x1011 4492 #define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG2_BASE_IDX 2 4493 #define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG3 0x1012 4494 #define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG3_BASE_IDX 2 4495 #define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG4 0x1013 4496 #define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG4_BASE_IDX 2 4497 #define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG5 0x1014 4498 #define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG5_BASE_IDX 2 4499 #define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG6 0x1015 4500 #define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG6_BASE_IDX 2 4501 #define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG7 0x1016 4502 #define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG7_BASE_IDX 2 4503 #define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG0 0x1017 4504 #define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG0_BASE_IDX 2 4505 #define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG1 0x1018 4506 #define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG1_BASE_IDX 2 4507 #define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG2 0x1019 4508 #define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG2_BASE_IDX 2 4509 #define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG3 0x101a 4510 #define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG3_BASE_IDX 2 4511 #define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG4 0x101b 4512 #define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG4_BASE_IDX 2 4513 #define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG5 0x101c 4514 #define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG5_BASE_IDX 2 4515 #define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG6 0x101d 4516 #define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG6_BASE_IDX 2 4517 #define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG7 0x101e 4518 #define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG7_BASE_IDX 2 4519 #define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG0 0x101f 4520 #define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG0_BASE_IDX 2 4521 #define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG1 0x1020 4522 #define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG1_BASE_IDX 2 4523 #define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG2 0x1021 4524 #define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG2_BASE_IDX 2 4525 #define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG3 0x1022 4526 #define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG3_BASE_IDX 2 4527 #define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG4 0x1023 4528 #define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG4_BASE_IDX 2 4529 #define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG5 0x1024 4530 #define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG5_BASE_IDX 2 4531 #define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG0 0x1025 4532 #define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG0_BASE_IDX 2 4533 #define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG1 0x1026 4534 #define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG1_BASE_IDX 2 4535 #define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG2 0x1027 4536 #define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG2_BASE_IDX 2 4537 #define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG3 0x1028 4538 #define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG3_BASE_IDX 2 4539 #define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG4 0x1029 4540 #define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG4_BASE_IDX 2 4541 #define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG5 0x102a 4542 #define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG5_BASE_IDX 2 4543 #define regDSCL2_ISHARP_MODE 0x102b 4544 #define regDSCL2_ISHARP_MODE_BASE_IDX 2 4545 #define regDSCL2_ISHARP_DELTA_CTRL 0x102c 4546 #define regDSCL2_ISHARP_DELTA_CTRL_BASE_IDX 2 4547 #define regDSCL2_ISHARP_DELTA_INDEX 0x102d 4548 #define regDSCL2_ISHARP_DELTA_INDEX_BASE_IDX 2 4549 #define regDSCL2_ISHARP_DELTA_DATA 0x102e 4550 #define regDSCL2_ISHARP_DELTA_DATA_BASE_IDX 2 4551 #define regDSCL2_ISHARP_NLDELTA_SOFT_CLIP 0x102f 4552 #define regDSCL2_ISHARP_NLDELTA_SOFT_CLIP_BASE_IDX 2 4553 #define regDSCL2_ISHARP_NOISEDET_THRESHOLD 0x1030 4554 #define regDSCL2_ISHARP_NOISEDET_THRESHOLD_BASE_IDX 2 4555 #define regDSCL2_ISHARP_NOISE_GAIN_PWL 0x1031 4556 #define regDSCL2_ISHARP_NOISE_GAIN_PWL_BASE_IDX 2 4557 #define regDSCL2_ISHARP_LBA_PWL_SEG0 0x1032 4558 #define regDSCL2_ISHARP_LBA_PWL_SEG0_BASE_IDX 2 4559 #define regDSCL2_ISHARP_LBA_PWL_SEG1 0x1033 4560 #define regDSCL2_ISHARP_LBA_PWL_SEG1_BASE_IDX 2 4561 #define regDSCL2_ISHARP_LBA_PWL_SEG2 0x1034 4562 #define regDSCL2_ISHARP_LBA_PWL_SEG2_BASE_IDX 2 4563 #define regDSCL2_ISHARP_LBA_PWL_SEG3 0x1035 4564 #define regDSCL2_ISHARP_LBA_PWL_SEG3_BASE_IDX 2 4565 #define regDSCL2_ISHARP_LBA_PWL_SEG4 0x1036 4566 #define regDSCL2_ISHARP_LBA_PWL_SEG4_BASE_IDX 2 4567 #define regDSCL2_ISHARP_LBA_PWL_SEG5 0x1037 4568 #define regDSCL2_ISHARP_LBA_PWL_SEG5_BASE_IDX 2 4569 #define regDSCL2_ISHARP_DELTA_LUT_MEM_PWR_CTRL 0x1038 4570 #define regDSCL2_ISHARP_DELTA_LUT_MEM_PWR_CTRL_BASE_IDX 2 4571 4572 4573 // addressBlock: dcn_dcec_dpp2_dispdec_cm_dispdec 4574 // base address: 0xb58 4575 #define regCM2_CM_CONTROL 0x103d 4576 #define regCM2_CM_CONTROL_BASE_IDX 2 4577 #define regCM2_CM_POST_CSC_CONTROL 0x103e 4578 #define regCM2_CM_POST_CSC_CONTROL_BASE_IDX 2 4579 #define regCM2_CM_POST_CSC_C11_C12 0x103f 4580 #define regCM2_CM_POST_CSC_C11_C12_BASE_IDX 2 4581 #define regCM2_CM_POST_CSC_C13_C14 0x1040 4582 #define regCM2_CM_POST_CSC_C13_C14_BASE_IDX 2 4583 #define regCM2_CM_POST_CSC_C21_C22 0x1041 4584 #define regCM2_CM_POST_CSC_C21_C22_BASE_IDX 2 4585 #define regCM2_CM_POST_CSC_C23_C24 0x1042 4586 #define regCM2_CM_POST_CSC_C23_C24_BASE_IDX 2 4587 #define regCM2_CM_POST_CSC_C31_C32 0x1043 4588 #define regCM2_CM_POST_CSC_C31_C32_BASE_IDX 2 4589 #define regCM2_CM_POST_CSC_C33_C34 0x1044 4590 #define regCM2_CM_POST_CSC_C33_C34_BASE_IDX 2 4591 #define regCM2_CM_POST_CSC_B_C11_C12 0x1045 4592 #define regCM2_CM_POST_CSC_B_C11_C12_BASE_IDX 2 4593 #define regCM2_CM_POST_CSC_B_C13_C14 0x1046 4594 #define regCM2_CM_POST_CSC_B_C13_C14_BASE_IDX 2 4595 #define regCM2_CM_POST_CSC_B_C21_C22 0x1047 4596 #define regCM2_CM_POST_CSC_B_C21_C22_BASE_IDX 2 4597 #define regCM2_CM_POST_CSC_B_C23_C24 0x1048 4598 #define regCM2_CM_POST_CSC_B_C23_C24_BASE_IDX 2 4599 #define regCM2_CM_POST_CSC_B_C31_C32 0x1049 4600 #define regCM2_CM_POST_CSC_B_C31_C32_BASE_IDX 2 4601 #define regCM2_CM_POST_CSC_B_C33_C34 0x104a 4602 #define regCM2_CM_POST_CSC_B_C33_C34_BASE_IDX 2 4603 #define regCM2_CM_BIAS_CR_R 0x104b 4604 #define regCM2_CM_BIAS_CR_R_BASE_IDX 2 4605 #define regCM2_CM_BIAS_Y_G_CB_B 0x104c 4606 #define regCM2_CM_BIAS_Y_G_CB_B_BASE_IDX 2 4607 #define regCM2_CM_GAMCOR_CONTROL 0x104d 4608 #define regCM2_CM_GAMCOR_CONTROL_BASE_IDX 2 4609 #define regCM2_CM_GAMCOR_LUT_INDEX 0x104e 4610 #define regCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 4611 #define regCM2_CM_GAMCOR_LUT_DATA 0x104f 4612 #define regCM2_CM_GAMCOR_LUT_DATA_BASE_IDX 2 4613 #define regCM2_CM_GAMCOR_LUT_CONTROL 0x1050 4614 #define regCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 4615 #define regCM2_CM_GAMCOR_RAMA_START_CNTL_B 0x1051 4616 #define regCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 4617 #define regCM2_CM_GAMCOR_RAMA_START_CNTL_G 0x1052 4618 #define regCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 4619 #define regCM2_CM_GAMCOR_RAMA_START_CNTL_R 0x1053 4620 #define regCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 4621 #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x1054 4622 #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 4623 #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x1055 4624 #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 4625 #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x1056 4626 #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 4627 #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x1057 4628 #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 4629 #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x1058 4630 #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 4631 #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x1059 4632 #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 4633 #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B 0x105a 4634 #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 4635 #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B 0x105b 4636 #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 4637 #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G 0x105c 4638 #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 4639 #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G 0x105d 4640 #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 4641 #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R 0x105e 4642 #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 4643 #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R 0x105f 4644 #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 4645 #define regCM2_CM_GAMCOR_RAMA_OFFSET_B 0x1060 4646 #define regCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 4647 #define regCM2_CM_GAMCOR_RAMA_OFFSET_G 0x1061 4648 #define regCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 4649 #define regCM2_CM_GAMCOR_RAMA_OFFSET_R 0x1062 4650 #define regCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 4651 #define regCM2_CM_GAMCOR_RAMA_REGION_0_1 0x1063 4652 #define regCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 4653 #define regCM2_CM_GAMCOR_RAMA_REGION_2_3 0x1064 4654 #define regCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 4655 #define regCM2_CM_GAMCOR_RAMA_REGION_4_5 0x1065 4656 #define regCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 4657 #define regCM2_CM_GAMCOR_RAMA_REGION_6_7 0x1066 4658 #define regCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 4659 #define regCM2_CM_GAMCOR_RAMA_REGION_8_9 0x1067 4660 #define regCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 4661 #define regCM2_CM_GAMCOR_RAMA_REGION_10_11 0x1068 4662 #define regCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 4663 #define regCM2_CM_GAMCOR_RAMA_REGION_12_13 0x1069 4664 #define regCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 4665 #define regCM2_CM_GAMCOR_RAMA_REGION_14_15 0x106a 4666 #define regCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 4667 #define regCM2_CM_GAMCOR_RAMA_REGION_16_17 0x106b 4668 #define regCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 4669 #define regCM2_CM_GAMCOR_RAMA_REGION_18_19 0x106c 4670 #define regCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 4671 #define regCM2_CM_GAMCOR_RAMA_REGION_20_21 0x106d 4672 #define regCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 4673 #define regCM2_CM_GAMCOR_RAMA_REGION_22_23 0x106e 4674 #define regCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 4675 #define regCM2_CM_GAMCOR_RAMA_REGION_24_25 0x106f 4676 #define regCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 4677 #define regCM2_CM_GAMCOR_RAMA_REGION_26_27 0x1070 4678 #define regCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 4679 #define regCM2_CM_GAMCOR_RAMA_REGION_28_29 0x1071 4680 #define regCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 4681 #define regCM2_CM_GAMCOR_RAMA_REGION_30_31 0x1072 4682 #define regCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 4683 #define regCM2_CM_GAMCOR_RAMA_REGION_32_33 0x1073 4684 #define regCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 4685 #define regCM2_CM_GAMCOR_RAMB_START_CNTL_B 0x1074 4686 #define regCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 4687 #define regCM2_CM_GAMCOR_RAMB_START_CNTL_G 0x1075 4688 #define regCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 4689 #define regCM2_CM_GAMCOR_RAMB_START_CNTL_R 0x1076 4690 #define regCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 4691 #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x1077 4692 #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 4693 #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x1078 4694 #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 4695 #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x1079 4696 #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 4697 #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x107a 4698 #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 4699 #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x107b 4700 #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 4701 #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x107c 4702 #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 4703 #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B 0x107d 4704 #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 4705 #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B 0x107e 4706 #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 4707 #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G 0x107f 4708 #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 4709 #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G 0x1080 4710 #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 4711 #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R 0x1081 4712 #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 4713 #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R 0x1082 4714 #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 4715 #define regCM2_CM_GAMCOR_RAMB_OFFSET_B 0x1083 4716 #define regCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 4717 #define regCM2_CM_GAMCOR_RAMB_OFFSET_G 0x1084 4718 #define regCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 4719 #define regCM2_CM_GAMCOR_RAMB_OFFSET_R 0x1085 4720 #define regCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 4721 #define regCM2_CM_GAMCOR_RAMB_REGION_0_1 0x1086 4722 #define regCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 4723 #define regCM2_CM_GAMCOR_RAMB_REGION_2_3 0x1087 4724 #define regCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 4725 #define regCM2_CM_GAMCOR_RAMB_REGION_4_5 0x1088 4726 #define regCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 4727 #define regCM2_CM_GAMCOR_RAMB_REGION_6_7 0x1089 4728 #define regCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 4729 #define regCM2_CM_GAMCOR_RAMB_REGION_8_9 0x108a 4730 #define regCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 4731 #define regCM2_CM_GAMCOR_RAMB_REGION_10_11 0x108b 4732 #define regCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 4733 #define regCM2_CM_GAMCOR_RAMB_REGION_12_13 0x108c 4734 #define regCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 4735 #define regCM2_CM_GAMCOR_RAMB_REGION_14_15 0x108d 4736 #define regCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 4737 #define regCM2_CM_GAMCOR_RAMB_REGION_16_17 0x108e 4738 #define regCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 4739 #define regCM2_CM_GAMCOR_RAMB_REGION_18_19 0x108f 4740 #define regCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 4741 #define regCM2_CM_GAMCOR_RAMB_REGION_20_21 0x1090 4742 #define regCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 4743 #define regCM2_CM_GAMCOR_RAMB_REGION_22_23 0x1091 4744 #define regCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 4745 #define regCM2_CM_GAMCOR_RAMB_REGION_24_25 0x1092 4746 #define regCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 4747 #define regCM2_CM_GAMCOR_RAMB_REGION_26_27 0x1093 4748 #define regCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 4749 #define regCM2_CM_GAMCOR_RAMB_REGION_28_29 0x1094 4750 #define regCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 4751 #define regCM2_CM_GAMCOR_RAMB_REGION_30_31 0x1095 4752 #define regCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 4753 #define regCM2_CM_GAMCOR_RAMB_REGION_32_33 0x1096 4754 #define regCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 4755 #define regCM2_CM_HDR_MULT_COEF 0x1097 4756 #define regCM2_CM_HDR_MULT_COEF_BASE_IDX 2 4757 #define regCM2_CM_MEM_PWR_CTRL 0x1098 4758 #define regCM2_CM_MEM_PWR_CTRL_BASE_IDX 2 4759 #define regCM2_CM_MEM_PWR_STATUS 0x1099 4760 #define regCM2_CM_MEM_PWR_STATUS_BASE_IDX 2 4761 #define regCM2_CM_DEALPHA 0x109b 4762 #define regCM2_CM_DEALPHA_BASE_IDX 2 4763 #define regCM2_CM_COEF_FORMAT 0x109c 4764 #define regCM2_CM_COEF_FORMAT_BASE_IDX 2 4765 #define regCM2_CM_TEST_DEBUG_INDEX 0x109d 4766 #define regCM2_CM_TEST_DEBUG_INDEX_BASE_IDX 2 4767 #define regCM2_CM_TEST_DEBUG_DATA 0x109e 4768 #define regCM2_CM_TEST_DEBUG_DATA_BASE_IDX 2 4769 4770 4771 // addressBlock: dcn_dcec_dpp2_dispdec_dpp_top_dispdec 4772 // base address: 0xb58 4773 #define regDPP_TOP2_DPP_CONTROL 0x0f9b 4774 #define regDPP_TOP2_DPP_CONTROL_BASE_IDX 2 4775 #define regDPP_TOP2_DPP_SOFT_RESET 0x0f9c 4776 #define regDPP_TOP2_DPP_SOFT_RESET_BASE_IDX 2 4777 #define regDPP_TOP2_DPP_CRC_VAL_R_G 0x0f9d 4778 #define regDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX 2 4779 #define regDPP_TOP2_DPP_CRC_VAL_B_A 0x0f9e 4780 #define regDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX 2 4781 #define regDPP_TOP2_DPP_CRC_CTRL 0x0f9f 4782 #define regDPP_TOP2_DPP_CRC_CTRL_BASE_IDX 2 4783 #define regDPP_TOP2_HOST_READ_CONTROL 0x0fa0 4784 #define regDPP_TOP2_HOST_READ_CONTROL_BASE_IDX 2 4785 4786 // addressBlock: dcn_dcec_dpp3_dispdec_cnvc_cfg_dispdec 4787 // base address: 0x1104 4788 #define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0x1110 4789 #define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 4790 #define regCNVC_CFG3_FORMAT_CONTROL 0x1111 4791 #define regCNVC_CFG3_FORMAT_CONTROL_BASE_IDX 2 4792 #define regCNVC_CFG3_FCNV_FP_BIAS_R 0x1112 4793 #define regCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX 2 4794 #define regCNVC_CFG3_FCNV_FP_BIAS_G 0x1113 4795 #define regCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX 2 4796 #define regCNVC_CFG3_FCNV_FP_BIAS_B 0x1114 4797 #define regCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX 2 4798 #define regCNVC_CFG3_FCNV_FP_SCALE_R 0x1115 4799 #define regCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX 2 4800 #define regCNVC_CFG3_FCNV_FP_SCALE_G 0x1116 4801 #define regCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX 2 4802 #define regCNVC_CFG3_FCNV_FP_SCALE_B 0x1117 4803 #define regCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX 2 4804 #define regCNVC_CFG3_COLOR_KEYER_CONTROL 0x1118 4805 #define regCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX 2 4806 #define regCNVC_CFG3_COLOR_KEYER_ALPHA 0x1119 4807 #define regCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX 2 4808 #define regCNVC_CFG3_COLOR_KEYER_RED 0x111a 4809 #define regCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX 2 4810 #define regCNVC_CFG3_COLOR_KEYER_GREEN 0x111b 4811 #define regCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX 2 4812 #define regCNVC_CFG3_COLOR_KEYER_BLUE 0x111c 4813 #define regCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX 2 4814 #define regCNVC_CFG3_ALPHA_2BIT_LUT 0x111e 4815 #define regCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX 2 4816 #define regCNVC_CFG3_PRE_DEALPHA 0x111f 4817 #define regCNVC_CFG3_PRE_DEALPHA_BASE_IDX 2 4818 #define regCNVC_CFG3_PRE_CSC_MODE 0x1120 4819 #define regCNVC_CFG3_PRE_CSC_MODE_BASE_IDX 2 4820 #define regCNVC_CFG3_PRE_CSC_C11_C12 0x1121 4821 #define regCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX 2 4822 #define regCNVC_CFG3_PRE_CSC_C13_C14 0x1122 4823 #define regCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX 2 4824 #define regCNVC_CFG3_PRE_CSC_C21_C22 0x1123 4825 #define regCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX 2 4826 #define regCNVC_CFG3_PRE_CSC_C23_C24 0x1124 4827 #define regCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX 2 4828 #define regCNVC_CFG3_PRE_CSC_C31_C32 0x1125 4829 #define regCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX 2 4830 #define regCNVC_CFG3_PRE_CSC_C33_C34 0x1126 4831 #define regCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX 2 4832 #define regCNVC_CFG3_PRE_CSC_B_C11_C12 0x1127 4833 #define regCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX 2 4834 #define regCNVC_CFG3_PRE_CSC_B_C13_C14 0x1128 4835 #define regCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX 2 4836 #define regCNVC_CFG3_PRE_CSC_B_C21_C22 0x1129 4837 #define regCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX 2 4838 #define regCNVC_CFG3_PRE_CSC_B_C23_C24 0x112a 4839 #define regCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX 2 4840 #define regCNVC_CFG3_PRE_CSC_B_C31_C32 0x112b 4841 #define regCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX 2 4842 #define regCNVC_CFG3_PRE_CSC_B_C33_C34 0x112c 4843 #define regCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX 2 4844 #define regCNVC_CFG3_CNVC_COEF_FORMAT 0x112d 4845 #define regCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX 2 4846 #define regCNVC_CFG3_PRE_DEGAM 0x112e 4847 #define regCNVC_CFG3_PRE_DEGAM_BASE_IDX 2 4848 #define regCNVC_CFG3_PRE_REALPHA 0x112f 4849 #define regCNVC_CFG3_PRE_REALPHA_BASE_IDX 2 4850 4851 4852 // addressBlock: dcn_dcec_dpp3_dispdec_cm_cur_dispdec 4853 // base address: 0x1104 4854 #define regCM_CUR3_CURSOR0_CONTROL 0x1132 4855 #define regCM_CUR3_CURSOR0_CONTROL_BASE_IDX 2 4856 #define regCM_CUR3_CURSOR0_COLOR0 0x1133 4857 #define regCM_CUR3_CURSOR0_COLOR0_BASE_IDX 2 4858 #define regCM_CUR3_CURSOR0_COLOR1 0x1134 4859 #define regCM_CUR3_CURSOR0_COLOR1_BASE_IDX 2 4860 #define regCM_CUR3_CURSOR0_FP_SCALE_BIAS_G_Y 0x1135 4861 #define regCM_CUR3_CURSOR0_FP_SCALE_BIAS_G_Y_BASE_IDX 2 4862 #define regCM_CUR3_CURSOR0_FP_SCALE_BIAS_RB_CRCB 0x1136 4863 #define regCM_CUR3_CURSOR0_FP_SCALE_BIAS_RB_CRCB_BASE_IDX 2 4864 #define regCM_CUR3_CUR0_MATRIX_MODE 0x1137 4865 #define regCM_CUR3_CUR0_MATRIX_MODE_BASE_IDX 2 4866 #define regCM_CUR3_CUR0_MATRIX_C11_C12_A 0x1138 4867 #define regCM_CUR3_CUR0_MATRIX_C11_C12_A_BASE_IDX 2 4868 #define regCM_CUR3_CUR0_MATRIX_C13_C14_A 0x1139 4869 #define regCM_CUR3_CUR0_MATRIX_C13_C14_A_BASE_IDX 2 4870 #define regCM_CUR3_CUR0_MATRIX_C21_C22_A 0x113a 4871 #define regCM_CUR3_CUR0_MATRIX_C21_C22_A_BASE_IDX 2 4872 #define regCM_CUR3_CUR0_MATRIX_C23_C24_A 0x113b 4873 #define regCM_CUR3_CUR0_MATRIX_C23_C24_A_BASE_IDX 2 4874 #define regCM_CUR3_CUR0_MATRIX_C31_C32_A 0x113c 4875 #define regCM_CUR3_CUR0_MATRIX_C31_C32_A_BASE_IDX 2 4876 #define regCM_CUR3_CUR0_MATRIX_C33_C34_A 0x113d 4877 #define regCM_CUR3_CUR0_MATRIX_C33_C34_A_BASE_IDX 2 4878 #define regCM_CUR3_CUR0_MATRIX_C11_C12_B 0x113e 4879 #define regCM_CUR3_CUR0_MATRIX_C11_C12_B_BASE_IDX 2 4880 #define regCM_CUR3_CUR0_MATRIX_C13_C14_B 0x113f 4881 #define regCM_CUR3_CUR0_MATRIX_C13_C14_B_BASE_IDX 2 4882 #define regCM_CUR3_CUR0_MATRIX_C21_C22_B 0x1140 4883 #define regCM_CUR3_CUR0_MATRIX_C21_C22_B_BASE_IDX 2 4884 #define regCM_CUR3_CUR0_MATRIX_C23_C24_B 0x1141 4885 #define regCM_CUR3_CUR0_MATRIX_C23_C24_B_BASE_IDX 2 4886 #define regCM_CUR3_CUR0_MATRIX_C31_C32_B 0x1142 4887 #define regCM_CUR3_CUR0_MATRIX_C31_C32_B_BASE_IDX 2 4888 #define regCM_CUR3_CUR0_MATRIX_C33_C34_B 0x1143 4889 #define regCM_CUR3_CUR0_MATRIX_C33_C34_B_BASE_IDX 2 4890 4891 4892 // addressBlock: dcn_dcec_dpp3_dispdec_dscl_dispdec 4893 // base address: 0x1104 4894 #define regDSCL3_SCL_COEF_RAM_TAP_SELECT 0x1147 4895 #define regDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 4896 #define regDSCL3_SCL_COEF_RAM_TAP_DATA 0x1148 4897 #define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 4898 #define regDSCL3_SCL_MODE 0x1149 4899 #define regDSCL3_SCL_MODE_BASE_IDX 2 4900 #define regDSCL3_SCL_TAP_CONTROL 0x114a 4901 #define regDSCL3_SCL_TAP_CONTROL_BASE_IDX 2 4902 #define regDSCL3_DSCL_CONTROL 0x114b 4903 #define regDSCL3_DSCL_CONTROL_BASE_IDX 2 4904 #define regDSCL3_DSCL_2TAP_CONTROL 0x114c 4905 #define regDSCL3_DSCL_2TAP_CONTROL_BASE_IDX 2 4906 #define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x114d 4907 #define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 4908 #define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x114e 4909 #define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 4910 #define regDSCL3_SCL_HORZ_FILTER_INIT 0x114f 4911 #define regDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2 4912 #define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0x1150 4913 #define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 4914 #define regDSCL3_SCL_HORZ_FILTER_INIT_C 0x1151 4915 #define regDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 4916 #define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x1152 4917 #define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 4918 #define regDSCL3_SCL_VERT_FILTER_INIT 0x1153 4919 #define regDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2 4920 #define regDSCL3_SCL_VERT_FILTER_INIT_BOT 0x1154 4921 #define regDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 4922 #define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0x1155 4923 #define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 4924 #define regDSCL3_SCL_VERT_FILTER_INIT_C 0x1156 4925 #define regDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 4926 #define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0x1157 4927 #define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 4928 #define regDSCL3_SCL_BLACK_COLOR 0x1158 4929 #define regDSCL3_SCL_BLACK_COLOR_BASE_IDX 2 4930 #define regDSCL3_DSCL_UPDATE 0x1159 4931 #define regDSCL3_DSCL_UPDATE_BASE_IDX 2 4932 #define regDSCL3_DSCL_AUTOCAL 0x115a 4933 #define regDSCL3_DSCL_AUTOCAL_BASE_IDX 2 4934 #define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x115b 4935 #define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 4936 #define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x115c 4937 #define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 4938 #define regDSCL3_OTG_H_BLANK 0x115d 4939 #define regDSCL3_OTG_H_BLANK_BASE_IDX 2 4940 #define regDSCL3_OTG_V_BLANK 0x115e 4941 #define regDSCL3_OTG_V_BLANK_BASE_IDX 2 4942 #define regDSCL3_RECOUT_START 0x115f 4943 #define regDSCL3_RECOUT_START_BASE_IDX 2 4944 #define regDSCL3_RECOUT_SIZE 0x1160 4945 #define regDSCL3_RECOUT_SIZE_BASE_IDX 2 4946 #define regDSCL3_MPC_SIZE 0x1161 4947 #define regDSCL3_MPC_SIZE_BASE_IDX 2 4948 #define regDSCL3_LB_DATA_FORMAT 0x1162 4949 #define regDSCL3_LB_DATA_FORMAT_BASE_IDX 2 4950 #define regDSCL3_LB_MEMORY_CTRL 0x1163 4951 #define regDSCL3_LB_MEMORY_CTRL_BASE_IDX 2 4952 #define regDSCL3_LB_V_COUNTER 0x1164 4953 #define regDSCL3_LB_V_COUNTER_BASE_IDX 2 4954 #define regDSCL3_DSCL_MEM_PWR_CTRL 0x1165 4955 #define regDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX 2 4956 #define regDSCL3_DSCL_MEM_PWR_STATUS 0x1166 4957 #define regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 2 4958 #define regDSCL3_OBUF_CONTROL 0x1167 4959 #define regDSCL3_OBUF_CONTROL_BASE_IDX 2 4960 #define regDSCL3_OBUF_MEM_PWR_CTRL 0x1168 4961 #define regDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX 2 4962 #define regDSCL3_DSCL_EASF_H_MODE 0x1169 4963 #define regDSCL3_DSCL_EASF_H_MODE_BASE_IDX 2 4964 #define regDSCL3_DSCL_EASF_V_MODE 0x116a 4965 #define regDSCL3_DSCL_EASF_V_MODE_BASE_IDX 2 4966 #define regDSCL3_DSCL_SC_MODE 0x116b 4967 #define regDSCL3_DSCL_SC_MODE_BASE_IDX 2 4968 #define regDSCL3_DSCL_SC_MATRIX_C0C1 0x116c 4969 #define regDSCL3_DSCL_SC_MATRIX_C0C1_BASE_IDX 2 4970 #define regDSCL3_DSCL_SC_MATRIX_C2C3 0x116d 4971 #define regDSCL3_DSCL_SC_MATRIX_C2C3_BASE_IDX 2 4972 #define regDSCL3_DSCL_EASF_H_RINGEST_EVENTAP_GAIN 0x116e 4973 #define regDSCL3_DSCL_EASF_H_RINGEST_EVENTAP_GAIN_BASE_IDX 2 4974 #define regDSCL3_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE 0x116f 4975 #define regDSCL3_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE_BASE_IDX 2 4976 #define regDSCL3_DSCL_EASF_V_RINGEST_EVENTAP_GAIN 0x1170 4977 #define regDSCL3_DSCL_EASF_V_RINGEST_EVENTAP_GAIN_BASE_IDX 2 4978 #define regDSCL3_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE 0x1171 4979 #define regDSCL3_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE_BASE_IDX 2 4980 #define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL1 0x1172 4981 #define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL1_BASE_IDX 2 4982 #define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL2 0x1173 4983 #define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL2_BASE_IDX 2 4984 #define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL3 0x1174 4985 #define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL3_BASE_IDX 2 4986 #define regDSCL3_DSCL_EASF_RINGEST_FORCE 0x1175 4987 #define regDSCL3_DSCL_EASF_RINGEST_FORCE_BASE_IDX 2 4988 #define regDSCL3_DSCL_EASF_H_BF_CNTL 0x1176 4989 #define regDSCL3_DSCL_EASF_H_BF_CNTL_BASE_IDX 2 4990 #define regDSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN 0x1177 4991 #define regDSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN_BASE_IDX 2 4992 #define regDSCL3_DSCL_EASF_V_BF_CNTL 0x1178 4993 #define regDSCL3_DSCL_EASF_V_BF_CNTL_BASE_IDX 2 4994 #define regDSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN 0x1179 4995 #define regDSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN_BASE_IDX 2 4996 #define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG0 0x117a 4997 #define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG0_BASE_IDX 2 4998 #define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG1 0x117b 4999 #define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG1_BASE_IDX 2 5000 #define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG2 0x117c 5001 #define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG2_BASE_IDX 2 5002 #define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG3 0x117d 5003 #define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG3_BASE_IDX 2 5004 #define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG4 0x117e 5005 #define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG4_BASE_IDX 2 5006 #define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG5 0x117f 5007 #define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG5_BASE_IDX 2 5008 #define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG6 0x1180 5009 #define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG6_BASE_IDX 2 5010 #define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG7 0x1181 5011 #define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG7_BASE_IDX 2 5012 #define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG0 0x1182 5013 #define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG0_BASE_IDX 2 5014 #define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG1 0x1183 5015 #define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG1_BASE_IDX 2 5016 #define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG2 0x1184 5017 #define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG2_BASE_IDX 2 5018 #define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG3 0x1185 5019 #define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG3_BASE_IDX 2 5020 #define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG4 0x1186 5021 #define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG4_BASE_IDX 2 5022 #define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG5 0x1187 5023 #define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG5_BASE_IDX 2 5024 #define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG6 0x1188 5025 #define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG6_BASE_IDX 2 5026 #define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG7 0x1189 5027 #define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG7_BASE_IDX 2 5028 #define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG0 0x118a 5029 #define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG0_BASE_IDX 2 5030 #define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG1 0x118b 5031 #define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG1_BASE_IDX 2 5032 #define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG2 0x118c 5033 #define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG2_BASE_IDX 2 5034 #define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG3 0x118d 5035 #define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG3_BASE_IDX 2 5036 #define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG4 0x118e 5037 #define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG4_BASE_IDX 2 5038 #define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG5 0x118f 5039 #define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG5_BASE_IDX 2 5040 #define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG0 0x1190 5041 #define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG0_BASE_IDX 2 5042 #define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG1 0x1191 5043 #define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG1_BASE_IDX 2 5044 #define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG2 0x1192 5045 #define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG2_BASE_IDX 2 5046 #define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG3 0x1193 5047 #define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG3_BASE_IDX 2 5048 #define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG4 0x1194 5049 #define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG4_BASE_IDX 2 5050 #define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG5 0x1195 5051 #define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG5_BASE_IDX 2 5052 #define regDSCL3_ISHARP_MODE 0x1196 5053 #define regDSCL3_ISHARP_MODE_BASE_IDX 2 5054 #define regDSCL3_ISHARP_DELTA_CTRL 0x1197 5055 #define regDSCL3_ISHARP_DELTA_CTRL_BASE_IDX 2 5056 #define regDSCL3_ISHARP_DELTA_INDEX 0x1198 5057 #define regDSCL3_ISHARP_DELTA_INDEX_BASE_IDX 2 5058 #define regDSCL3_ISHARP_DELTA_DATA 0x1199 5059 #define regDSCL3_ISHARP_DELTA_DATA_BASE_IDX 2 5060 #define regDSCL3_ISHARP_NLDELTA_SOFT_CLIP 0x119a 5061 #define regDSCL3_ISHARP_NLDELTA_SOFT_CLIP_BASE_IDX 2 5062 #define regDSCL3_ISHARP_NOISEDET_THRESHOLD 0x119b 5063 #define regDSCL3_ISHARP_NOISEDET_THRESHOLD_BASE_IDX 2 5064 #define regDSCL3_ISHARP_NOISE_GAIN_PWL 0x119c 5065 #define regDSCL3_ISHARP_NOISE_GAIN_PWL_BASE_IDX 2 5066 #define regDSCL3_ISHARP_LBA_PWL_SEG0 0x119d 5067 #define regDSCL3_ISHARP_LBA_PWL_SEG0_BASE_IDX 2 5068 #define regDSCL3_ISHARP_LBA_PWL_SEG1 0x119e 5069 #define regDSCL3_ISHARP_LBA_PWL_SEG1_BASE_IDX 2 5070 #define regDSCL3_ISHARP_LBA_PWL_SEG2 0x119f 5071 #define regDSCL3_ISHARP_LBA_PWL_SEG2_BASE_IDX 2 5072 #define regDSCL3_ISHARP_LBA_PWL_SEG3 0x11a0 5073 #define regDSCL3_ISHARP_LBA_PWL_SEG3_BASE_IDX 2 5074 #define regDSCL3_ISHARP_LBA_PWL_SEG4 0x11a1 5075 #define regDSCL3_ISHARP_LBA_PWL_SEG4_BASE_IDX 2 5076 #define regDSCL3_ISHARP_LBA_PWL_SEG5 0x11a2 5077 #define regDSCL3_ISHARP_LBA_PWL_SEG5_BASE_IDX 2 5078 #define regDSCL3_ISHARP_DELTA_LUT_MEM_PWR_CTRL 0x11a3 5079 #define regDSCL3_ISHARP_DELTA_LUT_MEM_PWR_CTRL_BASE_IDX 2 5080 5081 5082 // addressBlock: dcn_dcec_dpp3_dispdec_cm_dispdec 5083 // base address: 0x1104 5084 #define regCM3_CM_CONTROL 0x11a8 5085 #define regCM3_CM_CONTROL_BASE_IDX 2 5086 #define regCM3_CM_POST_CSC_CONTROL 0x11a9 5087 #define regCM3_CM_POST_CSC_CONTROL_BASE_IDX 2 5088 #define regCM3_CM_POST_CSC_C11_C12 0x11aa 5089 #define regCM3_CM_POST_CSC_C11_C12_BASE_IDX 2 5090 #define regCM3_CM_POST_CSC_C13_C14 0x11ab 5091 #define regCM3_CM_POST_CSC_C13_C14_BASE_IDX 2 5092 #define regCM3_CM_POST_CSC_C21_C22 0x11ac 5093 #define regCM3_CM_POST_CSC_C21_C22_BASE_IDX 2 5094 #define regCM3_CM_POST_CSC_C23_C24 0x11ad 5095 #define regCM3_CM_POST_CSC_C23_C24_BASE_IDX 2 5096 #define regCM3_CM_POST_CSC_C31_C32 0x11ae 5097 #define regCM3_CM_POST_CSC_C31_C32_BASE_IDX 2 5098 #define regCM3_CM_POST_CSC_C33_C34 0x11af 5099 #define regCM3_CM_POST_CSC_C33_C34_BASE_IDX 2 5100 #define regCM3_CM_POST_CSC_B_C11_C12 0x11b0 5101 #define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX 2 5102 #define regCM3_CM_POST_CSC_B_C13_C14 0x11b1 5103 #define regCM3_CM_POST_CSC_B_C13_C14_BASE_IDX 2 5104 #define regCM3_CM_POST_CSC_B_C21_C22 0x11b2 5105 #define regCM3_CM_POST_CSC_B_C21_C22_BASE_IDX 2 5106 #define regCM3_CM_POST_CSC_B_C23_C24 0x11b3 5107 #define regCM3_CM_POST_CSC_B_C23_C24_BASE_IDX 2 5108 #define regCM3_CM_POST_CSC_B_C31_C32 0x11b4 5109 #define regCM3_CM_POST_CSC_B_C31_C32_BASE_IDX 2 5110 #define regCM3_CM_POST_CSC_B_C33_C34 0x11b5 5111 #define regCM3_CM_POST_CSC_B_C33_C34_BASE_IDX 2 5112 #define regCM3_CM_BIAS_CR_R 0x11b6 5113 #define regCM3_CM_BIAS_CR_R_BASE_IDX 2 5114 #define regCM3_CM_BIAS_Y_G_CB_B 0x11b7 5115 #define regCM3_CM_BIAS_Y_G_CB_B_BASE_IDX 2 5116 #define regCM3_CM_GAMCOR_CONTROL 0x11b8 5117 #define regCM3_CM_GAMCOR_CONTROL_BASE_IDX 2 5118 #define regCM3_CM_GAMCOR_LUT_INDEX 0x11b9 5119 #define regCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 5120 #define regCM3_CM_GAMCOR_LUT_DATA 0x11ba 5121 #define regCM3_CM_GAMCOR_LUT_DATA_BASE_IDX 2 5122 #define regCM3_CM_GAMCOR_LUT_CONTROL 0x11bb 5123 #define regCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 5124 #define regCM3_CM_GAMCOR_RAMA_START_CNTL_B 0x11bc 5125 #define regCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 5126 #define regCM3_CM_GAMCOR_RAMA_START_CNTL_G 0x11bd 5127 #define regCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 5128 #define regCM3_CM_GAMCOR_RAMA_START_CNTL_R 0x11be 5129 #define regCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 5130 #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x11bf 5131 #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 5132 #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x11c0 5133 #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 5134 #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x11c1 5135 #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 5136 #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x11c2 5137 #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 5138 #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x11c3 5139 #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 5140 #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x11c4 5141 #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 5142 #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B 0x11c5 5143 #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 5144 #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B 0x11c6 5145 #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 5146 #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G 0x11c7 5147 #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 5148 #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G 0x11c8 5149 #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 5150 #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R 0x11c9 5151 #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 5152 #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R 0x11ca 5153 #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 5154 #define regCM3_CM_GAMCOR_RAMA_OFFSET_B 0x11cb 5155 #define regCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 5156 #define regCM3_CM_GAMCOR_RAMA_OFFSET_G 0x11cc 5157 #define regCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 5158 #define regCM3_CM_GAMCOR_RAMA_OFFSET_R 0x11cd 5159 #define regCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 5160 #define regCM3_CM_GAMCOR_RAMA_REGION_0_1 0x11ce 5161 #define regCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 5162 #define regCM3_CM_GAMCOR_RAMA_REGION_2_3 0x11cf 5163 #define regCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 5164 #define regCM3_CM_GAMCOR_RAMA_REGION_4_5 0x11d0 5165 #define regCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 5166 #define regCM3_CM_GAMCOR_RAMA_REGION_6_7 0x11d1 5167 #define regCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 5168 #define regCM3_CM_GAMCOR_RAMA_REGION_8_9 0x11d2 5169 #define regCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 5170 #define regCM3_CM_GAMCOR_RAMA_REGION_10_11 0x11d3 5171 #define regCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 5172 #define regCM3_CM_GAMCOR_RAMA_REGION_12_13 0x11d4 5173 #define regCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 5174 #define regCM3_CM_GAMCOR_RAMA_REGION_14_15 0x11d5 5175 #define regCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 5176 #define regCM3_CM_GAMCOR_RAMA_REGION_16_17 0x11d6 5177 #define regCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 5178 #define regCM3_CM_GAMCOR_RAMA_REGION_18_19 0x11d7 5179 #define regCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 5180 #define regCM3_CM_GAMCOR_RAMA_REGION_20_21 0x11d8 5181 #define regCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 5182 #define regCM3_CM_GAMCOR_RAMA_REGION_22_23 0x11d9 5183 #define regCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 5184 #define regCM3_CM_GAMCOR_RAMA_REGION_24_25 0x11da 5185 #define regCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 5186 #define regCM3_CM_GAMCOR_RAMA_REGION_26_27 0x11db 5187 #define regCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 5188 #define regCM3_CM_GAMCOR_RAMA_REGION_28_29 0x11dc 5189 #define regCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 5190 #define regCM3_CM_GAMCOR_RAMA_REGION_30_31 0x11dd 5191 #define regCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 5192 #define regCM3_CM_GAMCOR_RAMA_REGION_32_33 0x11de 5193 #define regCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 5194 #define regCM3_CM_GAMCOR_RAMB_START_CNTL_B 0x11df 5195 #define regCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 5196 #define regCM3_CM_GAMCOR_RAMB_START_CNTL_G 0x11e0 5197 #define regCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 5198 #define regCM3_CM_GAMCOR_RAMB_START_CNTL_R 0x11e1 5199 #define regCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 5200 #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x11e2 5201 #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 5202 #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x11e3 5203 #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 5204 #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x11e4 5205 #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 5206 #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x11e5 5207 #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 5208 #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x11e6 5209 #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 5210 #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x11e7 5211 #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 5212 #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B 0x11e8 5213 #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 5214 #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B 0x11e9 5215 #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 5216 #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G 0x11ea 5217 #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 5218 #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G 0x11eb 5219 #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 5220 #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R 0x11ec 5221 #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 5222 #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R 0x11ed 5223 #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 5224 #define regCM3_CM_GAMCOR_RAMB_OFFSET_B 0x11ee 5225 #define regCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 5226 #define regCM3_CM_GAMCOR_RAMB_OFFSET_G 0x11ef 5227 #define regCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 5228 #define regCM3_CM_GAMCOR_RAMB_OFFSET_R 0x11f0 5229 #define regCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 5230 #define regCM3_CM_GAMCOR_RAMB_REGION_0_1 0x11f1 5231 #define regCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 5232 #define regCM3_CM_GAMCOR_RAMB_REGION_2_3 0x11f2 5233 #define regCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 5234 #define regCM3_CM_GAMCOR_RAMB_REGION_4_5 0x11f3 5235 #define regCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 5236 #define regCM3_CM_GAMCOR_RAMB_REGION_6_7 0x11f4 5237 #define regCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 5238 #define regCM3_CM_GAMCOR_RAMB_REGION_8_9 0x11f5 5239 #define regCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 5240 #define regCM3_CM_GAMCOR_RAMB_REGION_10_11 0x11f6 5241 #define regCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 5242 #define regCM3_CM_GAMCOR_RAMB_REGION_12_13 0x11f7 5243 #define regCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 5244 #define regCM3_CM_GAMCOR_RAMB_REGION_14_15 0x11f8 5245 #define regCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 5246 #define regCM3_CM_GAMCOR_RAMB_REGION_16_17 0x11f9 5247 #define regCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 5248 #define regCM3_CM_GAMCOR_RAMB_REGION_18_19 0x11fa 5249 #define regCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 5250 #define regCM3_CM_GAMCOR_RAMB_REGION_20_21 0x11fb 5251 #define regCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 5252 #define regCM3_CM_GAMCOR_RAMB_REGION_22_23 0x11fc 5253 #define regCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 5254 #define regCM3_CM_GAMCOR_RAMB_REGION_24_25 0x11fd 5255 #define regCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 5256 #define regCM3_CM_GAMCOR_RAMB_REGION_26_27 0x11fe 5257 #define regCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 5258 #define regCM3_CM_GAMCOR_RAMB_REGION_28_29 0x11ff 5259 #define regCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 5260 #define regCM3_CM_GAMCOR_RAMB_REGION_30_31 0x1200 5261 #define regCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 5262 #define regCM3_CM_GAMCOR_RAMB_REGION_32_33 0x1201 5263 #define regCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 5264 #define regCM3_CM_HDR_MULT_COEF 0x1202 5265 #define regCM3_CM_HDR_MULT_COEF_BASE_IDX 2 5266 #define regCM3_CM_MEM_PWR_CTRL 0x1203 5267 #define regCM3_CM_MEM_PWR_CTRL_BASE_IDX 2 5268 #define regCM3_CM_MEM_PWR_STATUS 0x1204 5269 #define regCM3_CM_MEM_PWR_STATUS_BASE_IDX 2 5270 #define regCM3_CM_DEALPHA 0x1206 5271 #define regCM3_CM_DEALPHA_BASE_IDX 2 5272 #define regCM3_CM_COEF_FORMAT 0x1207 5273 #define regCM3_CM_COEF_FORMAT_BASE_IDX 2 5274 #define regCM3_CM_TEST_DEBUG_INDEX 0x1208 5275 #define regCM3_CM_TEST_DEBUG_INDEX_BASE_IDX 2 5276 #define regCM3_CM_TEST_DEBUG_DATA 0x1209 5277 #define regCM3_CM_TEST_DEBUG_DATA_BASE_IDX 2 5278 5279 5280 // addressBlock: dcn_dcec_dpp3_dispdec_dpp_top_dispdec 5281 // base address: 0x1104 5282 #define regDPP_TOP3_DPP_CONTROL 0x1106 5283 #define regDPP_TOP3_DPP_CONTROL_BASE_IDX 2 5284 #define regDPP_TOP3_DPP_SOFT_RESET 0x1107 5285 #define regDPP_TOP3_DPP_SOFT_RESET_BASE_IDX 2 5286 #define regDPP_TOP3_DPP_CRC_VAL_R_G 0x1108 5287 #define regDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX 2 5288 #define regDPP_TOP3_DPP_CRC_VAL_B_A 0x1109 5289 #define regDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX 2 5290 #define regDPP_TOP3_DPP_CRC_CTRL 0x110a 5291 #define regDPP_TOP3_DPP_CRC_CTRL_BASE_IDX 2 5292 #define regDPP_TOP3_HOST_READ_CONTROL 0x110b 5293 #define regDPP_TOP3_HOST_READ_CONTROL_BASE_IDX 2 5294 5295 5296 // addressBlock: dcn_dcec_mpc_mpcc0_dispdec 5297 // base address: 0x0 5298 #define regMPCC0_MPCC_TOP_SEL 0x0000 5299 #define regMPCC0_MPCC_TOP_SEL_BASE_IDX 3 5300 #define regMPCC0_MPCC_BOT_SEL 0x0001 5301 #define regMPCC0_MPCC_BOT_SEL_BASE_IDX 3 5302 #define regMPCC0_MPCC_OPP_ID 0x0002 5303 #define regMPCC0_MPCC_OPP_ID_BASE_IDX 3 5304 #define regMPCC0_MPCC_CONTROL 0x0003 5305 #define regMPCC0_MPCC_CONTROL_BASE_IDX 3 5306 #define regMPCC0_MPCC_SM_CONTROL 0x0004 5307 #define regMPCC0_MPCC_SM_CONTROL_BASE_IDX 3 5308 #define regMPCC0_MPCC_UPDATE_LOCK_SEL 0x0005 5309 #define regMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 5310 #define regMPCC0_MPCC_TOP_GAIN 0x0006 5311 #define regMPCC0_MPCC_TOP_GAIN_BASE_IDX 3 5312 #define regMPCC0_MPCC_BOT_GAIN_INSIDE 0x0007 5313 #define regMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 5314 #define regMPCC0_MPCC_BOT_GAIN_OUTSIDE 0x0008 5315 #define regMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 5316 #define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x0009 5317 #define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 5318 #define regMPCC0_MPCC_BG_R_CR 0x000a 5319 #define regMPCC0_MPCC_BG_R_CR_BASE_IDX 3 5320 #define regMPCC0_MPCC_BG_G_Y 0x000b 5321 #define regMPCC0_MPCC_BG_G_Y_BASE_IDX 3 5322 #define regMPCC0_MPCC_BG_B_CB 0x000c 5323 #define regMPCC0_MPCC_BG_B_CB_BASE_IDX 3 5324 #define regMPCC0_MPCC_MEM_PWR_CTRL 0x000d 5325 #define regMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX 3 5326 #define regMPCC0_MPCC_STATUS 0x000e 5327 #define regMPCC0_MPCC_STATUS_BASE_IDX 3 5328 5329 5330 // addressBlock: dcn_dcec_mpc_mpcc1_dispdec 5331 // base address: 0x54 5332 #define regMPCC1_MPCC_TOP_SEL 0x0015 5333 #define regMPCC1_MPCC_TOP_SEL_BASE_IDX 3 5334 #define regMPCC1_MPCC_BOT_SEL 0x0016 5335 #define regMPCC1_MPCC_BOT_SEL_BASE_IDX 3 5336 #define regMPCC1_MPCC_OPP_ID 0x0017 5337 #define regMPCC1_MPCC_OPP_ID_BASE_IDX 3 5338 #define regMPCC1_MPCC_CONTROL 0x0018 5339 #define regMPCC1_MPCC_CONTROL_BASE_IDX 3 5340 #define regMPCC1_MPCC_SM_CONTROL 0x0019 5341 #define regMPCC1_MPCC_SM_CONTROL_BASE_IDX 3 5342 #define regMPCC1_MPCC_UPDATE_LOCK_SEL 0x001a 5343 #define regMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 5344 #define regMPCC1_MPCC_TOP_GAIN 0x001b 5345 #define regMPCC1_MPCC_TOP_GAIN_BASE_IDX 3 5346 #define regMPCC1_MPCC_BOT_GAIN_INSIDE 0x001c 5347 #define regMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 5348 #define regMPCC1_MPCC_BOT_GAIN_OUTSIDE 0x001d 5349 #define regMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 5350 #define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x001e 5351 #define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 5352 #define regMPCC1_MPCC_BG_R_CR 0x001f 5353 #define regMPCC1_MPCC_BG_R_CR_BASE_IDX 3 5354 #define regMPCC1_MPCC_BG_G_Y 0x0020 5355 #define regMPCC1_MPCC_BG_G_Y_BASE_IDX 3 5356 #define regMPCC1_MPCC_BG_B_CB 0x0021 5357 #define regMPCC1_MPCC_BG_B_CB_BASE_IDX 3 5358 #define regMPCC1_MPCC_MEM_PWR_CTRL 0x0022 5359 #define regMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX 3 5360 #define regMPCC1_MPCC_STATUS 0x0023 5361 #define regMPCC1_MPCC_STATUS_BASE_IDX 3 5362 5363 5364 // addressBlock: dcn_dcec_mpc_mpcc2_dispdec 5365 // base address: 0xa8 5366 #define regMPCC2_MPCC_TOP_SEL 0x002a 5367 #define regMPCC2_MPCC_TOP_SEL_BASE_IDX 3 5368 #define regMPCC2_MPCC_BOT_SEL 0x002b 5369 #define regMPCC2_MPCC_BOT_SEL_BASE_IDX 3 5370 #define regMPCC2_MPCC_OPP_ID 0x002c 5371 #define regMPCC2_MPCC_OPP_ID_BASE_IDX 3 5372 #define regMPCC2_MPCC_CONTROL 0x002d 5373 #define regMPCC2_MPCC_CONTROL_BASE_IDX 3 5374 #define regMPCC2_MPCC_SM_CONTROL 0x002e 5375 #define regMPCC2_MPCC_SM_CONTROL_BASE_IDX 3 5376 #define regMPCC2_MPCC_UPDATE_LOCK_SEL 0x002f 5377 #define regMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 5378 #define regMPCC2_MPCC_TOP_GAIN 0x0030 5379 #define regMPCC2_MPCC_TOP_GAIN_BASE_IDX 3 5380 #define regMPCC2_MPCC_BOT_GAIN_INSIDE 0x0031 5381 #define regMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 5382 #define regMPCC2_MPCC_BOT_GAIN_OUTSIDE 0x0032 5383 #define regMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 5384 #define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x0033 5385 #define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 5386 #define regMPCC2_MPCC_BG_R_CR 0x0034 5387 #define regMPCC2_MPCC_BG_R_CR_BASE_IDX 3 5388 #define regMPCC2_MPCC_BG_G_Y 0x0035 5389 #define regMPCC2_MPCC_BG_G_Y_BASE_IDX 3 5390 #define regMPCC2_MPCC_BG_B_CB 0x0036 5391 #define regMPCC2_MPCC_BG_B_CB_BASE_IDX 3 5392 #define regMPCC2_MPCC_MEM_PWR_CTRL 0x0037 5393 #define regMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX 3 5394 #define regMPCC2_MPCC_STATUS 0x0038 5395 #define regMPCC2_MPCC_STATUS_BASE_IDX 3 5396 5397 5398 // addressBlock: dcn_dcec_mpc_mpcc3_dispdec 5399 // base address: 0xfc 5400 #define regMPCC3_MPCC_TOP_SEL 0x003f 5401 #define regMPCC3_MPCC_TOP_SEL_BASE_IDX 3 5402 #define regMPCC3_MPCC_BOT_SEL 0x0040 5403 #define regMPCC3_MPCC_BOT_SEL_BASE_IDX 3 5404 #define regMPCC3_MPCC_OPP_ID 0x0041 5405 #define regMPCC3_MPCC_OPP_ID_BASE_IDX 3 5406 #define regMPCC3_MPCC_CONTROL 0x0042 5407 #define regMPCC3_MPCC_CONTROL_BASE_IDX 3 5408 #define regMPCC3_MPCC_SM_CONTROL 0x0043 5409 #define regMPCC3_MPCC_SM_CONTROL_BASE_IDX 3 5410 #define regMPCC3_MPCC_UPDATE_LOCK_SEL 0x0044 5411 #define regMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 5412 #define regMPCC3_MPCC_TOP_GAIN 0x0045 5413 #define regMPCC3_MPCC_TOP_GAIN_BASE_IDX 3 5414 #define regMPCC3_MPCC_BOT_GAIN_INSIDE 0x0046 5415 #define regMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 5416 #define regMPCC3_MPCC_BOT_GAIN_OUTSIDE 0x0047 5417 #define regMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 5418 #define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x0048 5419 #define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 5420 #define regMPCC3_MPCC_BG_R_CR 0x0049 5421 #define regMPCC3_MPCC_BG_R_CR_BASE_IDX 3 5422 #define regMPCC3_MPCC_BG_G_Y 0x004a 5423 #define regMPCC3_MPCC_BG_G_Y_BASE_IDX 3 5424 #define regMPCC3_MPCC_BG_B_CB 0x004b 5425 #define regMPCC3_MPCC_BG_B_CB_BASE_IDX 3 5426 #define regMPCC3_MPCC_MEM_PWR_CTRL 0x004c 5427 #define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX 3 5428 #define regMPCC3_MPCC_STATUS 0x004d 5429 #define regMPCC3_MPCC_STATUS_BASE_IDX 3 5430 5431 5432 // addressBlock: dcn_dcec_mpc_mpc_cfg_dispdec 5433 // base address: 0x0 5434 #define regMPC_CLOCK_CONTROL 0x02b2 5435 #define regMPC_CLOCK_CONTROL_BASE_IDX 3 5436 #define regMPC_SOFT_RESET 0x02b3 5437 #define regMPC_SOFT_RESET_BASE_IDX 3 5438 #define regMPC_CRC_CTRL 0x02b4 5439 #define regMPC_CRC_CTRL_BASE_IDX 3 5440 #define regMPC_CRC_SEL_CONTROL 0x02b5 5441 #define regMPC_CRC_SEL_CONTROL_BASE_IDX 3 5442 #define regMPC_CRC_RESULT_AR 0x02b6 5443 #define regMPC_CRC_RESULT_AR_BASE_IDX 3 5444 #define regMPC_CRC_RESULT_GB 0x02b7 5445 #define regMPC_CRC_RESULT_GB_BASE_IDX 3 5446 #define regMPC_CRC_RESULT_C 0x02b8 5447 #define regMPC_CRC_RESULT_C_BASE_IDX 3 5448 #define regMPC_BYPASS_BG_AR 0x02bc 5449 #define regMPC_BYPASS_BG_AR_BASE_IDX 3 5450 #define regMPC_BYPASS_BG_GB 0x02bd 5451 #define regMPC_BYPASS_BG_GB_BASE_IDX 3 5452 #define regMPC_HOST_READ_CONTROL 0x02be 5453 #define regMPC_HOST_READ_CONTROL_BASE_IDX 3 5454 #define regMPC_DPP_PENDING_STATUS 0x02bf 5455 #define regMPC_DPP_PENDING_STATUS_BASE_IDX 3 5456 #define regMPC_PENDING_STATUS_MISC 0x02c0 5457 #define regMPC_PENDING_STATUS_MISC_BASE_IDX 3 5458 #define regADR_CFG_CUR_VUPDATE_LOCK_SET0 0x02c1 5459 #define regADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX 3 5460 #define regADR_CFG_VUPDATE_LOCK_SET0 0x02c2 5461 #define regADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX 3 5462 #define regADR_VUPDATE_LOCK_SET0 0x02c3 5463 #define regADR_VUPDATE_LOCK_SET0_BASE_IDX 3 5464 #define regCFG_VUPDATE_LOCK_SET0 0x02c4 5465 #define regCFG_VUPDATE_LOCK_SET0_BASE_IDX 3 5466 #define regCUR_VUPDATE_LOCK_SET0 0x02c5 5467 #define regCUR_VUPDATE_LOCK_SET0_BASE_IDX 3 5468 #define regADR_CFG_CUR_VUPDATE_LOCK_SET1 0x02c6 5469 #define regADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX 3 5470 #define regADR_CFG_VUPDATE_LOCK_SET1 0x02c7 5471 #define regADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX 3 5472 #define regADR_VUPDATE_LOCK_SET1 0x02c8 5473 #define regADR_VUPDATE_LOCK_SET1_BASE_IDX 3 5474 #define regCFG_VUPDATE_LOCK_SET1 0x02c9 5475 #define regCFG_VUPDATE_LOCK_SET1_BASE_IDX 3 5476 #define regCUR_VUPDATE_LOCK_SET1 0x02ca 5477 #define regCUR_VUPDATE_LOCK_SET1_BASE_IDX 3 5478 #define regADR_CFG_CUR_VUPDATE_LOCK_SET2 0x02cb 5479 #define regADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX 3 5480 #define regADR_CFG_VUPDATE_LOCK_SET2 0x02cc 5481 #define regADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX 3 5482 #define regADR_VUPDATE_LOCK_SET2 0x02cd 5483 #define regADR_VUPDATE_LOCK_SET2_BASE_IDX 3 5484 #define regCFG_VUPDATE_LOCK_SET2 0x02ce 5485 #define regCFG_VUPDATE_LOCK_SET2_BASE_IDX 3 5486 #define regCUR_VUPDATE_LOCK_SET2 0x02cf 5487 #define regCUR_VUPDATE_LOCK_SET2_BASE_IDX 3 5488 #define regADR_CFG_CUR_VUPDATE_LOCK_SET3 0x02d0 5489 #define regADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX 3 5490 #define regADR_CFG_VUPDATE_LOCK_SET3 0x02d1 5491 #define regADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX 3 5492 #define regADR_VUPDATE_LOCK_SET3 0x02d2 5493 #define regADR_VUPDATE_LOCK_SET3_BASE_IDX 3 5494 #define regCFG_VUPDATE_LOCK_SET3 0x02d3 5495 #define regCFG_VUPDATE_LOCK_SET3_BASE_IDX 3 5496 #define regCUR_VUPDATE_LOCK_SET3 0x02d4 5497 #define regCUR_VUPDATE_LOCK_SET3_BASE_IDX 3 5498 #define regHUBP0_3DLUT_FL_CONFIG 0x02d5 5499 #define regHUBP0_3DLUT_FL_CONFIG_BASE_IDX 3 5500 #define regHUBP0_3DLUT_FL_BIAS_SCALE 0x02d6 5501 #define regHUBP0_3DLUT_FL_BIAS_SCALE_BASE_IDX 3 5502 #define regHUBP1_3DLUT_FL_CONFIG 0x02d7 5503 #define regHUBP1_3DLUT_FL_CONFIG_BASE_IDX 3 5504 #define regHUBP1_3DLUT_FL_BIAS_SCALE 0x02d8 5505 #define regHUBP1_3DLUT_FL_BIAS_SCALE_BASE_IDX 3 5506 #define regHUBP2_3DLUT_FL_CONFIG 0x02d9 5507 #define regHUBP2_3DLUT_FL_CONFIG_BASE_IDX 3 5508 #define regHUBP2_3DLUT_FL_BIAS_SCALE 0x02da 5509 #define regHUBP2_3DLUT_FL_BIAS_SCALE_BASE_IDX 3 5510 #define regHUBP3_3DLUT_FL_CONFIG 0x02db 5511 #define regHUBP3_3DLUT_FL_CONFIG_BASE_IDX 3 5512 #define regHUBP3_3DLUT_FL_BIAS_SCALE 0x02dc 5513 #define regHUBP3_3DLUT_FL_BIAS_SCALE_BASE_IDX 3 5514 #define regMPC_DWB0_MUX 0x02ee 5515 #define regMPC_DWB0_MUX_BASE_IDX 3 5516 5517 5518 // addressBlock: dcn_dcec_mpc_mpcc_ogam0_dispdec 5519 // base address: 0x0 5520 #define regMPCC_OGAM0_MPCC_OGAM_CONTROL 0x007e 5521 #define regMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX 3 5522 #define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX 0x007f 5523 #define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 5524 #define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA 0x0080 5525 #define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX 3 5526 #define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL 0x0081 5527 #define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 5528 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B 0x0082 5529 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 5530 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G 0x0083 5531 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 5532 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R 0x0084 5533 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 5534 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0085 5535 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 5536 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0086 5537 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 5538 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0087 5539 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 5540 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x0088 5541 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 5542 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x0089 5543 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 5544 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x008a 5545 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 5546 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B 0x008b 5547 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 5548 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B 0x008c 5549 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 5550 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G 0x008d 5551 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 5552 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G 0x008e 5553 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 5554 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R 0x008f 5555 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 5556 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R 0x0090 5557 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 5558 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B 0x0091 5559 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 5560 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G 0x0092 5561 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 5562 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R 0x0093 5563 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 5564 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 0x0094 5565 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 5566 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 0x0095 5567 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 5568 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 0x0096 5569 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 5570 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 0x0097 5571 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 5572 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 0x0098 5573 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 5574 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 0x0099 5575 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 5576 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 0x009a 5577 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 5578 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 0x009b 5579 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 5580 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 0x009c 5581 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 5582 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 0x009d 5583 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 5584 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 0x009e 5585 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 5586 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 0x009f 5587 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 5588 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 0x00a0 5589 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 5590 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 0x00a1 5591 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 5592 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 0x00a2 5593 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 5594 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 0x00a3 5595 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 5596 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 0x00a4 5597 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 5598 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B 0x00a5 5599 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 5600 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G 0x00a6 5601 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 5602 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R 0x00a7 5603 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 5604 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x00a8 5605 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 5606 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x00a9 5607 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 5608 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x00aa 5609 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 5610 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x00ab 5611 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 5612 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x00ac 5613 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 5614 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x00ad 5615 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 5616 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B 0x00ae 5617 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 5618 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B 0x00af 5619 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 5620 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G 0x00b0 5621 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 5622 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G 0x00b1 5623 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 5624 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R 0x00b2 5625 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 5626 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R 0x00b3 5627 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 5628 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B 0x00b4 5629 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 5630 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G 0x00b5 5631 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 5632 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R 0x00b6 5633 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 5634 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 0x00b7 5635 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 5636 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 0x00b8 5637 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 5638 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 0x00b9 5639 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 5640 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 0x00ba 5641 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 5642 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 0x00bb 5643 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 5644 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 0x00bc 5645 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 5646 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 0x00bd 5647 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 5648 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 0x00be 5649 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 5650 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 0x00bf 5651 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 5652 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 0x00c0 5653 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 5654 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 0x00c1 5655 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 5656 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 0x00c2 5657 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 5658 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 0x00c3 5659 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 5660 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 0x00c4 5661 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 5662 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 0x00c5 5663 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 5664 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 0x00c6 5665 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 5666 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 0x00c7 5667 #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 5668 #define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT 0x00c8 5669 #define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 5670 #define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE 0x00c9 5671 #define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 5672 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A 0x00ca 5673 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 5674 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A 0x00cb 5675 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 5676 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A 0x00cc 5677 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 5678 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A 0x00cd 5679 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 5680 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A 0x00ce 5681 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 5682 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A 0x00cf 5683 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 5684 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B 0x00d0 5685 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 5686 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B 0x00d1 5687 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 5688 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B 0x00d2 5689 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 5690 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B 0x00d3 5691 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 5692 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B 0x00d4 5693 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 5694 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B 0x00d5 5695 #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 5696 5697 5698 // addressBlock: dcn_dcec_mpc_mpcc_ogam1_dispdec 5699 // base address: 0x178 5700 #define regMPCC_OGAM1_MPCC_OGAM_CONTROL 0x00dc 5701 #define regMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX 3 5702 #define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX 0x00dd 5703 #define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 5704 #define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA 0x00de 5705 #define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX 3 5706 #define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL 0x00df 5707 #define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 5708 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B 0x00e0 5709 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 5710 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G 0x00e1 5711 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 5712 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R 0x00e2 5713 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 5714 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x00e3 5715 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 5716 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x00e4 5717 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 5718 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x00e5 5719 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 5720 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x00e6 5721 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 5722 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x00e7 5723 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 5724 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x00e8 5725 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 5726 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B 0x00e9 5727 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 5728 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B 0x00ea 5729 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 5730 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G 0x00eb 5731 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 5732 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G 0x00ec 5733 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 5734 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R 0x00ed 5735 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 5736 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R 0x00ee 5737 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 5738 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B 0x00ef 5739 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 5740 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G 0x00f0 5741 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 5742 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R 0x00f1 5743 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 5744 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 0x00f2 5745 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 5746 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 0x00f3 5747 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 5748 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 0x00f4 5749 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 5750 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 0x00f5 5751 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 5752 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 0x00f6 5753 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 5754 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 0x00f7 5755 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 5756 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 0x00f8 5757 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 5758 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 0x00f9 5759 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 5760 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 0x00fa 5761 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 5762 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 0x00fb 5763 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 5764 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 0x00fc 5765 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 5766 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 0x00fd 5767 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 5768 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 0x00fe 5769 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 5770 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 0x00ff 5771 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 5772 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 0x0100 5773 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 5774 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 0x0101 5775 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 5776 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 0x0102 5777 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 5778 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B 0x0103 5779 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 5780 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G 0x0104 5781 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 5782 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R 0x0105 5783 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 5784 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x0106 5785 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 5786 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x0107 5787 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 5788 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x0108 5789 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 5790 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x0109 5791 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 5792 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x010a 5793 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 5794 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x010b 5795 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 5796 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B 0x010c 5797 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 5798 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B 0x010d 5799 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 5800 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G 0x010e 5801 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 5802 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G 0x010f 5803 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 5804 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R 0x0110 5805 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 5806 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R 0x0111 5807 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 5808 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B 0x0112 5809 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 5810 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G 0x0113 5811 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 5812 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R 0x0114 5813 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 5814 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 0x0115 5815 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 5816 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 0x0116 5817 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 5818 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 0x0117 5819 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 5820 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 0x0118 5821 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 5822 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 0x0119 5823 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 5824 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 0x011a 5825 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 5826 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 0x011b 5827 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 5828 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 0x011c 5829 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 5830 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 0x011d 5831 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 5832 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 0x011e 5833 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 5834 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 0x011f 5835 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 5836 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 0x0120 5837 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 5838 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 0x0121 5839 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 5840 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 0x0122 5841 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 5842 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 0x0123 5843 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 5844 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 0x0124 5845 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 5846 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 0x0125 5847 #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 5848 #define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT 0x0126 5849 #define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 5850 #define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE 0x0127 5851 #define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 5852 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A 0x0128 5853 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 5854 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A 0x0129 5855 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 5856 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A 0x012a 5857 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 5858 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A 0x012b 5859 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 5860 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A 0x012c 5861 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 5862 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A 0x012d 5863 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 5864 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B 0x012e 5865 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 5866 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B 0x012f 5867 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 5868 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B 0x0130 5869 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 5870 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B 0x0131 5871 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 5872 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B 0x0132 5873 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 5874 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B 0x0133 5875 #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 5876 5877 5878 // addressBlock: dcn_dcec_mpc_mpcc_ogam2_dispdec 5879 // base address: 0x2f0 5880 #define regMPCC_OGAM2_MPCC_OGAM_CONTROL 0x013a 5881 #define regMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX 3 5882 #define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX 0x013b 5883 #define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 5884 #define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA 0x013c 5885 #define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX 3 5886 #define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL 0x013d 5887 #define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 5888 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B 0x013e 5889 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 5890 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G 0x013f 5891 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 5892 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R 0x0140 5893 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 5894 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0141 5895 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 5896 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0142 5897 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 5898 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0143 5899 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 5900 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x0144 5901 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 5902 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x0145 5903 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 5904 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x0146 5905 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 5906 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B 0x0147 5907 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 5908 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B 0x0148 5909 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 5910 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G 0x0149 5911 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 5912 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G 0x014a 5913 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 5914 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R 0x014b 5915 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 5916 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R 0x014c 5917 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 5918 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B 0x014d 5919 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 5920 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G 0x014e 5921 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 5922 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R 0x014f 5923 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 5924 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 0x0150 5925 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 5926 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 0x0151 5927 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 5928 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 0x0152 5929 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 5930 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 0x0153 5931 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 5932 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 0x0154 5933 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 5934 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 0x0155 5935 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 5936 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 0x0156 5937 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 5938 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 0x0157 5939 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 5940 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 0x0158 5941 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 5942 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 0x0159 5943 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 5944 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 0x015a 5945 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 5946 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 0x015b 5947 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 5948 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 0x015c 5949 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 5950 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 0x015d 5951 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 5952 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 0x015e 5953 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 5954 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 0x015f 5955 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 5956 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 0x0160 5957 #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 5958 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B 0x0161 5959 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 5960 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G 0x0162 5961 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 5962 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R 0x0163 5963 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 5964 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x0164 5965 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 5966 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x0165 5967 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 5968 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x0166 5969 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 5970 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x0167 5971 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 5972 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x0168 5973 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 5974 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x0169 5975 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 5976 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B 0x016a 5977 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 5978 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B 0x016b 5979 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 5980 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G 0x016c 5981 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 5982 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G 0x016d 5983 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 5984 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R 0x016e 5985 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 5986 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R 0x016f 5987 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 5988 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B 0x0170 5989 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 5990 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G 0x0171 5991 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 5992 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R 0x0172 5993 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 5994 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 0x0173 5995 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 5996 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 0x0174 5997 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 5998 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 0x0175 5999 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 6000 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 0x0176 6001 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 6002 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 0x0177 6003 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 6004 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 0x0178 6005 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 6006 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 0x0179 6007 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 6008 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 0x017a 6009 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 6010 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 0x017b 6011 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 6012 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 0x017c 6013 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 6014 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 0x017d 6015 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 6016 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 0x017e 6017 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 6018 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 0x017f 6019 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 6020 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 0x0180 6021 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 6022 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 0x0181 6023 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 6024 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 0x0182 6025 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 6026 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 0x0183 6027 #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 6028 #define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT 0x0184 6029 #define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 6030 #define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE 0x0185 6031 #define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 6032 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A 0x0186 6033 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 6034 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A 0x0187 6035 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 6036 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A 0x0188 6037 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 6038 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A 0x0189 6039 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 6040 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A 0x018a 6041 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 6042 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A 0x018b 6043 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 6044 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B 0x018c 6045 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 6046 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B 0x018d 6047 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 6048 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B 0x018e 6049 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 6050 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B 0x018f 6051 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 6052 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B 0x0190 6053 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 6054 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B 0x0191 6055 #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 6056 6057 6058 // addressBlock: dcn_dcec_mpc_mpcc_ogam3_dispdec 6059 // base address: 0x468 6060 #define regMPCC_OGAM3_MPCC_OGAM_CONTROL 0x0198 6061 #define regMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX 3 6062 #define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX 0x0199 6063 #define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 6064 #define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA 0x019a 6065 #define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX 3 6066 #define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL 0x019b 6067 #define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 6068 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B 0x019c 6069 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 6070 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G 0x019d 6071 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 6072 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R 0x019e 6073 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 6074 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x019f 6075 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 6076 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x01a0 6077 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 6078 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x01a1 6079 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 6080 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x01a2 6081 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 6082 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x01a3 6083 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 6084 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x01a4 6085 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 6086 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B 0x01a5 6087 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 6088 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B 0x01a6 6089 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 6090 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G 0x01a7 6091 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 6092 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G 0x01a8 6093 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 6094 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R 0x01a9 6095 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 6096 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R 0x01aa 6097 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 6098 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B 0x01ab 6099 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 6100 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G 0x01ac 6101 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 6102 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R 0x01ad 6103 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 6104 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 0x01ae 6105 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 6106 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 0x01af 6107 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 6108 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 0x01b0 6109 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 6110 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 0x01b1 6111 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 6112 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 0x01b2 6113 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 6114 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 0x01b3 6115 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 6116 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 0x01b4 6117 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 6118 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 0x01b5 6119 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 6120 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 0x01b6 6121 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 6122 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 0x01b7 6123 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 6124 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 0x01b8 6125 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 6126 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 0x01b9 6127 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 6128 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 0x01ba 6129 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 6130 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 0x01bb 6131 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 6132 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 0x01bc 6133 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 6134 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 0x01bd 6135 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 6136 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 0x01be 6137 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 6138 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B 0x01bf 6139 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 6140 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G 0x01c0 6141 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 6142 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R 0x01c1 6143 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 6144 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x01c2 6145 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 6146 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x01c3 6147 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 6148 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x01c4 6149 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 6150 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x01c5 6151 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 6152 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x01c6 6153 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 6154 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x01c7 6155 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 6156 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B 0x01c8 6157 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 6158 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B 0x01c9 6159 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 6160 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G 0x01ca 6161 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 6162 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G 0x01cb 6163 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 6164 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R 0x01cc 6165 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 6166 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R 0x01cd 6167 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 6168 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B 0x01ce 6169 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 6170 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G 0x01cf 6171 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 6172 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R 0x01d0 6173 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 6174 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 0x01d1 6175 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 6176 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 0x01d2 6177 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 6178 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 0x01d3 6179 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 6180 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 0x01d4 6181 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 6182 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 0x01d5 6183 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 6184 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 0x01d6 6185 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 6186 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 0x01d7 6187 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 6188 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 0x01d8 6189 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 6190 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 0x01d9 6191 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 6192 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 0x01da 6193 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 6194 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 0x01db 6195 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 6196 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 0x01dc 6197 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 6198 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 0x01dd 6199 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 6200 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 0x01de 6201 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 6202 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 0x01df 6203 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 6204 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 0x01e0 6205 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 6206 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 0x01e1 6207 #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 6208 #define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT 0x01e2 6209 #define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 6210 #define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE 0x01e3 6211 #define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 6212 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A 0x01e4 6213 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 6214 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A 0x01e5 6215 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 6216 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A 0x01e6 6217 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 6218 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A 0x01e7 6219 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 6220 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A 0x01e8 6221 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 6222 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A 0x01e9 6223 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 6224 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B 0x01ea 6225 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 6226 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B 0x01eb 6227 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 6228 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B 0x01ec 6229 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 6230 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B 0x01ed 6231 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 6232 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B 0x01ee 6233 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 6234 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B 0x01ef 6235 #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 6236 6237 6238 // addressBlock: dcn_dcec_mpc_mpcc_mcm0_dispdec 6239 // base address: 0x0 6240 #define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL 0x0453 6241 #define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 6242 #define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R 0x0454 6243 #define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 6244 #define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G 0x0455 6245 #define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 6246 #define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B 0x0456 6247 #define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 6248 #define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R 0x0457 6249 #define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 6250 #define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B 0x0458 6251 #define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 6252 #define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX 0x0459 6253 #define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 6254 #define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA 0x045a 6255 #define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 6256 #define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x045b 6257 #define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 6258 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x045c 6259 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 6260 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x045d 6261 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 6262 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x045e 6263 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 6264 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x045f 6265 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 6266 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x0460 6267 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 6268 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x0461 6269 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 6270 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x0462 6271 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 6272 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x0463 6273 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 6274 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x0464 6275 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 6276 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x0465 6277 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 6278 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x0466 6279 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 6280 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x0467 6281 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 6282 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x0468 6283 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 6284 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x0469 6285 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 6286 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x046a 6287 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 6288 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x046b 6289 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 6290 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x046c 6291 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 6292 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x046d 6293 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 6294 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x046e 6295 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 6296 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x046f 6297 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 6298 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0470 6299 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 6300 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0471 6301 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 6302 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0472 6303 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 6304 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0473 6305 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 6306 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0474 6307 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 6308 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0475 6309 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 6310 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0476 6311 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 6312 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0477 6313 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 6314 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0478 6315 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 6316 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0479 6317 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 6318 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x047a 6319 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 6320 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x047b 6321 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 6322 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x047c 6323 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 6324 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x047d 6325 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 6326 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x047e 6327 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 6328 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x047f 6329 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 6330 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x0480 6331 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 6332 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x0481 6333 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 6334 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x0482 6335 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 6336 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x0483 6337 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 6338 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x0484 6339 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 6340 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x0485 6341 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 6342 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x0486 6343 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 6344 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x0487 6345 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 6346 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x0488 6347 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 6348 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x0489 6349 #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 6350 #define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE 0x048a 6351 #define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 6352 #define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX 0x048b 6353 #define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 6354 #define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA 0x048c 6355 #define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 6356 #define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT 0x048d 6357 #define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 6358 #define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x048e 6359 #define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 6360 #define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x048f 6361 #define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 6362 #define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x0490 6363 #define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 6364 #define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x0491 6365 #define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 6366 #define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x0492 6367 #define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 6368 #define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL 0x0493 6369 #define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 6370 #define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX 0x0494 6371 #define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 6372 #define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA 0x0495 6373 #define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 6374 #define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL 0x0496 6375 #define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 6376 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x0497 6377 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 6378 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x0498 6379 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 6380 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x0499 6381 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 6382 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x049a 6383 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 6384 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x049b 6385 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 6386 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x049c 6387 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 6388 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x049d 6389 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 6390 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x049e 6391 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 6392 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x049f 6393 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 6394 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x04a0 6395 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 6396 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x04a1 6397 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 6398 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x04a2 6399 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 6400 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x04a3 6401 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 6402 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x04a4 6403 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 6404 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x04a5 6405 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 6406 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x04a6 6407 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 6408 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x04a7 6409 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 6410 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x04a8 6411 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 6412 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x04a9 6413 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 6414 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x04aa 6415 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 6416 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x04ab 6417 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 6418 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x04ac 6419 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 6420 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x04ad 6421 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 6422 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x04ae 6423 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 6424 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x04af 6425 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 6426 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x04b0 6427 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 6428 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x04b1 6429 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 6430 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x04b2 6431 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 6432 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x04b3 6433 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 6434 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x04b4 6435 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 6436 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x04b5 6437 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 6438 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x04b6 6439 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 6440 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x04b7 6441 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 6442 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x04b8 6443 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 6444 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x04b9 6445 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 6446 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x04ba 6447 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 6448 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x04bb 6449 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 6450 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x04bc 6451 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 6452 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x04bd 6453 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 6454 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x04be 6455 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 6456 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x04bf 6457 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 6458 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x04c0 6459 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 6460 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x04c1 6461 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 6462 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x04c2 6463 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 6464 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x04c3 6465 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 6466 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x04c4 6467 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 6468 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x04c5 6469 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 6470 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x04c6 6471 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 6472 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x04c7 6473 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 6474 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x04c8 6475 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 6476 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x04c9 6477 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 6478 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x04ca 6479 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 6480 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x04cb 6481 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 6482 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x04cc 6483 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 6484 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x04cd 6485 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 6486 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x04ce 6487 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 6488 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x04cf 6489 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 6490 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x04d0 6491 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 6492 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x04d1 6493 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 6494 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x04d2 6495 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 6496 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x04d3 6497 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 6498 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x04d4 6499 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 6500 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x04d5 6501 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 6502 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x04d6 6503 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 6504 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x04d7 6505 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 6506 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x04d8 6507 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 6508 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x04d9 6509 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 6510 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x04da 6511 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 6512 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x04db 6513 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 6514 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x04dc 6515 #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 6516 #define regMPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT 0x04dd 6517 #define regMPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 6518 #define regMPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE 0x04de 6519 #define regMPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE_BASE_IDX 3 6520 #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A 0x04df 6521 #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 6522 #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A 0x04e0 6523 #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 6524 #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A 0x04e1 6525 #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 6526 #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A 0x04e2 6527 #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 6528 #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A 0x04e3 6529 #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 6530 #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A 0x04e4 6531 #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 6532 #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B 0x04e5 6533 #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 6534 #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B 0x04e6 6535 #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 6536 #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B 0x04e7 6537 #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 6538 #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B 0x04e8 6539 #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 6540 #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B 0x04e9 6541 #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 6542 #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B 0x04ea 6543 #define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 6544 #define regMPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT 0x04eb 6545 #define regMPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 6546 #define regMPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE 0x04ec 6547 #define regMPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE_BASE_IDX 3 6548 #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A 0x04ed 6549 #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 6550 #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A 0x04ee 6551 #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 6552 #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A 0x04ef 6553 #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 6554 #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A 0x04f0 6555 #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 6556 #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A 0x04f1 6557 #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 6558 #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A 0x04f2 6559 #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 6560 #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B 0x04f3 6561 #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 6562 #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B 0x04f4 6563 #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 6564 #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B 0x04f5 6565 #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 6566 #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B 0x04f6 6567 #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 6568 #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B 0x04f7 6569 #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 6570 #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B 0x04f8 6571 #define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 6572 #define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL 0x04f9 6573 #define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 6574 #define regMPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_SELECT 0x04fa 6575 #define regMPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_SELECT_BASE_IDX 3 6576 #define regMPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS 0x04fb 6577 #define regMPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS_BASE_IDX 3 6578 6579 6580 // addressBlock: dcn_dcec_mpc_mpcc_mcm1_dispdec 6581 // base address: 0x2c0 6582 #define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL 0x0503 6583 #define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 6584 #define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R 0x0504 6585 #define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 6586 #define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G 0x0505 6587 #define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 6588 #define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B 0x0506 6589 #define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 6590 #define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R 0x0507 6591 #define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 6592 #define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B 0x0508 6593 #define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 6594 #define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX 0x0509 6595 #define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 6596 #define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA 0x050a 6597 #define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 6598 #define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x050b 6599 #define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 6600 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x050c 6601 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 6602 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x050d 6603 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 6604 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x050e 6605 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 6606 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x050f 6607 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 6608 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x0510 6609 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 6610 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x0511 6611 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 6612 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x0512 6613 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 6614 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x0513 6615 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 6616 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x0514 6617 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 6618 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x0515 6619 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 6620 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x0516 6621 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 6622 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x0517 6623 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 6624 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x0518 6625 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 6626 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x0519 6627 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 6628 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x051a 6629 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 6630 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x051b 6631 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 6632 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x051c 6633 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 6634 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x051d 6635 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 6636 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x051e 6637 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 6638 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x051f 6639 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 6640 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0520 6641 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 6642 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0521 6643 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 6644 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0522 6645 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 6646 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0523 6647 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 6648 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0524 6649 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 6650 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0525 6651 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 6652 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0526 6653 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 6654 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0527 6655 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 6656 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0528 6657 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 6658 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0529 6659 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 6660 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x052a 6661 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 6662 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x052b 6663 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 6664 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x052c 6665 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 6666 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x052d 6667 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 6668 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x052e 6669 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 6670 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x052f 6671 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 6672 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x0530 6673 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 6674 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x0531 6675 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 6676 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x0532 6677 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 6678 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x0533 6679 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 6680 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x0534 6681 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 6682 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x0535 6683 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 6684 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x0536 6685 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 6686 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x0537 6687 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 6688 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x0538 6689 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 6690 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x0539 6691 #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 6692 #define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE 0x053a 6693 #define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 6694 #define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX 0x053b 6695 #define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 6696 #define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA 0x053c 6697 #define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 6698 #define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT 0x053d 6699 #define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 6700 #define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x053e 6701 #define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 6702 #define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x053f 6703 #define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 6704 #define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x0540 6705 #define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 6706 #define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x0541 6707 #define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 6708 #define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x0542 6709 #define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 6710 #define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL 0x0543 6711 #define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 6712 #define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX 0x0544 6713 #define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 6714 #define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA 0x0545 6715 #define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 6716 #define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL 0x0546 6717 #define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 6718 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x0547 6719 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 6720 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x0548 6721 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 6722 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x0549 6723 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 6724 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x054a 6725 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 6726 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x054b 6727 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 6728 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x054c 6729 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 6730 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x054d 6731 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 6732 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x054e 6733 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 6734 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x054f 6735 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 6736 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x0550 6737 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 6738 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x0551 6739 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 6740 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x0552 6741 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 6742 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x0553 6743 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 6744 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x0554 6745 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 6746 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x0555 6747 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 6748 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x0556 6749 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 6750 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x0557 6751 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 6752 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x0558 6753 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 6754 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x0559 6755 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 6756 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x055a 6757 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 6758 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x055b 6759 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 6760 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x055c 6761 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 6762 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x055d 6763 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 6764 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x055e 6765 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 6766 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x055f 6767 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 6768 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x0560 6769 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 6770 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x0561 6771 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 6772 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x0562 6773 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 6774 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x0563 6775 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 6776 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x0564 6777 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 6778 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x0565 6779 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 6780 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x0566 6781 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 6782 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x0567 6783 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 6784 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x0568 6785 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 6786 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x0569 6787 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 6788 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x056a 6789 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 6790 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x056b 6791 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 6792 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x056c 6793 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 6794 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x056d 6795 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 6796 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x056e 6797 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 6798 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x056f 6799 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 6800 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x0570 6801 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 6802 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x0571 6803 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 6804 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x0572 6805 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 6806 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x0573 6807 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 6808 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x0574 6809 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 6810 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x0575 6811 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 6812 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x0576 6813 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 6814 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x0577 6815 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 6816 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x0578 6817 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 6818 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x0579 6819 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 6820 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x057a 6821 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 6822 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x057b 6823 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 6824 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x057c 6825 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 6826 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x057d 6827 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 6828 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x057e 6829 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 6830 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x057f 6831 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 6832 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x0580 6833 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 6834 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x0581 6835 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 6836 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x0582 6837 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 6838 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x0583 6839 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 6840 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x0584 6841 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 6842 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x0585 6843 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 6844 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x0586 6845 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 6846 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x0587 6847 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 6848 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x0588 6849 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 6850 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x0589 6851 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 6852 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x058a 6853 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 6854 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x058b 6855 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 6856 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x058c 6857 #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 6858 #define regMPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT 0x058d 6859 #define regMPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 6860 #define regMPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_MODE 0x058e 6861 #define regMPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_MODE_BASE_IDX 3 6862 #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A 0x058f 6863 #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 6864 #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A 0x0590 6865 #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 6866 #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A 0x0591 6867 #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 6868 #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A 0x0592 6869 #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 6870 #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A 0x0593 6871 #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 6872 #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A 0x0594 6873 #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 6874 #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B 0x0595 6875 #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 6876 #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B 0x0596 6877 #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 6878 #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B 0x0597 6879 #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 6880 #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B 0x0598 6881 #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 6882 #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B 0x0599 6883 #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 6884 #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B 0x059a 6885 #define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 6886 #define regMPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT 0x059b 6887 #define regMPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 6888 #define regMPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_MODE 0x059c 6889 #define regMPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_MODE_BASE_IDX 3 6890 #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A 0x059d 6891 #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 6892 #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A 0x059e 6893 #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 6894 #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A 0x059f 6895 #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 6896 #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A 0x05a0 6897 #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 6898 #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A 0x05a1 6899 #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 6900 #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A 0x05a2 6901 #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 6902 #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B 0x05a3 6903 #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 6904 #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B 0x05a4 6905 #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 6906 #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B 0x05a5 6907 #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 6908 #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B 0x05a6 6909 #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 6910 #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B 0x05a7 6911 #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 6912 #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B 0x05a8 6913 #define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 6914 #define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL 0x05a9 6915 #define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 6916 #define regMPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_SELECT 0x05aa 6917 #define regMPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_SELECT_BASE_IDX 3 6918 #define regMPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_STATUS 0x05ab 6919 #define regMPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_STATUS_BASE_IDX 3 6920 6921 6922 // addressBlock: dcn_dcec_mpc_mpcc_mcm2_dispdec 6923 // base address: 0x580 6924 #define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL 0x05b3 6925 #define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 6926 #define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R 0x05b4 6927 #define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 6928 #define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G 0x05b5 6929 #define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 6930 #define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B 0x05b6 6931 #define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 6932 #define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R 0x05b7 6933 #define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 6934 #define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B 0x05b8 6935 #define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 6936 #define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX 0x05b9 6937 #define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 6938 #define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA 0x05ba 6939 #define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 6940 #define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x05bb 6941 #define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 6942 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x05bc 6943 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 6944 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x05bd 6945 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 6946 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x05be 6947 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 6948 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x05bf 6949 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 6950 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x05c0 6951 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 6952 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x05c1 6953 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 6954 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x05c2 6955 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 6956 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x05c3 6957 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 6958 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x05c4 6959 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 6960 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x05c5 6961 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 6962 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x05c6 6963 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 6964 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x05c7 6965 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 6966 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x05c8 6967 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 6968 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x05c9 6969 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 6970 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x05ca 6971 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 6972 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x05cb 6973 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 6974 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x05cc 6975 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 6976 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x05cd 6977 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 6978 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x05ce 6979 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 6980 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x05cf 6981 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 6982 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x05d0 6983 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 6984 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x05d1 6985 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 6986 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x05d2 6987 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 6988 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x05d3 6989 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 6990 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x05d4 6991 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 6992 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x05d5 6993 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 6994 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x05d6 6995 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 6996 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x05d7 6997 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 6998 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x05d8 6999 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 7000 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x05d9 7001 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 7002 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x05da 7003 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 7004 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x05db 7005 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 7006 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x05dc 7007 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 7008 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x05dd 7009 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 7010 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x05de 7011 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 7012 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x05df 7013 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 7014 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x05e0 7015 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 7016 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x05e1 7017 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 7018 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x05e2 7019 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 7020 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x05e3 7021 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 7022 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x05e4 7023 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 7024 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x05e5 7025 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 7026 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x05e6 7027 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 7028 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x05e7 7029 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 7030 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x05e8 7031 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 7032 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x05e9 7033 #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 7034 #define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE 0x05ea 7035 #define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 7036 #define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX 0x05eb 7037 #define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 7038 #define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA 0x05ec 7039 #define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 7040 #define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT 0x05ed 7041 #define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 7042 #define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x05ee 7043 #define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 7044 #define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x05ef 7045 #define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 7046 #define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x05f0 7047 #define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 7048 #define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x05f1 7049 #define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 7050 #define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x05f2 7051 #define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 7052 #define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL 0x05f3 7053 #define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 7054 #define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX 0x05f4 7055 #define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 7056 #define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA 0x05f5 7057 #define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 7058 #define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL 0x05f6 7059 #define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 7060 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x05f7 7061 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 7062 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x05f8 7063 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 7064 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x05f9 7065 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 7066 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x05fa 7067 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 7068 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x05fb 7069 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 7070 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x05fc 7071 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 7072 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x05fd 7073 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 7074 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x05fe 7075 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 7076 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x05ff 7077 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 7078 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x0600 7079 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 7080 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x0601 7081 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 7082 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x0602 7083 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 7084 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x0603 7085 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 7086 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x0604 7087 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 7088 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x0605 7089 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 7090 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x0606 7091 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 7092 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x0607 7093 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 7094 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x0608 7095 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 7096 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x0609 7097 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 7098 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x060a 7099 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 7100 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x060b 7101 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 7102 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x060c 7103 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 7104 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x060d 7105 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 7106 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x060e 7107 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 7108 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x060f 7109 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 7110 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x0610 7111 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 7112 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x0611 7113 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 7114 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x0612 7115 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 7116 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x0613 7117 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 7118 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x0614 7119 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 7120 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x0615 7121 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 7122 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x0616 7123 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 7124 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x0617 7125 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 7126 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x0618 7127 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 7128 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x0619 7129 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 7130 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x061a 7131 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 7132 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x061b 7133 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 7134 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x061c 7135 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 7136 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x061d 7137 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 7138 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x061e 7139 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 7140 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x061f 7141 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 7142 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x0620 7143 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 7144 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x0621 7145 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 7146 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x0622 7147 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 7148 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x0623 7149 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 7150 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x0624 7151 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 7152 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x0625 7153 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 7154 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x0626 7155 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 7156 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x0627 7157 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 7158 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x0628 7159 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 7160 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x0629 7161 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 7162 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x062a 7163 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 7164 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x062b 7165 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 7166 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x062c 7167 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 7168 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x062d 7169 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 7170 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x062e 7171 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 7172 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x062f 7173 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 7174 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x0630 7175 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 7176 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x0631 7177 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 7178 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x0632 7179 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 7180 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x0633 7181 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 7182 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x0634 7183 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 7184 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x0635 7185 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 7186 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x0636 7187 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 7188 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x0637 7189 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 7190 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x0638 7191 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 7192 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x0639 7193 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 7194 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x063a 7195 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 7196 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x063b 7197 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 7198 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x063c 7199 #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 7200 #define regMPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT 0x063d 7201 #define regMPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 7202 #define regMPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_MODE 0x063e 7203 #define regMPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_MODE_BASE_IDX 3 7204 #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A 0x063f 7205 #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 7206 #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A 0x0640 7207 #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 7208 #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A 0x0641 7209 #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 7210 #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A 0x0642 7211 #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 7212 #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A 0x0643 7213 #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 7214 #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A 0x0644 7215 #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 7216 #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B 0x0645 7217 #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 7218 #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B 0x0646 7219 #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 7220 #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B 0x0647 7221 #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 7222 #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B 0x0648 7223 #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 7224 #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B 0x0649 7225 #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 7226 #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B 0x064a 7227 #define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 7228 #define regMPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT 0x064b 7229 #define regMPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 7230 #define regMPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_MODE 0x064c 7231 #define regMPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_MODE_BASE_IDX 3 7232 #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A 0x064d 7233 #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 7234 #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A 0x064e 7235 #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 7236 #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A 0x064f 7237 #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 7238 #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A 0x0650 7239 #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 7240 #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A 0x0651 7241 #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 7242 #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A 0x0652 7243 #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 7244 #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B 0x0653 7245 #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 7246 #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B 0x0654 7247 #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 7248 #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B 0x0655 7249 #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 7250 #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B 0x0656 7251 #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 7252 #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B 0x0657 7253 #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 7254 #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B 0x0658 7255 #define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 7256 #define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL 0x0659 7257 #define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 7258 #define regMPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_SELECT 0x065a 7259 #define regMPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_SELECT_BASE_IDX 3 7260 #define regMPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_STATUS 0x065b 7261 #define regMPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_STATUS_BASE_IDX 3 7262 7263 7264 // addressBlock: dcn_dcec_mpc_mpcc_mcm3_dispdec 7265 // base address: 0x840 7266 #define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL 0x0663 7267 #define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 7268 #define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R 0x0664 7269 #define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 7270 #define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G 0x0665 7271 #define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 7272 #define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B 0x0666 7273 #define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 7274 #define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R 0x0667 7275 #define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 7276 #define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B 0x0668 7277 #define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 7278 #define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX 0x0669 7279 #define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 7280 #define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA 0x066a 7281 #define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 7282 #define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x066b 7283 #define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 7284 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x066c 7285 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 7286 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x066d 7287 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 7288 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x066e 7289 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 7290 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x066f 7291 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 7292 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x0670 7293 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 7294 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x0671 7295 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 7296 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x0672 7297 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 7298 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x0673 7299 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 7300 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x0674 7301 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 7302 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x0675 7303 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 7304 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x0676 7305 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 7306 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x0677 7307 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 7308 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x0678 7309 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 7310 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x0679 7311 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 7312 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x067a 7313 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 7314 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x067b 7315 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 7316 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x067c 7317 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 7318 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x067d 7319 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 7320 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x067e 7321 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 7322 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x067f 7323 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 7324 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0680 7325 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 7326 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0681 7327 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 7328 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0682 7329 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 7330 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0683 7331 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 7332 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0684 7333 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 7334 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0685 7335 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 7336 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0686 7337 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 7338 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0687 7339 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 7340 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0688 7341 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 7342 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0689 7343 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 7344 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x068a 7345 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 7346 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x068b 7347 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 7348 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x068c 7349 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 7350 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x068d 7351 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 7352 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x068e 7353 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 7354 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x068f 7355 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 7356 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x0690 7357 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 7358 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x0691 7359 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 7360 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x0692 7361 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 7362 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x0693 7363 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 7364 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x0694 7365 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 7366 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x0695 7367 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 7368 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x0696 7369 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 7370 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x0697 7371 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 7372 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x0698 7373 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 7374 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x0699 7375 #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 7376 #define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE 0x069a 7377 #define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 7378 #define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX 0x069b 7379 #define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 7380 #define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA 0x069c 7381 #define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 7382 #define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT 0x069d 7383 #define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 7384 #define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x069e 7385 #define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 7386 #define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x069f 7387 #define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 7388 #define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x06a0 7389 #define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 7390 #define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x06a1 7391 #define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 7392 #define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x06a2 7393 #define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 7394 #define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL 0x06a3 7395 #define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 7396 #define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX 0x06a4 7397 #define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 7398 #define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA 0x06a5 7399 #define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 7400 #define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL 0x06a6 7401 #define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 7402 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x06a7 7403 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 7404 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x06a8 7405 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 7406 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x06a9 7407 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 7408 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x06aa 7409 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 7410 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x06ab 7411 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 7412 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x06ac 7413 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 7414 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x06ad 7415 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 7416 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x06ae 7417 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 7418 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x06af 7419 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 7420 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x06b0 7421 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 7422 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x06b1 7423 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 7424 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x06b2 7425 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 7426 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x06b3 7427 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 7428 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x06b4 7429 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 7430 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x06b5 7431 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 7432 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x06b6 7433 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 7434 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x06b7 7435 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 7436 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x06b8 7437 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 7438 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x06b9 7439 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 7440 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x06ba 7441 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 7442 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x06bb 7443 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 7444 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x06bc 7445 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 7446 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x06bd 7447 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 7448 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x06be 7449 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 7450 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x06bf 7451 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 7452 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x06c0 7453 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 7454 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x06c1 7455 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 7456 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x06c2 7457 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 7458 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x06c3 7459 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 7460 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x06c4 7461 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 7462 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x06c5 7463 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 7464 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x06c6 7465 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 7466 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x06c7 7467 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 7468 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x06c8 7469 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 7470 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x06c9 7471 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 7472 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x06ca 7473 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 7474 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x06cb 7475 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 7476 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x06cc 7477 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 7478 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x06cd 7479 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 7480 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x06ce 7481 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 7482 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x06cf 7483 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 7484 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x06d0 7485 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 7486 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x06d1 7487 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 7488 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x06d2 7489 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 7490 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x06d3 7491 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 7492 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x06d4 7493 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 7494 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x06d5 7495 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 7496 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x06d6 7497 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 7498 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x06d7 7499 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 7500 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x06d8 7501 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 7502 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x06d9 7503 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 7504 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x06da 7505 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 7506 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x06db 7507 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 7508 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x06dc 7509 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 7510 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x06dd 7511 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 7512 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x06de 7513 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 7514 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x06df 7515 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 7516 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x06e0 7517 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 7518 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x06e1 7519 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 7520 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x06e2 7521 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 7522 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x06e3 7523 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 7524 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x06e4 7525 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 7526 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x06e5 7527 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 7528 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x06e6 7529 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 7530 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x06e7 7531 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 7532 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x06e8 7533 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 7534 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x06e9 7535 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 7536 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x06ea 7537 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 7538 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x06eb 7539 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 7540 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x06ec 7541 #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 7542 #define regMPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT 0x06ed 7543 #define regMPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 7544 #define regMPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_MODE 0x06ee 7545 #define regMPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_MODE_BASE_IDX 3 7546 #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A 0x06ef 7547 #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 7548 #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A 0x06f0 7549 #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 7550 #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A 0x06f1 7551 #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 7552 #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A 0x06f2 7553 #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 7554 #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A 0x06f3 7555 #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 7556 #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A 0x06f4 7557 #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 7558 #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B 0x06f5 7559 #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 7560 #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B 0x06f6 7561 #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 7562 #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B 0x06f7 7563 #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 7564 #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B 0x06f8 7565 #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 7566 #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B 0x06f9 7567 #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 7568 #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B 0x06fa 7569 #define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 7570 #define regMPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT 0x06fb 7571 #define regMPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 7572 #define regMPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_MODE 0x06fc 7573 #define regMPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_MODE_BASE_IDX 3 7574 #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A 0x06fd 7575 #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 7576 #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A 0x06fe 7577 #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 7578 #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A 0x06ff 7579 #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 7580 #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A 0x0700 7581 #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 7582 #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A 0x0701 7583 #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 7584 #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A 0x0702 7585 #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 7586 #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B 0x0703 7587 #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 7588 #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B 0x0704 7589 #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 7590 #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B 0x0705 7591 #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 7592 #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B 0x0706 7593 #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 7594 #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B 0x0707 7595 #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 7596 #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B 0x0708 7597 #define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 7598 #define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL 0x0709 7599 #define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 7600 #define regMPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_SELECT 0x070a 7601 #define regMPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_SELECT_BASE_IDX 3 7602 #define regMPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_STATUS 0x070b 7603 #define regMPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_STATUS_BASE_IDX 3 7604 7605 7606 // addressBlock: dcn_dcec_mpc_mpc_ocsc_dispdec 7607 // base address: 0x0 7608 #define regMPC_OUT0_MUX 0x02f2 7609 #define regMPC_OUT0_MUX_BASE_IDX 3 7610 #define regMPC_OUT0_DENORM_CONTROL 0x02f3 7611 #define regMPC_OUT0_DENORM_CONTROL_BASE_IDX 3 7612 #define regMPC_OUT0_DENORM_CLAMP_G_Y 0x02f4 7613 #define regMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX 3 7614 #define regMPC_OUT0_DENORM_CLAMP_B_CB 0x02f5 7615 #define regMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX 3 7616 #define regMPC_OUT1_MUX 0x02f6 7617 #define regMPC_OUT1_MUX_BASE_IDX 3 7618 #define regMPC_OUT1_DENORM_CONTROL 0x02f7 7619 #define regMPC_OUT1_DENORM_CONTROL_BASE_IDX 3 7620 #define regMPC_OUT1_DENORM_CLAMP_G_Y 0x02f8 7621 #define regMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX 3 7622 #define regMPC_OUT1_DENORM_CLAMP_B_CB 0x02f9 7623 #define regMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX 3 7624 #define regMPC_OUT2_MUX 0x02fa 7625 #define regMPC_OUT2_MUX_BASE_IDX 3 7626 #define regMPC_OUT2_DENORM_CONTROL 0x02fb 7627 #define regMPC_OUT2_DENORM_CONTROL_BASE_IDX 3 7628 #define regMPC_OUT2_DENORM_CLAMP_G_Y 0x02fc 7629 #define regMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX 3 7630 #define regMPC_OUT2_DENORM_CLAMP_B_CB 0x02fd 7631 #define regMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX 3 7632 #define regMPC_OUT3_MUX 0x02fe 7633 #define regMPC_OUT3_MUX_BASE_IDX 3 7634 #define regMPC_OUT3_DENORM_CONTROL 0x02ff 7635 #define regMPC_OUT3_DENORM_CONTROL_BASE_IDX 3 7636 #define regMPC_OUT3_DENORM_CLAMP_G_Y 0x0300 7637 #define regMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX 3 7638 #define regMPC_OUT3_DENORM_CLAMP_B_CB 0x0301 7639 #define regMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX 3 7640 #define regMPC_OUT_CSC_COEF_FORMAT 0x030a 7641 #define regMPC_OUT_CSC_COEF_FORMAT_BASE_IDX 3 7642 #define regMPC_OUT0_CSC_MODE 0x030b 7643 #define regMPC_OUT0_CSC_MODE_BASE_IDX 3 7644 #define regMPC_OUT0_CSC_C11_C12_A 0x030c 7645 #define regMPC_OUT0_CSC_C11_C12_A_BASE_IDX 3 7646 #define regMPC_OUT0_CSC_C13_C14_A 0x030d 7647 #define regMPC_OUT0_CSC_C13_C14_A_BASE_IDX 3 7648 #define regMPC_OUT0_CSC_C21_C22_A 0x030e 7649 #define regMPC_OUT0_CSC_C21_C22_A_BASE_IDX 3 7650 #define regMPC_OUT0_CSC_C23_C24_A 0x030f 7651 #define regMPC_OUT0_CSC_C23_C24_A_BASE_IDX 3 7652 #define regMPC_OUT0_CSC_C31_C32_A 0x0310 7653 #define regMPC_OUT0_CSC_C31_C32_A_BASE_IDX 3 7654 #define regMPC_OUT0_CSC_C33_C34_A 0x0311 7655 #define regMPC_OUT0_CSC_C33_C34_A_BASE_IDX 3 7656 #define regMPC_OUT0_CSC_C11_C12_B 0x0312 7657 #define regMPC_OUT0_CSC_C11_C12_B_BASE_IDX 3 7658 #define regMPC_OUT0_CSC_C13_C14_B 0x0313 7659 #define regMPC_OUT0_CSC_C13_C14_B_BASE_IDX 3 7660 #define regMPC_OUT0_CSC_C21_C22_B 0x0314 7661 #define regMPC_OUT0_CSC_C21_C22_B_BASE_IDX 3 7662 #define regMPC_OUT0_CSC_C23_C24_B 0x0315 7663 #define regMPC_OUT0_CSC_C23_C24_B_BASE_IDX 3 7664 #define regMPC_OUT0_CSC_C31_C32_B 0x0316 7665 #define regMPC_OUT0_CSC_C31_C32_B_BASE_IDX 3 7666 #define regMPC_OUT0_CSC_C33_C34_B 0x0317 7667 #define regMPC_OUT0_CSC_C33_C34_B_BASE_IDX 3 7668 #define regMPC_OUT1_CSC_MODE 0x0318 7669 #define regMPC_OUT1_CSC_MODE_BASE_IDX 3 7670 #define regMPC_OUT1_CSC_C11_C12_A 0x0319 7671 #define regMPC_OUT1_CSC_C11_C12_A_BASE_IDX 3 7672 #define regMPC_OUT1_CSC_C13_C14_A 0x031a 7673 #define regMPC_OUT1_CSC_C13_C14_A_BASE_IDX 3 7674 #define regMPC_OUT1_CSC_C21_C22_A 0x031b 7675 #define regMPC_OUT1_CSC_C21_C22_A_BASE_IDX 3 7676 #define regMPC_OUT1_CSC_C23_C24_A 0x031c 7677 #define regMPC_OUT1_CSC_C23_C24_A_BASE_IDX 3 7678 #define regMPC_OUT1_CSC_C31_C32_A 0x031d 7679 #define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX 3 7680 #define regMPC_OUT1_CSC_C33_C34_A 0x031e 7681 #define regMPC_OUT1_CSC_C33_C34_A_BASE_IDX 3 7682 #define regMPC_OUT1_CSC_C11_C12_B 0x031f 7683 #define regMPC_OUT1_CSC_C11_C12_B_BASE_IDX 3 7684 #define regMPC_OUT1_CSC_C13_C14_B 0x0320 7685 #define regMPC_OUT1_CSC_C13_C14_B_BASE_IDX 3 7686 #define regMPC_OUT1_CSC_C21_C22_B 0x0321 7687 #define regMPC_OUT1_CSC_C21_C22_B_BASE_IDX 3 7688 #define regMPC_OUT1_CSC_C23_C24_B 0x0322 7689 #define regMPC_OUT1_CSC_C23_C24_B_BASE_IDX 3 7690 #define regMPC_OUT1_CSC_C31_C32_B 0x0323 7691 #define regMPC_OUT1_CSC_C31_C32_B_BASE_IDX 3 7692 #define regMPC_OUT1_CSC_C33_C34_B 0x0324 7693 #define regMPC_OUT1_CSC_C33_C34_B_BASE_IDX 3 7694 #define regMPC_OUT2_CSC_MODE 0x0325 7695 #define regMPC_OUT2_CSC_MODE_BASE_IDX 3 7696 #define regMPC_OUT2_CSC_C11_C12_A 0x0326 7697 #define regMPC_OUT2_CSC_C11_C12_A_BASE_IDX 3 7698 #define regMPC_OUT2_CSC_C13_C14_A 0x0327 7699 #define regMPC_OUT2_CSC_C13_C14_A_BASE_IDX 3 7700 #define regMPC_OUT2_CSC_C21_C22_A 0x0328 7701 #define regMPC_OUT2_CSC_C21_C22_A_BASE_IDX 3 7702 #define regMPC_OUT2_CSC_C23_C24_A 0x0329 7703 #define regMPC_OUT2_CSC_C23_C24_A_BASE_IDX 3 7704 #define regMPC_OUT2_CSC_C31_C32_A 0x032a 7705 #define regMPC_OUT2_CSC_C31_C32_A_BASE_IDX 3 7706 #define regMPC_OUT2_CSC_C33_C34_A 0x032b 7707 #define regMPC_OUT2_CSC_C33_C34_A_BASE_IDX 3 7708 #define regMPC_OUT2_CSC_C11_C12_B 0x032c 7709 #define regMPC_OUT2_CSC_C11_C12_B_BASE_IDX 3 7710 #define regMPC_OUT2_CSC_C13_C14_B 0x032d 7711 #define regMPC_OUT2_CSC_C13_C14_B_BASE_IDX 3 7712 #define regMPC_OUT2_CSC_C21_C22_B 0x032e 7713 #define regMPC_OUT2_CSC_C21_C22_B_BASE_IDX 3 7714 #define regMPC_OUT2_CSC_C23_C24_B 0x032f 7715 #define regMPC_OUT2_CSC_C23_C24_B_BASE_IDX 3 7716 #define regMPC_OUT2_CSC_C31_C32_B 0x0330 7717 #define regMPC_OUT2_CSC_C31_C32_B_BASE_IDX 3 7718 #define regMPC_OUT2_CSC_C33_C34_B 0x0331 7719 #define regMPC_OUT2_CSC_C33_C34_B_BASE_IDX 3 7720 #define regMPC_OUT3_CSC_MODE 0x0332 7721 #define regMPC_OUT3_CSC_MODE_BASE_IDX 3 7722 #define regMPC_OUT3_CSC_C11_C12_A 0x0333 7723 #define regMPC_OUT3_CSC_C11_C12_A_BASE_IDX 3 7724 #define regMPC_OUT3_CSC_C13_C14_A 0x0334 7725 #define regMPC_OUT3_CSC_C13_C14_A_BASE_IDX 3 7726 #define regMPC_OUT3_CSC_C21_C22_A 0x0335 7727 #define regMPC_OUT3_CSC_C21_C22_A_BASE_IDX 3 7728 #define regMPC_OUT3_CSC_C23_C24_A 0x0336 7729 #define regMPC_OUT3_CSC_C23_C24_A_BASE_IDX 3 7730 #define regMPC_OUT3_CSC_C31_C32_A 0x0337 7731 #define regMPC_OUT3_CSC_C31_C32_A_BASE_IDX 3 7732 #define regMPC_OUT3_CSC_C33_C34_A 0x0338 7733 #define regMPC_OUT3_CSC_C33_C34_A_BASE_IDX 3 7734 #define regMPC_OUT3_CSC_C11_C12_B 0x0339 7735 #define regMPC_OUT3_CSC_C11_C12_B_BASE_IDX 3 7736 #define regMPC_OUT3_CSC_C13_C14_B 0x033a 7737 #define regMPC_OUT3_CSC_C13_C14_B_BASE_IDX 3 7738 #define regMPC_OUT3_CSC_C21_C22_B 0x033b 7739 #define regMPC_OUT3_CSC_C21_C22_B_BASE_IDX 3 7740 #define regMPC_OUT3_CSC_C23_C24_B 0x033c 7741 #define regMPC_OUT3_CSC_C23_C24_B_BASE_IDX 3 7742 #define regMPC_OUT3_CSC_C31_C32_B 0x033d 7743 #define regMPC_OUT3_CSC_C31_C32_B_BASE_IDX 3 7744 #define regMPC_OUT3_CSC_C33_C34_B 0x033e 7745 #define regMPC_OUT3_CSC_C33_C34_B_BASE_IDX 3 7746 #define regMPC_OCSC_TEST_DEBUG_INDEX 0x035b 7747 #define regMPC_OCSC_TEST_DEBUG_INDEX_BASE_IDX 3 7748 #define regMPC_OCSC_TEST_DEBUG_DATA 0x035c 7749 #define regMPC_OCSC_TEST_DEBUG_DATA_BASE_IDX 3 7750 7751 // addressBlock: dcn_dcec_opp_abm0_dispdec 7752 // base address: 0x0 7753 #define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0e7a 7754 #define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 7755 #define regABM0_BL1_PWM_USER_LEVEL 0x0e7b 7756 #define regABM0_BL1_PWM_USER_LEVEL_BASE_IDX 3 7757 #define regABM0_BL1_PWM_TARGET_ABM_LEVEL 0x0e7c 7758 #define regABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 7759 #define regABM0_BL1_PWM_CURRENT_ABM_LEVEL 0x0e7d 7760 #define regABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 7761 #define regABM0_BL1_PWM_FINAL_DUTY_CYCLE 0x0e7e 7762 #define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 7763 #define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0e7f 7764 #define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 7765 #define regABM0_BL1_PWM_ABM_CNTL 0x0e80 7766 #define regABM0_BL1_PWM_ABM_CNTL_BASE_IDX 3 7767 #define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0e81 7768 #define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 7769 #define regABM0_BL1_PWM_GRP2_REG_LOCK 0x0e82 7770 #define regABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 7771 #define regABM0_DC_ABM1_CNTL 0x0e83 7772 #define regABM0_DC_ABM1_CNTL_BASE_IDX 3 7773 #define regABM0_DC_ABM1_IPCSC_COEFF_SEL 0x0e84 7774 #define regABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 7775 #define regABM0_DC_ABM1_ACE_PWL_CNTL 0x0e85 7776 #define regABM0_DC_ABM1_ACE_PWL_CNTL_BASE_IDX 3 7777 #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA 0x0e86 7778 #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA_BASE_IDX 3 7779 #define regABM0_DC_ABM1_ACE_THRES_DATA 0x0e87 7780 #define regABM0_DC_ABM1_ACE_THRES_DATA_BASE_IDX 3 7781 #define regABM0_DC_ABM1_ACE_CNTL_MISC 0x0e88 7782 #define regABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 7783 #define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0e8a 7784 #define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 7785 #define regABM0_DC_ABM1_HG_MISC_CTRL 0x0e8b 7786 #define regABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 7787 #define regABM0_DC_ABM1_LS_SUM_OF_LUMA 0x0e8c 7788 #define regABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 7789 #define regABM0_DC_ABM1_LS_MIN_MAX_LUMA 0x0e8d 7790 #define regABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 7791 #define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0e8e 7792 #define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 7793 #define regABM0_DC_ABM1_LS_PIXEL_COUNT 0x0e8f 7794 #define regABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 7795 #define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0e90 7796 #define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 7797 #define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0e91 7798 #define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 7799 #define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0e92 7800 #define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 7801 #define regABM0_DC_ABM1_HG_SAMPLE_RATE 0x0e93 7802 #define regABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 7803 #define regABM0_DC_ABM1_LS_SAMPLE_RATE 0x0e94 7804 #define regABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 7805 #define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0e95 7806 #define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 7807 #define regABM0_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG 0x0e96 7808 #define regABM0_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG_BASE_IDX 3 7809 #define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0e97 7810 #define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 7811 #define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0e98 7812 #define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 7813 #define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0e99 7814 #define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 7815 #define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0e9a 7816 #define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 7817 #define regABM0_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX 0x0e9b 7818 #define regABM0_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX_BASE_IDX 3 7819 #define regABM0_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX 0x0e9c 7820 #define regABM0_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX_BASE_IDX 3 7821 #define regABM0_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX 0x0e9d 7822 #define regABM0_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX_BASE_IDX 3 7823 #define regABM0_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX 0x0e9e 7824 #define regABM0_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX_BASE_IDX 3 7825 #define regABM0_DC_ABM1_HG_RESULT_INDEX 0x0e9f 7826 #define regABM0_DC_ABM1_HG_RESULT_INDEX_BASE_IDX 3 7827 #define regABM0_DC_ABM1_HG_RESULT_DATA 0x0ea0 7828 #define regABM0_DC_ABM1_HG_RESULT_DATA_BASE_IDX 3 7829 #define regABM0_DC_ABM1_BL_MASTER_LOCK 0x0ea1 7830 #define regABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 7831 7832 7833 // addressBlock: dcn_dcec_opp_abm1_dispdec 7834 // base address: 0x104 7835 #define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0ebb 7836 #define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 7837 #define regABM1_BL1_PWM_USER_LEVEL 0x0ebc 7838 #define regABM1_BL1_PWM_USER_LEVEL_BASE_IDX 3 7839 #define regABM1_BL1_PWM_TARGET_ABM_LEVEL 0x0ebd 7840 #define regABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 7841 #define regABM1_BL1_PWM_CURRENT_ABM_LEVEL 0x0ebe 7842 #define regABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 7843 #define regABM1_BL1_PWM_FINAL_DUTY_CYCLE 0x0ebf 7844 #define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 7845 #define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0ec0 7846 #define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 7847 #define regABM1_BL1_PWM_ABM_CNTL 0x0ec1 7848 #define regABM1_BL1_PWM_ABM_CNTL_BASE_IDX 3 7849 #define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0ec2 7850 #define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 7851 #define regABM1_BL1_PWM_GRP2_REG_LOCK 0x0ec3 7852 #define regABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 7853 #define regABM1_DC_ABM1_CNTL 0x0ec4 7854 #define regABM1_DC_ABM1_CNTL_BASE_IDX 3 7855 #define regABM1_DC_ABM1_IPCSC_COEFF_SEL 0x0ec5 7856 #define regABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 7857 #define regABM1_DC_ABM1_ACE_PWL_CNTL 0x0ec6 7858 #define regABM1_DC_ABM1_ACE_PWL_CNTL_BASE_IDX 3 7859 #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_DATA 0x0ec7 7860 #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_DATA_BASE_IDX 3 7861 #define regABM1_DC_ABM1_ACE_THRES_DATA 0x0ec8 7862 #define regABM1_DC_ABM1_ACE_THRES_DATA_BASE_IDX 3 7863 #define regABM1_DC_ABM1_ACE_CNTL_MISC 0x0ec9 7864 #define regABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 7865 #define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0ecb 7866 #define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 7867 #define regABM1_DC_ABM1_HG_MISC_CTRL 0x0ecc 7868 #define regABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 7869 #define regABM1_DC_ABM1_LS_SUM_OF_LUMA 0x0ecd 7870 #define regABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 7871 #define regABM1_DC_ABM1_LS_MIN_MAX_LUMA 0x0ece 7872 #define regABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 7873 #define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0ecf 7874 #define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 7875 #define regABM1_DC_ABM1_LS_PIXEL_COUNT 0x0ed0 7876 #define regABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 7877 #define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0ed1 7878 #define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 7879 #define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0ed2 7880 #define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 7881 #define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0ed3 7882 #define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 7883 #define regABM1_DC_ABM1_HG_SAMPLE_RATE 0x0ed4 7884 #define regABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 7885 #define regABM1_DC_ABM1_LS_SAMPLE_RATE 0x0ed5 7886 #define regABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 7887 #define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0ed6 7888 #define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 7889 #define regABM1_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG 0x0ed7 7890 #define regABM1_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG_BASE_IDX 3 7891 #define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0ed8 7892 #define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 7893 #define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0ed9 7894 #define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 7895 #define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0eda 7896 #define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 7897 #define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0edb 7898 #define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 7899 #define regABM1_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX 0x0edc 7900 #define regABM1_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX_BASE_IDX 3 7901 #define regABM1_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX 0x0edd 7902 #define regABM1_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX_BASE_IDX 3 7903 #define regABM1_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX 0x0ede 7904 #define regABM1_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX_BASE_IDX 3 7905 #define regABM1_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX 0x0edf 7906 #define regABM1_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX_BASE_IDX 3 7907 #define regABM1_DC_ABM1_HG_RESULT_INDEX 0x0ee0 7908 #define regABM1_DC_ABM1_HG_RESULT_INDEX_BASE_IDX 3 7909 #define regABM1_DC_ABM1_HG_RESULT_DATA 0x0ee1 7910 #define regABM1_DC_ABM1_HG_RESULT_DATA_BASE_IDX 3 7911 #define regABM1_DC_ABM1_BL_MASTER_LOCK 0x0ee2 7912 #define regABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 7913 7914 7915 // addressBlock: dcn_dcec_opp_abm2_dispdec 7916 // base address: 0x208 7917 #define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0efc 7918 #define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 7919 #define regABM2_BL1_PWM_USER_LEVEL 0x0efd 7920 #define regABM2_BL1_PWM_USER_LEVEL_BASE_IDX 3 7921 #define regABM2_BL1_PWM_TARGET_ABM_LEVEL 0x0efe 7922 #define regABM2_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 7923 #define regABM2_BL1_PWM_CURRENT_ABM_LEVEL 0x0eff 7924 #define regABM2_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 7925 #define regABM2_BL1_PWM_FINAL_DUTY_CYCLE 0x0f00 7926 #define regABM2_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 7927 #define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f01 7928 #define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 7929 #define regABM2_BL1_PWM_ABM_CNTL 0x0f02 7930 #define regABM2_BL1_PWM_ABM_CNTL_BASE_IDX 3 7931 #define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f03 7932 #define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 7933 #define regABM2_BL1_PWM_GRP2_REG_LOCK 0x0f04 7934 #define regABM2_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 7935 #define regABM2_DC_ABM1_CNTL 0x0f05 7936 #define regABM2_DC_ABM1_CNTL_BASE_IDX 3 7937 #define regABM2_DC_ABM1_IPCSC_COEFF_SEL 0x0f06 7938 #define regABM2_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 7939 #define regABM2_DC_ABM1_ACE_PWL_CNTL 0x0f07 7940 #define regABM2_DC_ABM1_ACE_PWL_CNTL_BASE_IDX 3 7941 #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_DATA 0x0f08 7942 #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_DATA_BASE_IDX 3 7943 #define regABM2_DC_ABM1_ACE_THRES_DATA 0x0f09 7944 #define regABM2_DC_ABM1_ACE_THRES_DATA_BASE_IDX 3 7945 #define regABM2_DC_ABM1_ACE_CNTL_MISC 0x0f0a 7946 #define regABM2_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 7947 #define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f0c 7948 #define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 7949 #define regABM2_DC_ABM1_HG_MISC_CTRL 0x0f0d 7950 #define regABM2_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 7951 #define regABM2_DC_ABM1_LS_SUM_OF_LUMA 0x0f0e 7952 #define regABM2_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 7953 #define regABM2_DC_ABM1_LS_MIN_MAX_LUMA 0x0f0f 7954 #define regABM2_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 7955 #define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f10 7956 #define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 7957 #define regABM2_DC_ABM1_LS_PIXEL_COUNT 0x0f11 7958 #define regABM2_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 7959 #define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f12 7960 #define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 7961 #define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f13 7962 #define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 7963 #define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f14 7964 #define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 7965 #define regABM2_DC_ABM1_HG_SAMPLE_RATE 0x0f15 7966 #define regABM2_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 7967 #define regABM2_DC_ABM1_LS_SAMPLE_RATE 0x0f16 7968 #define regABM2_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 7969 #define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f17 7970 #define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 7971 #define regABM2_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG 0x0f18 7972 #define regABM2_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG_BASE_IDX 3 7973 #define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f19 7974 #define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 7975 #define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f1a 7976 #define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 7977 #define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f1b 7978 #define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 7979 #define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f1c 7980 #define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 7981 #define regABM2_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX 0x0f1d 7982 #define regABM2_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX_BASE_IDX 3 7983 #define regABM2_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX 0x0f1e 7984 #define regABM2_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX_BASE_IDX 3 7985 #define regABM2_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX 0x0f1f 7986 #define regABM2_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX_BASE_IDX 3 7987 #define regABM2_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX 0x0f20 7988 #define regABM2_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX_BASE_IDX 3 7989 #define regABM2_DC_ABM1_HG_RESULT_INDEX 0x0f21 7990 #define regABM2_DC_ABM1_HG_RESULT_INDEX_BASE_IDX 3 7991 #define regABM2_DC_ABM1_HG_RESULT_DATA 0x0f22 7992 #define regABM2_DC_ABM1_HG_RESULT_DATA_BASE_IDX 3 7993 #define regABM2_DC_ABM1_BL_MASTER_LOCK 0x0f23 7994 #define regABM2_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 7995 7996 7997 // addressBlock: dcn_dcec_opp_abm3_dispdec 7998 // base address: 0x30c 7999 #define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0f3d 8000 #define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 8001 #define regABM3_BL1_PWM_USER_LEVEL 0x0f3e 8002 #define regABM3_BL1_PWM_USER_LEVEL_BASE_IDX 3 8003 #define regABM3_BL1_PWM_TARGET_ABM_LEVEL 0x0f3f 8004 #define regABM3_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 8005 #define regABM3_BL1_PWM_CURRENT_ABM_LEVEL 0x0f40 8006 #define regABM3_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 8007 #define regABM3_BL1_PWM_FINAL_DUTY_CYCLE 0x0f41 8008 #define regABM3_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 8009 #define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f42 8010 #define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 8011 #define regABM3_BL1_PWM_ABM_CNTL 0x0f43 8012 #define regABM3_BL1_PWM_ABM_CNTL_BASE_IDX 3 8013 #define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f44 8014 #define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 8015 #define regABM3_BL1_PWM_GRP2_REG_LOCK 0x0f45 8016 #define regABM3_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 8017 #define regABM3_DC_ABM1_CNTL 0x0f46 8018 #define regABM3_DC_ABM1_CNTL_BASE_IDX 3 8019 #define regABM3_DC_ABM1_IPCSC_COEFF_SEL 0x0f47 8020 #define regABM3_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 8021 #define regABM3_DC_ABM1_ACE_PWL_CNTL 0x0f48 8022 #define regABM3_DC_ABM1_ACE_PWL_CNTL_BASE_IDX 3 8023 #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_DATA 0x0f49 8024 #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_DATA_BASE_IDX 3 8025 #define regABM3_DC_ABM1_ACE_THRES_DATA 0x0f4a 8026 #define regABM3_DC_ABM1_ACE_THRES_DATA_BASE_IDX 3 8027 #define regABM3_DC_ABM1_ACE_CNTL_MISC 0x0f4b 8028 #define regABM3_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 8029 #define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f4d 8030 #define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 8031 #define regABM3_DC_ABM1_HG_MISC_CTRL 0x0f4e 8032 #define regABM3_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 8033 #define regABM3_DC_ABM1_LS_SUM_OF_LUMA 0x0f4f 8034 #define regABM3_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 8035 #define regABM3_DC_ABM1_LS_MIN_MAX_LUMA 0x0f50 8036 #define regABM3_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 8037 #define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f51 8038 #define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 8039 #define regABM3_DC_ABM1_LS_PIXEL_COUNT 0x0f52 8040 #define regABM3_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 8041 #define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f53 8042 #define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 8043 #define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f54 8044 #define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 8045 #define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f55 8046 #define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 8047 #define regABM3_DC_ABM1_HG_SAMPLE_RATE 0x0f56 8048 #define regABM3_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 8049 #define regABM3_DC_ABM1_LS_SAMPLE_RATE 0x0f57 8050 #define regABM3_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 8051 #define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f58 8052 #define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 8053 #define regABM3_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG 0x0f59 8054 #define regABM3_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG_BASE_IDX 3 8055 #define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f5a 8056 #define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 8057 #define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f5b 8058 #define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 8059 #define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f5c 8060 #define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 8061 #define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f5d 8062 #define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 8063 #define regABM3_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX 0x0f5e 8064 #define regABM3_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX_BASE_IDX 3 8065 #define regABM3_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX 0x0f5f 8066 #define regABM3_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX_BASE_IDX 3 8067 #define regABM3_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX 0x0f60 8068 #define regABM3_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX_BASE_IDX 3 8069 #define regABM3_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX 0x0f61 8070 #define regABM3_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX_BASE_IDX 3 8071 #define regABM3_DC_ABM1_HG_RESULT_INDEX 0x0f62 8072 #define regABM3_DC_ABM1_HG_RESULT_INDEX_BASE_IDX 3 8073 #define regABM3_DC_ABM1_HG_RESULT_DATA 0x0f63 8074 #define regABM3_DC_ABM1_HG_RESULT_DATA_BASE_IDX 3 8075 #define regABM3_DC_ABM1_BL_MASTER_LOCK 0x0f64 8076 #define regABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 8077 8078 8079 // addressBlock: dcn_dcec_opp_dpg0_dispdec 8080 // base address: 0x0 8081 #define regDPG0_DPG_CONTROL 0x1854 8082 #define regDPG0_DPG_CONTROL_BASE_IDX 2 8083 #define regDPG0_DPG_RAMP_CONTROL 0x1855 8084 #define regDPG0_DPG_RAMP_CONTROL_BASE_IDX 2 8085 #define regDPG0_DPG_DIMENSIONS 0x1856 8086 #define regDPG0_DPG_DIMENSIONS_BASE_IDX 2 8087 #define regDPG0_DPG_COLOUR_R_CR 0x1857 8088 #define regDPG0_DPG_COLOUR_R_CR_BASE_IDX 2 8089 #define regDPG0_DPG_COLOUR_G_Y 0x1858 8090 #define regDPG0_DPG_COLOUR_G_Y_BASE_IDX 2 8091 #define regDPG0_DPG_COLOUR_B_CB 0x1859 8092 #define regDPG0_DPG_COLOUR_B_CB_BASE_IDX 2 8093 #define regDPG0_DPG_OFFSET_SEGMENT 0x185a 8094 #define regDPG0_DPG_OFFSET_SEGMENT_BASE_IDX 2 8095 #define regDPG0_DPG_STATUS 0x185b 8096 #define regDPG0_DPG_STATUS_BASE_IDX 2 8097 8098 8099 // addressBlock: dcn_dcec_opp_fmt0_dispdec 8100 // base address: 0x0 8101 #define regFMT0_FMT_CLAMP_COMPONENT_R 0x183c 8102 #define regFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 8103 #define regFMT0_FMT_CLAMP_COMPONENT_G 0x183d 8104 #define regFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 8105 #define regFMT0_FMT_CLAMP_COMPONENT_B 0x183e 8106 #define regFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 8107 #define regFMT0_FMT_DYNAMIC_EXP_CNTL 0x183f 8108 #define regFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 8109 #define regFMT0_FMT_CONTROL 0x1840 8110 #define regFMT0_FMT_CONTROL_BASE_IDX 2 8111 #define regFMT0_FMT_BIT_DEPTH_CONTROL 0x1841 8112 #define regFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 8113 #define regFMT0_FMT_DITHER_RAND_R_SEED 0x1842 8114 #define regFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 8115 #define regFMT0_FMT_DITHER_RAND_G_SEED 0x1843 8116 #define regFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 8117 #define regFMT0_FMT_DITHER_RAND_B_SEED 0x1844 8118 #define regFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 8119 #define regFMT0_FMT_CLAMP_CNTL 0x1845 8120 #define regFMT0_FMT_CLAMP_CNTL_BASE_IDX 2 8121 #define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1846 8122 #define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 8123 #define regFMT0_FMT_MAP420_MEMORY_CONTROL 0x1847 8124 #define regFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 8125 #define regFMT0_FMT_422_CONTROL 0x1849 8126 #define regFMT0_FMT_422_CONTROL_BASE_IDX 2 8127 8128 8129 // addressBlock: dcn_dcec_opp_oppbuf0_dispdec 8130 // base address: 0x0 8131 #define regOPPBUF0_OPPBUF_CONTROL 0x1884 8132 #define regOPPBUF0_OPPBUF_CONTROL_BASE_IDX 2 8133 #define regOPPBUF0_OPPBUF_3D_PARAMETERS_0 0x1885 8134 #define regOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 8135 #define regOPPBUF0_OPPBUF_3D_PARAMETERS_1 0x1886 8136 #define regOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 8137 #define regOPPBUF0_OPPBUF_CONTROL1 0x1889 8138 #define regOPPBUF0_OPPBUF_CONTROL1_BASE_IDX 2 8139 8140 8141 // addressBlock: dcn_dcec_opp_opp_pipe0_dispdec 8142 // base address: 0x0 8143 #define regOPP_PIPE0_OPP_PIPE_CONTROL 0x188c 8144 #define regOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX 2 8145 8146 8147 // addressBlock: dcn_dcec_opp_opp_pipe_crc0_dispdec 8148 // base address: 0x0 8149 #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0x1891 8150 #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 8151 #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0x1892 8152 #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX 2 8153 #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 0x1893 8154 #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 8155 #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 0x1894 8156 #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 8157 #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 0x1895 8158 #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 8159 8160 8161 // addressBlock: dcn_dcec_opp_dpg1_dispdec 8162 // base address: 0x168 8163 #define regDPG1_DPG_CONTROL 0x18ae 8164 #define regDPG1_DPG_CONTROL_BASE_IDX 2 8165 #define regDPG1_DPG_RAMP_CONTROL 0x18af 8166 #define regDPG1_DPG_RAMP_CONTROL_BASE_IDX 2 8167 #define regDPG1_DPG_DIMENSIONS 0x18b0 8168 #define regDPG1_DPG_DIMENSIONS_BASE_IDX 2 8169 #define regDPG1_DPG_COLOUR_R_CR 0x18b1 8170 #define regDPG1_DPG_COLOUR_R_CR_BASE_IDX 2 8171 #define regDPG1_DPG_COLOUR_G_Y 0x18b2 8172 #define regDPG1_DPG_COLOUR_G_Y_BASE_IDX 2 8173 #define regDPG1_DPG_COLOUR_B_CB 0x18b3 8174 #define regDPG1_DPG_COLOUR_B_CB_BASE_IDX 2 8175 #define regDPG1_DPG_OFFSET_SEGMENT 0x18b4 8176 #define regDPG1_DPG_OFFSET_SEGMENT_BASE_IDX 2 8177 #define regDPG1_DPG_STATUS 0x18b5 8178 #define regDPG1_DPG_STATUS_BASE_IDX 2 8179 8180 8181 // addressBlock: dcn_dcec_opp_fmt1_dispdec 8182 // base address: 0x168 8183 #define regFMT1_FMT_CLAMP_COMPONENT_R 0x1896 8184 #define regFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 8185 #define regFMT1_FMT_CLAMP_COMPONENT_G 0x1897 8186 #define regFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 8187 #define regFMT1_FMT_CLAMP_COMPONENT_B 0x1898 8188 #define regFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 8189 #define regFMT1_FMT_DYNAMIC_EXP_CNTL 0x1899 8190 #define regFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 8191 #define regFMT1_FMT_CONTROL 0x189a 8192 #define regFMT1_FMT_CONTROL_BASE_IDX 2 8193 #define regFMT1_FMT_BIT_DEPTH_CONTROL 0x189b 8194 #define regFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 8195 #define regFMT1_FMT_DITHER_RAND_R_SEED 0x189c 8196 #define regFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 8197 #define regFMT1_FMT_DITHER_RAND_G_SEED 0x189d 8198 #define regFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 8199 #define regFMT1_FMT_DITHER_RAND_B_SEED 0x189e 8200 #define regFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 8201 #define regFMT1_FMT_CLAMP_CNTL 0x189f 8202 #define regFMT1_FMT_CLAMP_CNTL_BASE_IDX 2 8203 #define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18a0 8204 #define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 8205 #define regFMT1_FMT_MAP420_MEMORY_CONTROL 0x18a1 8206 #define regFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 8207 #define regFMT1_FMT_422_CONTROL 0x18a3 8208 #define regFMT1_FMT_422_CONTROL_BASE_IDX 2 8209 8210 8211 // addressBlock: dcn_dcec_opp_oppbuf1_dispdec 8212 // base address: 0x168 8213 #define regOPPBUF1_OPPBUF_CONTROL 0x18de 8214 #define regOPPBUF1_OPPBUF_CONTROL_BASE_IDX 2 8215 #define regOPPBUF1_OPPBUF_3D_PARAMETERS_0 0x18df 8216 #define regOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 8217 #define regOPPBUF1_OPPBUF_3D_PARAMETERS_1 0x18e0 8218 #define regOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 8219 #define regOPPBUF1_OPPBUF_CONTROL1 0x18e3 8220 #define regOPPBUF1_OPPBUF_CONTROL1_BASE_IDX 2 8221 8222 8223 // addressBlock: dcn_dcec_opp_opp_pipe1_dispdec 8224 // base address: 0x168 8225 #define regOPP_PIPE1_OPP_PIPE_CONTROL 0x18e6 8226 #define regOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX 2 8227 8228 8229 // addressBlock: dcn_dcec_opp_opp_pipe_crc1_dispdec 8230 // base address: 0x168 8231 #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0x18eb 8232 #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 8233 #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0x18ec 8234 #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX 2 8235 #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 0x18ed 8236 #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 8237 #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 0x18ee 8238 #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 8239 #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 0x18ef 8240 #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 8241 8242 8243 // addressBlock: dcn_dcec_opp_dpg2_dispdec 8244 // base address: 0x2d0 8245 #define regDPG2_DPG_CONTROL 0x1908 8246 #define regDPG2_DPG_CONTROL_BASE_IDX 2 8247 #define regDPG2_DPG_RAMP_CONTROL 0x1909 8248 #define regDPG2_DPG_RAMP_CONTROL_BASE_IDX 2 8249 #define regDPG2_DPG_DIMENSIONS 0x190a 8250 #define regDPG2_DPG_DIMENSIONS_BASE_IDX 2 8251 #define regDPG2_DPG_COLOUR_R_CR 0x190b 8252 #define regDPG2_DPG_COLOUR_R_CR_BASE_IDX 2 8253 #define regDPG2_DPG_COLOUR_G_Y 0x190c 8254 #define regDPG2_DPG_COLOUR_G_Y_BASE_IDX 2 8255 #define regDPG2_DPG_COLOUR_B_CB 0x190d 8256 #define regDPG2_DPG_COLOUR_B_CB_BASE_IDX 2 8257 #define regDPG2_DPG_OFFSET_SEGMENT 0x190e 8258 #define regDPG2_DPG_OFFSET_SEGMENT_BASE_IDX 2 8259 #define regDPG2_DPG_STATUS 0x190f 8260 #define regDPG2_DPG_STATUS_BASE_IDX 2 8261 8262 8263 // addressBlock: dcn_dcec_opp_fmt2_dispdec 8264 // base address: 0x2d0 8265 #define regFMT2_FMT_CLAMP_COMPONENT_R 0x18f0 8266 #define regFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 8267 #define regFMT2_FMT_CLAMP_COMPONENT_G 0x18f1 8268 #define regFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 8269 #define regFMT2_FMT_CLAMP_COMPONENT_B 0x18f2 8270 #define regFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 8271 #define regFMT2_FMT_DYNAMIC_EXP_CNTL 0x18f3 8272 #define regFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 8273 #define regFMT2_FMT_CONTROL 0x18f4 8274 #define regFMT2_FMT_CONTROL_BASE_IDX 2 8275 #define regFMT2_FMT_BIT_DEPTH_CONTROL 0x18f5 8276 #define regFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 8277 #define regFMT2_FMT_DITHER_RAND_R_SEED 0x18f6 8278 #define regFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 8279 #define regFMT2_FMT_DITHER_RAND_G_SEED 0x18f7 8280 #define regFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 8281 #define regFMT2_FMT_DITHER_RAND_B_SEED 0x18f8 8282 #define regFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 8283 #define regFMT2_FMT_CLAMP_CNTL 0x18f9 8284 #define regFMT2_FMT_CLAMP_CNTL_BASE_IDX 2 8285 #define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18fa 8286 #define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 8287 #define regFMT2_FMT_MAP420_MEMORY_CONTROL 0x18fb 8288 #define regFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 8289 #define regFMT2_FMT_422_CONTROL 0x18fd 8290 #define regFMT2_FMT_422_CONTROL_BASE_IDX 2 8291 8292 8293 // addressBlock: dcn_dcec_opp_oppbuf2_dispdec 8294 // base address: 0x2d0 8295 #define regOPPBUF2_OPPBUF_CONTROL 0x1938 8296 #define regOPPBUF2_OPPBUF_CONTROL_BASE_IDX 2 8297 #define regOPPBUF2_OPPBUF_3D_PARAMETERS_0 0x1939 8298 #define regOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 8299 #define regOPPBUF2_OPPBUF_3D_PARAMETERS_1 0x193a 8300 #define regOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 8301 #define regOPPBUF2_OPPBUF_CONTROL1 0x193d 8302 #define regOPPBUF2_OPPBUF_CONTROL1_BASE_IDX 2 8303 8304 8305 // addressBlock: dcn_dcec_opp_opp_pipe2_dispdec 8306 // base address: 0x2d0 8307 #define regOPP_PIPE2_OPP_PIPE_CONTROL 0x1940 8308 #define regOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX 2 8309 8310 8311 // addressBlock: dcn_dcec_opp_opp_pipe_crc2_dispdec 8312 // base address: 0x2d0 8313 #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL 0x1945 8314 #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 8315 #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK 0x1946 8316 #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX 2 8317 #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 0x1947 8318 #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 8319 #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 0x1948 8320 #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 8321 #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 0x1949 8322 #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 8323 8324 8325 // addressBlock: dcn_dcec_opp_dpg3_dispdec 8326 // base address: 0x438 8327 #define regDPG3_DPG_CONTROL 0x1962 8328 #define regDPG3_DPG_CONTROL_BASE_IDX 2 8329 #define regDPG3_DPG_RAMP_CONTROL 0x1963 8330 #define regDPG3_DPG_RAMP_CONTROL_BASE_IDX 2 8331 #define regDPG3_DPG_DIMENSIONS 0x1964 8332 #define regDPG3_DPG_DIMENSIONS_BASE_IDX 2 8333 #define regDPG3_DPG_COLOUR_R_CR 0x1965 8334 #define regDPG3_DPG_COLOUR_R_CR_BASE_IDX 2 8335 #define regDPG3_DPG_COLOUR_G_Y 0x1966 8336 #define regDPG3_DPG_COLOUR_G_Y_BASE_IDX 2 8337 #define regDPG3_DPG_COLOUR_B_CB 0x1967 8338 #define regDPG3_DPG_COLOUR_B_CB_BASE_IDX 2 8339 #define regDPG3_DPG_OFFSET_SEGMENT 0x1968 8340 #define regDPG3_DPG_OFFSET_SEGMENT_BASE_IDX 2 8341 #define regDPG3_DPG_STATUS 0x1969 8342 #define regDPG3_DPG_STATUS_BASE_IDX 2 8343 8344 8345 // addressBlock: dcn_dcec_opp_fmt3_dispdec 8346 // base address: 0x438 8347 #define regFMT3_FMT_CLAMP_COMPONENT_R 0x194a 8348 #define regFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 8349 #define regFMT3_FMT_CLAMP_COMPONENT_G 0x194b 8350 #define regFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 8351 #define regFMT3_FMT_CLAMP_COMPONENT_B 0x194c 8352 #define regFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 8353 #define regFMT3_FMT_DYNAMIC_EXP_CNTL 0x194d 8354 #define regFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 8355 #define regFMT3_FMT_CONTROL 0x194e 8356 #define regFMT3_FMT_CONTROL_BASE_IDX 2 8357 #define regFMT3_FMT_BIT_DEPTH_CONTROL 0x194f 8358 #define regFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 8359 #define regFMT3_FMT_DITHER_RAND_R_SEED 0x1950 8360 #define regFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 8361 #define regFMT3_FMT_DITHER_RAND_G_SEED 0x1951 8362 #define regFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 8363 #define regFMT3_FMT_DITHER_RAND_B_SEED 0x1952 8364 #define regFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 8365 #define regFMT3_FMT_CLAMP_CNTL 0x1953 8366 #define regFMT3_FMT_CLAMP_CNTL_BASE_IDX 2 8367 #define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1954 8368 #define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 8369 #define regFMT3_FMT_MAP420_MEMORY_CONTROL 0x1955 8370 #define regFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 8371 #define regFMT3_FMT_422_CONTROL 0x1957 8372 #define regFMT3_FMT_422_CONTROL_BASE_IDX 2 8373 8374 8375 // addressBlock: dcn_dcec_opp_oppbuf3_dispdec 8376 // base address: 0x438 8377 #define regOPPBUF3_OPPBUF_CONTROL 0x1992 8378 #define regOPPBUF3_OPPBUF_CONTROL_BASE_IDX 2 8379 #define regOPPBUF3_OPPBUF_3D_PARAMETERS_0 0x1993 8380 #define regOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 8381 #define regOPPBUF3_OPPBUF_3D_PARAMETERS_1 0x1994 8382 #define regOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 8383 #define regOPPBUF3_OPPBUF_CONTROL1 0x1997 8384 #define regOPPBUF3_OPPBUF_CONTROL1_BASE_IDX 2 8385 8386 8387 // addressBlock: dcn_dcec_opp_opp_pipe3_dispdec 8388 // base address: 0x438 8389 #define regOPP_PIPE3_OPP_PIPE_CONTROL 0x199a 8390 #define regOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX 2 8391 8392 8393 // addressBlock: dcn_dcec_opp_opp_pipe_crc3_dispdec 8394 // base address: 0x438 8395 #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL 0x199f 8396 #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 8397 #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK 0x19a0 8398 #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX 2 8399 #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 0x19a1 8400 #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 8401 #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 0x19a2 8402 #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 8403 #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 0x19a3 8404 #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 8405 8406 8407 // addressBlock: dcn_dcec_opp_dscrm0_dispdec 8408 // base address: 0x0 8409 #define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG 0x1a64 8410 #define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 8411 8412 8413 // addressBlock: dcn_dcec_opp_dscrm1_dispdec 8414 // base address: 0x4 8415 #define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG 0x1a65 8416 #define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 8417 8418 8419 // addressBlock: dcn_dcec_opp_dscrm2_dispdec 8420 // base address: 0x8 8421 #define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG 0x1a66 8422 #define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 8423 8424 8425 // addressBlock: dcn_dcec_opp_dscrm3_dispdec 8426 // base address: 0xc 8427 #define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG 0x1a67 8428 #define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 8429 8430 8431 // addressBlock: dcn_dcec_opp_opp_top_dispdec 8432 // base address: 0x0 8433 #define regOPP_TOP_CLK_CONTROL 0x1a5e 8434 #define regOPP_TOP_CLK_CONTROL_BASE_IDX 2 8435 #define regOPP_ABM_CONTROL 0x1a60 8436 #define regOPP_ABM_CONTROL_BASE_IDX 2 8437 8438 8439 // addressBlock: dcn_dcec_optc_odm0_dispdec 8440 // base address: 0x0 8441 #define regODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca 8442 #define regODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8443 #define regODM0_OPTC_DATA_SOURCE_SELECT 0x1acb 8444 #define regODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8445 #define regODM0_OPTC_DATA_FORMAT_CONTROL 0x1acc 8446 #define regODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8447 #define regODM0_OPTC_BYTES_PER_PIXEL 0x1acd 8448 #define regODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8449 #define regODM0_OPTC_WIDTH_CONTROL 0x1ace 8450 #define regODM0_OPTC_WIDTH_CONTROL_BASE_IDX 2 8451 #define regODM0_OPTC_WIDTH_CONTROL2 0x1acf 8452 #define regODM0_OPTC_WIDTH_CONTROL2_BASE_IDX 2 8453 #define regODM0_OPTC_INPUT_CLOCK_CONTROL 0x1ad0 8454 #define regODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8455 #define regODM0_OPTC_MEMORY_CONFIG 0x1ad1 8456 #define regODM0_OPTC_MEMORY_CONFIG_BASE_IDX 2 8457 #define regODM0_OPTC_INPUT_SPARE_REGISTER 0x1ad2 8458 #define regODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8459 8460 8461 // addressBlock: dcn_dcec_optc_odm1_dispdec 8462 // base address: 0x40 8463 #define regODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada 8464 #define regODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8465 #define regODM1_OPTC_DATA_SOURCE_SELECT 0x1adb 8466 #define regODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8467 #define regODM1_OPTC_DATA_FORMAT_CONTROL 0x1adc 8468 #define regODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8469 #define regODM1_OPTC_BYTES_PER_PIXEL 0x1add 8470 #define regODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8471 #define regODM1_OPTC_WIDTH_CONTROL 0x1ade 8472 #define regODM1_OPTC_WIDTH_CONTROL_BASE_IDX 2 8473 #define regODM1_OPTC_WIDTH_CONTROL2 0x1adf 8474 #define regODM1_OPTC_WIDTH_CONTROL2_BASE_IDX 2 8475 #define regODM1_OPTC_INPUT_CLOCK_CONTROL 0x1ae0 8476 #define regODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8477 #define regODM1_OPTC_MEMORY_CONFIG 0x1ae1 8478 #define regODM1_OPTC_MEMORY_CONFIG_BASE_IDX 2 8479 #define regODM1_OPTC_INPUT_SPARE_REGISTER 0x1ae2 8480 #define regODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8481 8482 8483 // addressBlock: dcn_dcec_optc_odm2_dispdec 8484 // base address: 0x80 8485 #define regODM2_OPTC_INPUT_GLOBAL_CONTROL 0x1aea 8486 #define regODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8487 #define regODM2_OPTC_DATA_SOURCE_SELECT 0x1aeb 8488 #define regODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8489 #define regODM2_OPTC_DATA_FORMAT_CONTROL 0x1aec 8490 #define regODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8491 #define regODM2_OPTC_BYTES_PER_PIXEL 0x1aed 8492 #define regODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8493 #define regODM2_OPTC_WIDTH_CONTROL 0x1aee 8494 #define regODM2_OPTC_WIDTH_CONTROL_BASE_IDX 2 8495 #define regODM2_OPTC_WIDTH_CONTROL2 0x1aef 8496 #define regODM2_OPTC_WIDTH_CONTROL2_BASE_IDX 2 8497 #define regODM2_OPTC_INPUT_CLOCK_CONTROL 0x1af0 8498 #define regODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8499 #define regODM2_OPTC_MEMORY_CONFIG 0x1af1 8500 #define regODM2_OPTC_MEMORY_CONFIG_BASE_IDX 2 8501 #define regODM2_OPTC_INPUT_SPARE_REGISTER 0x1af2 8502 #define regODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8503 8504 8505 // addressBlock: dcn_dcec_optc_odm3_dispdec 8506 // base address: 0xc0 8507 #define regODM3_OPTC_INPUT_GLOBAL_CONTROL 0x1afa 8508 #define regODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8509 #define regODM3_OPTC_DATA_SOURCE_SELECT 0x1afb 8510 #define regODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8511 #define regODM3_OPTC_DATA_FORMAT_CONTROL 0x1afc 8512 #define regODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8513 #define regODM3_OPTC_BYTES_PER_PIXEL 0x1afd 8514 #define regODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8515 #define regODM3_OPTC_WIDTH_CONTROL 0x1afe 8516 #define regODM3_OPTC_WIDTH_CONTROL_BASE_IDX 2 8517 #define regODM3_OPTC_WIDTH_CONTROL2 0x1aff 8518 #define regODM3_OPTC_WIDTH_CONTROL2_BASE_IDX 2 8519 #define regODM3_OPTC_INPUT_CLOCK_CONTROL 0x1b00 8520 #define regODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8521 #define regODM3_OPTC_MEMORY_CONFIG 0x1b01 8522 #define regODM3_OPTC_MEMORY_CONFIG_BASE_IDX 2 8523 #define regODM3_OPTC_INPUT_SPARE_REGISTER 0x1b02 8524 #define regODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8525 8526 8527 // addressBlock: dcn_dcec_optc_otg0_dispdec 8528 // base address: 0x0 8529 #define regOTG0_OTG_H_TOTAL 0x1b2a 8530 #define regOTG0_OTG_H_TOTAL_BASE_IDX 2 8531 #define regOTG0_OTG_H_BLANK_START_END 0x1b2b 8532 #define regOTG0_OTG_H_BLANK_START_END_BASE_IDX 2 8533 #define regOTG0_OTG_H_SYNC_A 0x1b2c 8534 #define regOTG0_OTG_H_SYNC_A_BASE_IDX 2 8535 #define regOTG0_OTG_H_SYNC_A_CNTL 0x1b2d 8536 #define regOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX 2 8537 #define regOTG0_OTG_H_TIMING_CNTL 0x1b2e 8538 #define regOTG0_OTG_H_TIMING_CNTL_BASE_IDX 2 8539 #define regOTG0_OTG_V_TOTAL 0x1b2f 8540 #define regOTG0_OTG_V_TOTAL_BASE_IDX 2 8541 #define regOTG0_OTG_V_TOTAL_MIN 0x1b30 8542 #define regOTG0_OTG_V_TOTAL_MIN_BASE_IDX 2 8543 #define regOTG0_OTG_V_TOTAL_MAX 0x1b31 8544 #define regOTG0_OTG_V_TOTAL_MAX_BASE_IDX 2 8545 #define regOTG0_OTG_V_TOTAL_MID 0x1b32 8546 #define regOTG0_OTG_V_TOTAL_MID_BASE_IDX 2 8547 #define regOTG0_OTG_V_TOTAL_CONTROL 0x1b33 8548 #define regOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX 2 8549 #define regOTG0_OTG_V_COUNT_STOP_CONTROL 0x1b34 8550 #define regOTG0_OTG_V_COUNT_STOP_CONTROL_BASE_IDX 2 8551 #define regOTG0_OTG_V_COUNT_STOP_CONTROL2 0x1b35 8552 #define regOTG0_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX 2 8553 #define regOTG0_OTG_V_TOTAL_INT_STATUS 0x1b36 8554 #define regOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 8555 #define regOTG0_OTG_VSYNC_NOM_INT_STATUS 0x1b37 8556 #define regOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 8557 #define regOTG0_OTG_V_BLANK_START_END 0x1b38 8558 #define regOTG0_OTG_V_BLANK_START_END_BASE_IDX 2 8559 #define regOTG0_OTG_V_SYNC_A 0x1b39 8560 #define regOTG0_OTG_V_SYNC_A_BASE_IDX 2 8561 #define regOTG0_OTG_V_SYNC_A_CNTL 0x1b3a 8562 #define regOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX 2 8563 #define regOTG0_OTG_TRIGA_CNTL 0x1b3b 8564 #define regOTG0_OTG_TRIGA_CNTL_BASE_IDX 2 8565 #define regOTG0_OTG_TRIGA_MANUAL_TRIG 0x1b3c 8566 #define regOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 8567 #define regOTG0_OTG_TRIGB_CNTL 0x1b3d 8568 #define regOTG0_OTG_TRIGB_CNTL_BASE_IDX 2 8569 #define regOTG0_OTG_TRIGB_MANUAL_TRIG 0x1b3e 8570 #define regOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 8571 #define regOTG0_OTG_FORCE_COUNT_NOW_CNTL 0x1b3f 8572 #define regOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 8573 #define regOTG0_OTG_FLOW_CONTROL 0x1b40 8574 #define regOTG0_OTG_FLOW_CONTROL_BASE_IDX 2 8575 #define regOTG0_OTG_STEREO_FORCE_NEXT_EYE 0x1b41 8576 #define regOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 8577 #define regOTG0_OTG_CONTROL 0x1b43 8578 #define regOTG0_OTG_CONTROL_BASE_IDX 2 8579 #define regOTG0_OTG_DLPC_CONTROL 0x1b44 8580 #define regOTG0_OTG_DLPC_CONTROL_BASE_IDX 2 8581 #define regOTG0_OTG_INTERLACE_CONTROL 0x1b45 8582 #define regOTG0_OTG_INTERLACE_CONTROL_BASE_IDX 2 8583 #define regOTG0_OTG_INTERLACE_STATUS 0x1b46 8584 #define regOTG0_OTG_INTERLACE_STATUS_BASE_IDX 2 8585 #define regOTG0_OTG_PIXEL_DATA_READBACK0 0x1b47 8586 #define regOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 8587 #define regOTG0_OTG_PIXEL_DATA_READBACK1 0x1b48 8588 #define regOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 8589 #define regOTG0_OTG_STATUS 0x1b49 8590 #define regOTG0_OTG_STATUS_BASE_IDX 2 8591 #define regOTG0_OTG_STATUS_POSITION 0x1b4a 8592 #define regOTG0_OTG_STATUS_POSITION_BASE_IDX 2 8593 #define regOTG0_OTG_LONG_VBLANK_STATUS 0x1b4b 8594 #define regOTG0_OTG_LONG_VBLANK_STATUS_BASE_IDX 2 8595 #define regOTG0_OTG_NOM_VERT_POSITION 0x1b4c 8596 #define regOTG0_OTG_NOM_VERT_POSITION_BASE_IDX 2 8597 #define regOTG0_OTG_STATUS_FRAME_COUNT 0x1b4d 8598 #define regOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 8599 #define regOTG0_OTG_STATUS_VF_COUNT 0x1b4e 8600 #define regOTG0_OTG_STATUS_VF_COUNT_BASE_IDX 2 8601 #define regOTG0_OTG_STATUS_HV_COUNT 0x1b4f 8602 #define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX 2 8603 #define regOTG0_OTG_COUNT_CONTROL 0x1b50 8604 #define regOTG0_OTG_COUNT_CONTROL_BASE_IDX 2 8605 #define regOTG0_OTG_COUNT_RESET 0x1b51 8606 #define regOTG0_OTG_COUNT_RESET_BASE_IDX 2 8607 #define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1b52 8608 #define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 8609 #define regOTG0_OTG_VERT_SYNC_CONTROL 0x1b53 8610 #define regOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 8611 #define regOTG0_OTG_STEREO_STATUS 0x1b54 8612 #define regOTG0_OTG_STEREO_STATUS_BASE_IDX 2 8613 #define regOTG0_OTG_STEREO_CONTROL 0x1b55 8614 #define regOTG0_OTG_STEREO_CONTROL_BASE_IDX 2 8615 #define regOTG0_OTG_SNAPSHOT_STATUS 0x1b56 8616 #define regOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX 2 8617 #define regOTG0_OTG_SNAPSHOT_CONTROL 0x1b57 8618 #define regOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 8619 #define regOTG0_OTG_SNAPSHOT_POSITION 0x1b58 8620 #define regOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX 2 8621 #define regOTG0_OTG_SNAPSHOT_FRAME 0x1b59 8622 #define regOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX 2 8623 #define regOTG0_OTG_INTERRUPT_CONTROL 0x1b5a 8624 #define regOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX 2 8625 #define regOTG0_OTG_UPDATE_LOCK 0x1b5b 8626 #define regOTG0_OTG_UPDATE_LOCK_BASE_IDX 2 8627 #define regOTG0_OTG_DOUBLE_BUFFER_CONTROL 0x1b5c 8628 #define regOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 8629 #define regOTG0_OTG_MASTER_EN 0x1b5d 8630 #define regOTG0_OTG_MASTER_EN_BASE_IDX 2 8631 #define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0x1b5f 8632 #define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 8633 #define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1b60 8634 #define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 8635 #define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0x1b61 8636 #define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 8637 #define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1b62 8638 #define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 8639 #define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0x1b63 8640 #define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 8641 #define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1b64 8642 #define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 8643 #define regOTG0_OTG_CRC_CNTL 0x1b65 8644 #define regOTG0_OTG_CRC_CNTL_BASE_IDX 2 8645 #define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0x1b66 8646 #define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 8647 #define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0x1b67 8648 #define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 8649 #define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0x1b68 8650 #define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 8651 #define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0x1b69 8652 #define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 8653 #define regOTG0_OTG_CRC0_DATA_RG 0x1b6a 8654 #define regOTG0_OTG_CRC0_DATA_RG_BASE_IDX 2 8655 #define regOTG0_OTG_CRC0_DATA_B 0x1b6b 8656 #define regOTG0_OTG_CRC0_DATA_B_BASE_IDX 2 8657 #define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0x1b6c 8658 #define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 8659 #define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0x1b6d 8660 #define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 8661 #define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0x1b6e 8662 #define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 8663 #define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0x1b6f 8664 #define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 8665 #define regOTG0_OTG_CRC1_DATA_RG 0x1b70 8666 #define regOTG0_OTG_CRC1_DATA_RG_BASE_IDX 2 8667 #define regOTG0_OTG_CRC1_DATA_B 0x1b71 8668 #define regOTG0_OTG_CRC1_DATA_B_BASE_IDX 2 8669 #define regOTG0_OTG_CRC2_DATA_RG 0x1b72 8670 #define regOTG0_OTG_CRC2_DATA_RG_BASE_IDX 2 8671 #define regOTG0_OTG_CRC2_DATA_B 0x1b73 8672 #define regOTG0_OTG_CRC2_DATA_B_BASE_IDX 2 8673 #define regOTG0_OTG_CRC3_DATA_RG 0x1b74 8674 #define regOTG0_OTG_CRC3_DATA_RG_BASE_IDX 2 8675 #define regOTG0_OTG_CRC3_DATA_B 0x1b75 8676 #define regOTG0_OTG_CRC3_DATA_B_BASE_IDX 2 8677 #define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0x1b76 8678 #define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 8679 #define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1b77 8680 #define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 8681 #define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK 0x1b78 8682 #define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 8683 #define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK 0x1b79 8684 #define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 8685 #define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK 0x1b7a 8686 #define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 8687 #define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK 0x1b7b 8688 #define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 8689 #define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK 0x1b7c 8690 #define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 8691 #define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK 0x1b7d 8692 #define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 8693 #define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK 0x1b7e 8694 #define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 8695 #define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK 0x1b7f 8696 #define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 8697 #define regOTG0_OTG_STATIC_SCREEN_CONTROL 0x1b80 8698 #define regOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 8699 #define regOTG0_OTG_3D_STRUCTURE_CONTROL 0x1b81 8700 #define regOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 8701 #define regOTG0_OTG_GSL_VSYNC_GAP 0x1b82 8702 #define regOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX 2 8703 #define regOTG0_OTG_MASTER_UPDATE_MODE 0x1b83 8704 #define regOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 8705 #define regOTG0_OTG_CLOCK_CONTROL 0x1b84 8706 #define regOTG0_OTG_CLOCK_CONTROL_BASE_IDX 2 8707 #define regOTG0_OTG_VSTARTUP_PARAM 0x1b85 8708 #define regOTG0_OTG_VSTARTUP_PARAM_BASE_IDX 2 8709 #define regOTG0_OTG_VUPDATE_PARAM 0x1b86 8710 #define regOTG0_OTG_VUPDATE_PARAM_BASE_IDX 2 8711 #define regOTG0_OTG_VREADY_PARAM 0x1b87 8712 #define regOTG0_OTG_VREADY_PARAM_BASE_IDX 2 8713 #define regOTG0_OTG_GLOBAL_SYNC_STATUS 0x1b88 8714 #define regOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 8715 #define regOTG0_OTG_MASTER_UPDATE_LOCK 0x1b89 8716 #define regOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 8717 #define regOTG0_OTG_GSL_CONTROL 0x1b8a 8718 #define regOTG0_OTG_GSL_CONTROL_BASE_IDX 2 8719 #define regOTG0_OTG_GSL_WINDOW_X 0x1b8b 8720 #define regOTG0_OTG_GSL_WINDOW_X_BASE_IDX 2 8721 #define regOTG0_OTG_GSL_WINDOW_Y 0x1b8c 8722 #define regOTG0_OTG_GSL_WINDOW_Y_BASE_IDX 2 8723 #define regOTG0_OTG_VUPDATE_KEEPOUT 0x1b8d 8724 #define regOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 8725 #define regOTG0_OTG_GLOBAL_CONTROL0 0x1b8e 8726 #define regOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX 2 8727 #define regOTG0_OTG_GLOBAL_CONTROL1 0x1b8f 8728 #define regOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX 2 8729 #define regOTG0_OTG_GLOBAL_CONTROL2 0x1b90 8730 #define regOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX 2 8731 #define regOTG0_OTG_GLOBAL_CONTROL3 0x1b91 8732 #define regOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX 2 8733 #define regOTG0_OTG_GLOBAL_CONTROL4 0x1b92 8734 #define regOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX 2 8735 #define regOTG0_OTG_TRIG_MANUAL_CONTROL 0x1b93 8736 #define regOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 8737 #define regOTG0_OTG_MANUAL_FLOW_CONTROL 0x1b94 8738 #define regOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 8739 #define regOTG0_OTG_DRR_TIMING_INT_STATUS 0x1b95 8740 #define regOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 8741 #define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE 0x1b96 8742 #define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 8743 #define regOTG0_OTG_DRR_V_TOTAL_CHANGE 0x1b97 8744 #define regOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 8745 #define regOTG0_OTG_DRR_TRIGGER_WINDOW 0x1b98 8746 #define regOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 8747 #define regOTG0_OTG_DRR_CONTROL 0x1b99 8748 #define regOTG0_OTG_DRR_CONTROL_BASE_IDX 2 8749 #define regOTG0_OTG_DRR_CONTOL2 0x1b9a 8750 #define regOTG0_OTG_DRR_CONTOL2_BASE_IDX 2 8751 #define regOTG0_OTG_M_CONST_DTO0 0x1b9b 8752 #define regOTG0_OTG_M_CONST_DTO0_BASE_IDX 2 8753 #define regOTG0_OTG_M_CONST_DTO1 0x1b9c 8754 #define regOTG0_OTG_M_CONST_DTO1_BASE_IDX 2 8755 #define regOTG0_OTG_REQUEST_CONTROL 0x1b9d 8756 #define regOTG0_OTG_REQUEST_CONTROL_BASE_IDX 2 8757 #define regOTG0_OTG_PIPE_UPDATE_STATUS 0x1b9e 8758 #define regOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 8759 #define regOTG0_OTG_PSTATE_REGISTER 0x1b9f 8760 #define regOTG0_OTG_PSTATE_REGISTER_BASE_IDX 2 8761 #define regOTG0_OTG_SPARE_REGISTER 0x1ba1 8762 #define regOTG0_OTG_SPARE_REGISTER_BASE_IDX 2 8763 8764 8765 // addressBlock: dcn_dcec_optc_otg1_dispdec 8766 // base address: 0x200 8767 #define regOTG1_OTG_H_TOTAL 0x1baa 8768 #define regOTG1_OTG_H_TOTAL_BASE_IDX 2 8769 #define regOTG1_OTG_H_BLANK_START_END 0x1bab 8770 #define regOTG1_OTG_H_BLANK_START_END_BASE_IDX 2 8771 #define regOTG1_OTG_H_SYNC_A 0x1bac 8772 #define regOTG1_OTG_H_SYNC_A_BASE_IDX 2 8773 #define regOTG1_OTG_H_SYNC_A_CNTL 0x1bad 8774 #define regOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX 2 8775 #define regOTG1_OTG_H_TIMING_CNTL 0x1bae 8776 #define regOTG1_OTG_H_TIMING_CNTL_BASE_IDX 2 8777 #define regOTG1_OTG_V_TOTAL 0x1baf 8778 #define regOTG1_OTG_V_TOTAL_BASE_IDX 2 8779 #define regOTG1_OTG_V_TOTAL_MIN 0x1bb0 8780 #define regOTG1_OTG_V_TOTAL_MIN_BASE_IDX 2 8781 #define regOTG1_OTG_V_TOTAL_MAX 0x1bb1 8782 #define regOTG1_OTG_V_TOTAL_MAX_BASE_IDX 2 8783 #define regOTG1_OTG_V_TOTAL_MID 0x1bb2 8784 #define regOTG1_OTG_V_TOTAL_MID_BASE_IDX 2 8785 #define regOTG1_OTG_V_TOTAL_CONTROL 0x1bb3 8786 #define regOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX 2 8787 #define regOTG1_OTG_V_COUNT_STOP_CONTROL 0x1bb4 8788 #define regOTG1_OTG_V_COUNT_STOP_CONTROL_BASE_IDX 2 8789 #define regOTG1_OTG_V_COUNT_STOP_CONTROL2 0x1bb5 8790 #define regOTG1_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX 2 8791 #define regOTG1_OTG_V_TOTAL_INT_STATUS 0x1bb6 8792 #define regOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 8793 #define regOTG1_OTG_VSYNC_NOM_INT_STATUS 0x1bb7 8794 #define regOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 8795 #define regOTG1_OTG_V_BLANK_START_END 0x1bb8 8796 #define regOTG1_OTG_V_BLANK_START_END_BASE_IDX 2 8797 #define regOTG1_OTG_V_SYNC_A 0x1bb9 8798 #define regOTG1_OTG_V_SYNC_A_BASE_IDX 2 8799 #define regOTG1_OTG_V_SYNC_A_CNTL 0x1bba 8800 #define regOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX 2 8801 #define regOTG1_OTG_TRIGA_CNTL 0x1bbb 8802 #define regOTG1_OTG_TRIGA_CNTL_BASE_IDX 2 8803 #define regOTG1_OTG_TRIGA_MANUAL_TRIG 0x1bbc 8804 #define regOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 8805 #define regOTG1_OTG_TRIGB_CNTL 0x1bbd 8806 #define regOTG1_OTG_TRIGB_CNTL_BASE_IDX 2 8807 #define regOTG1_OTG_TRIGB_MANUAL_TRIG 0x1bbe 8808 #define regOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 8809 #define regOTG1_OTG_FORCE_COUNT_NOW_CNTL 0x1bbf 8810 #define regOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 8811 #define regOTG1_OTG_FLOW_CONTROL 0x1bc0 8812 #define regOTG1_OTG_FLOW_CONTROL_BASE_IDX 2 8813 #define regOTG1_OTG_STEREO_FORCE_NEXT_EYE 0x1bc1 8814 #define regOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 8815 #define regOTG1_OTG_CONTROL 0x1bc3 8816 #define regOTG1_OTG_CONTROL_BASE_IDX 2 8817 #define regOTG1_OTG_DLPC_CONTROL 0x1bc4 8818 #define regOTG1_OTG_DLPC_CONTROL_BASE_IDX 2 8819 #define regOTG1_OTG_INTERLACE_CONTROL 0x1bc5 8820 #define regOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2 8821 #define regOTG1_OTG_INTERLACE_STATUS 0x1bc6 8822 #define regOTG1_OTG_INTERLACE_STATUS_BASE_IDX 2 8823 #define regOTG1_OTG_PIXEL_DATA_READBACK0 0x1bc7 8824 #define regOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 8825 #define regOTG1_OTG_PIXEL_DATA_READBACK1 0x1bc8 8826 #define regOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 8827 #define regOTG1_OTG_STATUS 0x1bc9 8828 #define regOTG1_OTG_STATUS_BASE_IDX 2 8829 #define regOTG1_OTG_STATUS_POSITION 0x1bca 8830 #define regOTG1_OTG_STATUS_POSITION_BASE_IDX 2 8831 #define regOTG1_OTG_LONG_VBLANK_STATUS 0x1bcb 8832 #define regOTG1_OTG_LONG_VBLANK_STATUS_BASE_IDX 2 8833 #define regOTG1_OTG_NOM_VERT_POSITION 0x1bcc 8834 #define regOTG1_OTG_NOM_VERT_POSITION_BASE_IDX 2 8835 #define regOTG1_OTG_STATUS_FRAME_COUNT 0x1bcd 8836 #define regOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 8837 #define regOTG1_OTG_STATUS_VF_COUNT 0x1bce 8838 #define regOTG1_OTG_STATUS_VF_COUNT_BASE_IDX 2 8839 #define regOTG1_OTG_STATUS_HV_COUNT 0x1bcf 8840 #define regOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 2 8841 #define regOTG1_OTG_COUNT_CONTROL 0x1bd0 8842 #define regOTG1_OTG_COUNT_CONTROL_BASE_IDX 2 8843 #define regOTG1_OTG_COUNT_RESET 0x1bd1 8844 #define regOTG1_OTG_COUNT_RESET_BASE_IDX 2 8845 #define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bd2 8846 #define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 8847 #define regOTG1_OTG_VERT_SYNC_CONTROL 0x1bd3 8848 #define regOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 8849 #define regOTG1_OTG_STEREO_STATUS 0x1bd4 8850 #define regOTG1_OTG_STEREO_STATUS_BASE_IDX 2 8851 #define regOTG1_OTG_STEREO_CONTROL 0x1bd5 8852 #define regOTG1_OTG_STEREO_CONTROL_BASE_IDX 2 8853 #define regOTG1_OTG_SNAPSHOT_STATUS 0x1bd6 8854 #define regOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX 2 8855 #define regOTG1_OTG_SNAPSHOT_CONTROL 0x1bd7 8856 #define regOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 8857 #define regOTG1_OTG_SNAPSHOT_POSITION 0x1bd8 8858 #define regOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX 2 8859 #define regOTG1_OTG_SNAPSHOT_FRAME 0x1bd9 8860 #define regOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX 2 8861 #define regOTG1_OTG_INTERRUPT_CONTROL 0x1bda 8862 #define regOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX 2 8863 #define regOTG1_OTG_UPDATE_LOCK 0x1bdb 8864 #define regOTG1_OTG_UPDATE_LOCK_BASE_IDX 2 8865 #define regOTG1_OTG_DOUBLE_BUFFER_CONTROL 0x1bdc 8866 #define regOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 8867 #define regOTG1_OTG_MASTER_EN 0x1bdd 8868 #define regOTG1_OTG_MASTER_EN_BASE_IDX 2 8869 #define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0x1bdf 8870 #define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 8871 #define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1be0 8872 #define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 8873 #define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0x1be1 8874 #define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 8875 #define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1be2 8876 #define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 8877 #define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0x1be3 8878 #define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 8879 #define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1be4 8880 #define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 8881 #define regOTG1_OTG_CRC_CNTL 0x1be5 8882 #define regOTG1_OTG_CRC_CNTL_BASE_IDX 2 8883 #define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0x1be6 8884 #define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 8885 #define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0x1be7 8886 #define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 8887 #define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0x1be8 8888 #define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 8889 #define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0x1be9 8890 #define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 8891 #define regOTG1_OTG_CRC0_DATA_RG 0x1bea 8892 #define regOTG1_OTG_CRC0_DATA_RG_BASE_IDX 2 8893 #define regOTG1_OTG_CRC0_DATA_B 0x1beb 8894 #define regOTG1_OTG_CRC0_DATA_B_BASE_IDX 2 8895 #define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0x1bec 8896 #define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 8897 #define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0x1bed 8898 #define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 8899 #define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0x1bee 8900 #define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 8901 #define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0x1bef 8902 #define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 8903 #define regOTG1_OTG_CRC1_DATA_RG 0x1bf0 8904 #define regOTG1_OTG_CRC1_DATA_RG_BASE_IDX 2 8905 #define regOTG1_OTG_CRC1_DATA_B 0x1bf1 8906 #define regOTG1_OTG_CRC1_DATA_B_BASE_IDX 2 8907 #define regOTG1_OTG_CRC2_DATA_RG 0x1bf2 8908 #define regOTG1_OTG_CRC2_DATA_RG_BASE_IDX 2 8909 #define regOTG1_OTG_CRC2_DATA_B 0x1bf3 8910 #define regOTG1_OTG_CRC2_DATA_B_BASE_IDX 2 8911 #define regOTG1_OTG_CRC3_DATA_RG 0x1bf4 8912 #define regOTG1_OTG_CRC3_DATA_RG_BASE_IDX 2 8913 #define regOTG1_OTG_CRC3_DATA_B 0x1bf5 8914 #define regOTG1_OTG_CRC3_DATA_B_BASE_IDX 2 8915 #define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0x1bf6 8916 #define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 8917 #define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1bf7 8918 #define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 8919 #define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK 0x1bf8 8920 #define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 8921 #define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK 0x1bf9 8922 #define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 8923 #define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK 0x1bfa 8924 #define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 8925 #define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK 0x1bfb 8926 #define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 8927 #define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK 0x1bfc 8928 #define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 8929 #define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK 0x1bfd 8930 #define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 8931 #define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK 0x1bfe 8932 #define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 8933 #define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK 0x1bff 8934 #define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 8935 #define regOTG1_OTG_STATIC_SCREEN_CONTROL 0x1c00 8936 #define regOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 8937 #define regOTG1_OTG_3D_STRUCTURE_CONTROL 0x1c01 8938 #define regOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 8939 #define regOTG1_OTG_GSL_VSYNC_GAP 0x1c02 8940 #define regOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX 2 8941 #define regOTG1_OTG_MASTER_UPDATE_MODE 0x1c03 8942 #define regOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 8943 #define regOTG1_OTG_CLOCK_CONTROL 0x1c04 8944 #define regOTG1_OTG_CLOCK_CONTROL_BASE_IDX 2 8945 #define regOTG1_OTG_VSTARTUP_PARAM 0x1c05 8946 #define regOTG1_OTG_VSTARTUP_PARAM_BASE_IDX 2 8947 #define regOTG1_OTG_VUPDATE_PARAM 0x1c06 8948 #define regOTG1_OTG_VUPDATE_PARAM_BASE_IDX 2 8949 #define regOTG1_OTG_VREADY_PARAM 0x1c07 8950 #define regOTG1_OTG_VREADY_PARAM_BASE_IDX 2 8951 #define regOTG1_OTG_GLOBAL_SYNC_STATUS 0x1c08 8952 #define regOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 8953 #define regOTG1_OTG_MASTER_UPDATE_LOCK 0x1c09 8954 #define regOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 8955 #define regOTG1_OTG_GSL_CONTROL 0x1c0a 8956 #define regOTG1_OTG_GSL_CONTROL_BASE_IDX 2 8957 #define regOTG1_OTG_GSL_WINDOW_X 0x1c0b 8958 #define regOTG1_OTG_GSL_WINDOW_X_BASE_IDX 2 8959 #define regOTG1_OTG_GSL_WINDOW_Y 0x1c0c 8960 #define regOTG1_OTG_GSL_WINDOW_Y_BASE_IDX 2 8961 #define regOTG1_OTG_VUPDATE_KEEPOUT 0x1c0d 8962 #define regOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 8963 #define regOTG1_OTG_GLOBAL_CONTROL0 0x1c0e 8964 #define regOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX 2 8965 #define regOTG1_OTG_GLOBAL_CONTROL1 0x1c0f 8966 #define regOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX 2 8967 #define regOTG1_OTG_GLOBAL_CONTROL2 0x1c10 8968 #define regOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX 2 8969 #define regOTG1_OTG_GLOBAL_CONTROL3 0x1c11 8970 #define regOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX 2 8971 #define regOTG1_OTG_GLOBAL_CONTROL4 0x1c12 8972 #define regOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX 2 8973 #define regOTG1_OTG_TRIG_MANUAL_CONTROL 0x1c13 8974 #define regOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 8975 #define regOTG1_OTG_MANUAL_FLOW_CONTROL 0x1c14 8976 #define regOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 8977 #define regOTG1_OTG_DRR_TIMING_INT_STATUS 0x1c15 8978 #define regOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 8979 #define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c16 8980 #define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 8981 #define regOTG1_OTG_DRR_V_TOTAL_CHANGE 0x1c17 8982 #define regOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 8983 #define regOTG1_OTG_DRR_TRIGGER_WINDOW 0x1c18 8984 #define regOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 8985 #define regOTG1_OTG_DRR_CONTROL 0x1c19 8986 #define regOTG1_OTG_DRR_CONTROL_BASE_IDX 2 8987 #define regOTG1_OTG_DRR_CONTOL2 0x1c1a 8988 #define regOTG1_OTG_DRR_CONTOL2_BASE_IDX 2 8989 #define regOTG1_OTG_M_CONST_DTO0 0x1c1b 8990 #define regOTG1_OTG_M_CONST_DTO0_BASE_IDX 2 8991 #define regOTG1_OTG_M_CONST_DTO1 0x1c1c 8992 #define regOTG1_OTG_M_CONST_DTO1_BASE_IDX 2 8993 #define regOTG1_OTG_REQUEST_CONTROL 0x1c1d 8994 #define regOTG1_OTG_REQUEST_CONTROL_BASE_IDX 2 8995 #define regOTG1_OTG_PIPE_UPDATE_STATUS 0x1c1e 8996 #define regOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 8997 #define regOTG1_OTG_PSTATE_REGISTER 0x1c1f 8998 #define regOTG1_OTG_PSTATE_REGISTER_BASE_IDX 2 8999 #define regOTG1_OTG_SPARE_REGISTER 0x1c21 9000 #define regOTG1_OTG_SPARE_REGISTER_BASE_IDX 2 9001 9002 9003 // addressBlock: dcn_dcec_optc_otg2_dispdec 9004 // base address: 0x400 9005 #define regOTG2_OTG_H_TOTAL 0x1c2a 9006 #define regOTG2_OTG_H_TOTAL_BASE_IDX 2 9007 #define regOTG2_OTG_H_BLANK_START_END 0x1c2b 9008 #define regOTG2_OTG_H_BLANK_START_END_BASE_IDX 2 9009 #define regOTG2_OTG_H_SYNC_A 0x1c2c 9010 #define regOTG2_OTG_H_SYNC_A_BASE_IDX 2 9011 #define regOTG2_OTG_H_SYNC_A_CNTL 0x1c2d 9012 #define regOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX 2 9013 #define regOTG2_OTG_H_TIMING_CNTL 0x1c2e 9014 #define regOTG2_OTG_H_TIMING_CNTL_BASE_IDX 2 9015 #define regOTG2_OTG_V_TOTAL 0x1c2f 9016 #define regOTG2_OTG_V_TOTAL_BASE_IDX 2 9017 #define regOTG2_OTG_V_TOTAL_MIN 0x1c30 9018 #define regOTG2_OTG_V_TOTAL_MIN_BASE_IDX 2 9019 #define regOTG2_OTG_V_TOTAL_MAX 0x1c31 9020 #define regOTG2_OTG_V_TOTAL_MAX_BASE_IDX 2 9021 #define regOTG2_OTG_V_TOTAL_MID 0x1c32 9022 #define regOTG2_OTG_V_TOTAL_MID_BASE_IDX 2 9023 #define regOTG2_OTG_V_TOTAL_CONTROL 0x1c33 9024 #define regOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX 2 9025 #define regOTG2_OTG_V_COUNT_STOP_CONTROL 0x1c34 9026 #define regOTG2_OTG_V_COUNT_STOP_CONTROL_BASE_IDX 2 9027 #define regOTG2_OTG_V_COUNT_STOP_CONTROL2 0x1c35 9028 #define regOTG2_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX 2 9029 #define regOTG2_OTG_V_TOTAL_INT_STATUS 0x1c36 9030 #define regOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 9031 #define regOTG2_OTG_VSYNC_NOM_INT_STATUS 0x1c37 9032 #define regOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 9033 #define regOTG2_OTG_V_BLANK_START_END 0x1c38 9034 #define regOTG2_OTG_V_BLANK_START_END_BASE_IDX 2 9035 #define regOTG2_OTG_V_SYNC_A 0x1c39 9036 #define regOTG2_OTG_V_SYNC_A_BASE_IDX 2 9037 #define regOTG2_OTG_V_SYNC_A_CNTL 0x1c3a 9038 #define regOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX 2 9039 #define regOTG2_OTG_TRIGA_CNTL 0x1c3b 9040 #define regOTG2_OTG_TRIGA_CNTL_BASE_IDX 2 9041 #define regOTG2_OTG_TRIGA_MANUAL_TRIG 0x1c3c 9042 #define regOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 9043 #define regOTG2_OTG_TRIGB_CNTL 0x1c3d 9044 #define regOTG2_OTG_TRIGB_CNTL_BASE_IDX 2 9045 #define regOTG2_OTG_TRIGB_MANUAL_TRIG 0x1c3e 9046 #define regOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 9047 #define regOTG2_OTG_FORCE_COUNT_NOW_CNTL 0x1c3f 9048 #define regOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 9049 #define regOTG2_OTG_FLOW_CONTROL 0x1c40 9050 #define regOTG2_OTG_FLOW_CONTROL_BASE_IDX 2 9051 #define regOTG2_OTG_STEREO_FORCE_NEXT_EYE 0x1c41 9052 #define regOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 9053 #define regOTG2_OTG_CONTROL 0x1c43 9054 #define regOTG2_OTG_CONTROL_BASE_IDX 2 9055 #define regOTG2_OTG_DLPC_CONTROL 0x1c44 9056 #define regOTG2_OTG_DLPC_CONTROL_BASE_IDX 2 9057 #define regOTG2_OTG_INTERLACE_CONTROL 0x1c45 9058 #define regOTG2_OTG_INTERLACE_CONTROL_BASE_IDX 2 9059 #define regOTG2_OTG_INTERLACE_STATUS 0x1c46 9060 #define regOTG2_OTG_INTERLACE_STATUS_BASE_IDX 2 9061 #define regOTG2_OTG_PIXEL_DATA_READBACK0 0x1c47 9062 #define regOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 9063 #define regOTG2_OTG_PIXEL_DATA_READBACK1 0x1c48 9064 #define regOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 9065 #define regOTG2_OTG_STATUS 0x1c49 9066 #define regOTG2_OTG_STATUS_BASE_IDX 2 9067 #define regOTG2_OTG_STATUS_POSITION 0x1c4a 9068 #define regOTG2_OTG_STATUS_POSITION_BASE_IDX 2 9069 #define regOTG2_OTG_LONG_VBLANK_STATUS 0x1c4b 9070 #define regOTG2_OTG_LONG_VBLANK_STATUS_BASE_IDX 2 9071 #define regOTG2_OTG_NOM_VERT_POSITION 0x1c4c 9072 #define regOTG2_OTG_NOM_VERT_POSITION_BASE_IDX 2 9073 #define regOTG2_OTG_STATUS_FRAME_COUNT 0x1c4d 9074 #define regOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 9075 #define regOTG2_OTG_STATUS_VF_COUNT 0x1c4e 9076 #define regOTG2_OTG_STATUS_VF_COUNT_BASE_IDX 2 9077 #define regOTG2_OTG_STATUS_HV_COUNT 0x1c4f 9078 #define regOTG2_OTG_STATUS_HV_COUNT_BASE_IDX 2 9079 #define regOTG2_OTG_COUNT_CONTROL 0x1c50 9080 #define regOTG2_OTG_COUNT_CONTROL_BASE_IDX 2 9081 #define regOTG2_OTG_COUNT_RESET 0x1c51 9082 #define regOTG2_OTG_COUNT_RESET_BASE_IDX 2 9083 #define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1c52 9084 #define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 9085 #define regOTG2_OTG_VERT_SYNC_CONTROL 0x1c53 9086 #define regOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 9087 #define regOTG2_OTG_STEREO_STATUS 0x1c54 9088 #define regOTG2_OTG_STEREO_STATUS_BASE_IDX 2 9089 #define regOTG2_OTG_STEREO_CONTROL 0x1c55 9090 #define regOTG2_OTG_STEREO_CONTROL_BASE_IDX 2 9091 #define regOTG2_OTG_SNAPSHOT_STATUS 0x1c56 9092 #define regOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX 2 9093 #define regOTG2_OTG_SNAPSHOT_CONTROL 0x1c57 9094 #define regOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 9095 #define regOTG2_OTG_SNAPSHOT_POSITION 0x1c58 9096 #define regOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX 2 9097 #define regOTG2_OTG_SNAPSHOT_FRAME 0x1c59 9098 #define regOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX 2 9099 #define regOTG2_OTG_INTERRUPT_CONTROL 0x1c5a 9100 #define regOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX 2 9101 #define regOTG2_OTG_UPDATE_LOCK 0x1c5b 9102 #define regOTG2_OTG_UPDATE_LOCK_BASE_IDX 2 9103 #define regOTG2_OTG_DOUBLE_BUFFER_CONTROL 0x1c5c 9104 #define regOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 9105 #define regOTG2_OTG_MASTER_EN 0x1c5d 9106 #define regOTG2_OTG_MASTER_EN_BASE_IDX 2 9107 #define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION 0x1c5f 9108 #define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 9109 #define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1c60 9110 #define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 9111 #define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION 0x1c61 9112 #define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 9113 #define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1c62 9114 #define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 9115 #define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION 0x1c63 9116 #define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 9117 #define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1c64 9118 #define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 9119 #define regOTG2_OTG_CRC_CNTL 0x1c65 9120 #define regOTG2_OTG_CRC_CNTL_BASE_IDX 2 9121 #define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL 0x1c66 9122 #define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 9123 #define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL 0x1c67 9124 #define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 9125 #define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL 0x1c68 9126 #define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 9127 #define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL 0x1c69 9128 #define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 9129 #define regOTG2_OTG_CRC0_DATA_RG 0x1c6a 9130 #define regOTG2_OTG_CRC0_DATA_RG_BASE_IDX 2 9131 #define regOTG2_OTG_CRC0_DATA_B 0x1c6b 9132 #define regOTG2_OTG_CRC0_DATA_B_BASE_IDX 2 9133 #define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL 0x1c6c 9134 #define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 9135 #define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL 0x1c6d 9136 #define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 9137 #define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL 0x1c6e 9138 #define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 9139 #define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL 0x1c6f 9140 #define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 9141 #define regOTG2_OTG_CRC1_DATA_RG 0x1c70 9142 #define regOTG2_OTG_CRC1_DATA_RG_BASE_IDX 2 9143 #define regOTG2_OTG_CRC1_DATA_B 0x1c71 9144 #define regOTG2_OTG_CRC1_DATA_B_BASE_IDX 2 9145 #define regOTG2_OTG_CRC2_DATA_RG 0x1c72 9146 #define regOTG2_OTG_CRC2_DATA_RG_BASE_IDX 2 9147 #define regOTG2_OTG_CRC2_DATA_B 0x1c73 9148 #define regOTG2_OTG_CRC2_DATA_B_BASE_IDX 2 9149 #define regOTG2_OTG_CRC3_DATA_RG 0x1c74 9150 #define regOTG2_OTG_CRC3_DATA_RG_BASE_IDX 2 9151 #define regOTG2_OTG_CRC3_DATA_B 0x1c75 9152 #define regOTG2_OTG_CRC3_DATA_B_BASE_IDX 2 9153 #define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK 0x1c76 9154 #define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 9155 #define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1c77 9156 #define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 9157 #define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK 0x1c78 9158 #define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 9159 #define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK 0x1c79 9160 #define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 9161 #define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK 0x1c7a 9162 #define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 9163 #define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK 0x1c7b 9164 #define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 9165 #define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK 0x1c7c 9166 #define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 9167 #define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK 0x1c7d 9168 #define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 9169 #define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK 0x1c7e 9170 #define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 9171 #define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK 0x1c7f 9172 #define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 9173 #define regOTG2_OTG_STATIC_SCREEN_CONTROL 0x1c80 9174 #define regOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 9175 #define regOTG2_OTG_3D_STRUCTURE_CONTROL 0x1c81 9176 #define regOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 9177 #define regOTG2_OTG_GSL_VSYNC_GAP 0x1c82 9178 #define regOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX 2 9179 #define regOTG2_OTG_MASTER_UPDATE_MODE 0x1c83 9180 #define regOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 9181 #define regOTG2_OTG_CLOCK_CONTROL 0x1c84 9182 #define regOTG2_OTG_CLOCK_CONTROL_BASE_IDX 2 9183 #define regOTG2_OTG_VSTARTUP_PARAM 0x1c85 9184 #define regOTG2_OTG_VSTARTUP_PARAM_BASE_IDX 2 9185 #define regOTG2_OTG_VUPDATE_PARAM 0x1c86 9186 #define regOTG2_OTG_VUPDATE_PARAM_BASE_IDX 2 9187 #define regOTG2_OTG_VREADY_PARAM 0x1c87 9188 #define regOTG2_OTG_VREADY_PARAM_BASE_IDX 2 9189 #define regOTG2_OTG_GLOBAL_SYNC_STATUS 0x1c88 9190 #define regOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 9191 #define regOTG2_OTG_MASTER_UPDATE_LOCK 0x1c89 9192 #define regOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 9193 #define regOTG2_OTG_GSL_CONTROL 0x1c8a 9194 #define regOTG2_OTG_GSL_CONTROL_BASE_IDX 2 9195 #define regOTG2_OTG_GSL_WINDOW_X 0x1c8b 9196 #define regOTG2_OTG_GSL_WINDOW_X_BASE_IDX 2 9197 #define regOTG2_OTG_GSL_WINDOW_Y 0x1c8c 9198 #define regOTG2_OTG_GSL_WINDOW_Y_BASE_IDX 2 9199 #define regOTG2_OTG_VUPDATE_KEEPOUT 0x1c8d 9200 #define regOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 9201 #define regOTG2_OTG_GLOBAL_CONTROL0 0x1c8e 9202 #define regOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX 2 9203 #define regOTG2_OTG_GLOBAL_CONTROL1 0x1c8f 9204 #define regOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX 2 9205 #define regOTG2_OTG_GLOBAL_CONTROL2 0x1c90 9206 #define regOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX 2 9207 #define regOTG2_OTG_GLOBAL_CONTROL3 0x1c91 9208 #define regOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX 2 9209 #define regOTG2_OTG_GLOBAL_CONTROL4 0x1c92 9210 #define regOTG2_OTG_GLOBAL_CONTROL4_BASE_IDX 2 9211 #define regOTG2_OTG_TRIG_MANUAL_CONTROL 0x1c93 9212 #define regOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 9213 #define regOTG2_OTG_MANUAL_FLOW_CONTROL 0x1c94 9214 #define regOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 9215 #define regOTG2_OTG_DRR_TIMING_INT_STATUS 0x1c95 9216 #define regOTG2_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 9217 #define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c96 9218 #define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 9219 #define regOTG2_OTG_DRR_V_TOTAL_CHANGE 0x1c97 9220 #define regOTG2_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 9221 #define regOTG2_OTG_DRR_TRIGGER_WINDOW 0x1c98 9222 #define regOTG2_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 9223 #define regOTG2_OTG_DRR_CONTROL 0x1c99 9224 #define regOTG2_OTG_DRR_CONTROL_BASE_IDX 2 9225 #define regOTG2_OTG_DRR_CONTOL2 0x1c9a 9226 #define regOTG2_OTG_DRR_CONTOL2_BASE_IDX 2 9227 #define regOTG2_OTG_M_CONST_DTO0 0x1c9b 9228 #define regOTG2_OTG_M_CONST_DTO0_BASE_IDX 2 9229 #define regOTG2_OTG_M_CONST_DTO1 0x1c9c 9230 #define regOTG2_OTG_M_CONST_DTO1_BASE_IDX 2 9231 #define regOTG2_OTG_REQUEST_CONTROL 0x1c9d 9232 #define regOTG2_OTG_REQUEST_CONTROL_BASE_IDX 2 9233 #define regOTG2_OTG_PIPE_UPDATE_STATUS 0x1c9e 9234 #define regOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 9235 #define regOTG2_OTG_PSTATE_REGISTER 0x1c9f 9236 #define regOTG2_OTG_PSTATE_REGISTER_BASE_IDX 2 9237 #define regOTG2_OTG_SPARE_REGISTER 0x1ca1 9238 #define regOTG2_OTG_SPARE_REGISTER_BASE_IDX 2 9239 9240 9241 // addressBlock: dcn_dcec_optc_otg3_dispdec 9242 // base address: 0x600 9243 #define regOTG3_OTG_H_TOTAL 0x1caa 9244 #define regOTG3_OTG_H_TOTAL_BASE_IDX 2 9245 #define regOTG3_OTG_H_BLANK_START_END 0x1cab 9246 #define regOTG3_OTG_H_BLANK_START_END_BASE_IDX 2 9247 #define regOTG3_OTG_H_SYNC_A 0x1cac 9248 #define regOTG3_OTG_H_SYNC_A_BASE_IDX 2 9249 #define regOTG3_OTG_H_SYNC_A_CNTL 0x1cad 9250 #define regOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX 2 9251 #define regOTG3_OTG_H_TIMING_CNTL 0x1cae 9252 #define regOTG3_OTG_H_TIMING_CNTL_BASE_IDX 2 9253 #define regOTG3_OTG_V_TOTAL 0x1caf 9254 #define regOTG3_OTG_V_TOTAL_BASE_IDX 2 9255 #define regOTG3_OTG_V_TOTAL_MIN 0x1cb0 9256 #define regOTG3_OTG_V_TOTAL_MIN_BASE_IDX 2 9257 #define regOTG3_OTG_V_TOTAL_MAX 0x1cb1 9258 #define regOTG3_OTG_V_TOTAL_MAX_BASE_IDX 2 9259 #define regOTG3_OTG_V_TOTAL_MID 0x1cb2 9260 #define regOTG3_OTG_V_TOTAL_MID_BASE_IDX 2 9261 #define regOTG3_OTG_V_TOTAL_CONTROL 0x1cb3 9262 #define regOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX 2 9263 #define regOTG3_OTG_V_COUNT_STOP_CONTROL 0x1cb4 9264 #define regOTG3_OTG_V_COUNT_STOP_CONTROL_BASE_IDX 2 9265 #define regOTG3_OTG_V_COUNT_STOP_CONTROL2 0x1cb5 9266 #define regOTG3_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX 2 9267 #define regOTG3_OTG_V_TOTAL_INT_STATUS 0x1cb6 9268 #define regOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 9269 #define regOTG3_OTG_VSYNC_NOM_INT_STATUS 0x1cb7 9270 #define regOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 9271 #define regOTG3_OTG_V_BLANK_START_END 0x1cb8 9272 #define regOTG3_OTG_V_BLANK_START_END_BASE_IDX 2 9273 #define regOTG3_OTG_V_SYNC_A 0x1cb9 9274 #define regOTG3_OTG_V_SYNC_A_BASE_IDX 2 9275 #define regOTG3_OTG_V_SYNC_A_CNTL 0x1cba 9276 #define regOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX 2 9277 #define regOTG3_OTG_TRIGA_CNTL 0x1cbb 9278 #define regOTG3_OTG_TRIGA_CNTL_BASE_IDX 2 9279 #define regOTG3_OTG_TRIGA_MANUAL_TRIG 0x1cbc 9280 #define regOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 9281 #define regOTG3_OTG_TRIGB_CNTL 0x1cbd 9282 #define regOTG3_OTG_TRIGB_CNTL_BASE_IDX 2 9283 #define regOTG3_OTG_TRIGB_MANUAL_TRIG 0x1cbe 9284 #define regOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 9285 #define regOTG3_OTG_FORCE_COUNT_NOW_CNTL 0x1cbf 9286 #define regOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 9287 #define regOTG3_OTG_FLOW_CONTROL 0x1cc0 9288 #define regOTG3_OTG_FLOW_CONTROL_BASE_IDX 2 9289 #define regOTG3_OTG_STEREO_FORCE_NEXT_EYE 0x1cc1 9290 #define regOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 9291 #define regOTG3_OTG_CONTROL 0x1cc3 9292 #define regOTG3_OTG_CONTROL_BASE_IDX 2 9293 #define regOTG3_OTG_DLPC_CONTROL 0x1cc4 9294 #define regOTG3_OTG_DLPC_CONTROL_BASE_IDX 2 9295 #define regOTG3_OTG_INTERLACE_CONTROL 0x1cc5 9296 #define regOTG3_OTG_INTERLACE_CONTROL_BASE_IDX 2 9297 #define regOTG3_OTG_INTERLACE_STATUS 0x1cc6 9298 #define regOTG3_OTG_INTERLACE_STATUS_BASE_IDX 2 9299 #define regOTG3_OTG_PIXEL_DATA_READBACK0 0x1cc7 9300 #define regOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 9301 #define regOTG3_OTG_PIXEL_DATA_READBACK1 0x1cc8 9302 #define regOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 9303 #define regOTG3_OTG_STATUS 0x1cc9 9304 #define regOTG3_OTG_STATUS_BASE_IDX 2 9305 #define regOTG3_OTG_STATUS_POSITION 0x1cca 9306 #define regOTG3_OTG_STATUS_POSITION_BASE_IDX 2 9307 #define regOTG3_OTG_LONG_VBLANK_STATUS 0x1ccb 9308 #define regOTG3_OTG_LONG_VBLANK_STATUS_BASE_IDX 2 9309 #define regOTG3_OTG_NOM_VERT_POSITION 0x1ccc 9310 #define regOTG3_OTG_NOM_VERT_POSITION_BASE_IDX 2 9311 #define regOTG3_OTG_STATUS_FRAME_COUNT 0x1ccd 9312 #define regOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 9313 #define regOTG3_OTG_STATUS_VF_COUNT 0x1cce 9314 #define regOTG3_OTG_STATUS_VF_COUNT_BASE_IDX 2 9315 #define regOTG3_OTG_STATUS_HV_COUNT 0x1ccf 9316 #define regOTG3_OTG_STATUS_HV_COUNT_BASE_IDX 2 9317 #define regOTG3_OTG_COUNT_CONTROL 0x1cd0 9318 #define regOTG3_OTG_COUNT_CONTROL_BASE_IDX 2 9319 #define regOTG3_OTG_COUNT_RESET 0x1cd1 9320 #define regOTG3_OTG_COUNT_RESET_BASE_IDX 2 9321 #define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1cd2 9322 #define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 9323 #define regOTG3_OTG_VERT_SYNC_CONTROL 0x1cd3 9324 #define regOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 9325 #define regOTG3_OTG_STEREO_STATUS 0x1cd4 9326 #define regOTG3_OTG_STEREO_STATUS_BASE_IDX 2 9327 #define regOTG3_OTG_STEREO_CONTROL 0x1cd5 9328 #define regOTG3_OTG_STEREO_CONTROL_BASE_IDX 2 9329 #define regOTG3_OTG_SNAPSHOT_STATUS 0x1cd6 9330 #define regOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX 2 9331 #define regOTG3_OTG_SNAPSHOT_CONTROL 0x1cd7 9332 #define regOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 9333 #define regOTG3_OTG_SNAPSHOT_POSITION 0x1cd8 9334 #define regOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX 2 9335 #define regOTG3_OTG_SNAPSHOT_FRAME 0x1cd9 9336 #define regOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX 2 9337 #define regOTG3_OTG_INTERRUPT_CONTROL 0x1cda 9338 #define regOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX 2 9339 #define regOTG3_OTG_UPDATE_LOCK 0x1cdb 9340 #define regOTG3_OTG_UPDATE_LOCK_BASE_IDX 2 9341 #define regOTG3_OTG_DOUBLE_BUFFER_CONTROL 0x1cdc 9342 #define regOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 9343 #define regOTG3_OTG_MASTER_EN 0x1cdd 9344 #define regOTG3_OTG_MASTER_EN_BASE_IDX 2 9345 #define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION 0x1cdf 9346 #define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 9347 #define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1ce0 9348 #define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 9349 #define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION 0x1ce1 9350 #define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 9351 #define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1ce2 9352 #define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 9353 #define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION 0x1ce3 9354 #define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 9355 #define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1ce4 9356 #define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 9357 #define regOTG3_OTG_CRC_CNTL 0x1ce5 9358 #define regOTG3_OTG_CRC_CNTL_BASE_IDX 2 9359 #define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL 0x1ce6 9360 #define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 9361 #define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL 0x1ce7 9362 #define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 9363 #define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL 0x1ce8 9364 #define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 9365 #define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL 0x1ce9 9366 #define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 9367 #define regOTG3_OTG_CRC0_DATA_RG 0x1cea 9368 #define regOTG3_OTG_CRC0_DATA_RG_BASE_IDX 2 9369 #define regOTG3_OTG_CRC0_DATA_B 0x1ceb 9370 #define regOTG3_OTG_CRC0_DATA_B_BASE_IDX 2 9371 #define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL 0x1cec 9372 #define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 9373 #define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL 0x1ced 9374 #define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 9375 #define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL 0x1cee 9376 #define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 9377 #define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL 0x1cef 9378 #define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 9379 #define regOTG3_OTG_CRC1_DATA_RG 0x1cf0 9380 #define regOTG3_OTG_CRC1_DATA_RG_BASE_IDX 2 9381 #define regOTG3_OTG_CRC1_DATA_B 0x1cf1 9382 #define regOTG3_OTG_CRC1_DATA_B_BASE_IDX 2 9383 #define regOTG3_OTG_CRC2_DATA_RG 0x1cf2 9384 #define regOTG3_OTG_CRC2_DATA_RG_BASE_IDX 2 9385 #define regOTG3_OTG_CRC2_DATA_B 0x1cf3 9386 #define regOTG3_OTG_CRC2_DATA_B_BASE_IDX 2 9387 #define regOTG3_OTG_CRC3_DATA_RG 0x1cf4 9388 #define regOTG3_OTG_CRC3_DATA_RG_BASE_IDX 2 9389 #define regOTG3_OTG_CRC3_DATA_B 0x1cf5 9390 #define regOTG3_OTG_CRC3_DATA_B_BASE_IDX 2 9391 #define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK 0x1cf6 9392 #define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 9393 #define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1cf7 9394 #define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 9395 #define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK 0x1cf8 9396 #define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 9397 #define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK 0x1cf9 9398 #define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 9399 #define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK 0x1cfa 9400 #define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 9401 #define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK 0x1cfb 9402 #define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 9403 #define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK 0x1cfc 9404 #define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 9405 #define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK 0x1cfd 9406 #define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 9407 #define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK 0x1cfe 9408 #define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 9409 #define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK 0x1cff 9410 #define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 9411 #define regOTG3_OTG_STATIC_SCREEN_CONTROL 0x1d00 9412 #define regOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 9413 #define regOTG3_OTG_3D_STRUCTURE_CONTROL 0x1d01 9414 #define regOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 9415 #define regOTG3_OTG_GSL_VSYNC_GAP 0x1d02 9416 #define regOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX 2 9417 #define regOTG3_OTG_MASTER_UPDATE_MODE 0x1d03 9418 #define regOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 9419 #define regOTG3_OTG_CLOCK_CONTROL 0x1d04 9420 #define regOTG3_OTG_CLOCK_CONTROL_BASE_IDX 2 9421 #define regOTG3_OTG_VSTARTUP_PARAM 0x1d05 9422 #define regOTG3_OTG_VSTARTUP_PARAM_BASE_IDX 2 9423 #define regOTG3_OTG_VUPDATE_PARAM 0x1d06 9424 #define regOTG3_OTG_VUPDATE_PARAM_BASE_IDX 2 9425 #define regOTG3_OTG_VREADY_PARAM 0x1d07 9426 #define regOTG3_OTG_VREADY_PARAM_BASE_IDX 2 9427 #define regOTG3_OTG_GLOBAL_SYNC_STATUS 0x1d08 9428 #define regOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 9429 #define regOTG3_OTG_MASTER_UPDATE_LOCK 0x1d09 9430 #define regOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 9431 #define regOTG3_OTG_GSL_CONTROL 0x1d0a 9432 #define regOTG3_OTG_GSL_CONTROL_BASE_IDX 2 9433 #define regOTG3_OTG_GSL_WINDOW_X 0x1d0b 9434 #define regOTG3_OTG_GSL_WINDOW_X_BASE_IDX 2 9435 #define regOTG3_OTG_GSL_WINDOW_Y 0x1d0c 9436 #define regOTG3_OTG_GSL_WINDOW_Y_BASE_IDX 2 9437 #define regOTG3_OTG_VUPDATE_KEEPOUT 0x1d0d 9438 #define regOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 9439 #define regOTG3_OTG_GLOBAL_CONTROL0 0x1d0e 9440 #define regOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX 2 9441 #define regOTG3_OTG_GLOBAL_CONTROL1 0x1d0f 9442 #define regOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX 2 9443 #define regOTG3_OTG_GLOBAL_CONTROL2 0x1d10 9444 #define regOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX 2 9445 #define regOTG3_OTG_GLOBAL_CONTROL3 0x1d11 9446 #define regOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX 2 9447 #define regOTG3_OTG_GLOBAL_CONTROL4 0x1d12 9448 #define regOTG3_OTG_GLOBAL_CONTROL4_BASE_IDX 2 9449 #define regOTG3_OTG_TRIG_MANUAL_CONTROL 0x1d13 9450 #define regOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 9451 #define regOTG3_OTG_MANUAL_FLOW_CONTROL 0x1d14 9452 #define regOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 9453 #define regOTG3_OTG_DRR_TIMING_INT_STATUS 0x1d15 9454 #define regOTG3_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 9455 #define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE 0x1d16 9456 #define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 9457 #define regOTG3_OTG_DRR_V_TOTAL_CHANGE 0x1d17 9458 #define regOTG3_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 9459 #define regOTG3_OTG_DRR_TRIGGER_WINDOW 0x1d18 9460 #define regOTG3_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 9461 #define regOTG3_OTG_DRR_CONTROL 0x1d19 9462 #define regOTG3_OTG_DRR_CONTROL_BASE_IDX 2 9463 #define regOTG3_OTG_DRR_CONTOL2 0x1d1a 9464 #define regOTG3_OTG_DRR_CONTOL2_BASE_IDX 2 9465 #define regOTG3_OTG_M_CONST_DTO0 0x1d1b 9466 #define regOTG3_OTG_M_CONST_DTO0_BASE_IDX 2 9467 #define regOTG3_OTG_M_CONST_DTO1 0x1d1c 9468 #define regOTG3_OTG_M_CONST_DTO1_BASE_IDX 2 9469 #define regOTG3_OTG_REQUEST_CONTROL 0x1d1d 9470 #define regOTG3_OTG_REQUEST_CONTROL_BASE_IDX 2 9471 #define regOTG3_OTG_PIPE_UPDATE_STATUS 0x1d1e 9472 #define regOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 9473 #define regOTG3_OTG_PSTATE_REGISTER 0x1d1f 9474 #define regOTG3_OTG_PSTATE_REGISTER_BASE_IDX 2 9475 #define regOTG3_OTG_SPARE_REGISTER 0x1d21 9476 #define regOTG3_OTG_SPARE_REGISTER_BASE_IDX 2 9477 9478 9479 // addressBlock: dcn_dcec_optc_optc_misc_dispdec 9480 // base address: 0x0 9481 #define regGSL_SOURCE_SELECT 0x1e2b 9482 #define regGSL_SOURCE_SELECT_BASE_IDX 2 9483 #define regOPTC_DLPC_CONTROL 0x1e2c 9484 #define regOPTC_DLPC_CONTROL_BASE_IDX 2 9485 #define regOPTC_CLOCK_CONTROL 0x1e2d 9486 #define regOPTC_CLOCK_CONTROL_BASE_IDX 2 9487 #define regODM_MEM_PWR_CTRL 0x1e2e 9488 #define regODM_MEM_PWR_CTRL_BASE_IDX 2 9489 #define regODM_MEM_PWR_CTRL2 0x1e2f 9490 #define regODM_MEM_PWR_CTRL2_BASE_IDX 2 9491 #define regODM_MEM_PWR_CTRL3 0x1e30 9492 #define regODM_MEM_PWR_CTRL3_BASE_IDX 2 9493 #define regODM_MEM_PWR_STATUS 0x1e31 9494 #define regODM_MEM_PWR_STATUS_BASE_IDX 2 9495 #define regOPTC_MISC_SPARE_REGISTER 0x1e32 9496 #define regOPTC_MISC_SPARE_REGISTER_BASE_IDX 2 9497 9498 9499 // addressBlock: dcn_dcec_dio_dp0_dispdec 9500 // base address: 0x0 9501 #define regDP0_DP_LINK_CNTL 0x211e 9502 #define regDP0_DP_LINK_CNTL_BASE_IDX 2 9503 #define regDP0_DP_PIXEL_FORMAT 0x211f 9504 #define regDP0_DP_PIXEL_FORMAT_BASE_IDX 2 9505 #define regDP0_DP_MSA_COLORIMETRY 0x2120 9506 #define regDP0_DP_MSA_COLORIMETRY_BASE_IDX 2 9507 #define regDP0_DP_CONFIG 0x2121 9508 #define regDP0_DP_CONFIG_BASE_IDX 2 9509 #define regDP0_DP_VID_STREAM_CNTL 0x2122 9510 #define regDP0_DP_VID_STREAM_CNTL_BASE_IDX 2 9511 #define regDP0_DP_STEER_FIFO 0x2123 9512 #define regDP0_DP_STEER_FIFO_BASE_IDX 2 9513 #define regDP0_DP_MSA_MISC 0x2124 9514 #define regDP0_DP_MSA_MISC_BASE_IDX 2 9515 #define regDP0_DP_DPHY_INTERNAL_CTRL 0x2125 9516 #define regDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 9517 #define regDP0_DP_VID_TIMING 0x2126 9518 #define regDP0_DP_VID_TIMING_BASE_IDX 2 9519 #define regDP0_DP_VID_N 0x2127 9520 #define regDP0_DP_VID_N_BASE_IDX 2 9521 #define regDP0_DP_VID_M 0x2128 9522 #define regDP0_DP_VID_M_BASE_IDX 2 9523 #define regDP0_DP_LINK_FRAMING_CNTL 0x2129 9524 #define regDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2 9525 #define regDP0_DP_HBR2_EYE_PATTERN 0x212a 9526 #define regDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2 9527 #define regDP0_DP_VID_MSA_VBID 0x212b 9528 #define regDP0_DP_VID_MSA_VBID_BASE_IDX 2 9529 #define regDP0_DP_VID_INTERRUPT_CNTL 0x212c 9530 #define regDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 9531 #define regDP0_DP_DPHY_CNTL 0x212d 9532 #define regDP0_DP_DPHY_CNTL_BASE_IDX 2 9533 #define regDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x212e 9534 #define regDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 9535 #define regDP0_DP_DPHY_SYM0 0x212f 9536 #define regDP0_DP_DPHY_SYM0_BASE_IDX 2 9537 #define regDP0_DP_DPHY_SYM1 0x2130 9538 #define regDP0_DP_DPHY_SYM1_BASE_IDX 2 9539 #define regDP0_DP_DPHY_SYM2 0x2131 9540 #define regDP0_DP_DPHY_SYM2_BASE_IDX 2 9541 #define regDP0_DP_DPHY_8B10B_CNTL 0x2132 9542 #define regDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2 9543 #define regDP0_DP_DPHY_PRBS_CNTL 0x2133 9544 #define regDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2 9545 #define regDP0_DP_DPHY_SCRAM_CNTL 0x2134 9546 #define regDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 9547 #define regDP0_DP_DPHY_CRC_EN 0x2135 9548 #define regDP0_DP_DPHY_CRC_EN_BASE_IDX 2 9549 #define regDP0_DP_DPHY_CRC_CNTL 0x2136 9550 #define regDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2 9551 #define regDP0_DP_DPHY_CRC_RESULT 0x2137 9552 #define regDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2 9553 #define regDP0_DP_DPHY_CRC_MST_CNTL 0x2138 9554 #define regDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 9555 #define regDP0_DP_DPHY_CRC_MST_STATUS 0x2139 9556 #define regDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 9557 #define regDP0_DP_DPHY_FAST_TRAINING 0x213a 9558 #define regDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2 9559 #define regDP0_DP_DPHY_FAST_TRAINING_STATUS 0x213b 9560 #define regDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 9561 #define regDP0_DP_TU_CNTL 0x213c 9562 #define regDP0_DP_TU_CNTL_BASE_IDX 2 9563 #define regDP0_DP_PIXEL_FORMAT_DB_CNTL 0x213d 9564 #define regDP0_DP_PIXEL_FORMAT_DB_CNTL_BASE_IDX 2 9565 #define regDP0_DP_CP_LINK_VERIFICATION_PATTERN 0x213e 9566 #define regDP0_DP_CP_LINK_VERIFICATION_PATTERN_BASE_IDX 2 9567 #define regDP0_DP_SEC_CNTL 0x2141 9568 #define regDP0_DP_SEC_CNTL_BASE_IDX 2 9569 #define regDP0_DP_SEC_CNTL1 0x2142 9570 #define regDP0_DP_SEC_CNTL1_BASE_IDX 2 9571 #define regDP0_DP_SEC_FRAMING1 0x2143 9572 #define regDP0_DP_SEC_FRAMING1_BASE_IDX 2 9573 #define regDP0_DP_SEC_FRAMING2 0x2144 9574 #define regDP0_DP_SEC_FRAMING2_BASE_IDX 2 9575 #define regDP0_DP_SEC_FRAMING3 0x2145 9576 #define regDP0_DP_SEC_FRAMING3_BASE_IDX 2 9577 #define regDP0_DP_SEC_FRAMING4 0x2146 9578 #define regDP0_DP_SEC_FRAMING4_BASE_IDX 2 9579 #define regDP0_DP_SEC_AUD_N 0x2147 9580 #define regDP0_DP_SEC_AUD_N_BASE_IDX 2 9581 #define regDP0_DP_SEC_AUD_N_READBACK 0x2148 9582 #define regDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2 9583 #define regDP0_DP_SEC_AUD_M 0x2149 9584 #define regDP0_DP_SEC_AUD_M_BASE_IDX 2 9585 #define regDP0_DP_SEC_AUD_M_READBACK 0x214a 9586 #define regDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2 9587 #define regDP0_DP_SEC_TIMESTAMP 0x214b 9588 #define regDP0_DP_SEC_TIMESTAMP_BASE_IDX 2 9589 #define regDP0_DP_SEC_PACKET_CNTL 0x214c 9590 #define regDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2 9591 #define regDP0_DP_MSE_RATE_CNTL 0x214d 9592 #define regDP0_DP_MSE_RATE_CNTL_BASE_IDX 2 9593 #define regDP0_DP_CP_MSE_STATUS 0x214e 9594 #define regDP0_DP_CP_MSE_STATUS_BASE_IDX 2 9595 #define regDP0_DP_MSE_RATE_UPDATE 0x214f 9596 #define regDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2 9597 #define regDP0_DP_MSE_SAT0 0x2150 9598 #define regDP0_DP_MSE_SAT0_BASE_IDX 2 9599 #define regDP0_DP_MSE_SAT1 0x2151 9600 #define regDP0_DP_MSE_SAT1_BASE_IDX 2 9601 #define regDP0_DP_MSE_SAT2 0x2152 9602 #define regDP0_DP_MSE_SAT2_BASE_IDX 2 9603 #define regDP0_DP_MSE_SAT_UPDATE 0x2153 9604 #define regDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2 9605 #define regDP0_DP_MSE_LINK_TIMING 0x2154 9606 #define regDP0_DP_MSE_LINK_TIMING_BASE_IDX 2 9607 #define regDP0_DP_MSE_MISC_CNTL 0x2155 9608 #define regDP0_DP_MSE_MISC_CNTL_BASE_IDX 2 9609 #define regDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x215a 9610 #define regDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 9611 #define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x215b 9612 #define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 9613 #define regDP0_DP_MSE_SAT0_STATUS 0x215d 9614 #define regDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2 9615 #define regDP0_DP_MSE_SAT1_STATUS 0x215e 9616 #define regDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2 9617 #define regDP0_DP_MSE_SAT2_STATUS 0x215f 9618 #define regDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2 9619 #define regDP0_DP_DPIA_SPARE 0x2160 9620 #define regDP0_DP_DPIA_SPARE_BASE_IDX 2 9621 #define regDP0_DP_HBLANK_CONTROL 0x2161 9622 #define regDP0_DP_HBLANK_CONTROL_BASE_IDX 2 9623 #define regDP0_DP_MSA_TIMING_PARAM1 0x2162 9624 #define regDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 2 9625 #define regDP0_DP_MSA_TIMING_PARAM2 0x2163 9626 #define regDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 2 9627 #define regDP0_DP_MSA_TIMING_PARAM3 0x2164 9628 #define regDP0_DP_MSA_TIMING_PARAM3_BASE_IDX 2 9629 #define regDP0_DP_MSA_TIMING_PARAM4 0x2165 9630 #define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 2 9631 #define regDP0_DP_MSO_CNTL 0x2166 9632 #define regDP0_DP_MSO_CNTL_BASE_IDX 2 9633 #define regDP0_DP_MSO_CNTL1 0x2167 9634 #define regDP0_DP_MSO_CNTL1_BASE_IDX 2 9635 #define regDP0_DP_STEER_FIFO_CNTL 0x2168 9636 #define regDP0_DP_STEER_FIFO_CNTL_BASE_IDX 2 9637 #define regDP0_DP_SEC_CNTL2 0x2169 9638 #define regDP0_DP_SEC_CNTL2_BASE_IDX 2 9639 #define regDP0_DP_SEC_CNTL3 0x216a 9640 #define regDP0_DP_SEC_CNTL3_BASE_IDX 2 9641 #define regDP0_DP_SEC_CNTL4 0x216b 9642 #define regDP0_DP_SEC_CNTL4_BASE_IDX 2 9643 #define regDP0_DP_SEC_CNTL5 0x216c 9644 #define regDP0_DP_SEC_CNTL5_BASE_IDX 2 9645 #define regDP0_DP_SEC_CNTL6 0x216d 9646 #define regDP0_DP_SEC_CNTL6_BASE_IDX 2 9647 #define regDP0_DP_SEC_CNTL7 0x216e 9648 #define regDP0_DP_SEC_CNTL7_BASE_IDX 2 9649 #define regDP0_DP_DB_CNTL 0x216f 9650 #define regDP0_DP_DB_CNTL_BASE_IDX 2 9651 #define regDP0_DP_MSA_VBID_MISC 0x2170 9652 #define regDP0_DP_MSA_VBID_MISC_BASE_IDX 2 9653 #define regDP0_DP_SEC_METADATA_TRANSMISSION 0x2171 9654 #define regDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 9655 #define regDP0_DP_ALPM_CNTL 0x2173 9656 #define regDP0_DP_ALPM_CNTL_BASE_IDX 2 9657 #define regDP0_DP_GSP8_CNTL 0x2174 9658 #define regDP0_DP_GSP8_CNTL_BASE_IDX 2 9659 #define regDP0_DP_GSP9_CNTL 0x2175 9660 #define regDP0_DP_GSP9_CNTL_BASE_IDX 2 9661 #define regDP0_DP_GSP10_CNTL 0x2176 9662 #define regDP0_DP_GSP10_CNTL_BASE_IDX 2 9663 #define regDP0_DP_GSP11_CNTL 0x2177 9664 #define regDP0_DP_GSP11_CNTL_BASE_IDX 2 9665 #define regDP0_DP_GSP_EN_DB_STATUS 0x2178 9666 #define regDP0_DP_GSP_EN_DB_STATUS_BASE_IDX 2 9667 #define regDP0_DP_AUXLESS_ALPM_CNTL1 0x2179 9668 #define regDP0_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 9669 #define regDP0_DP_AUXLESS_ALPM_CNTL2 0x217a 9670 #define regDP0_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 9671 #define regDP0_DP_AUXLESS_ALPM_CNTL3 0x217b 9672 #define regDP0_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 9673 #define regDP0_DP_AUXLESS_ALPM_CNTL4 0x217c 9674 #define regDP0_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 9675 #define regDP0_DP_AUXLESS_ALPM_CNTL5 0x217d 9676 #define regDP0_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 9677 #define regDP0_DP_STREAM_SYMBOL_COUNT_STATUS 0x217e 9678 #define regDP0_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX 2 9679 #define regDP0_DP_STREAM_SYMBOL_COUNT_CONTROL 0x217f 9680 #define regDP0_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX 2 9681 #define regDP0_DP_LINK_SYMBOL_COUNT_STATUS0 0x2180 9682 #define regDP0_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX 2 9683 #define regDP0_DP_LINK_SYMBOL_COUNT_STATUS1 0x2181 9684 #define regDP0_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX 2 9685 #define regDP0_DP_LINK_SYMBOL_COUNT_CONTROL 0x2182 9686 #define regDP0_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX 2 9687 #define regDP0_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL 0x2183 9688 #define regDP0_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 9689 9690 9691 // addressBlock: dcn_dcec_dio_dig0_dispdec 9692 // base address: 0x0 9693 #define regDIG0_DIG_FE_CNTL 0x2093 9694 #define regDIG0_DIG_FE_CNTL_BASE_IDX 2 9695 #define regDIG0_DIG_FE_CLK_CNTL 0x2094 9696 #define regDIG0_DIG_FE_CLK_CNTL_BASE_IDX 2 9697 #define regDIG0_DIG_FE_EN_CNTL 0x2095 9698 #define regDIG0_DIG_FE_EN_CNTL_BASE_IDX 2 9699 #define regDIG0_DIG_OUTPUT_CRC_CNTL 0x2096 9700 #define regDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 9701 #define regDIG0_DIG_OUTPUT_CRC_RESULT 0x2097 9702 #define regDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 9703 #define regDIG0_DIG_CLOCK_PATTERN 0x2098 9704 #define regDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2 9705 #define regDIG0_DIG_TEST_PATTERN 0x2099 9706 #define regDIG0_DIG_TEST_PATTERN_BASE_IDX 2 9707 #define regDIG0_DIG_RANDOM_PATTERN_SEED 0x209a 9708 #define regDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 9709 #define regDIG0_DIG_FIFO_CTRL0 0x209b 9710 #define regDIG0_DIG_FIFO_CTRL0_BASE_IDX 2 9711 #define regDIG0_DIG_FIFO_CTRL1 0x209c 9712 #define regDIG0_DIG_FIFO_CTRL1_BASE_IDX 2 9713 #define regDIG0_HDMI_METADATA_PACKET_CONTROL 0x209d 9714 #define regDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 9715 #define regDIG0_HDMI_CONTROL 0x209e 9716 #define regDIG0_HDMI_CONTROL_BASE_IDX 2 9717 #define regDIG0_HDMI_STATUS 0x209f 9718 #define regDIG0_HDMI_STATUS_BASE_IDX 2 9719 #define regDIG0_HDMI_AUDIO_PACKET_CONTROL 0x20a0 9720 #define regDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 9721 #define regDIG0_HDMI_ACR_PACKET_CONTROL 0x20a1 9722 #define regDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 9723 #define regDIG0_HDMI_VBI_PACKET_CONTROL 0x20a2 9724 #define regDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 9725 #define regDIG0_HDMI_INFOFRAME_CONTROL0 0x20a3 9726 #define regDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 9727 #define regDIG0_HDMI_INFOFRAME_CONTROL1 0x20a4 9728 #define regDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 9729 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x20a5 9730 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 9731 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL6 0x20a6 9732 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 9733 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL5 0x20a7 9734 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 9735 #define regDIG0_HDMI_GC 0x20a8 9736 #define regDIG0_HDMI_GC_BASE_IDX 2 9737 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x20a9 9738 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 9739 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL2 0x20aa 9740 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 9741 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL3 0x20ab 9742 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 9743 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL4 0x20ac 9744 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 9745 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL7 0x20ad 9746 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 9747 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL8 0x20ae 9748 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 9749 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL9 0x20af 9750 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 9751 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL10 0x20b0 9752 #define regDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 9753 #define regDIG0_HDMI_DB_CONTROL 0x20b1 9754 #define regDIG0_HDMI_DB_CONTROL_BASE_IDX 2 9755 #define regDIG0_HDMI_ACR_32_0 0x20b2 9756 #define regDIG0_HDMI_ACR_32_0_BASE_IDX 2 9757 #define regDIG0_HDMI_ACR_32_1 0x20b3 9758 #define regDIG0_HDMI_ACR_32_1_BASE_IDX 2 9759 #define regDIG0_HDMI_ACR_44_0 0x20b4 9760 #define regDIG0_HDMI_ACR_44_0_BASE_IDX 2 9761 #define regDIG0_HDMI_ACR_44_1 0x20b5 9762 #define regDIG0_HDMI_ACR_44_1_BASE_IDX 2 9763 #define regDIG0_HDMI_ACR_48_0 0x20b6 9764 #define regDIG0_HDMI_ACR_48_0_BASE_IDX 2 9765 #define regDIG0_HDMI_ACR_48_1 0x20b7 9766 #define regDIG0_HDMI_ACR_48_1_BASE_IDX 2 9767 #define regDIG0_HDMI_ACR_STATUS_0 0x20b8 9768 #define regDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2 9769 #define regDIG0_HDMI_ACR_STATUS_1 0x20b9 9770 #define regDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2 9771 #define regDIG0_AFMT_CNTL 0x20ba 9772 #define regDIG0_AFMT_CNTL_BASE_IDX 2 9773 #define regDIG0_DIG_BE_CLK_CNTL 0x20bb 9774 #define regDIG0_DIG_BE_CLK_CNTL_BASE_IDX 2 9775 #define regDIG0_DIG_BE_CNTL 0x20bc 9776 #define regDIG0_DIG_BE_CNTL_BASE_IDX 2 9777 #define regDIG0_DIG_BE_EN_CNTL 0x20bd 9778 #define regDIG0_DIG_BE_EN_CNTL_BASE_IDX 2 9779 #define regDIG0_TMDS_CNTL 0x20e4 9780 #define regDIG0_TMDS_CNTL_BASE_IDX 2 9781 #define regDIG0_TMDS_CONTROL_CHAR 0x20e5 9782 #define regDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2 9783 #define regDIG0_TMDS_CONTROL0_FEEDBACK 0x20e6 9784 #define regDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 9785 #define regDIG0_TMDS_STEREOSYNC_CTL_SEL 0x20e7 9786 #define regDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 9787 #define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x20e8 9788 #define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 9789 #define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x20e9 9790 #define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 9791 #define regDIG0_TMDS_CTL_BITS 0x20eb 9792 #define regDIG0_TMDS_CTL_BITS_BASE_IDX 2 9793 #define regDIG0_TMDS_DCBALANCER_CONTROL 0x20ec 9794 #define regDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 9795 #define regDIG0_TMDS_SYNC_DCBALANCE_CHAR 0x20ed 9796 #define regDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 9797 #define regDIG0_TMDS_CTL0_1_GEN_CNTL 0x20ee 9798 #define regDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 9799 #define regDIG0_TMDS_CTL2_3_GEN_CNTL 0x20ef 9800 #define regDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 9801 #define regDIG0_DIG_VERSION 0x20f1 9802 #define regDIG0_DIG_VERSION_BASE_IDX 2 9803 9804 // addressBlock: dcn_dcec_dio_dp1_dispdec 9805 // base address: 0x490 9806 #define regDP1_DP_LINK_CNTL 0x2242 9807 #define regDP1_DP_LINK_CNTL_BASE_IDX 2 9808 #define regDP1_DP_PIXEL_FORMAT 0x2243 9809 #define regDP1_DP_PIXEL_FORMAT_BASE_IDX 2 9810 #define regDP1_DP_MSA_COLORIMETRY 0x2244 9811 #define regDP1_DP_MSA_COLORIMETRY_BASE_IDX 2 9812 #define regDP1_DP_CONFIG 0x2245 9813 #define regDP1_DP_CONFIG_BASE_IDX 2 9814 #define regDP1_DP_VID_STREAM_CNTL 0x2246 9815 #define regDP1_DP_VID_STREAM_CNTL_BASE_IDX 2 9816 #define regDP1_DP_STEER_FIFO 0x2247 9817 #define regDP1_DP_STEER_FIFO_BASE_IDX 2 9818 #define regDP1_DP_MSA_MISC 0x2248 9819 #define regDP1_DP_MSA_MISC_BASE_IDX 2 9820 #define regDP1_DP_DPHY_INTERNAL_CTRL 0x2249 9821 #define regDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 9822 #define regDP1_DP_VID_TIMING 0x224a 9823 #define regDP1_DP_VID_TIMING_BASE_IDX 2 9824 #define regDP1_DP_VID_N 0x224b 9825 #define regDP1_DP_VID_N_BASE_IDX 2 9826 #define regDP1_DP_VID_M 0x224c 9827 #define regDP1_DP_VID_M_BASE_IDX 2 9828 #define regDP1_DP_LINK_FRAMING_CNTL 0x224d 9829 #define regDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2 9830 #define regDP1_DP_HBR2_EYE_PATTERN 0x224e 9831 #define regDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2 9832 #define regDP1_DP_VID_MSA_VBID 0x224f 9833 #define regDP1_DP_VID_MSA_VBID_BASE_IDX 2 9834 #define regDP1_DP_VID_INTERRUPT_CNTL 0x2250 9835 #define regDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 9836 #define regDP1_DP_DPHY_CNTL 0x2251 9837 #define regDP1_DP_DPHY_CNTL_BASE_IDX 2 9838 #define regDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x2252 9839 #define regDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 9840 #define regDP1_DP_DPHY_SYM0 0x2253 9841 #define regDP1_DP_DPHY_SYM0_BASE_IDX 2 9842 #define regDP1_DP_DPHY_SYM1 0x2254 9843 #define regDP1_DP_DPHY_SYM1_BASE_IDX 2 9844 #define regDP1_DP_DPHY_SYM2 0x2255 9845 #define regDP1_DP_DPHY_SYM2_BASE_IDX 2 9846 #define regDP1_DP_DPHY_8B10B_CNTL 0x2256 9847 #define regDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2 9848 #define regDP1_DP_DPHY_PRBS_CNTL 0x2257 9849 #define regDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2 9850 #define regDP1_DP_DPHY_SCRAM_CNTL 0x2258 9851 #define regDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 9852 #define regDP1_DP_DPHY_CRC_EN 0x2259 9853 #define regDP1_DP_DPHY_CRC_EN_BASE_IDX 2 9854 #define regDP1_DP_DPHY_CRC_CNTL 0x225a 9855 #define regDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2 9856 #define regDP1_DP_DPHY_CRC_RESULT 0x225b 9857 #define regDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2 9858 #define regDP1_DP_DPHY_CRC_MST_CNTL 0x225c 9859 #define regDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 9860 #define regDP1_DP_DPHY_CRC_MST_STATUS 0x225d 9861 #define regDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 9862 #define regDP1_DP_DPHY_FAST_TRAINING 0x225e 9863 #define regDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2 9864 #define regDP1_DP_DPHY_FAST_TRAINING_STATUS 0x225f 9865 #define regDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 9866 #define regDP1_DP_TU_CNTL 0x2260 9867 #define regDP1_DP_TU_CNTL_BASE_IDX 2 9868 #define regDP1_DP_PIXEL_FORMAT_DB_CNTL 0x2261 9869 #define regDP1_DP_PIXEL_FORMAT_DB_CNTL_BASE_IDX 2 9870 #define regDP1_DP_CP_LINK_VERIFICATION_PATTERN 0x2262 9871 #define regDP1_DP_CP_LINK_VERIFICATION_PATTERN_BASE_IDX 2 9872 #define regDP1_DP_SEC_CNTL 0x2265 9873 #define regDP1_DP_SEC_CNTL_BASE_IDX 2 9874 #define regDP1_DP_SEC_CNTL1 0x2266 9875 #define regDP1_DP_SEC_CNTL1_BASE_IDX 2 9876 #define regDP1_DP_SEC_FRAMING1 0x2267 9877 #define regDP1_DP_SEC_FRAMING1_BASE_IDX 2 9878 #define regDP1_DP_SEC_FRAMING2 0x2268 9879 #define regDP1_DP_SEC_FRAMING2_BASE_IDX 2 9880 #define regDP1_DP_SEC_FRAMING3 0x2269 9881 #define regDP1_DP_SEC_FRAMING3_BASE_IDX 2 9882 #define regDP1_DP_SEC_FRAMING4 0x226a 9883 #define regDP1_DP_SEC_FRAMING4_BASE_IDX 2 9884 #define regDP1_DP_SEC_AUD_N 0x226b 9885 #define regDP1_DP_SEC_AUD_N_BASE_IDX 2 9886 #define regDP1_DP_SEC_AUD_N_READBACK 0x226c 9887 #define regDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2 9888 #define regDP1_DP_SEC_AUD_M 0x226d 9889 #define regDP1_DP_SEC_AUD_M_BASE_IDX 2 9890 #define regDP1_DP_SEC_AUD_M_READBACK 0x226e 9891 #define regDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2 9892 #define regDP1_DP_SEC_TIMESTAMP 0x226f 9893 #define regDP1_DP_SEC_TIMESTAMP_BASE_IDX 2 9894 #define regDP1_DP_SEC_PACKET_CNTL 0x2270 9895 #define regDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2 9896 #define regDP1_DP_MSE_RATE_CNTL 0x2271 9897 #define regDP1_DP_MSE_RATE_CNTL_BASE_IDX 2 9898 #define regDP1_DP_CP_MSE_STATUS 0x2272 9899 #define regDP1_DP_CP_MSE_STATUS_BASE_IDX 2 9900 #define regDP1_DP_MSE_RATE_UPDATE 0x2273 9901 #define regDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2 9902 #define regDP1_DP_MSE_SAT0 0x2274 9903 #define regDP1_DP_MSE_SAT0_BASE_IDX 2 9904 #define regDP1_DP_MSE_SAT1 0x2275 9905 #define regDP1_DP_MSE_SAT1_BASE_IDX 2 9906 #define regDP1_DP_MSE_SAT2 0x2276 9907 #define regDP1_DP_MSE_SAT2_BASE_IDX 2 9908 #define regDP1_DP_MSE_SAT_UPDATE 0x2277 9909 #define regDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2 9910 #define regDP1_DP_MSE_LINK_TIMING 0x2278 9911 #define regDP1_DP_MSE_LINK_TIMING_BASE_IDX 2 9912 #define regDP1_DP_MSE_MISC_CNTL 0x2279 9913 #define regDP1_DP_MSE_MISC_CNTL_BASE_IDX 2 9914 #define regDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x227e 9915 #define regDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 9916 #define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x227f 9917 #define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 9918 #define regDP1_DP_MSE_SAT0_STATUS 0x2281 9919 #define regDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2 9920 #define regDP1_DP_MSE_SAT1_STATUS 0x2282 9921 #define regDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2 9922 #define regDP1_DP_MSE_SAT2_STATUS 0x2283 9923 #define regDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2 9924 #define regDP1_DP_DPIA_SPARE 0x2284 9925 #define regDP1_DP_DPIA_SPARE_BASE_IDX 2 9926 #define regDP1_DP_HBLANK_CONTROL 0x2285 9927 #define regDP1_DP_HBLANK_CONTROL_BASE_IDX 2 9928 #define regDP1_DP_MSA_TIMING_PARAM1 0x2286 9929 #define regDP1_DP_MSA_TIMING_PARAM1_BASE_IDX 2 9930 #define regDP1_DP_MSA_TIMING_PARAM2 0x2287 9931 #define regDP1_DP_MSA_TIMING_PARAM2_BASE_IDX 2 9932 #define regDP1_DP_MSA_TIMING_PARAM3 0x2288 9933 #define regDP1_DP_MSA_TIMING_PARAM3_BASE_IDX 2 9934 #define regDP1_DP_MSA_TIMING_PARAM4 0x2289 9935 #define regDP1_DP_MSA_TIMING_PARAM4_BASE_IDX 2 9936 #define regDP1_DP_MSO_CNTL 0x228a 9937 #define regDP1_DP_MSO_CNTL_BASE_IDX 2 9938 #define regDP1_DP_MSO_CNTL1 0x228b 9939 #define regDP1_DP_MSO_CNTL1_BASE_IDX 2 9940 #define regDP1_DP_STEER_FIFO_CNTL 0x228c 9941 #define regDP1_DP_STEER_FIFO_CNTL_BASE_IDX 2 9942 #define regDP1_DP_SEC_CNTL2 0x228d 9943 #define regDP1_DP_SEC_CNTL2_BASE_IDX 2 9944 #define regDP1_DP_SEC_CNTL3 0x228e 9945 #define regDP1_DP_SEC_CNTL3_BASE_IDX 2 9946 #define regDP1_DP_SEC_CNTL4 0x228f 9947 #define regDP1_DP_SEC_CNTL4_BASE_IDX 2 9948 #define regDP1_DP_SEC_CNTL5 0x2290 9949 #define regDP1_DP_SEC_CNTL5_BASE_IDX 2 9950 #define regDP1_DP_SEC_CNTL6 0x2291 9951 #define regDP1_DP_SEC_CNTL6_BASE_IDX 2 9952 #define regDP1_DP_SEC_CNTL7 0x2292 9953 #define regDP1_DP_SEC_CNTL7_BASE_IDX 2 9954 #define regDP1_DP_DB_CNTL 0x2293 9955 #define regDP1_DP_DB_CNTL_BASE_IDX 2 9956 #define regDP1_DP_MSA_VBID_MISC 0x2294 9957 #define regDP1_DP_MSA_VBID_MISC_BASE_IDX 2 9958 #define regDP1_DP_SEC_METADATA_TRANSMISSION 0x2295 9959 #define regDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 9960 #define regDP1_DP_ALPM_CNTL 0x2297 9961 #define regDP1_DP_ALPM_CNTL_BASE_IDX 2 9962 #define regDP1_DP_GSP8_CNTL 0x2298 9963 #define regDP1_DP_GSP8_CNTL_BASE_IDX 2 9964 #define regDP1_DP_GSP9_CNTL 0x2299 9965 #define regDP1_DP_GSP9_CNTL_BASE_IDX 2 9966 #define regDP1_DP_GSP10_CNTL 0x229a 9967 #define regDP1_DP_GSP10_CNTL_BASE_IDX 2 9968 #define regDP1_DP_GSP11_CNTL 0x229b 9969 #define regDP1_DP_GSP11_CNTL_BASE_IDX 2 9970 #define regDP1_DP_GSP_EN_DB_STATUS 0x229c 9971 #define regDP1_DP_GSP_EN_DB_STATUS_BASE_IDX 2 9972 #define regDP1_DP_AUXLESS_ALPM_CNTL1 0x229d 9973 #define regDP1_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 9974 #define regDP1_DP_AUXLESS_ALPM_CNTL2 0x229e 9975 #define regDP1_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 9976 #define regDP1_DP_AUXLESS_ALPM_CNTL3 0x229f 9977 #define regDP1_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 9978 #define regDP1_DP_AUXLESS_ALPM_CNTL4 0x22a0 9979 #define regDP1_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 9980 #define regDP1_DP_AUXLESS_ALPM_CNTL5 0x22a1 9981 #define regDP1_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 9982 #define regDP1_DP_STREAM_SYMBOL_COUNT_STATUS 0x22a2 9983 #define regDP1_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX 2 9984 #define regDP1_DP_STREAM_SYMBOL_COUNT_CONTROL 0x22a3 9985 #define regDP1_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX 2 9986 #define regDP1_DP_LINK_SYMBOL_COUNT_STATUS0 0x22a4 9987 #define regDP1_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX 2 9988 #define regDP1_DP_LINK_SYMBOL_COUNT_STATUS1 0x22a5 9989 #define regDP1_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX 2 9990 #define regDP1_DP_LINK_SYMBOL_COUNT_CONTROL 0x22a6 9991 #define regDP1_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX 2 9992 #define regDP1_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL 0x22a7 9993 #define regDP1_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 9994 9995 9996 // addressBlock: dcn_dcec_dio_dig1_dispdec 9997 // base address: 0x490 9998 #define regDIG1_DIG_FE_CNTL 0x21b7 9999 #define regDIG1_DIG_FE_CNTL_BASE_IDX 2 10000 #define regDIG1_DIG_FE_CLK_CNTL 0x21b8 10001 #define regDIG1_DIG_FE_CLK_CNTL_BASE_IDX 2 10002 #define regDIG1_DIG_FE_EN_CNTL 0x21b9 10003 #define regDIG1_DIG_FE_EN_CNTL_BASE_IDX 2 10004 #define regDIG1_DIG_OUTPUT_CRC_CNTL 0x21ba 10005 #define regDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 10006 #define regDIG1_DIG_OUTPUT_CRC_RESULT 0x21bb 10007 #define regDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 10008 #define regDIG1_DIG_CLOCK_PATTERN 0x21bc 10009 #define regDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2 10010 #define regDIG1_DIG_TEST_PATTERN 0x21bd 10011 #define regDIG1_DIG_TEST_PATTERN_BASE_IDX 2 10012 #define regDIG1_DIG_RANDOM_PATTERN_SEED 0x21be 10013 #define regDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 10014 #define regDIG1_DIG_FIFO_CTRL0 0x21bf 10015 #define regDIG1_DIG_FIFO_CTRL0_BASE_IDX 2 10016 #define regDIG1_DIG_FIFO_CTRL1 0x21c0 10017 #define regDIG1_DIG_FIFO_CTRL1_BASE_IDX 2 10018 #define regDIG1_HDMI_METADATA_PACKET_CONTROL 0x21c1 10019 #define regDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 10020 #define regDIG1_HDMI_CONTROL 0x21c2 10021 #define regDIG1_HDMI_CONTROL_BASE_IDX 2 10022 #define regDIG1_HDMI_STATUS 0x21c3 10023 #define regDIG1_HDMI_STATUS_BASE_IDX 2 10024 #define regDIG1_HDMI_AUDIO_PACKET_CONTROL 0x21c4 10025 #define regDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 10026 #define regDIG1_HDMI_ACR_PACKET_CONTROL 0x21c5 10027 #define regDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 10028 #define regDIG1_HDMI_VBI_PACKET_CONTROL 0x21c6 10029 #define regDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 10030 #define regDIG1_HDMI_INFOFRAME_CONTROL0 0x21c7 10031 #define regDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 10032 #define regDIG1_HDMI_INFOFRAME_CONTROL1 0x21c8 10033 #define regDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 10034 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x21c9 10035 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 10036 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL6 0x21ca 10037 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 10038 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL5 0x21cb 10039 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 10040 #define regDIG1_HDMI_GC 0x21cc 10041 #define regDIG1_HDMI_GC_BASE_IDX 2 10042 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x21cd 10043 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 10044 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL2 0x21ce 10045 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 10046 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL3 0x21cf 10047 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 10048 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL4 0x21d0 10049 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 10050 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL7 0x21d1 10051 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 10052 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL8 0x21d2 10053 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 10054 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL9 0x21d3 10055 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 10056 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL10 0x21d4 10057 #define regDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 10058 #define regDIG1_HDMI_DB_CONTROL 0x21d5 10059 #define regDIG1_HDMI_DB_CONTROL_BASE_IDX 2 10060 #define regDIG1_HDMI_ACR_32_0 0x21d6 10061 #define regDIG1_HDMI_ACR_32_0_BASE_IDX 2 10062 #define regDIG1_HDMI_ACR_32_1 0x21d7 10063 #define regDIG1_HDMI_ACR_32_1_BASE_IDX 2 10064 #define regDIG1_HDMI_ACR_44_0 0x21d8 10065 #define regDIG1_HDMI_ACR_44_0_BASE_IDX 2 10066 #define regDIG1_HDMI_ACR_44_1 0x21d9 10067 #define regDIG1_HDMI_ACR_44_1_BASE_IDX 2 10068 #define regDIG1_HDMI_ACR_48_0 0x21da 10069 #define regDIG1_HDMI_ACR_48_0_BASE_IDX 2 10070 #define regDIG1_HDMI_ACR_48_1 0x21db 10071 #define regDIG1_HDMI_ACR_48_1_BASE_IDX 2 10072 #define regDIG1_HDMI_ACR_STATUS_0 0x21dc 10073 #define regDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2 10074 #define regDIG1_HDMI_ACR_STATUS_1 0x21dd 10075 #define regDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2 10076 #define regDIG1_AFMT_CNTL 0x21de 10077 #define regDIG1_AFMT_CNTL_BASE_IDX 2 10078 #define regDIG1_DIG_BE_CLK_CNTL 0x21df 10079 #define regDIG1_DIG_BE_CLK_CNTL_BASE_IDX 2 10080 #define regDIG1_DIG_BE_CNTL 0x21e0 10081 #define regDIG1_DIG_BE_CNTL_BASE_IDX 2 10082 #define regDIG1_DIG_BE_EN_CNTL 0x21e1 10083 #define regDIG1_DIG_BE_EN_CNTL_BASE_IDX 2 10084 #define regDIG1_TMDS_CNTL 0x2208 10085 #define regDIG1_TMDS_CNTL_BASE_IDX 2 10086 #define regDIG1_TMDS_CONTROL_CHAR 0x2209 10087 #define regDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2 10088 #define regDIG1_TMDS_CONTROL0_FEEDBACK 0x220a 10089 #define regDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 10090 #define regDIG1_TMDS_STEREOSYNC_CTL_SEL 0x220b 10091 #define regDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 10092 #define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x220c 10093 #define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 10094 #define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x220d 10095 #define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 10096 #define regDIG1_TMDS_CTL_BITS 0x220f 10097 #define regDIG1_TMDS_CTL_BITS_BASE_IDX 2 10098 #define regDIG1_TMDS_DCBALANCER_CONTROL 0x2210 10099 #define regDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 10100 #define regDIG1_TMDS_SYNC_DCBALANCE_CHAR 0x2211 10101 #define regDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 10102 #define regDIG1_TMDS_CTL0_1_GEN_CNTL 0x2212 10103 #define regDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 10104 #define regDIG1_TMDS_CTL2_3_GEN_CNTL 0x2213 10105 #define regDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 10106 #define regDIG1_DIG_VERSION 0x2215 10107 #define regDIG1_DIG_VERSION_BASE_IDX 2 10108 10109 // addressBlock: dcn_dcec_dio_dp2_dispdec 10110 // base address: 0x920 10111 #define regDP2_DP_LINK_CNTL 0x2366 10112 #define regDP2_DP_LINK_CNTL_BASE_IDX 2 10113 #define regDP2_DP_PIXEL_FORMAT 0x2367 10114 #define regDP2_DP_PIXEL_FORMAT_BASE_IDX 2 10115 #define regDP2_DP_MSA_COLORIMETRY 0x2368 10116 #define regDP2_DP_MSA_COLORIMETRY_BASE_IDX 2 10117 #define regDP2_DP_CONFIG 0x2369 10118 #define regDP2_DP_CONFIG_BASE_IDX 2 10119 #define regDP2_DP_VID_STREAM_CNTL 0x236a 10120 #define regDP2_DP_VID_STREAM_CNTL_BASE_IDX 2 10121 #define regDP2_DP_STEER_FIFO 0x236b 10122 #define regDP2_DP_STEER_FIFO_BASE_IDX 2 10123 #define regDP2_DP_MSA_MISC 0x236c 10124 #define regDP2_DP_MSA_MISC_BASE_IDX 2 10125 #define regDP2_DP_DPHY_INTERNAL_CTRL 0x236d 10126 #define regDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 10127 #define regDP2_DP_VID_TIMING 0x236e 10128 #define regDP2_DP_VID_TIMING_BASE_IDX 2 10129 #define regDP2_DP_VID_N 0x236f 10130 #define regDP2_DP_VID_N_BASE_IDX 2 10131 #define regDP2_DP_VID_M 0x2370 10132 #define regDP2_DP_VID_M_BASE_IDX 2 10133 #define regDP2_DP_LINK_FRAMING_CNTL 0x2371 10134 #define regDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2 10135 #define regDP2_DP_HBR2_EYE_PATTERN 0x2372 10136 #define regDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2 10137 #define regDP2_DP_VID_MSA_VBID 0x2373 10138 #define regDP2_DP_VID_MSA_VBID_BASE_IDX 2 10139 #define regDP2_DP_VID_INTERRUPT_CNTL 0x2374 10140 #define regDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 10141 #define regDP2_DP_DPHY_CNTL 0x2375 10142 #define regDP2_DP_DPHY_CNTL_BASE_IDX 2 10143 #define regDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x2376 10144 #define regDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 10145 #define regDP2_DP_DPHY_SYM0 0x2377 10146 #define regDP2_DP_DPHY_SYM0_BASE_IDX 2 10147 #define regDP2_DP_DPHY_SYM1 0x2378 10148 #define regDP2_DP_DPHY_SYM1_BASE_IDX 2 10149 #define regDP2_DP_DPHY_SYM2 0x2379 10150 #define regDP2_DP_DPHY_SYM2_BASE_IDX 2 10151 #define regDP2_DP_DPHY_8B10B_CNTL 0x237a 10152 #define regDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2 10153 #define regDP2_DP_DPHY_PRBS_CNTL 0x237b 10154 #define regDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2 10155 #define regDP2_DP_DPHY_SCRAM_CNTL 0x237c 10156 #define regDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 10157 #define regDP2_DP_DPHY_CRC_EN 0x237d 10158 #define regDP2_DP_DPHY_CRC_EN_BASE_IDX 2 10159 #define regDP2_DP_DPHY_CRC_CNTL 0x237e 10160 #define regDP2_DP_DPHY_CRC_CNTL_BASE_IDX 2 10161 #define regDP2_DP_DPHY_CRC_RESULT 0x237f 10162 #define regDP2_DP_DPHY_CRC_RESULT_BASE_IDX 2 10163 #define regDP2_DP_DPHY_CRC_MST_CNTL 0x2380 10164 #define regDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 10165 #define regDP2_DP_DPHY_CRC_MST_STATUS 0x2381 10166 #define regDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 10167 #define regDP2_DP_DPHY_FAST_TRAINING 0x2382 10168 #define regDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2 10169 #define regDP2_DP_DPHY_FAST_TRAINING_STATUS 0x2383 10170 #define regDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 10171 #define regDP2_DP_TU_CNTL 0x2384 10172 #define regDP2_DP_TU_CNTL_BASE_IDX 2 10173 #define regDP2_DP_PIXEL_FORMAT_DB_CNTL 0x2385 10174 #define regDP2_DP_PIXEL_FORMAT_DB_CNTL_BASE_IDX 2 10175 #define regDP2_DP_CP_LINK_VERIFICATION_PATTERN 0x2386 10176 #define regDP2_DP_CP_LINK_VERIFICATION_PATTERN_BASE_IDX 2 10177 #define regDP2_DP_SEC_CNTL 0x2389 10178 #define regDP2_DP_SEC_CNTL_BASE_IDX 2 10179 #define regDP2_DP_SEC_CNTL1 0x238a 10180 #define regDP2_DP_SEC_CNTL1_BASE_IDX 2 10181 #define regDP2_DP_SEC_FRAMING1 0x238b 10182 #define regDP2_DP_SEC_FRAMING1_BASE_IDX 2 10183 #define regDP2_DP_SEC_FRAMING2 0x238c 10184 #define regDP2_DP_SEC_FRAMING2_BASE_IDX 2 10185 #define regDP2_DP_SEC_FRAMING3 0x238d 10186 #define regDP2_DP_SEC_FRAMING3_BASE_IDX 2 10187 #define regDP2_DP_SEC_FRAMING4 0x238e 10188 #define regDP2_DP_SEC_FRAMING4_BASE_IDX 2 10189 #define regDP2_DP_SEC_AUD_N 0x238f 10190 #define regDP2_DP_SEC_AUD_N_BASE_IDX 2 10191 #define regDP2_DP_SEC_AUD_N_READBACK 0x2390 10192 #define regDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2 10193 #define regDP2_DP_SEC_AUD_M 0x2391 10194 #define regDP2_DP_SEC_AUD_M_BASE_IDX 2 10195 #define regDP2_DP_SEC_AUD_M_READBACK 0x2392 10196 #define regDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2 10197 #define regDP2_DP_SEC_TIMESTAMP 0x2393 10198 #define regDP2_DP_SEC_TIMESTAMP_BASE_IDX 2 10199 #define regDP2_DP_SEC_PACKET_CNTL 0x2394 10200 #define regDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2 10201 #define regDP2_DP_MSE_RATE_CNTL 0x2395 10202 #define regDP2_DP_MSE_RATE_CNTL_BASE_IDX 2 10203 #define regDP2_DP_CP_MSE_STATUS 0x2396 10204 #define regDP2_DP_CP_MSE_STATUS_BASE_IDX 2 10205 #define regDP2_DP_MSE_RATE_UPDATE 0x2397 10206 #define regDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2 10207 #define regDP2_DP_MSE_SAT0 0x2398 10208 #define regDP2_DP_MSE_SAT0_BASE_IDX 2 10209 #define regDP2_DP_MSE_SAT1 0x2399 10210 #define regDP2_DP_MSE_SAT1_BASE_IDX 2 10211 #define regDP2_DP_MSE_SAT2 0x239a 10212 #define regDP2_DP_MSE_SAT2_BASE_IDX 2 10213 #define regDP2_DP_MSE_SAT_UPDATE 0x239b 10214 #define regDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2 10215 #define regDP2_DP_MSE_LINK_TIMING 0x239c 10216 #define regDP2_DP_MSE_LINK_TIMING_BASE_IDX 2 10217 #define regDP2_DP_MSE_MISC_CNTL 0x239d 10218 #define regDP2_DP_MSE_MISC_CNTL_BASE_IDX 2 10219 #define regDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x23a2 10220 #define regDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 10221 #define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x23a3 10222 #define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 10223 #define regDP2_DP_MSE_SAT0_STATUS 0x23a5 10224 #define regDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2 10225 #define regDP2_DP_MSE_SAT1_STATUS 0x23a6 10226 #define regDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2 10227 #define regDP2_DP_MSE_SAT2_STATUS 0x23a7 10228 #define regDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2 10229 #define regDP2_DP_DPIA_SPARE 0x23a8 10230 #define regDP2_DP_DPIA_SPARE_BASE_IDX 2 10231 #define regDP2_DP_HBLANK_CONTROL 0x23a9 10232 #define regDP2_DP_HBLANK_CONTROL_BASE_IDX 2 10233 #define regDP2_DP_MSA_TIMING_PARAM1 0x23aa 10234 #define regDP2_DP_MSA_TIMING_PARAM1_BASE_IDX 2 10235 #define regDP2_DP_MSA_TIMING_PARAM2 0x23ab 10236 #define regDP2_DP_MSA_TIMING_PARAM2_BASE_IDX 2 10237 #define regDP2_DP_MSA_TIMING_PARAM3 0x23ac 10238 #define regDP2_DP_MSA_TIMING_PARAM3_BASE_IDX 2 10239 #define regDP2_DP_MSA_TIMING_PARAM4 0x23ad 10240 #define regDP2_DP_MSA_TIMING_PARAM4_BASE_IDX 2 10241 #define regDP2_DP_MSO_CNTL 0x23ae 10242 #define regDP2_DP_MSO_CNTL_BASE_IDX 2 10243 #define regDP2_DP_MSO_CNTL1 0x23af 10244 #define regDP2_DP_MSO_CNTL1_BASE_IDX 2 10245 #define regDP2_DP_STEER_FIFO_CNTL 0x23b0 10246 #define regDP2_DP_STEER_FIFO_CNTL_BASE_IDX 2 10247 #define regDP2_DP_SEC_CNTL2 0x23b1 10248 #define regDP2_DP_SEC_CNTL2_BASE_IDX 2 10249 #define regDP2_DP_SEC_CNTL3 0x23b2 10250 #define regDP2_DP_SEC_CNTL3_BASE_IDX 2 10251 #define regDP2_DP_SEC_CNTL4 0x23b3 10252 #define regDP2_DP_SEC_CNTL4_BASE_IDX 2 10253 #define regDP2_DP_SEC_CNTL5 0x23b4 10254 #define regDP2_DP_SEC_CNTL5_BASE_IDX 2 10255 #define regDP2_DP_SEC_CNTL6 0x23b5 10256 #define regDP2_DP_SEC_CNTL6_BASE_IDX 2 10257 #define regDP2_DP_SEC_CNTL7 0x23b6 10258 #define regDP2_DP_SEC_CNTL7_BASE_IDX 2 10259 #define regDP2_DP_DB_CNTL 0x23b7 10260 #define regDP2_DP_DB_CNTL_BASE_IDX 2 10261 #define regDP2_DP_MSA_VBID_MISC 0x23b8 10262 #define regDP2_DP_MSA_VBID_MISC_BASE_IDX 2 10263 #define regDP2_DP_SEC_METADATA_TRANSMISSION 0x23b9 10264 #define regDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 10265 #define regDP2_DP_ALPM_CNTL 0x23bb 10266 #define regDP2_DP_ALPM_CNTL_BASE_IDX 2 10267 #define regDP2_DP_GSP8_CNTL 0x23bc 10268 #define regDP2_DP_GSP8_CNTL_BASE_IDX 2 10269 #define regDP2_DP_GSP9_CNTL 0x23bd 10270 #define regDP2_DP_GSP9_CNTL_BASE_IDX 2 10271 #define regDP2_DP_GSP10_CNTL 0x23be 10272 #define regDP2_DP_GSP10_CNTL_BASE_IDX 2 10273 #define regDP2_DP_GSP11_CNTL 0x23bf 10274 #define regDP2_DP_GSP11_CNTL_BASE_IDX 2 10275 #define regDP2_DP_GSP_EN_DB_STATUS 0x23c0 10276 #define regDP2_DP_GSP_EN_DB_STATUS_BASE_IDX 2 10277 #define regDP2_DP_AUXLESS_ALPM_CNTL1 0x23c1 10278 #define regDP2_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 10279 #define regDP2_DP_AUXLESS_ALPM_CNTL2 0x23c2 10280 #define regDP2_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 10281 #define regDP2_DP_AUXLESS_ALPM_CNTL3 0x23c3 10282 #define regDP2_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 10283 #define regDP2_DP_AUXLESS_ALPM_CNTL4 0x23c4 10284 #define regDP2_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 10285 #define regDP2_DP_AUXLESS_ALPM_CNTL5 0x23c5 10286 #define regDP2_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 10287 #define regDP2_DP_STREAM_SYMBOL_COUNT_STATUS 0x23c6 10288 #define regDP2_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX 2 10289 #define regDP2_DP_STREAM_SYMBOL_COUNT_CONTROL 0x23c7 10290 #define regDP2_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX 2 10291 #define regDP2_DP_LINK_SYMBOL_COUNT_STATUS0 0x23c8 10292 #define regDP2_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX 2 10293 #define regDP2_DP_LINK_SYMBOL_COUNT_STATUS1 0x23c9 10294 #define regDP2_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX 2 10295 #define regDP2_DP_LINK_SYMBOL_COUNT_CONTROL 0x23ca 10296 #define regDP2_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX 2 10297 #define regDP2_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL 0x23cb 10298 #define regDP2_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 10299 10300 10301 // addressBlock: dcn_dcec_dio_dig2_dispdec 10302 // base address: 0x920 10303 #define regDIG2_DIG_FE_CNTL 0x22db 10304 #define regDIG2_DIG_FE_CNTL_BASE_IDX 2 10305 #define regDIG2_DIG_FE_CLK_CNTL 0x22dc 10306 #define regDIG2_DIG_FE_CLK_CNTL_BASE_IDX 2 10307 #define regDIG2_DIG_FE_EN_CNTL 0x22dd 10308 #define regDIG2_DIG_FE_EN_CNTL_BASE_IDX 2 10309 #define regDIG2_DIG_OUTPUT_CRC_CNTL 0x22de 10310 #define regDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 10311 #define regDIG2_DIG_OUTPUT_CRC_RESULT 0x22df 10312 #define regDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 10313 #define regDIG2_DIG_CLOCK_PATTERN 0x22e0 10314 #define regDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2 10315 #define regDIG2_DIG_TEST_PATTERN 0x22e1 10316 #define regDIG2_DIG_TEST_PATTERN_BASE_IDX 2 10317 #define regDIG2_DIG_RANDOM_PATTERN_SEED 0x22e2 10318 #define regDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 10319 #define regDIG2_DIG_FIFO_CTRL0 0x22e3 10320 #define regDIG2_DIG_FIFO_CTRL0_BASE_IDX 2 10321 #define regDIG2_DIG_FIFO_CTRL1 0x22e4 10322 #define regDIG2_DIG_FIFO_CTRL1_BASE_IDX 2 10323 #define regDIG2_HDMI_METADATA_PACKET_CONTROL 0x22e5 10324 #define regDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 10325 #define regDIG2_HDMI_CONTROL 0x22e6 10326 #define regDIG2_HDMI_CONTROL_BASE_IDX 2 10327 #define regDIG2_HDMI_STATUS 0x22e7 10328 #define regDIG2_HDMI_STATUS_BASE_IDX 2 10329 #define regDIG2_HDMI_AUDIO_PACKET_CONTROL 0x22e8 10330 #define regDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 10331 #define regDIG2_HDMI_ACR_PACKET_CONTROL 0x22e9 10332 #define regDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 10333 #define regDIG2_HDMI_VBI_PACKET_CONTROL 0x22ea 10334 #define regDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 10335 #define regDIG2_HDMI_INFOFRAME_CONTROL0 0x22eb 10336 #define regDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 10337 #define regDIG2_HDMI_INFOFRAME_CONTROL1 0x22ec 10338 #define regDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 10339 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x22ed 10340 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 10341 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL6 0x22ee 10342 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 10343 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL5 0x22ef 10344 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 10345 #define regDIG2_HDMI_GC 0x22f0 10346 #define regDIG2_HDMI_GC_BASE_IDX 2 10347 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x22f1 10348 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 10349 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL2 0x22f2 10350 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 10351 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL3 0x22f3 10352 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 10353 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL4 0x22f4 10354 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 10355 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL7 0x22f5 10356 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 10357 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL8 0x22f6 10358 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 10359 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL9 0x22f7 10360 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 10361 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL10 0x22f8 10362 #define regDIG2_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 10363 #define regDIG2_HDMI_DB_CONTROL 0x22f9 10364 #define regDIG2_HDMI_DB_CONTROL_BASE_IDX 2 10365 #define regDIG2_HDMI_ACR_32_0 0x22fa 10366 #define regDIG2_HDMI_ACR_32_0_BASE_IDX 2 10367 #define regDIG2_HDMI_ACR_32_1 0x22fb 10368 #define regDIG2_HDMI_ACR_32_1_BASE_IDX 2 10369 #define regDIG2_HDMI_ACR_44_0 0x22fc 10370 #define regDIG2_HDMI_ACR_44_0_BASE_IDX 2 10371 #define regDIG2_HDMI_ACR_44_1 0x22fd 10372 #define regDIG2_HDMI_ACR_44_1_BASE_IDX 2 10373 #define regDIG2_HDMI_ACR_48_0 0x22fe 10374 #define regDIG2_HDMI_ACR_48_0_BASE_IDX 2 10375 #define regDIG2_HDMI_ACR_48_1 0x22ff 10376 #define regDIG2_HDMI_ACR_48_1_BASE_IDX 2 10377 #define regDIG2_HDMI_ACR_STATUS_0 0x2300 10378 #define regDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2 10379 #define regDIG2_HDMI_ACR_STATUS_1 0x2301 10380 #define regDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2 10381 #define regDIG2_AFMT_CNTL 0x2302 10382 #define regDIG2_AFMT_CNTL_BASE_IDX 2 10383 #define regDIG2_DIG_BE_CLK_CNTL 0x2303 10384 #define regDIG2_DIG_BE_CLK_CNTL_BASE_IDX 2 10385 #define regDIG2_DIG_BE_CNTL 0x2304 10386 #define regDIG2_DIG_BE_CNTL_BASE_IDX 2 10387 #define regDIG2_DIG_BE_EN_CNTL 0x2305 10388 #define regDIG2_DIG_BE_EN_CNTL_BASE_IDX 2 10389 #define regDIG2_TMDS_CNTL 0x232c 10390 #define regDIG2_TMDS_CNTL_BASE_IDX 2 10391 #define regDIG2_TMDS_CONTROL_CHAR 0x232d 10392 #define regDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2 10393 #define regDIG2_TMDS_CONTROL0_FEEDBACK 0x232e 10394 #define regDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 10395 #define regDIG2_TMDS_STEREOSYNC_CTL_SEL 0x232f 10396 #define regDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 10397 #define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x2330 10398 #define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 10399 #define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x2331 10400 #define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 10401 #define regDIG2_TMDS_CTL_BITS 0x2333 10402 #define regDIG2_TMDS_CTL_BITS_BASE_IDX 2 10403 #define regDIG2_TMDS_DCBALANCER_CONTROL 0x2334 10404 #define regDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 10405 #define regDIG2_TMDS_SYNC_DCBALANCE_CHAR 0x2335 10406 #define regDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 10407 #define regDIG2_TMDS_CTL0_1_GEN_CNTL 0x2336 10408 #define regDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 10409 #define regDIG2_TMDS_CTL2_3_GEN_CNTL 0x2337 10410 #define regDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 10411 #define regDIG2_DIG_VERSION 0x2339 10412 #define regDIG2_DIG_VERSION_BASE_IDX 2 10413 10414 // addressBlock: dcn_dcec_dio_dp3_dispdec 10415 // base address: 0xdb0 10416 #define regDP3_DP_LINK_CNTL 0x248a 10417 #define regDP3_DP_LINK_CNTL_BASE_IDX 2 10418 #define regDP3_DP_PIXEL_FORMAT 0x248b 10419 #define regDP3_DP_PIXEL_FORMAT_BASE_IDX 2 10420 #define regDP3_DP_MSA_COLORIMETRY 0x248c 10421 #define regDP3_DP_MSA_COLORIMETRY_BASE_IDX 2 10422 #define regDP3_DP_CONFIG 0x248d 10423 #define regDP3_DP_CONFIG_BASE_IDX 2 10424 #define regDP3_DP_VID_STREAM_CNTL 0x248e 10425 #define regDP3_DP_VID_STREAM_CNTL_BASE_IDX 2 10426 #define regDP3_DP_STEER_FIFO 0x248f 10427 #define regDP3_DP_STEER_FIFO_BASE_IDX 2 10428 #define regDP3_DP_MSA_MISC 0x2490 10429 #define regDP3_DP_MSA_MISC_BASE_IDX 2 10430 #define regDP3_DP_DPHY_INTERNAL_CTRL 0x2491 10431 #define regDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 10432 #define regDP3_DP_VID_TIMING 0x2492 10433 #define regDP3_DP_VID_TIMING_BASE_IDX 2 10434 #define regDP3_DP_VID_N 0x2493 10435 #define regDP3_DP_VID_N_BASE_IDX 2 10436 #define regDP3_DP_VID_M 0x2494 10437 #define regDP3_DP_VID_M_BASE_IDX 2 10438 #define regDP3_DP_LINK_FRAMING_CNTL 0x2495 10439 #define regDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2 10440 #define regDP3_DP_HBR2_EYE_PATTERN 0x2496 10441 #define regDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2 10442 #define regDP3_DP_VID_MSA_VBID 0x2497 10443 #define regDP3_DP_VID_MSA_VBID_BASE_IDX 2 10444 #define regDP3_DP_VID_INTERRUPT_CNTL 0x2498 10445 #define regDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 10446 #define regDP3_DP_DPHY_CNTL 0x2499 10447 #define regDP3_DP_DPHY_CNTL_BASE_IDX 2 10448 #define regDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x249a 10449 #define regDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 10450 #define regDP3_DP_DPHY_SYM0 0x249b 10451 #define regDP3_DP_DPHY_SYM0_BASE_IDX 2 10452 #define regDP3_DP_DPHY_SYM1 0x249c 10453 #define regDP3_DP_DPHY_SYM1_BASE_IDX 2 10454 #define regDP3_DP_DPHY_SYM2 0x249d 10455 #define regDP3_DP_DPHY_SYM2_BASE_IDX 2 10456 #define regDP3_DP_DPHY_8B10B_CNTL 0x249e 10457 #define regDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2 10458 #define regDP3_DP_DPHY_PRBS_CNTL 0x249f 10459 #define regDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2 10460 #define regDP3_DP_DPHY_SCRAM_CNTL 0x24a0 10461 #define regDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 10462 #define regDP3_DP_DPHY_CRC_EN 0x24a1 10463 #define regDP3_DP_DPHY_CRC_EN_BASE_IDX 2 10464 #define regDP3_DP_DPHY_CRC_CNTL 0x24a2 10465 #define regDP3_DP_DPHY_CRC_CNTL_BASE_IDX 2 10466 #define regDP3_DP_DPHY_CRC_RESULT 0x24a3 10467 #define regDP3_DP_DPHY_CRC_RESULT_BASE_IDX 2 10468 #define regDP3_DP_DPHY_CRC_MST_CNTL 0x24a4 10469 #define regDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 10470 #define regDP3_DP_DPHY_CRC_MST_STATUS 0x24a5 10471 #define regDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 10472 #define regDP3_DP_DPHY_FAST_TRAINING 0x24a6 10473 #define regDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2 10474 #define regDP3_DP_DPHY_FAST_TRAINING_STATUS 0x24a7 10475 #define regDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 10476 #define regDP3_DP_TU_CNTL 0x24a8 10477 #define regDP3_DP_TU_CNTL_BASE_IDX 2 10478 #define regDP3_DP_PIXEL_FORMAT_DB_CNTL 0x24a9 10479 #define regDP3_DP_PIXEL_FORMAT_DB_CNTL_BASE_IDX 2 10480 #define regDP3_DP_CP_LINK_VERIFICATION_PATTERN 0x24aa 10481 #define regDP3_DP_CP_LINK_VERIFICATION_PATTERN_BASE_IDX 2 10482 #define regDP3_DP_SEC_CNTL 0x24ad 10483 #define regDP3_DP_SEC_CNTL_BASE_IDX 2 10484 #define regDP3_DP_SEC_CNTL1 0x24ae 10485 #define regDP3_DP_SEC_CNTL1_BASE_IDX 2 10486 #define regDP3_DP_SEC_FRAMING1 0x24af 10487 #define regDP3_DP_SEC_FRAMING1_BASE_IDX 2 10488 #define regDP3_DP_SEC_FRAMING2 0x24b0 10489 #define regDP3_DP_SEC_FRAMING2_BASE_IDX 2 10490 #define regDP3_DP_SEC_FRAMING3 0x24b1 10491 #define regDP3_DP_SEC_FRAMING3_BASE_IDX 2 10492 #define regDP3_DP_SEC_FRAMING4 0x24b2 10493 #define regDP3_DP_SEC_FRAMING4_BASE_IDX 2 10494 #define regDP3_DP_SEC_AUD_N 0x24b3 10495 #define regDP3_DP_SEC_AUD_N_BASE_IDX 2 10496 #define regDP3_DP_SEC_AUD_N_READBACK 0x24b4 10497 #define regDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2 10498 #define regDP3_DP_SEC_AUD_M 0x24b5 10499 #define regDP3_DP_SEC_AUD_M_BASE_IDX 2 10500 #define regDP3_DP_SEC_AUD_M_READBACK 0x24b6 10501 #define regDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2 10502 #define regDP3_DP_SEC_TIMESTAMP 0x24b7 10503 #define regDP3_DP_SEC_TIMESTAMP_BASE_IDX 2 10504 #define regDP3_DP_SEC_PACKET_CNTL 0x24b8 10505 #define regDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2 10506 #define regDP3_DP_MSE_RATE_CNTL 0x24b9 10507 #define regDP3_DP_MSE_RATE_CNTL_BASE_IDX 2 10508 #define regDP3_DP_CP_MSE_STATUS 0x24ba 10509 #define regDP3_DP_CP_MSE_STATUS_BASE_IDX 2 10510 #define regDP3_DP_MSE_RATE_UPDATE 0x24bb 10511 #define regDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2 10512 #define regDP3_DP_MSE_SAT0 0x24bc 10513 #define regDP3_DP_MSE_SAT0_BASE_IDX 2 10514 #define regDP3_DP_MSE_SAT1 0x24bd 10515 #define regDP3_DP_MSE_SAT1_BASE_IDX 2 10516 #define regDP3_DP_MSE_SAT2 0x24be 10517 #define regDP3_DP_MSE_SAT2_BASE_IDX 2 10518 #define regDP3_DP_MSE_SAT_UPDATE 0x24bf 10519 #define regDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2 10520 #define regDP3_DP_MSE_LINK_TIMING 0x24c0 10521 #define regDP3_DP_MSE_LINK_TIMING_BASE_IDX 2 10522 #define regDP3_DP_MSE_MISC_CNTL 0x24c1 10523 #define regDP3_DP_MSE_MISC_CNTL_BASE_IDX 2 10524 #define regDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x24c6 10525 #define regDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 10526 #define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x24c7 10527 #define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 10528 #define regDP3_DP_MSE_SAT0_STATUS 0x24c9 10529 #define regDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2 10530 #define regDP3_DP_MSE_SAT1_STATUS 0x24ca 10531 #define regDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2 10532 #define regDP3_DP_MSE_SAT2_STATUS 0x24cb 10533 #define regDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2 10534 #define regDP3_DP_DPIA_SPARE 0x24cc 10535 #define regDP3_DP_DPIA_SPARE_BASE_IDX 2 10536 #define regDP3_DP_HBLANK_CONTROL 0x24cd 10537 #define regDP3_DP_HBLANK_CONTROL_BASE_IDX 2 10538 #define regDP3_DP_MSA_TIMING_PARAM1 0x24ce 10539 #define regDP3_DP_MSA_TIMING_PARAM1_BASE_IDX 2 10540 #define regDP3_DP_MSA_TIMING_PARAM2 0x24cf 10541 #define regDP3_DP_MSA_TIMING_PARAM2_BASE_IDX 2 10542 #define regDP3_DP_MSA_TIMING_PARAM3 0x24d0 10543 #define regDP3_DP_MSA_TIMING_PARAM3_BASE_IDX 2 10544 #define regDP3_DP_MSA_TIMING_PARAM4 0x24d1 10545 #define regDP3_DP_MSA_TIMING_PARAM4_BASE_IDX 2 10546 #define regDP3_DP_MSO_CNTL 0x24d2 10547 #define regDP3_DP_MSO_CNTL_BASE_IDX 2 10548 #define regDP3_DP_MSO_CNTL1 0x24d3 10549 #define regDP3_DP_MSO_CNTL1_BASE_IDX 2 10550 #define regDP3_DP_STEER_FIFO_CNTL 0x24d4 10551 #define regDP3_DP_STEER_FIFO_CNTL_BASE_IDX 2 10552 #define regDP3_DP_SEC_CNTL2 0x24d5 10553 #define regDP3_DP_SEC_CNTL2_BASE_IDX 2 10554 #define regDP3_DP_SEC_CNTL3 0x24d6 10555 #define regDP3_DP_SEC_CNTL3_BASE_IDX 2 10556 #define regDP3_DP_SEC_CNTL4 0x24d7 10557 #define regDP3_DP_SEC_CNTL4_BASE_IDX 2 10558 #define regDP3_DP_SEC_CNTL5 0x24d8 10559 #define regDP3_DP_SEC_CNTL5_BASE_IDX 2 10560 #define regDP3_DP_SEC_CNTL6 0x24d9 10561 #define regDP3_DP_SEC_CNTL6_BASE_IDX 2 10562 #define regDP3_DP_SEC_CNTL7 0x24da 10563 #define regDP3_DP_SEC_CNTL7_BASE_IDX 2 10564 #define regDP3_DP_DB_CNTL 0x24db 10565 #define regDP3_DP_DB_CNTL_BASE_IDX 2 10566 #define regDP3_DP_MSA_VBID_MISC 0x24dc 10567 #define regDP3_DP_MSA_VBID_MISC_BASE_IDX 2 10568 #define regDP3_DP_SEC_METADATA_TRANSMISSION 0x24dd 10569 #define regDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 10570 #define regDP3_DP_ALPM_CNTL 0x24df 10571 #define regDP3_DP_ALPM_CNTL_BASE_IDX 2 10572 #define regDP3_DP_GSP8_CNTL 0x24e0 10573 #define regDP3_DP_GSP8_CNTL_BASE_IDX 2 10574 #define regDP3_DP_GSP9_CNTL 0x24e1 10575 #define regDP3_DP_GSP9_CNTL_BASE_IDX 2 10576 #define regDP3_DP_GSP10_CNTL 0x24e2 10577 #define regDP3_DP_GSP10_CNTL_BASE_IDX 2 10578 #define regDP3_DP_GSP11_CNTL 0x24e3 10579 #define regDP3_DP_GSP11_CNTL_BASE_IDX 2 10580 #define regDP3_DP_GSP_EN_DB_STATUS 0x24e4 10581 #define regDP3_DP_GSP_EN_DB_STATUS_BASE_IDX 2 10582 #define regDP3_DP_AUXLESS_ALPM_CNTL1 0x24e5 10583 #define regDP3_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 10584 #define regDP3_DP_AUXLESS_ALPM_CNTL2 0x24e6 10585 #define regDP3_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 10586 #define regDP3_DP_AUXLESS_ALPM_CNTL3 0x24e7 10587 #define regDP3_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 10588 #define regDP3_DP_AUXLESS_ALPM_CNTL4 0x24e8 10589 #define regDP3_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 10590 #define regDP3_DP_AUXLESS_ALPM_CNTL5 0x24e9 10591 #define regDP3_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 10592 #define regDP3_DP_STREAM_SYMBOL_COUNT_STATUS 0x24ea 10593 #define regDP3_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX 2 10594 #define regDP3_DP_STREAM_SYMBOL_COUNT_CONTROL 0x24eb 10595 #define regDP3_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX 2 10596 #define regDP3_DP_LINK_SYMBOL_COUNT_STATUS0 0x24ec 10597 #define regDP3_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX 2 10598 #define regDP3_DP_LINK_SYMBOL_COUNT_STATUS1 0x24ed 10599 #define regDP3_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX 2 10600 #define regDP3_DP_LINK_SYMBOL_COUNT_CONTROL 0x24ee 10601 #define regDP3_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX 2 10602 #define regDP3_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL 0x24ef 10603 #define regDP3_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 10604 10605 10606 // addressBlock: dcn_dcec_dio_dig3_dispdec 10607 // base address: 0xdb0 10608 #define regDIG3_DIG_FE_CNTL 0x23ff 10609 #define regDIG3_DIG_FE_CNTL_BASE_IDX 2 10610 #define regDIG3_DIG_FE_CLK_CNTL 0x2400 10611 #define regDIG3_DIG_FE_CLK_CNTL_BASE_IDX 2 10612 #define regDIG3_DIG_FE_EN_CNTL 0x2401 10613 #define regDIG3_DIG_FE_EN_CNTL_BASE_IDX 2 10614 #define regDIG3_DIG_OUTPUT_CRC_CNTL 0x2402 10615 #define regDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 10616 #define regDIG3_DIG_OUTPUT_CRC_RESULT 0x2403 10617 #define regDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 10618 #define regDIG3_DIG_CLOCK_PATTERN 0x2404 10619 #define regDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2 10620 #define regDIG3_DIG_TEST_PATTERN 0x2405 10621 #define regDIG3_DIG_TEST_PATTERN_BASE_IDX 2 10622 #define regDIG3_DIG_RANDOM_PATTERN_SEED 0x2406 10623 #define regDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 10624 #define regDIG3_DIG_FIFO_CTRL0 0x2407 10625 #define regDIG3_DIG_FIFO_CTRL0_BASE_IDX 2 10626 #define regDIG3_DIG_FIFO_CTRL1 0x2408 10627 #define regDIG3_DIG_FIFO_CTRL1_BASE_IDX 2 10628 #define regDIG3_HDMI_METADATA_PACKET_CONTROL 0x2409 10629 #define regDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 10630 #define regDIG3_HDMI_CONTROL 0x240a 10631 #define regDIG3_HDMI_CONTROL_BASE_IDX 2 10632 #define regDIG3_HDMI_STATUS 0x240b 10633 #define regDIG3_HDMI_STATUS_BASE_IDX 2 10634 #define regDIG3_HDMI_AUDIO_PACKET_CONTROL 0x240c 10635 #define regDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 10636 #define regDIG3_HDMI_ACR_PACKET_CONTROL 0x240d 10637 #define regDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 10638 #define regDIG3_HDMI_VBI_PACKET_CONTROL 0x240e 10639 #define regDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 10640 #define regDIG3_HDMI_INFOFRAME_CONTROL0 0x240f 10641 #define regDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 10642 #define regDIG3_HDMI_INFOFRAME_CONTROL1 0x2410 10643 #define regDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 10644 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x2411 10645 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 10646 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL6 0x2412 10647 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 10648 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL5 0x2413 10649 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 10650 #define regDIG3_HDMI_GC 0x2414 10651 #define regDIG3_HDMI_GC_BASE_IDX 2 10652 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x2415 10653 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 10654 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL2 0x2416 10655 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 10656 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL3 0x2417 10657 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 10658 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL4 0x2418 10659 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 10660 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL7 0x2419 10661 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 10662 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL8 0x241a 10663 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 10664 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL9 0x241b 10665 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 10666 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL10 0x241c 10667 #define regDIG3_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 10668 #define regDIG3_HDMI_DB_CONTROL 0x241d 10669 #define regDIG3_HDMI_DB_CONTROL_BASE_IDX 2 10670 #define regDIG3_HDMI_ACR_32_0 0x241e 10671 #define regDIG3_HDMI_ACR_32_0_BASE_IDX 2 10672 #define regDIG3_HDMI_ACR_32_1 0x241f 10673 #define regDIG3_HDMI_ACR_32_1_BASE_IDX 2 10674 #define regDIG3_HDMI_ACR_44_0 0x2420 10675 #define regDIG3_HDMI_ACR_44_0_BASE_IDX 2 10676 #define regDIG3_HDMI_ACR_44_1 0x2421 10677 #define regDIG3_HDMI_ACR_44_1_BASE_IDX 2 10678 #define regDIG3_HDMI_ACR_48_0 0x2422 10679 #define regDIG3_HDMI_ACR_48_0_BASE_IDX 2 10680 #define regDIG3_HDMI_ACR_48_1 0x2423 10681 #define regDIG3_HDMI_ACR_48_1_BASE_IDX 2 10682 #define regDIG3_HDMI_ACR_STATUS_0 0x2424 10683 #define regDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2 10684 #define regDIG3_HDMI_ACR_STATUS_1 0x2425 10685 #define regDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2 10686 #define regDIG3_AFMT_CNTL 0x2426 10687 #define regDIG3_AFMT_CNTL_BASE_IDX 2 10688 #define regDIG3_DIG_BE_CLK_CNTL 0x2427 10689 #define regDIG3_DIG_BE_CLK_CNTL_BASE_IDX 2 10690 #define regDIG3_DIG_BE_CNTL 0x2428 10691 #define regDIG3_DIG_BE_CNTL_BASE_IDX 2 10692 #define regDIG3_DIG_BE_EN_CNTL 0x2429 10693 #define regDIG3_DIG_BE_EN_CNTL_BASE_IDX 2 10694 #define regDIG3_TMDS_CNTL 0x2450 10695 #define regDIG3_TMDS_CNTL_BASE_IDX 2 10696 #define regDIG3_TMDS_CONTROL_CHAR 0x2451 10697 #define regDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2 10698 #define regDIG3_TMDS_CONTROL0_FEEDBACK 0x2452 10699 #define regDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 10700 #define regDIG3_TMDS_STEREOSYNC_CTL_SEL 0x2453 10701 #define regDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 10702 #define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x2454 10703 #define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 10704 #define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x2455 10705 #define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 10706 #define regDIG3_TMDS_CTL_BITS 0x2457 10707 #define regDIG3_TMDS_CTL_BITS_BASE_IDX 2 10708 #define regDIG3_TMDS_DCBALANCER_CONTROL 0x2458 10709 #define regDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 10710 #define regDIG3_TMDS_SYNC_DCBALANCE_CHAR 0x2459 10711 #define regDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 10712 #define regDIG3_TMDS_CTL0_1_GEN_CNTL 0x245a 10713 #define regDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 10714 #define regDIG3_TMDS_CTL2_3_GEN_CNTL 0x245b 10715 #define regDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 10716 #define regDIG3_DIG_VERSION 0x245d 10717 #define regDIG3_DIG_VERSION_BASE_IDX 2 10718 10719 // addressBlock: dcn_dcec_dio_dig0_afmt_afmt_dispdec 10720 // base address: 0x154cc 10721 #define regAFMT0_AFMT_ACP 0x2073 10722 #define regAFMT0_AFMT_ACP_BASE_IDX 2 10723 #define regAFMT0_AFMT_VBI_PACKET_CONTROL 0x2074 10724 #define regAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 10725 #define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2 0x2075 10726 #define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 10727 #define regAFMT0_AFMT_AUDIO_INFO0 0x2076 10728 #define regAFMT0_AFMT_AUDIO_INFO0_BASE_IDX 2 10729 #define regAFMT0_AFMT_AUDIO_INFO1 0x2077 10730 #define regAFMT0_AFMT_AUDIO_INFO1_BASE_IDX 2 10731 #define regAFMT0_AFMT_60958_0 0x2078 10732 #define regAFMT0_AFMT_60958_0_BASE_IDX 2 10733 #define regAFMT0_AFMT_60958_1 0x2079 10734 #define regAFMT0_AFMT_60958_1_BASE_IDX 2 10735 #define regAFMT0_AFMT_AUDIO_CRC_CONTROL 0x207a 10736 #define regAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 10737 #define regAFMT0_AFMT_RAMP_CONTROL0 0x207b 10738 #define regAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX 2 10739 #define regAFMT0_AFMT_RAMP_CONTROL1 0x207c 10740 #define regAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX 2 10741 #define regAFMT0_AFMT_RAMP_CONTROL2 0x207d 10742 #define regAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX 2 10743 #define regAFMT0_AFMT_RAMP_CONTROL3 0x207e 10744 #define regAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX 2 10745 #define regAFMT0_AFMT_60958_2 0x207f 10746 #define regAFMT0_AFMT_60958_2_BASE_IDX 2 10747 #define regAFMT0_AFMT_AUDIO_CRC_RESULT 0x2080 10748 #define regAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 10749 #define regAFMT0_AFMT_STATUS 0x2081 10750 #define regAFMT0_AFMT_STATUS_BASE_IDX 2 10751 #define regAFMT0_AFMT_AUDIO_PACKET_CONTROL 0x2082 10752 #define regAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 10753 #define regAFMT0_AFMT_INFOFRAME_CONTROL0 0x2083 10754 #define regAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 10755 #define regAFMT0_AFMT_INTERRUPT_STATUS 0x2084 10756 #define regAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX 2 10757 #define regAFMT0_AFMT_AUDIO_SRC_CONTROL 0x2085 10758 #define regAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 10759 #define regAFMT0_AFMT_AUDIO_DBG_DTO_CNTL 0x2086 10760 #define regAFMT0_AFMT_AUDIO_DBG_DTO_CNTL_BASE_IDX 2 10761 #define regAFMT0_AFMT_MEM_PWR 0x2087 10762 #define regAFMT0_AFMT_MEM_PWR_BASE_IDX 2 10763 10764 10765 // addressBlock: dcn_dcec_dio_dig1_afmt_afmt_dispdec 10766 // base address: 0x1595c 10767 #define regAFMT1_AFMT_ACP 0x2197 10768 #define regAFMT1_AFMT_ACP_BASE_IDX 2 10769 #define regAFMT1_AFMT_VBI_PACKET_CONTROL 0x2198 10770 #define regAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 10771 #define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2 0x2199 10772 #define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 10773 #define regAFMT1_AFMT_AUDIO_INFO0 0x219a 10774 #define regAFMT1_AFMT_AUDIO_INFO0_BASE_IDX 2 10775 #define regAFMT1_AFMT_AUDIO_INFO1 0x219b 10776 #define regAFMT1_AFMT_AUDIO_INFO1_BASE_IDX 2 10777 #define regAFMT1_AFMT_60958_0 0x219c 10778 #define regAFMT1_AFMT_60958_0_BASE_IDX 2 10779 #define regAFMT1_AFMT_60958_1 0x219d 10780 #define regAFMT1_AFMT_60958_1_BASE_IDX 2 10781 #define regAFMT1_AFMT_AUDIO_CRC_CONTROL 0x219e 10782 #define regAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 10783 #define regAFMT1_AFMT_RAMP_CONTROL0 0x219f 10784 #define regAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX 2 10785 #define regAFMT1_AFMT_RAMP_CONTROL1 0x21a0 10786 #define regAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX 2 10787 #define regAFMT1_AFMT_RAMP_CONTROL2 0x21a1 10788 #define regAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX 2 10789 #define regAFMT1_AFMT_RAMP_CONTROL3 0x21a2 10790 #define regAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX 2 10791 #define regAFMT1_AFMT_60958_2 0x21a3 10792 #define regAFMT1_AFMT_60958_2_BASE_IDX 2 10793 #define regAFMT1_AFMT_AUDIO_CRC_RESULT 0x21a4 10794 #define regAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 10795 #define regAFMT1_AFMT_STATUS 0x21a5 10796 #define regAFMT1_AFMT_STATUS_BASE_IDX 2 10797 #define regAFMT1_AFMT_AUDIO_PACKET_CONTROL 0x21a6 10798 #define regAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 10799 #define regAFMT1_AFMT_INFOFRAME_CONTROL0 0x21a7 10800 #define regAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 10801 #define regAFMT1_AFMT_INTERRUPT_STATUS 0x21a8 10802 #define regAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX 2 10803 #define regAFMT1_AFMT_AUDIO_SRC_CONTROL 0x21a9 10804 #define regAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 10805 #define regAFMT1_AFMT_AUDIO_DBG_DTO_CNTL 0x21aa 10806 #define regAFMT1_AFMT_AUDIO_DBG_DTO_CNTL_BASE_IDX 2 10807 #define regAFMT1_AFMT_MEM_PWR 0x21ab 10808 #define regAFMT1_AFMT_MEM_PWR_BASE_IDX 2 10809 10810 10811 // addressBlock: dcn_dcec_dio_dig2_afmt_afmt_dispdec 10812 // base address: 0x15dec 10813 #define regAFMT2_AFMT_ACP 0x22bb 10814 #define regAFMT2_AFMT_ACP_BASE_IDX 2 10815 #define regAFMT2_AFMT_VBI_PACKET_CONTROL 0x22bc 10816 #define regAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 10817 #define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2 0x22bd 10818 #define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 10819 #define regAFMT2_AFMT_AUDIO_INFO0 0x22be 10820 #define regAFMT2_AFMT_AUDIO_INFO0_BASE_IDX 2 10821 #define regAFMT2_AFMT_AUDIO_INFO1 0x22bf 10822 #define regAFMT2_AFMT_AUDIO_INFO1_BASE_IDX 2 10823 #define regAFMT2_AFMT_60958_0 0x22c0 10824 #define regAFMT2_AFMT_60958_0_BASE_IDX 2 10825 #define regAFMT2_AFMT_60958_1 0x22c1 10826 #define regAFMT2_AFMT_60958_1_BASE_IDX 2 10827 #define regAFMT2_AFMT_AUDIO_CRC_CONTROL 0x22c2 10828 #define regAFMT2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 10829 #define regAFMT2_AFMT_RAMP_CONTROL0 0x22c3 10830 #define regAFMT2_AFMT_RAMP_CONTROL0_BASE_IDX 2 10831 #define regAFMT2_AFMT_RAMP_CONTROL1 0x22c4 10832 #define regAFMT2_AFMT_RAMP_CONTROL1_BASE_IDX 2 10833 #define regAFMT2_AFMT_RAMP_CONTROL2 0x22c5 10834 #define regAFMT2_AFMT_RAMP_CONTROL2_BASE_IDX 2 10835 #define regAFMT2_AFMT_RAMP_CONTROL3 0x22c6 10836 #define regAFMT2_AFMT_RAMP_CONTROL3_BASE_IDX 2 10837 #define regAFMT2_AFMT_60958_2 0x22c7 10838 #define regAFMT2_AFMT_60958_2_BASE_IDX 2 10839 #define regAFMT2_AFMT_AUDIO_CRC_RESULT 0x22c8 10840 #define regAFMT2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 10841 #define regAFMT2_AFMT_STATUS 0x22c9 10842 #define regAFMT2_AFMT_STATUS_BASE_IDX 2 10843 #define regAFMT2_AFMT_AUDIO_PACKET_CONTROL 0x22ca 10844 #define regAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 10845 #define regAFMT2_AFMT_INFOFRAME_CONTROL0 0x22cb 10846 #define regAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 10847 #define regAFMT2_AFMT_INTERRUPT_STATUS 0x22cc 10848 #define regAFMT2_AFMT_INTERRUPT_STATUS_BASE_IDX 2 10849 #define regAFMT2_AFMT_AUDIO_SRC_CONTROL 0x22cd 10850 #define regAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 10851 #define regAFMT2_AFMT_AUDIO_DBG_DTO_CNTL 0x22ce 10852 #define regAFMT2_AFMT_AUDIO_DBG_DTO_CNTL_BASE_IDX 2 10853 #define regAFMT2_AFMT_MEM_PWR 0x22cf 10854 #define regAFMT2_AFMT_MEM_PWR_BASE_IDX 2 10855 10856 10857 // addressBlock: dcn_dcec_dio_dig3_afmt_afmt_dispdec 10858 // base address: 0x1627c 10859 #define regAFMT3_AFMT_ACP 0x23df 10860 #define regAFMT3_AFMT_ACP_BASE_IDX 2 10861 #define regAFMT3_AFMT_VBI_PACKET_CONTROL 0x23e0 10862 #define regAFMT3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 10863 #define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2 0x23e1 10864 #define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 10865 #define regAFMT3_AFMT_AUDIO_INFO0 0x23e2 10866 #define regAFMT3_AFMT_AUDIO_INFO0_BASE_IDX 2 10867 #define regAFMT3_AFMT_AUDIO_INFO1 0x23e3 10868 #define regAFMT3_AFMT_AUDIO_INFO1_BASE_IDX 2 10869 #define regAFMT3_AFMT_60958_0 0x23e4 10870 #define regAFMT3_AFMT_60958_0_BASE_IDX 2 10871 #define regAFMT3_AFMT_60958_1 0x23e5 10872 #define regAFMT3_AFMT_60958_1_BASE_IDX 2 10873 #define regAFMT3_AFMT_AUDIO_CRC_CONTROL 0x23e6 10874 #define regAFMT3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 10875 #define regAFMT3_AFMT_RAMP_CONTROL0 0x23e7 10876 #define regAFMT3_AFMT_RAMP_CONTROL0_BASE_IDX 2 10877 #define regAFMT3_AFMT_RAMP_CONTROL1 0x23e8 10878 #define regAFMT3_AFMT_RAMP_CONTROL1_BASE_IDX 2 10879 #define regAFMT3_AFMT_RAMP_CONTROL2 0x23e9 10880 #define regAFMT3_AFMT_RAMP_CONTROL2_BASE_IDX 2 10881 #define regAFMT3_AFMT_RAMP_CONTROL3 0x23ea 10882 #define regAFMT3_AFMT_RAMP_CONTROL3_BASE_IDX 2 10883 #define regAFMT3_AFMT_60958_2 0x23eb 10884 #define regAFMT3_AFMT_60958_2_BASE_IDX 2 10885 #define regAFMT3_AFMT_AUDIO_CRC_RESULT 0x23ec 10886 #define regAFMT3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 10887 #define regAFMT3_AFMT_STATUS 0x23ed 10888 #define regAFMT3_AFMT_STATUS_BASE_IDX 2 10889 #define regAFMT3_AFMT_AUDIO_PACKET_CONTROL 0x23ee 10890 #define regAFMT3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 10891 #define regAFMT3_AFMT_INFOFRAME_CONTROL0 0x23ef 10892 #define regAFMT3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 10893 #define regAFMT3_AFMT_INTERRUPT_STATUS 0x23f0 10894 #define regAFMT3_AFMT_INTERRUPT_STATUS_BASE_IDX 2 10895 #define regAFMT3_AFMT_AUDIO_SRC_CONTROL 0x23f1 10896 #define regAFMT3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 10897 #define regAFMT3_AFMT_AUDIO_DBG_DTO_CNTL 0x23f2 10898 #define regAFMT3_AFMT_AUDIO_DBG_DTO_CNTL_BASE_IDX 2 10899 #define regAFMT3_AFMT_MEM_PWR 0x23f3 10900 #define regAFMT3_AFMT_MEM_PWR_BASE_IDX 2 10901 10902 10903 // addressBlock: dcn_dcec_dio_dig0_dme_dme_dispdec 10904 // base address: 0x15544 10905 #define regDME0_DME_CONTROL 0x2091 10906 #define regDME0_DME_CONTROL_BASE_IDX 2 10907 #define regDME0_DME_MEMORY_CONTROL 0x2092 10908 #define regDME0_DME_MEMORY_CONTROL_BASE_IDX 2 10909 10910 10911 // addressBlock: dcn_dcec_dio_dig0_vpg_vpg_dispdec 10912 // base address: 0x154a0 10913 #define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2068 10914 #define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 10915 #define regVPG0_VPG_GENERIC_PACKET_DATA 0x2069 10916 #define regVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 10917 #define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL 0x206a 10918 #define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 10919 #define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x206b 10920 #define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 10921 #define regVPG0_VPG_GENERIC_STATUS 0x206c 10922 #define regVPG0_VPG_GENERIC_STATUS_BASE_IDX 2 10923 #define regVPG0_VPG_MEM_PWR 0x206d 10924 #define regVPG0_VPG_MEM_PWR_BASE_IDX 2 10925 #define regVPG0_VPG_ISRC1_2_ACCESS_CTRL 0x206e 10926 #define regVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 10927 #define regVPG0_VPG_ISRC1_2_DATA 0x206f 10928 #define regVPG0_VPG_ISRC1_2_DATA_BASE_IDX 2 10929 #define regVPG0_VPG_MPEG_INFO0 0x2070 10930 #define regVPG0_VPG_MPEG_INFO0_BASE_IDX 2 10931 #define regVPG0_VPG_MPEG_INFO1 0x2071 10932 #define regVPG0_VPG_MPEG_INFO1_BASE_IDX 2 10933 10934 10935 // addressBlock: dcn_dcec_dio_dig1_dme_dme_dispdec 10936 // base address: 0x159d4 10937 #define regDME1_DME_CONTROL 0x21b5 10938 #define regDME1_DME_CONTROL_BASE_IDX 2 10939 #define regDME1_DME_MEMORY_CONTROL 0x21b6 10940 #define regDME1_DME_MEMORY_CONTROL_BASE_IDX 2 10941 10942 10943 // addressBlock: dcn_dcec_dio_dig1_vpg_vpg_dispdec 10944 // base address: 0x15930 10945 #define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL 0x218c 10946 #define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 10947 #define regVPG1_VPG_GENERIC_PACKET_DATA 0x218d 10948 #define regVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 10949 #define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL 0x218e 10950 #define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 10951 #define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x218f 10952 #define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 10953 #define regVPG1_VPG_GENERIC_STATUS 0x2190 10954 #define regVPG1_VPG_GENERIC_STATUS_BASE_IDX 2 10955 #define regVPG1_VPG_MEM_PWR 0x2191 10956 #define regVPG1_VPG_MEM_PWR_BASE_IDX 2 10957 #define regVPG1_VPG_ISRC1_2_ACCESS_CTRL 0x2192 10958 #define regVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 10959 #define regVPG1_VPG_ISRC1_2_DATA 0x2193 10960 #define regVPG1_VPG_ISRC1_2_DATA_BASE_IDX 2 10961 #define regVPG1_VPG_MPEG_INFO0 0x2194 10962 #define regVPG1_VPG_MPEG_INFO0_BASE_IDX 2 10963 #define regVPG1_VPG_MPEG_INFO1 0x2195 10964 #define regVPG1_VPG_MPEG_INFO1_BASE_IDX 2 10965 10966 10967 // addressBlock: dcn_dcec_dio_dig2_dme_dme_dispdec 10968 // base address: 0x15e64 10969 #define regDME2_DME_CONTROL 0x22d9 10970 #define regDME2_DME_CONTROL_BASE_IDX 2 10971 #define regDME2_DME_MEMORY_CONTROL 0x22da 10972 #define regDME2_DME_MEMORY_CONTROL_BASE_IDX 2 10973 10974 10975 // addressBlock: dcn_dcec_dio_dig2_vpg_vpg_dispdec 10976 // base address: 0x15dc0 10977 #define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL 0x22b0 10978 #define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 10979 #define regVPG2_VPG_GENERIC_PACKET_DATA 0x22b1 10980 #define regVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 10981 #define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL 0x22b2 10982 #define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 10983 #define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x22b3 10984 #define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 10985 #define regVPG2_VPG_GENERIC_STATUS 0x22b4 10986 #define regVPG2_VPG_GENERIC_STATUS_BASE_IDX 2 10987 #define regVPG2_VPG_MEM_PWR 0x22b5 10988 #define regVPG2_VPG_MEM_PWR_BASE_IDX 2 10989 #define regVPG2_VPG_ISRC1_2_ACCESS_CTRL 0x22b6 10990 #define regVPG2_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 10991 #define regVPG2_VPG_ISRC1_2_DATA 0x22b7 10992 #define regVPG2_VPG_ISRC1_2_DATA_BASE_IDX 2 10993 #define regVPG2_VPG_MPEG_INFO0 0x22b8 10994 #define regVPG2_VPG_MPEG_INFO0_BASE_IDX 2 10995 #define regVPG2_VPG_MPEG_INFO1 0x22b9 10996 #define regVPG2_VPG_MPEG_INFO1_BASE_IDX 2 10997 10998 10999 // addressBlock: dcn_dcec_dio_dig3_dme_dme_dispdec 11000 // base address: 0x162f4 11001 #define regDME3_DME_CONTROL 0x23fd 11002 #define regDME3_DME_CONTROL_BASE_IDX 2 11003 #define regDME3_DME_MEMORY_CONTROL 0x23fe 11004 #define regDME3_DME_MEMORY_CONTROL_BASE_IDX 2 11005 11006 11007 // addressBlock: dcn_dcec_dio_dig3_vpg_vpg_dispdec 11008 // base address: 0x16250 11009 #define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL 0x23d4 11010 #define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 11011 #define regVPG3_VPG_GENERIC_PACKET_DATA 0x23d5 11012 #define regVPG3_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 11013 #define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL 0x23d6 11014 #define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 11015 #define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x23d7 11016 #define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 11017 #define regVPG3_VPG_GENERIC_STATUS 0x23d8 11018 #define regVPG3_VPG_GENERIC_STATUS_BASE_IDX 2 11019 #define regVPG3_VPG_MEM_PWR 0x23d9 11020 #define regVPG3_VPG_MEM_PWR_BASE_IDX 2 11021 #define regVPG3_VPG_ISRC1_2_ACCESS_CTRL 0x23da 11022 #define regVPG3_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 11023 #define regVPG3_VPG_ISRC1_2_DATA 0x23db 11024 #define regVPG3_VPG_ISRC1_2_DATA_BASE_IDX 2 11025 #define regVPG3_VPG_MPEG_INFO0 0x23dc 11026 #define regVPG3_VPG_MPEG_INFO0_BASE_IDX 2 11027 #define regVPG3_VPG_MPEG_INFO1 0x23dd 11028 #define regVPG3_VPG_MPEG_INFO1_BASE_IDX 2 11029 11030 11031 // addressBlock: dcn_dcec_dio_hdcp1kp_dispdec 11032 // base address: 0x14cd8 11033 11034 11035 // addressBlock: dcn_dcec_dio_dout_i2c_dispdec 11036 // base address: 0x0 11037 #define regDC_I2C_CONTROL 0x1e98 11038 #define regDC_I2C_CONTROL_BASE_IDX 2 11039 #define regDC_I2C_ARBITRATION 0x1e99 11040 #define regDC_I2C_ARBITRATION_BASE_IDX 2 11041 #define regDC_I2C_INTERRUPT_CONTROL 0x1e9a 11042 #define regDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2 11043 #define regDC_I2C_SW_STATUS 0x1e9b 11044 #define regDC_I2C_SW_STATUS_BASE_IDX 2 11045 #define regDC_I2C_DDC1_HW_STATUS 0x1e9c 11046 #define regDC_I2C_DDC1_HW_STATUS_BASE_IDX 2 11047 #define regDC_I2C_DDC2_HW_STATUS 0x1e9d 11048 #define regDC_I2C_DDC2_HW_STATUS_BASE_IDX 2 11049 #define regDC_I2C_DDC3_HW_STATUS 0x1e9e 11050 #define regDC_I2C_DDC3_HW_STATUS_BASE_IDX 2 11051 #define regDC_I2C_DDC4_HW_STATUS 0x1e9f 11052 #define regDC_I2C_DDC4_HW_STATUS_BASE_IDX 2 11053 #define regDC_I2C_DDC5_HW_STATUS 0x1ea0 11054 #define regDC_I2C_DDC5_HW_STATUS_BASE_IDX 2 11055 #define regDC_I2C_DDC6_HW_STATUS 0x1ea1 11056 #define regDC_I2C_DDC6_HW_STATUS_BASE_IDX 2 11057 #define regDC_I2C_DDC1_SPEED 0x1ea2 11058 #define regDC_I2C_DDC1_SPEED_BASE_IDX 2 11059 #define regDC_I2C_DDC1_SETUP 0x1ea3 11060 #define regDC_I2C_DDC1_SETUP_BASE_IDX 2 11061 #define regDC_I2C_DDC2_SPEED 0x1ea4 11062 #define regDC_I2C_DDC2_SPEED_BASE_IDX 2 11063 #define regDC_I2C_DDC2_SETUP 0x1ea5 11064 #define regDC_I2C_DDC2_SETUP_BASE_IDX 2 11065 #define regDC_I2C_DDC3_SPEED 0x1ea6 11066 #define regDC_I2C_DDC3_SPEED_BASE_IDX 2 11067 #define regDC_I2C_DDC3_SETUP 0x1ea7 11068 #define regDC_I2C_DDC3_SETUP_BASE_IDX 2 11069 #define regDC_I2C_DDC4_SPEED 0x1ea8 11070 #define regDC_I2C_DDC4_SPEED_BASE_IDX 2 11071 #define regDC_I2C_DDC4_SETUP 0x1ea9 11072 #define regDC_I2C_DDC4_SETUP_BASE_IDX 2 11073 #define regDC_I2C_DDC5_SPEED 0x1eaa 11074 #define regDC_I2C_DDC5_SPEED_BASE_IDX 2 11075 #define regDC_I2C_DDC5_SETUP 0x1eab 11076 #define regDC_I2C_DDC5_SETUP_BASE_IDX 2 11077 #define regDC_I2C_DDC6_SPEED 0x1eac 11078 #define regDC_I2C_DDC6_SPEED_BASE_IDX 2 11079 #define regDC_I2C_DDC6_SETUP 0x1ead 11080 #define regDC_I2C_DDC6_SETUP_BASE_IDX 2 11081 #define regDC_I2C_TRANSACTION0 0x1eae 11082 #define regDC_I2C_TRANSACTION0_BASE_IDX 2 11083 #define regDC_I2C_TRANSACTION1 0x1eaf 11084 #define regDC_I2C_TRANSACTION1_BASE_IDX 2 11085 #define regDC_I2C_TRANSACTION2 0x1eb0 11086 #define regDC_I2C_TRANSACTION2_BASE_IDX 2 11087 #define regDC_I2C_TRANSACTION3 0x1eb1 11088 #define regDC_I2C_TRANSACTION3_BASE_IDX 2 11089 #define regDC_I2C_DATA 0x1eb2 11090 #define regDC_I2C_DATA_BASE_IDX 2 11091 #define regDC_I2C_DDCVGA_HW_STATUS 0x1eb3 11092 #define regDC_I2C_DDCVGA_HW_STATUS_BASE_IDX 2 11093 #define regDC_I2C_DDCVGA_SPEED 0x1eb4 11094 #define regDC_I2C_DDCVGA_SPEED_BASE_IDX 2 11095 #define regDC_I2C_DDCVGA_SETUP 0x1eb5 11096 #define regDC_I2C_DDCVGA_SETUP_BASE_IDX 2 11097 #define regDC_I2C_EDID_DETECT_CTRL 0x1eb6 11098 #define regDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2 11099 #define regDC_I2C_READ_REQUEST_INTERRUPT 0x1eb7 11100 #define regDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2 11101 11102 11103 // addressBlock: dcn_dcec_dio_dio_misc_dispdec 11104 // base address: 0x0 11105 #define regDIO_DCN_STATUS 0x1ec3 11106 #define regDIO_DCN_STATUS_BASE_IDX 2 11107 #define regDIO_SCRATCH0 0x1eca 11108 #define regDIO_SCRATCH0_BASE_IDX 2 11109 #define regDIO_SCRATCH1 0x1ecb 11110 #define regDIO_SCRATCH1_BASE_IDX 2 11111 #define regDIO_SCRATCH2 0x1ecc 11112 #define regDIO_SCRATCH2_BASE_IDX 2 11113 #define regDIO_SCRATCH3 0x1ecd 11114 #define regDIO_SCRATCH3_BASE_IDX 2 11115 #define regDIO_SCRATCH4 0x1ece 11116 #define regDIO_SCRATCH4_BASE_IDX 2 11117 #define regDIO_SCRATCH5 0x1ecf 11118 #define regDIO_SCRATCH5_BASE_IDX 2 11119 #define regDIO_SCRATCH6 0x1ed0 11120 #define regDIO_SCRATCH6_BASE_IDX 2 11121 #define regDIO_SCRATCH7 0x1ed1 11122 #define regDIO_SCRATCH7_BASE_IDX 2 11123 #define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS 0x1ed3 11124 #define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS_BASE_IDX 2 11125 #define regDIO_MEM_PWR_STATUS 0x1edd 11126 #define regDIO_MEM_PWR_STATUS_BASE_IDX 2 11127 #define regDIO_MEM_PWR_CTRL 0x1ede 11128 #define regDIO_MEM_PWR_CTRL_BASE_IDX 2 11129 #define regDIO_MEM_PWR_CTRL2 0x1edf 11130 #define regDIO_MEM_PWR_CTRL2_BASE_IDX 2 11131 #define regDIO_CLK_CNTL 0x1ee0 11132 #define regDIO_CLK_CNTL_BASE_IDX 2 11133 #define regDIO_POWER_MANAGEMENT_CNTL 0x1ee4 11134 #define regDIO_POWER_MANAGEMENT_CNTL_BASE_IDX 2 11135 #define regDIO_STEREOSYNC_SEL 0x1eea 11136 #define regDIO_STEREOSYNC_SEL_BASE_IDX 2 11137 #define regDIO_SOFT_RESET 0x1eed 11138 #define regDIO_SOFT_RESET_BASE_IDX 2 11139 #define regHDCP_CLK_STATUS 0x1ef4 11140 #define regHDCP_CLK_STATUS_BASE_IDX 2 11141 #define regDIO_HDMI_RXSTATUS_TIMER_CONTROL 0x1eff 11142 #define regDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2 11143 #define regDIO_PSP_INTERRUPT_STATUS 0x1f00 11144 #define regDIO_PSP_INTERRUPT_STATUS_BASE_IDX 2 11145 #define regDIO_PSP_INTERRUPT_CLEAR 0x1f01 11146 #define regDIO_PSP_INTERRUPT_CLEAR_BASE_IDX 2 11147 #define regDIO_STATUS 0x1f02 11148 #define regDIO_STATUS_BASE_IDX 2 11149 11150 11151 // addressBlock: dcn_dcec_dio_dig_stream_mapper_dispdec 11152 // base address: 0x0 11153 #define regDIG0_STREAM_MAPPER_CONTROL 0x1f0d 11154 #define regDIG0_STREAM_MAPPER_CONTROL_BASE_IDX 2 11155 #define regDIG1_STREAM_MAPPER_CONTROL 0x1f0e 11156 #define regDIG1_STREAM_MAPPER_CONTROL_BASE_IDX 2 11157 #define regDIG2_STREAM_MAPPER_CONTROL 0x1f0f 11158 #define regDIG2_STREAM_MAPPER_CONTROL_BASE_IDX 2 11159 #define regDIG3_STREAM_MAPPER_CONTROL 0x1f10 11160 #define regDIG3_STREAM_MAPPER_CONTROL_BASE_IDX 2 11161 #define regDIG4_STREAM_MAPPER_CONTROL 0x1f11 11162 #define regDIG4_STREAM_MAPPER_CONTROL_BASE_IDX 2 11163 #define regDIG5_STREAM_MAPPER_CONTROL 0x1f12 11164 #define regDIG5_STREAM_MAPPER_CONTROL_BASE_IDX 2 11165 #define regDIG6_STREAM_MAPPER_CONTROL 0x1f13 11166 #define regDIG6_STREAM_MAPPER_CONTROL_BASE_IDX 2 11167 11168 11169 // addressBlock: dcn_dcec_dcio_dcio_dispdec 11170 // base address: 0x0 11171 #define regDC_GENERICA 0x2868 11172 #define regDC_GENERICA_BASE_IDX 2 11173 #define regDC_GENERICB 0x2869 11174 #define regDC_GENERICB_BASE_IDX 2 11175 #define regDCIO_CLOCK_CNTL 0x286a 11176 #define regDCIO_CLOCK_CNTL_BASE_IDX 2 11177 #define regDC_REF_CLK_CNTL 0x286b 11178 #define regDC_REF_CLK_CNTL_BASE_IDX 2 11179 #define regUNIPHYA_LINK_CNTL 0x286d 11180 #define regUNIPHYA_LINK_CNTL_BASE_IDX 2 11181 #define regUNIPHYA_CHANNEL_XBAR_CNTL 0x286e 11182 #define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2 11183 #define regUNIPHYB_LINK_CNTL 0x286f 11184 #define regUNIPHYB_LINK_CNTL_BASE_IDX 2 11185 #define regUNIPHYB_CHANNEL_XBAR_CNTL 0x2870 11186 #define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2 11187 #define regUNIPHYC_LINK_CNTL 0x2871 11188 #define regUNIPHYC_LINK_CNTL_BASE_IDX 2 11189 #define regUNIPHYC_CHANNEL_XBAR_CNTL 0x2872 11190 #define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2 11191 #define regUNIPHYD_LINK_CNTL 0x2873 11192 #define regUNIPHYD_LINK_CNTL_BASE_IDX 2 11193 #define regUNIPHYD_CHANNEL_XBAR_CNTL 0x2874 11194 #define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2 11195 #define regUNIPHYE_LINK_CNTL 0x2875 11196 #define regUNIPHYE_LINK_CNTL_BASE_IDX 2 11197 #define regUNIPHYE_CHANNEL_XBAR_CNTL 0x2876 11198 #define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2 11199 #define regUNIPHYF_LINK_CNTL 0x2877 11200 #define regUNIPHYF_LINK_CNTL_BASE_IDX 2 11201 #define regUNIPHYF_CHANNEL_XBAR_CNTL 0x2878 11202 #define regUNIPHYF_CHANNEL_XBAR_CNTL_BASE_IDX 2 11203 #define regUNIPHYG_LINK_CNTL 0x2879 11204 #define regUNIPHYG_LINK_CNTL_BASE_IDX 2 11205 #define regUNIPHYG_CHANNEL_XBAR_CNTL 0x287a 11206 #define regUNIPHYG_CHANNEL_XBAR_CNTL_BASE_IDX 2 11207 #define regDCIO_WRCMD_DELAY 0x287e 11208 #define regDCIO_WRCMD_DELAY_BASE_IDX 2 11209 #define regDC_PINSTRAPS 0x2880 11210 #define regDC_PINSTRAPS_BASE_IDX 2 11211 #define regCC_DC_MISC_STRAPS 0x2881 11212 #define regCC_DC_MISC_STRAPS_BASE_IDX 2 11213 #define regDCIO_SPARE 0x2882 11214 #define regDCIO_SPARE_BASE_IDX 2 11215 #define regINTERCEPT_STATE 0x2884 11216 #define regINTERCEPT_STATE_BASE_IDX 2 11217 #define regDCIO_PATTERN_GEN_PAT 0x2886 11218 #define regDCIO_PATTERN_GEN_PAT_BASE_IDX 2 11219 #define regDCIO_PATTERN_GEN_EN 0x2887 11220 #define regDCIO_PATTERN_GEN_EN_BASE_IDX 2 11221 #define regDCIO_BL_PWM_FRAME_START_DISP_SEL 0x288b 11222 #define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX 2 11223 #define regDCIO_GSL_GENLK_PAD_CNTL 0x288c 11224 #define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2 11225 #define regDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d 11226 #define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2 11227 #define regDBG_OUT_CNTL 0x289c 11228 #define regDBG_OUT_CNTL_BASE_IDX 2 11229 #define regDCIO_SOFT_RESET 0x289e 11230 #define regDCIO_SOFT_RESET_BASE_IDX 2 11231 11232 11233 // addressBlock: dcn_dcec_dcio_dcio_chip_dispdec 11234 // base address: 0x0 11235 #define regDC_GPIO_GENERIC_MASK 0x28c8 11236 #define regDC_GPIO_GENERIC_MASK_BASE_IDX 2 11237 #define regDC_GPIO_GENERIC_A 0x28c9 11238 #define regDC_GPIO_GENERIC_A_BASE_IDX 2 11239 #define regDC_GPIO_GENERIC_EN 0x28ca 11240 #define regDC_GPIO_GENERIC_EN_BASE_IDX 2 11241 #define regDC_GPIO_GENERIC_Y 0x28cb 11242 #define regDC_GPIO_GENERIC_Y_BASE_IDX 2 11243 #define regDC_GPIO_DDC1_MASK 0x28d0 11244 #define regDC_GPIO_DDC1_MASK_BASE_IDX 2 11245 #define regDC_GPIO_DDC1_A 0x28d1 11246 #define regDC_GPIO_DDC1_A_BASE_IDX 2 11247 #define regDC_GPIO_DDC1_EN 0x28d2 11248 #define regDC_GPIO_DDC1_EN_BASE_IDX 2 11249 #define regDC_GPIO_DDC1_Y 0x28d3 11250 #define regDC_GPIO_DDC1_Y_BASE_IDX 2 11251 #define regDC_GPIO_DDC2_MASK 0x28d4 11252 #define regDC_GPIO_DDC2_MASK_BASE_IDX 2 11253 #define regDC_GPIO_DDC2_A 0x28d5 11254 #define regDC_GPIO_DDC2_A_BASE_IDX 2 11255 #define regDC_GPIO_DDC2_EN 0x28d6 11256 #define regDC_GPIO_DDC2_EN_BASE_IDX 2 11257 #define regDC_GPIO_DDC2_Y 0x28d7 11258 #define regDC_GPIO_DDC2_Y_BASE_IDX 2 11259 #define regDC_GPIO_DDC3_MASK 0x28d8 11260 #define regDC_GPIO_DDC3_MASK_BASE_IDX 2 11261 #define regDC_GPIO_DDC3_A 0x28d9 11262 #define regDC_GPIO_DDC3_A_BASE_IDX 2 11263 #define regDC_GPIO_DDC3_EN 0x28da 11264 #define regDC_GPIO_DDC3_EN_BASE_IDX 2 11265 #define regDC_GPIO_DDC3_Y 0x28db 11266 #define regDC_GPIO_DDC3_Y_BASE_IDX 2 11267 #define regDC_GPIO_DDC4_MASK 0x28dc 11268 #define regDC_GPIO_DDC4_MASK_BASE_IDX 2 11269 #define regDC_GPIO_DDC4_A 0x28dd 11270 #define regDC_GPIO_DDC4_A_BASE_IDX 2 11271 #define regDC_GPIO_DDC4_EN 0x28de 11272 #define regDC_GPIO_DDC4_EN_BASE_IDX 2 11273 #define regDC_GPIO_DDC4_Y 0x28df 11274 #define regDC_GPIO_DDC4_Y_BASE_IDX 2 11275 #define regDC_GPIO_DDC5_MASK 0x28e0 11276 #define regDC_GPIO_DDC5_MASK_BASE_IDX 2 11277 #define regDC_GPIO_DDC5_A 0x28e1 11278 #define regDC_GPIO_DDC5_A_BASE_IDX 2 11279 #define regDC_GPIO_DDC5_EN 0x28e2 11280 #define regDC_GPIO_DDC5_EN_BASE_IDX 2 11281 #define regDC_GPIO_DDC5_Y 0x28e3 11282 #define regDC_GPIO_DDC5_Y_BASE_IDX 2 11283 #define regDC_GPIO_DDC6_MASK 0x28e4 11284 #define regDC_GPIO_DDC6_MASK_BASE_IDX 2 11285 #define regDC_GPIO_DDC6_A 0x28e5 11286 #define regDC_GPIO_DDC6_A_BASE_IDX 2 11287 #define regDC_GPIO_DDC6_EN 0x28e6 11288 #define regDC_GPIO_DDC6_EN_BASE_IDX 2 11289 #define regDC_GPIO_DDC6_Y 0x28e7 11290 #define regDC_GPIO_DDC6_Y_BASE_IDX 2 11291 #define regDC_GPIO_DDCVGA_MASK 0x28e8 11292 #define regDC_GPIO_DDCVGA_MASK_BASE_IDX 2 11293 #define regDC_GPIO_DDCVGA_A 0x28e9 11294 #define regDC_GPIO_DDCVGA_A_BASE_IDX 2 11295 #define regDC_GPIO_DDCVGA_EN 0x28ea 11296 #define regDC_GPIO_DDCVGA_EN_BASE_IDX 2 11297 #define regDC_GPIO_DDCVGA_Y 0x28eb 11298 #define regDC_GPIO_DDCVGA_Y_BASE_IDX 2 11299 #define regDC_GPIO_SYNCA_MASK 0x28ec 11300 #define regDC_GPIO_SYNCA_MASK_BASE_IDX 2 11301 #define regDC_GPIO_GENLK_MASK 0x28f0 11302 #define regDC_GPIO_GENLK_MASK_BASE_IDX 2 11303 #define regDC_GPIO_GENLK_A 0x28f1 11304 #define regDC_GPIO_GENLK_A_BASE_IDX 2 11305 #define regDC_GPIO_GENLK_EN 0x28f2 11306 #define regDC_GPIO_GENLK_EN_BASE_IDX 2 11307 #define regDC_GPIO_GENLK_Y 0x28f3 11308 #define regDC_GPIO_GENLK_Y_BASE_IDX 2 11309 #define regDC_GPIO_HPD_MASK 0x28f4 11310 #define regDC_GPIO_HPD_MASK_BASE_IDX 2 11311 #define regDC_GPIO_HPD_A 0x28f5 11312 #define regDC_GPIO_HPD_A_BASE_IDX 2 11313 #define regDC_GPIO_HPD_EN 0x28f6 11314 #define regDC_GPIO_HPD_EN_BASE_IDX 2 11315 #define regDC_GPIO_HPD_Y 0x28f7 11316 #define regDC_GPIO_HPD_Y_BASE_IDX 2 11317 #define regDC_GPIO_DRIVE_STRENGTH_S0 0x28f8 11318 #define regDC_GPIO_DRIVE_STRENGTH_S0_BASE_IDX 2 11319 #define regDC_GPIO_DRIVE_STRENGTH_S1 0x28f9 11320 #define regDC_GPIO_DRIVE_STRENGTH_S1_BASE_IDX 2 11321 #define regDC_GPIO_PWRSEQ0_EN 0x28fa 11322 #define regDC_GPIO_PWRSEQ0_EN_BASE_IDX 2 11323 #define regDC_GPIO_PAD_STRENGTH_1 0x28fc 11324 #define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2 11325 #define regDC_GPIO_RESERVED 0x28fe 11326 #define regDC_GPIO_RESERVED_BASE_IDX 2 11327 #define regPHY_AUX_CNTL 0x28ff 11328 #define regPHY_AUX_CNTL_BASE_IDX 2 11329 #define regDC_GPIO_DRIVE_TXIMPSEL 0x2900 11330 #define regDC_GPIO_DRIVE_TXIMPSEL_BASE_IDX 2 11331 #define regDC_GPIO_PWRSEQ1_EN 0x2902 11332 #define regDC_GPIO_PWRSEQ1_EN_BASE_IDX 2 11333 #define regDC_GPIO_I2S_SPDIF_MASK 0x2910 11334 #define regDC_GPIO_I2S_SPDIF_MASK_BASE_IDX 2 11335 #define regDC_GPIO_I2S_SPDIF_A 0x2911 11336 #define regDC_GPIO_I2S_SPDIF_A_BASE_IDX 2 11337 #define regDC_GPIO_I2S_SPDIF_EN 0x2912 11338 #define regDC_GPIO_I2S_SPDIF_EN_BASE_IDX 2 11339 #define regDC_GPIO_I2S_SPDIF_Y 0x2913 11340 #define regDC_GPIO_I2S_SPDIF_Y_BASE_IDX 2 11341 #define regDC_GPIO_I2S_SPDIF_STRENGTH 0x2914 11342 #define regDC_GPIO_I2S_SPDIF_STRENGTH_BASE_IDX 2 11343 #define regDC_GPIO_TX12_EN 0x2915 11344 #define regDC_GPIO_TX12_EN_BASE_IDX 2 11345 #define regDC_GPIO_AUX_CTRL_0 0x2916 11346 #define regDC_GPIO_AUX_CTRL_0_BASE_IDX 2 11347 #define regDC_GPIO_AUX_CTRL_1 0x2917 11348 #define regDC_GPIO_AUX_CTRL_1_BASE_IDX 2 11349 #define regDC_GPIO_RXEN 0x2919 11350 #define regDC_GPIO_RXEN_BASE_IDX 2 11351 #define regDC_GPIO_PULLUPEN 0x291a 11352 #define regDC_GPIO_PULLUPEN_BASE_IDX 2 11353 #define regDC_GPIO_AUX_CTRL_3 0x291b 11354 #define regDC_GPIO_AUX_CTRL_3_BASE_IDX 2 11355 #define regDC_GPIO_AUX_CTRL_4 0x291c 11356 #define regDC_GPIO_AUX_CTRL_4_BASE_IDX 2 11357 #define regDC_GPIO_AUX_CTRL_5 0x291d 11358 #define regDC_GPIO_AUX_CTRL_5_BASE_IDX 2 11359 #define regAUXI2C_PAD_ALL_PWR_OK 0x291e 11360 #define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2 11361 11362 11363 // addressBlock: dcn_dcec_dcio_dcio_uniphy0_dispdec 11364 // base address: 0x0 11365 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x2928 11366 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 11367 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x2929 11368 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 11369 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x292a 11370 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 11371 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x292b 11372 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 11373 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x292c 11374 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 11375 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x292d 11376 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 11377 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x292e 11378 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 11379 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x292f 11380 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 11381 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x2930 11382 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 11383 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x2931 11384 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 11385 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x2932 11386 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 11387 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x2933 11388 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 11389 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x2934 11390 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 11391 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x2935 11392 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 11393 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x2936 11394 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 11395 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x2937 11396 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 11397 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x2938 11398 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 11399 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x2939 11400 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 11401 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x293a 11402 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 11403 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x293b 11404 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 11405 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x293c 11406 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 11407 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x293d 11408 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 11409 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x293e 11410 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 11411 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x293f 11412 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 11413 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x2940 11414 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 11415 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x2941 11416 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 11417 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x2942 11418 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 11419 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x2943 11420 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 11421 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x2944 11422 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 11423 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x2945 11424 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 11425 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x2946 11426 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 11427 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x2947 11428 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 11429 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32 0x2948 11430 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 11431 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33 0x2949 11432 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 11433 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34 0x294a 11434 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 11435 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35 0x294b 11436 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 11437 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36 0x294c 11438 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 11439 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37 0x294d 11440 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 11441 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38 0x294e 11442 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 11443 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39 0x294f 11444 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 11445 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40 0x2950 11446 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 11447 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41 0x2951 11448 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 11449 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42 0x2952 11450 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 11451 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43 0x2953 11452 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 11453 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44 0x2954 11454 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 11455 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45 0x2955 11456 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 11457 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46 0x2956 11458 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 11459 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47 0x2957 11460 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 11461 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48 0x2958 11462 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 11463 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49 0x2959 11464 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 11465 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50 0x295a 11466 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 11467 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51 0x295b 11468 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 11469 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52 0x295c 11470 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 11471 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53 0x295d 11472 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 11473 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54 0x295e 11474 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 11475 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55 0x295f 11476 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 11477 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56 0x2960 11478 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 11479 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57 0x2961 11480 #define regDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 11481 11482 11483 // addressBlock: dcn_dcec_dcio_dcio_uniphy1_dispdec 11484 // base address: 0x360 11485 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x2a00 11486 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 11487 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x2a01 11488 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 11489 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x2a02 11490 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 11491 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x2a03 11492 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 11493 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x2a04 11494 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 11495 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x2a05 11496 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 11497 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x2a06 11498 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 11499 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x2a07 11500 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 11501 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x2a08 11502 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 11503 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x2a09 11504 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 11505 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x2a0a 11506 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 11507 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x2a0b 11508 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 11509 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x2a0c 11510 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 11511 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x2a0d 11512 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 11513 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x2a0e 11514 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 11515 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x2a0f 11516 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 11517 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x2a10 11518 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 11519 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x2a11 11520 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 11521 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x2a12 11522 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 11523 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x2a13 11524 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 11525 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x2a14 11526 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 11527 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x2a15 11528 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 11529 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x2a16 11530 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 11531 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x2a17 11532 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 11533 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x2a18 11534 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 11535 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x2a19 11536 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 11537 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x2a1a 11538 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 11539 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x2a1b 11540 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 11541 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x2a1c 11542 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 11543 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x2a1d 11544 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 11545 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x2a1e 11546 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 11547 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x2a1f 11548 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 11549 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0x2a20 11550 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 11551 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0x2a21 11552 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 11553 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0x2a22 11554 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 11555 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0x2a23 11556 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 11557 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0x2a24 11558 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 11559 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0x2a25 11560 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 11561 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0x2a26 11562 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 11563 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0x2a27 11564 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 11565 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0x2a28 11566 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 11567 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0x2a29 11568 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 11569 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0x2a2a 11570 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 11571 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0x2a2b 11572 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 11573 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0x2a2c 11574 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 11575 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0x2a2d 11576 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 11577 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0x2a2e 11578 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 11579 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0x2a2f 11580 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 11581 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0x2a30 11582 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 11583 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0x2a31 11584 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 11585 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0x2a32 11586 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 11587 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0x2a33 11588 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 11589 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0x2a34 11590 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 11591 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0x2a35 11592 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 11593 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0x2a36 11594 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 11595 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0x2a37 11596 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 11597 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0x2a38 11598 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 11599 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0x2a39 11600 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 11601 11602 11603 // addressBlock: dcn_dcec_dcio_dcio_uniphy2_dispdec 11604 // base address: 0x6c0 11605 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x2ad8 11606 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 11607 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x2ad9 11608 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 11609 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x2ada 11610 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 11611 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x2adb 11612 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 11613 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x2adc 11614 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 11615 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x2add 11616 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 11617 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x2ade 11618 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 11619 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x2adf 11620 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 11621 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x2ae0 11622 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 11623 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x2ae1 11624 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 11625 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x2ae2 11626 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 11627 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x2ae3 11628 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 11629 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x2ae4 11630 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 11631 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x2ae5 11632 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 11633 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x2ae6 11634 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 11635 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x2ae7 11636 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 11637 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x2ae8 11638 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 11639 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x2ae9 11640 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 11641 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x2aea 11642 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 11643 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x2aeb 11644 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 11645 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x2aec 11646 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 11647 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x2aed 11648 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 11649 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x2aee 11650 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 11651 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x2aef 11652 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 11653 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x2af0 11654 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 11655 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x2af1 11656 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 11657 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x2af2 11658 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 11659 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x2af3 11660 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 11661 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x2af4 11662 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 11663 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x2af5 11664 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 11665 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x2af6 11666 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 11667 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x2af7 11668 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 11669 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0x2af8 11670 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 11671 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0x2af9 11672 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 11673 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0x2afa 11674 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 11675 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0x2afb 11676 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 11677 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0x2afc 11678 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 11679 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0x2afd 11680 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 11681 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0x2afe 11682 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 11683 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0x2aff 11684 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 11685 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0x2b00 11686 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 11687 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0x2b01 11688 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 11689 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0x2b02 11690 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 11691 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0x2b03 11692 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 11693 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0x2b04 11694 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 11695 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0x2b05 11696 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 11697 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0x2b06 11698 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 11699 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0x2b07 11700 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 11701 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0x2b08 11702 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 11703 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0x2b09 11704 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 11705 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0x2b0a 11706 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 11707 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0x2b0b 11708 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 11709 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0x2b0c 11710 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 11711 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0x2b0d 11712 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 11713 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0x2b0e 11714 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 11715 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0x2b0f 11716 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 11717 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0x2b10 11718 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 11719 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0x2b11 11720 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 11721 11722 11723 // addressBlock: dcn_dcec_dcio_dcio_uniphy3_dispdec 11724 // base address: 0xa20 11725 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x2bb0 11726 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 11727 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x2bb1 11728 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 11729 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x2bb2 11730 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 11731 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x2bb3 11732 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 11733 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x2bb4 11734 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 11735 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x2bb5 11736 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 11737 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x2bb6 11738 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 11739 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x2bb7 11740 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 11741 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x2bb8 11742 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 11743 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x2bb9 11744 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 11745 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x2bba 11746 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 11747 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x2bbb 11748 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 11749 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x2bbc 11750 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 11751 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x2bbd 11752 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 11753 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x2bbe 11754 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 11755 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x2bbf 11756 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 11757 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x2bc0 11758 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 11759 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x2bc1 11760 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 11761 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x2bc2 11762 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 11763 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x2bc3 11764 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 11765 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x2bc4 11766 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 11767 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x2bc5 11768 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 11769 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x2bc6 11770 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 11771 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x2bc7 11772 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 11773 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x2bc8 11774 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 11775 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x2bc9 11776 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 11777 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x2bca 11778 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 11779 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x2bcb 11780 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 11781 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x2bcc 11782 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 11783 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x2bcd 11784 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 11785 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x2bce 11786 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 11787 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x2bcf 11788 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 11789 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0x2bd0 11790 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 11791 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0x2bd1 11792 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 11793 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0x2bd2 11794 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 11795 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0x2bd3 11796 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 11797 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0x2bd4 11798 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 11799 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0x2bd5 11800 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 11801 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0x2bd6 11802 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 11803 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0x2bd7 11804 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 11805 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0x2bd8 11806 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 11807 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0x2bd9 11808 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 11809 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0x2bda 11810 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 11811 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0x2bdb 11812 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 11813 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0x2bdc 11814 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 11815 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0x2bdd 11816 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 11817 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0x2bde 11818 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 11819 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0x2bdf 11820 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 11821 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0x2be0 11822 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 11823 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0x2be1 11824 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 11825 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0x2be2 11826 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 11827 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0x2be3 11828 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 11829 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0x2be4 11830 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 11831 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0x2be5 11832 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 11833 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0x2be6 11834 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 11835 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0x2be7 11836 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 11837 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0x2be8 11838 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 11839 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0x2be9 11840 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 11841 11842 11843 // addressBlock: dcn_dcec_pwrseq0_dispdec_pwrseq_dispdec 11844 // base address: 0x0 11845 #define regDC_GPIO_PWRSEQ_EN 0x2f10 11846 #define regDC_GPIO_PWRSEQ_EN_BASE_IDX 2 11847 #define regDC_GPIO_PWRSEQ_CTRL 0x2f11 11848 #define regDC_GPIO_PWRSEQ_CTRL_BASE_IDX 2 11849 #define regDC_GPIO_PWRSEQ_MASK 0x2f12 11850 #define regDC_GPIO_PWRSEQ_MASK_BASE_IDX 2 11851 #define regDC_GPIO_PWRSEQ_A_Y 0x2f13 11852 #define regDC_GPIO_PWRSEQ_A_Y_BASE_IDX 2 11853 #define regPANEL_PWRSEQ_CNTL 0x2f14 11854 #define regPANEL_PWRSEQ_CNTL_BASE_IDX 2 11855 #define regPANEL_PWRSEQ_STATE 0x2f15 11856 #define regPANEL_PWRSEQ_STATE_BASE_IDX 2 11857 #define regPANEL_PWRSEQ_DELAY1 0x2f16 11858 #define regPANEL_PWRSEQ_DELAY1_BASE_IDX 2 11859 #define regPANEL_PWRSEQ_DELAY2 0x2f17 11860 #define regPANEL_PWRSEQ_DELAY2_BASE_IDX 2 11861 #define regPANEL_PWRSEQ_REF_DIV1 0x2f18 11862 #define regPANEL_PWRSEQ_REF_DIV1_BASE_IDX 2 11863 #define regBL_PWM_CNTL 0x2f19 11864 #define regBL_PWM_CNTL_BASE_IDX 2 11865 #define regBL_PWM_CNTL2 0x2f1a 11866 #define regBL_PWM_CNTL2_BASE_IDX 2 11867 #define regBL_PWM_PERIOD_CNTL 0x2f1b 11868 #define regBL_PWM_PERIOD_CNTL_BASE_IDX 2 11869 #define regBL_PWM_GRP1_REG_LOCK 0x2f1c 11870 #define regBL_PWM_GRP1_REG_LOCK_BASE_IDX 2 11871 #define regPANEL_PWRSEQ_REF_DIV2 0x2f1d 11872 #define regPANEL_PWRSEQ_REF_DIV2_BASE_IDX 2 11873 #define regPWRSEQ_DBG_SEL 0x2f20 11874 #define regPWRSEQ_DBG_SEL_BASE_IDX 2 11875 #define regPWRSEQ_SPARE 0x2f21 11876 #define regPWRSEQ_SPARE_BASE_IDX 2 11877 11878 11879 // addressBlock: dcn_dcec_dsc0_dispdec_dscc_dispdec 11880 // base address: 0x0 11881 #define regDSCC0_DSCC_CONFIG0 0x300a 11882 #define regDSCC0_DSCC_CONFIG0_BASE_IDX 2 11883 #define regDSCC0_DSCC_CONFIG1 0x300b 11884 #define regDSCC0_DSCC_CONFIG1_BASE_IDX 2 11885 #define regDSCC0_DSCC_CONFIG2 0x300c 11886 #define regDSCC0_DSCC_CONFIG2_BASE_IDX 2 11887 #define regDSCC0_DSCC_STATUS 0x300d 11888 #define regDSCC0_DSCC_STATUS_BASE_IDX 2 11889 #define regDSCC0_DSCC_INTERRUPT_CONTROL0 0x300e 11890 #define regDSCC0_DSCC_INTERRUPT_CONTROL0_BASE_IDX 2 11891 #define regDSCC0_DSCC_INTERRUPT_CONTROL1 0x300f 11892 #define regDSCC0_DSCC_INTERRUPT_CONTROL1_BASE_IDX 2 11893 #define regDSCC0_DSCC_INTERRUPT_STATUS0 0x3010 11894 #define regDSCC0_DSCC_INTERRUPT_STATUS0_BASE_IDX 2 11895 #define regDSCC0_DSCC_INTERRUPT_STATUS1 0x3011 11896 #define regDSCC0_DSCC_INTERRUPT_STATUS1_BASE_IDX 2 11897 #define regDSCC0_DSCC_PPS_CONFIG0 0x3012 11898 #define regDSCC0_DSCC_PPS_CONFIG0_BASE_IDX 2 11899 #define regDSCC0_DSCC_PPS_CONFIG1 0x3013 11900 #define regDSCC0_DSCC_PPS_CONFIG1_BASE_IDX 2 11901 #define regDSCC0_DSCC_PPS_CONFIG2 0x3014 11902 #define regDSCC0_DSCC_PPS_CONFIG2_BASE_IDX 2 11903 #define regDSCC0_DSCC_PPS_CONFIG3 0x3015 11904 #define regDSCC0_DSCC_PPS_CONFIG3_BASE_IDX 2 11905 #define regDSCC0_DSCC_PPS_CONFIG4 0x3016 11906 #define regDSCC0_DSCC_PPS_CONFIG4_BASE_IDX 2 11907 #define regDSCC0_DSCC_PPS_CONFIG5 0x3017 11908 #define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX 2 11909 #define regDSCC0_DSCC_PPS_CONFIG6 0x3018 11910 #define regDSCC0_DSCC_PPS_CONFIG6_BASE_IDX 2 11911 #define regDSCC0_DSCC_PPS_CONFIG7 0x3019 11912 #define regDSCC0_DSCC_PPS_CONFIG7_BASE_IDX 2 11913 #define regDSCC0_DSCC_PPS_CONFIG8 0x301a 11914 #define regDSCC0_DSCC_PPS_CONFIG8_BASE_IDX 2 11915 #define regDSCC0_DSCC_PPS_CONFIG9 0x301b 11916 #define regDSCC0_DSCC_PPS_CONFIG9_BASE_IDX 2 11917 #define regDSCC0_DSCC_PPS_CONFIG10 0x301c 11918 #define regDSCC0_DSCC_PPS_CONFIG10_BASE_IDX 2 11919 #define regDSCC0_DSCC_PPS_CONFIG11 0x301d 11920 #define regDSCC0_DSCC_PPS_CONFIG11_BASE_IDX 2 11921 #define regDSCC0_DSCC_PPS_CONFIG12 0x301e 11922 #define regDSCC0_DSCC_PPS_CONFIG12_BASE_IDX 2 11923 #define regDSCC0_DSCC_PPS_CONFIG13 0x301f 11924 #define regDSCC0_DSCC_PPS_CONFIG13_BASE_IDX 2 11925 #define regDSCC0_DSCC_PPS_CONFIG14 0x3020 11926 #define regDSCC0_DSCC_PPS_CONFIG14_BASE_IDX 2 11927 #define regDSCC0_DSCC_PPS_CONFIG15 0x3021 11928 #define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX 2 11929 #define regDSCC0_DSCC_PPS_CONFIG16 0x3022 11930 #define regDSCC0_DSCC_PPS_CONFIG16_BASE_IDX 2 11931 #define regDSCC0_DSCC_PPS_CONFIG17 0x3023 11932 #define regDSCC0_DSCC_PPS_CONFIG17_BASE_IDX 2 11933 #define regDSCC0_DSCC_PPS_CONFIG18 0x3024 11934 #define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX 2 11935 #define regDSCC0_DSCC_PPS_CONFIG19 0x3025 11936 #define regDSCC0_DSCC_PPS_CONFIG19_BASE_IDX 2 11937 #define regDSCC0_DSCC_PPS_CONFIG20 0x3026 11938 #define regDSCC0_DSCC_PPS_CONFIG20_BASE_IDX 2 11939 #define regDSCC0_DSCC_PPS_CONFIG21 0x3027 11940 #define regDSCC0_DSCC_PPS_CONFIG21_BASE_IDX 2 11941 #define regDSCC0_DSCC_PPS_CONFIG22 0x3028 11942 #define regDSCC0_DSCC_PPS_CONFIG22_BASE_IDX 2 11943 #define regDSCC0_DSCC_MEM_POWER_CONTROL0 0x3029 11944 #define regDSCC0_DSCC_MEM_POWER_CONTROL0_BASE_IDX 2 11945 #define regDSCC0_DSCC_MEM_POWER_CONTROL1 0x302a 11946 #define regDSCC0_DSCC_MEM_POWER_CONTROL1_BASE_IDX 2 11947 #define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER 0x302b 11948 #define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 11949 #define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER 0x302c 11950 #define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 11951 #define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER 0x302d 11952 #define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 11953 #define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER 0x302e 11954 #define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 11955 #define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER 0x302f 11956 #define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 11957 #define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER 0x3030 11958 #define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 11959 #define regDSCC0_DSCC_MAX_ABS_ERROR0 0x3031 11960 #define regDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 11961 #define regDSCC0_DSCC_MAX_ABS_ERROR1 0x3032 11962 #define regDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 11963 #define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0 0x3033 11964 #define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_BASE_IDX 2 11965 #define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1 0x3034 11966 #define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_BASE_IDX 2 11967 #define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2 0x3035 11968 #define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_BASE_IDX 2 11969 #define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3 0x3036 11970 #define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_BASE_IDX 2 11971 #define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0 0x3037 11972 #define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_BASE_IDX 2 11973 #define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1 0x3038 11974 #define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_BASE_IDX 2 11975 #define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2 0x3039 11976 #define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_BASE_IDX 2 11977 #define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3 0x303a 11978 #define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_BASE_IDX 2 11979 #define regDSCC0_DSCC_TEST_DEBUG_INDEX0 0x303b 11980 #define regDSCC0_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2 11981 #define regDSCC0_DSCC_TEST_DEBUG_INDEX1 0x303c 11982 #define regDSCC0_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2 11983 #define regDSCC0_DSCC_TEST_DEBUG_INDEX2 0x303d 11984 #define regDSCC0_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2 11985 #define regDSCC0_DSCC_TEST_DEBUG_INDEX3 0x303e 11986 #define regDSCC0_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2 11987 #define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE 0x303f 11988 #define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 11989 #define regDSCC0_DSCC_TEST_DEBUG_DATA0 0x3040 11990 #define regDSCC0_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2 11991 #define regDSCC0_DSCC_TEST_DEBUG_DATA1 0x3041 11992 #define regDSCC0_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2 11993 #define regDSCC0_DSCC_TEST_DEBUG_DATA2 0x3042 11994 #define regDSCC0_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2 11995 #define regDSCC0_DSCC_TEST_DEBUG_DATA3 0x3043 11996 #define regDSCC0_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2 11997 #define regDSCC0_DSCC_DISPCLK_TEST_DEBUG_INDEX0 0x3044 11998 #define regDSCC0_DSCC_DISPCLK_TEST_DEBUG_INDEX0_BASE_IDX 2 11999 #define regDSCC0_DSCC_DISPCLK_TEST_DEBUG_DATA0 0x3045 12000 #define regDSCC0_DSCC_DISPCLK_TEST_DEBUG_DATA0_BASE_IDX 2 12001 12002 12003 // addressBlock: dcn_dcec_dsc0_dispdec_dsccif_dispdec 12004 // base address: 0x0 12005 #define regDSCCIF0_DSCCIF_CONFIG0 0x3005 12006 #define regDSCCIF0_DSCCIF_CONFIG0_BASE_IDX 2 12007 12008 12009 // addressBlock: dcn_dcec_dsc0_dispdec_dsc_top_dispdec 12010 // base address: 0x0 12011 #define regDSC_TOP0_DSC_TOP_CONTROL 0x3000 12012 #define regDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX 2 12013 #define regDSC_TOP0_DSC_DEBUG_CONTROL 0x3001 12014 #define regDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX 2 12015 #define regDSC_TOP0_DSC_SPARE_DEBUG 0x3002 12016 #define regDSC_TOP0_DSC_SPARE_DEBUG_BASE_IDX 2 12017 #define regDSC_TOP0_DSC_TOP_TEST_DEBUG_INDEX 0x3003 12018 #define regDSC_TOP0_DSC_TOP_TEST_DEBUG_INDEX_BASE_IDX 2 12019 #define regDSC_TOP0_DSC_TOP_TEST_DEBUG_DATA 0x3004 12020 #define regDSC_TOP0_DSC_TOP_TEST_DEBUG_DATA_BASE_IDX 2 12021 12022 12023 // addressBlock: dcn_dcec_dsc1_dispdec_dscc_dispdec 12024 // base address: 0x170 12025 #define regDSCC1_DSCC_CONFIG0 0x3066 12026 #define regDSCC1_DSCC_CONFIG0_BASE_IDX 2 12027 #define regDSCC1_DSCC_CONFIG1 0x3067 12028 #define regDSCC1_DSCC_CONFIG1_BASE_IDX 2 12029 #define regDSCC1_DSCC_CONFIG2 0x3068 12030 #define regDSCC1_DSCC_CONFIG2_BASE_IDX 2 12031 #define regDSCC1_DSCC_STATUS 0x3069 12032 #define regDSCC1_DSCC_STATUS_BASE_IDX 2 12033 #define regDSCC1_DSCC_INTERRUPT_CONTROL0 0x306a 12034 #define regDSCC1_DSCC_INTERRUPT_CONTROL0_BASE_IDX 2 12035 #define regDSCC1_DSCC_INTERRUPT_CONTROL1 0x306b 12036 #define regDSCC1_DSCC_INTERRUPT_CONTROL1_BASE_IDX 2 12037 #define regDSCC1_DSCC_INTERRUPT_STATUS0 0x306c 12038 #define regDSCC1_DSCC_INTERRUPT_STATUS0_BASE_IDX 2 12039 #define regDSCC1_DSCC_INTERRUPT_STATUS1 0x306d 12040 #define regDSCC1_DSCC_INTERRUPT_STATUS1_BASE_IDX 2 12041 #define regDSCC1_DSCC_PPS_CONFIG0 0x306e 12042 #define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX 2 12043 #define regDSCC1_DSCC_PPS_CONFIG1 0x306f 12044 #define regDSCC1_DSCC_PPS_CONFIG1_BASE_IDX 2 12045 #define regDSCC1_DSCC_PPS_CONFIG2 0x3070 12046 #define regDSCC1_DSCC_PPS_CONFIG2_BASE_IDX 2 12047 #define regDSCC1_DSCC_PPS_CONFIG3 0x3071 12048 #define regDSCC1_DSCC_PPS_CONFIG3_BASE_IDX 2 12049 #define regDSCC1_DSCC_PPS_CONFIG4 0x3072 12050 #define regDSCC1_DSCC_PPS_CONFIG4_BASE_IDX 2 12051 #define regDSCC1_DSCC_PPS_CONFIG5 0x3073 12052 #define regDSCC1_DSCC_PPS_CONFIG5_BASE_IDX 2 12053 #define regDSCC1_DSCC_PPS_CONFIG6 0x3074 12054 #define regDSCC1_DSCC_PPS_CONFIG6_BASE_IDX 2 12055 #define regDSCC1_DSCC_PPS_CONFIG7 0x3075 12056 #define regDSCC1_DSCC_PPS_CONFIG7_BASE_IDX 2 12057 #define regDSCC1_DSCC_PPS_CONFIG8 0x3076 12058 #define regDSCC1_DSCC_PPS_CONFIG8_BASE_IDX 2 12059 #define regDSCC1_DSCC_PPS_CONFIG9 0x3077 12060 #define regDSCC1_DSCC_PPS_CONFIG9_BASE_IDX 2 12061 #define regDSCC1_DSCC_PPS_CONFIG10 0x3078 12062 #define regDSCC1_DSCC_PPS_CONFIG10_BASE_IDX 2 12063 #define regDSCC1_DSCC_PPS_CONFIG11 0x3079 12064 #define regDSCC1_DSCC_PPS_CONFIG11_BASE_IDX 2 12065 #define regDSCC1_DSCC_PPS_CONFIG12 0x307a 12066 #define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX 2 12067 #define regDSCC1_DSCC_PPS_CONFIG13 0x307b 12068 #define regDSCC1_DSCC_PPS_CONFIG13_BASE_IDX 2 12069 #define regDSCC1_DSCC_PPS_CONFIG14 0x307c 12070 #define regDSCC1_DSCC_PPS_CONFIG14_BASE_IDX 2 12071 #define regDSCC1_DSCC_PPS_CONFIG15 0x307d 12072 #define regDSCC1_DSCC_PPS_CONFIG15_BASE_IDX 2 12073 #define regDSCC1_DSCC_PPS_CONFIG16 0x307e 12074 #define regDSCC1_DSCC_PPS_CONFIG16_BASE_IDX 2 12075 #define regDSCC1_DSCC_PPS_CONFIG17 0x307f 12076 #define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX 2 12077 #define regDSCC1_DSCC_PPS_CONFIG18 0x3080 12078 #define regDSCC1_DSCC_PPS_CONFIG18_BASE_IDX 2 12079 #define regDSCC1_DSCC_PPS_CONFIG19 0x3081 12080 #define regDSCC1_DSCC_PPS_CONFIG19_BASE_IDX 2 12081 #define regDSCC1_DSCC_PPS_CONFIG20 0x3082 12082 #define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX 2 12083 #define regDSCC1_DSCC_PPS_CONFIG21 0x3083 12084 #define regDSCC1_DSCC_PPS_CONFIG21_BASE_IDX 2 12085 #define regDSCC1_DSCC_PPS_CONFIG22 0x3084 12086 #define regDSCC1_DSCC_PPS_CONFIG22_BASE_IDX 2 12087 #define regDSCC1_DSCC_MEM_POWER_CONTROL0 0x3085 12088 #define regDSCC1_DSCC_MEM_POWER_CONTROL0_BASE_IDX 2 12089 #define regDSCC1_DSCC_MEM_POWER_CONTROL1 0x3086 12090 #define regDSCC1_DSCC_MEM_POWER_CONTROL1_BASE_IDX 2 12091 #define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3087 12092 #define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 12093 #define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3088 12094 #define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 12095 #define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3089 12096 #define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 12097 #define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER 0x308a 12098 #define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 12099 #define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER 0x308b 12100 #define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 12101 #define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER 0x308c 12102 #define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 12103 #define regDSCC1_DSCC_MAX_ABS_ERROR0 0x308d 12104 #define regDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 12105 #define regDSCC1_DSCC_MAX_ABS_ERROR1 0x308e 12106 #define regDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 12107 #define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0 0x308f 12108 #define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_BASE_IDX 2 12109 #define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1 0x3090 12110 #define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_BASE_IDX 2 12111 #define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2 0x3091 12112 #define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_BASE_IDX 2 12113 #define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3 0x3092 12114 #define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_BASE_IDX 2 12115 #define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0 0x3093 12116 #define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_BASE_IDX 2 12117 #define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1 0x3094 12118 #define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_BASE_IDX 2 12119 #define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2 0x3095 12120 #define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_BASE_IDX 2 12121 #define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3 0x3096 12122 #define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_BASE_IDX 2 12123 #define regDSCC1_DSCC_TEST_DEBUG_INDEX0 0x3097 12124 #define regDSCC1_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2 12125 #define regDSCC1_DSCC_TEST_DEBUG_INDEX1 0x3098 12126 #define regDSCC1_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2 12127 #define regDSCC1_DSCC_TEST_DEBUG_INDEX2 0x3099 12128 #define regDSCC1_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2 12129 #define regDSCC1_DSCC_TEST_DEBUG_INDEX3 0x309a 12130 #define regDSCC1_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2 12131 #define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE 0x309b 12132 #define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 12133 #define regDSCC1_DSCC_TEST_DEBUG_DATA0 0x309c 12134 #define regDSCC1_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2 12135 #define regDSCC1_DSCC_TEST_DEBUG_DATA1 0x309d 12136 #define regDSCC1_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2 12137 #define regDSCC1_DSCC_TEST_DEBUG_DATA2 0x309e 12138 #define regDSCC1_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2 12139 #define regDSCC1_DSCC_TEST_DEBUG_DATA3 0x309f 12140 #define regDSCC1_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2 12141 #define regDSCC1_DSCC_DISPCLK_TEST_DEBUG_INDEX0 0x30a0 12142 #define regDSCC1_DSCC_DISPCLK_TEST_DEBUG_INDEX0_BASE_IDX 2 12143 #define regDSCC1_DSCC_DISPCLK_TEST_DEBUG_DATA0 0x30a1 12144 #define regDSCC1_DSCC_DISPCLK_TEST_DEBUG_DATA0_BASE_IDX 2 12145 12146 12147 // addressBlock: dcn_dcec_dsc1_dispdec_dsccif_dispdec 12148 // base address: 0x170 12149 #define regDSCCIF1_DSCCIF_CONFIG0 0x3061 12150 #define regDSCCIF1_DSCCIF_CONFIG0_BASE_IDX 2 12151 12152 12153 // addressBlock: dcn_dcec_dsc1_dispdec_dsc_top_dispdec 12154 // base address: 0x170 12155 #define regDSC_TOP1_DSC_TOP_CONTROL 0x305c 12156 #define regDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX 2 12157 #define regDSC_TOP1_DSC_DEBUG_CONTROL 0x305d 12158 #define regDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX 2 12159 #define regDSC_TOP1_DSC_SPARE_DEBUG 0x305e 12160 #define regDSC_TOP1_DSC_SPARE_DEBUG_BASE_IDX 2 12161 #define regDSC_TOP1_DSC_TOP_TEST_DEBUG_INDEX 0x305f 12162 #define regDSC_TOP1_DSC_TOP_TEST_DEBUG_INDEX_BASE_IDX 2 12163 #define regDSC_TOP1_DSC_TOP_TEST_DEBUG_DATA 0x3060 12164 #define regDSC_TOP1_DSC_TOP_TEST_DEBUG_DATA_BASE_IDX 2 12165 12166 12167 // addressBlock: dcn_dcec_dsc2_dispdec_dscc_dispdec 12168 // base address: 0x2e0 12169 #define regDSCC2_DSCC_CONFIG0 0x30c2 12170 #define regDSCC2_DSCC_CONFIG0_BASE_IDX 2 12171 #define regDSCC2_DSCC_CONFIG1 0x30c3 12172 #define regDSCC2_DSCC_CONFIG1_BASE_IDX 2 12173 #define regDSCC2_DSCC_CONFIG2 0x30c4 12174 #define regDSCC2_DSCC_CONFIG2_BASE_IDX 2 12175 #define regDSCC2_DSCC_STATUS 0x30c5 12176 #define regDSCC2_DSCC_STATUS_BASE_IDX 2 12177 #define regDSCC2_DSCC_INTERRUPT_CONTROL0 0x30c6 12178 #define regDSCC2_DSCC_INTERRUPT_CONTROL0_BASE_IDX 2 12179 #define regDSCC2_DSCC_INTERRUPT_CONTROL1 0x30c7 12180 #define regDSCC2_DSCC_INTERRUPT_CONTROL1_BASE_IDX 2 12181 #define regDSCC2_DSCC_INTERRUPT_STATUS0 0x30c8 12182 #define regDSCC2_DSCC_INTERRUPT_STATUS0_BASE_IDX 2 12183 #define regDSCC2_DSCC_INTERRUPT_STATUS1 0x30c9 12184 #define regDSCC2_DSCC_INTERRUPT_STATUS1_BASE_IDX 2 12185 #define regDSCC2_DSCC_PPS_CONFIG0 0x30ca 12186 #define regDSCC2_DSCC_PPS_CONFIG0_BASE_IDX 2 12187 #define regDSCC2_DSCC_PPS_CONFIG1 0x30cb 12188 #define regDSCC2_DSCC_PPS_CONFIG1_BASE_IDX 2 12189 #define regDSCC2_DSCC_PPS_CONFIG2 0x30cc 12190 #define regDSCC2_DSCC_PPS_CONFIG2_BASE_IDX 2 12191 #define regDSCC2_DSCC_PPS_CONFIG3 0x30cd 12192 #define regDSCC2_DSCC_PPS_CONFIG3_BASE_IDX 2 12193 #define regDSCC2_DSCC_PPS_CONFIG4 0x30ce 12194 #define regDSCC2_DSCC_PPS_CONFIG4_BASE_IDX 2 12195 #define regDSCC2_DSCC_PPS_CONFIG5 0x30cf 12196 #define regDSCC2_DSCC_PPS_CONFIG5_BASE_IDX 2 12197 #define regDSCC2_DSCC_PPS_CONFIG6 0x30d0 12198 #define regDSCC2_DSCC_PPS_CONFIG6_BASE_IDX 2 12199 #define regDSCC2_DSCC_PPS_CONFIG7 0x30d1 12200 #define regDSCC2_DSCC_PPS_CONFIG7_BASE_IDX 2 12201 #define regDSCC2_DSCC_PPS_CONFIG8 0x30d2 12202 #define regDSCC2_DSCC_PPS_CONFIG8_BASE_IDX 2 12203 #define regDSCC2_DSCC_PPS_CONFIG9 0x30d3 12204 #define regDSCC2_DSCC_PPS_CONFIG9_BASE_IDX 2 12205 #define regDSCC2_DSCC_PPS_CONFIG10 0x30d4 12206 #define regDSCC2_DSCC_PPS_CONFIG10_BASE_IDX 2 12207 #define regDSCC2_DSCC_PPS_CONFIG11 0x30d5 12208 #define regDSCC2_DSCC_PPS_CONFIG11_BASE_IDX 2 12209 #define regDSCC2_DSCC_PPS_CONFIG12 0x30d6 12210 #define regDSCC2_DSCC_PPS_CONFIG12_BASE_IDX 2 12211 #define regDSCC2_DSCC_PPS_CONFIG13 0x30d7 12212 #define regDSCC2_DSCC_PPS_CONFIG13_BASE_IDX 2 12213 #define regDSCC2_DSCC_PPS_CONFIG14 0x30d8 12214 #define regDSCC2_DSCC_PPS_CONFIG14_BASE_IDX 2 12215 #define regDSCC2_DSCC_PPS_CONFIG15 0x30d9 12216 #define regDSCC2_DSCC_PPS_CONFIG15_BASE_IDX 2 12217 #define regDSCC2_DSCC_PPS_CONFIG16 0x30da 12218 #define regDSCC2_DSCC_PPS_CONFIG16_BASE_IDX 2 12219 #define regDSCC2_DSCC_PPS_CONFIG17 0x30db 12220 #define regDSCC2_DSCC_PPS_CONFIG17_BASE_IDX 2 12221 #define regDSCC2_DSCC_PPS_CONFIG18 0x30dc 12222 #define regDSCC2_DSCC_PPS_CONFIG18_BASE_IDX 2 12223 #define regDSCC2_DSCC_PPS_CONFIG19 0x30dd 12224 #define regDSCC2_DSCC_PPS_CONFIG19_BASE_IDX 2 12225 #define regDSCC2_DSCC_PPS_CONFIG20 0x30de 12226 #define regDSCC2_DSCC_PPS_CONFIG20_BASE_IDX 2 12227 #define regDSCC2_DSCC_PPS_CONFIG21 0x30df 12228 #define regDSCC2_DSCC_PPS_CONFIG21_BASE_IDX 2 12229 #define regDSCC2_DSCC_PPS_CONFIG22 0x30e0 12230 #define regDSCC2_DSCC_PPS_CONFIG22_BASE_IDX 2 12231 #define regDSCC2_DSCC_MEM_POWER_CONTROL0 0x30e1 12232 #define regDSCC2_DSCC_MEM_POWER_CONTROL0_BASE_IDX 2 12233 #define regDSCC2_DSCC_MEM_POWER_CONTROL1 0x30e2 12234 #define regDSCC2_DSCC_MEM_POWER_CONTROL1_BASE_IDX 2 12235 #define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER 0x30e3 12236 #define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 12237 #define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER 0x30e4 12238 #define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 12239 #define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER 0x30e5 12240 #define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 12241 #define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER 0x30e6 12242 #define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 12243 #define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER 0x30e7 12244 #define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 12245 #define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER 0x30e8 12246 #define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 12247 #define regDSCC2_DSCC_MAX_ABS_ERROR0 0x30e9 12248 #define regDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 12249 #define regDSCC2_DSCC_MAX_ABS_ERROR1 0x30ea 12250 #define regDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 12251 #define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0 0x30eb 12252 #define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_BASE_IDX 2 12253 #define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1 0x30ec 12254 #define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_BASE_IDX 2 12255 #define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2 0x30ed 12256 #define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_BASE_IDX 2 12257 #define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3 0x30ee 12258 #define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_BASE_IDX 2 12259 #define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0 0x30ef 12260 #define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_BASE_IDX 2 12261 #define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1 0x30f0 12262 #define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_BASE_IDX 2 12263 #define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2 0x30f1 12264 #define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_BASE_IDX 2 12265 #define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3 0x30f2 12266 #define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_BASE_IDX 2 12267 #define regDSCC2_DSCC_TEST_DEBUG_INDEX0 0x30f3 12268 #define regDSCC2_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2 12269 #define regDSCC2_DSCC_TEST_DEBUG_INDEX1 0x30f4 12270 #define regDSCC2_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2 12271 #define regDSCC2_DSCC_TEST_DEBUG_INDEX2 0x30f5 12272 #define regDSCC2_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2 12273 #define regDSCC2_DSCC_TEST_DEBUG_INDEX3 0x30f6 12274 #define regDSCC2_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2 12275 #define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE 0x30f7 12276 #define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 12277 #define regDSCC2_DSCC_TEST_DEBUG_DATA0 0x30f8 12278 #define regDSCC2_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2 12279 #define regDSCC2_DSCC_TEST_DEBUG_DATA1 0x30f9 12280 #define regDSCC2_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2 12281 #define regDSCC2_DSCC_TEST_DEBUG_DATA2 0x30fa 12282 #define regDSCC2_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2 12283 #define regDSCC2_DSCC_TEST_DEBUG_DATA3 0x30fb 12284 #define regDSCC2_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2 12285 #define regDSCC2_DSCC_DISPCLK_TEST_DEBUG_INDEX0 0x30fc 12286 #define regDSCC2_DSCC_DISPCLK_TEST_DEBUG_INDEX0_BASE_IDX 2 12287 #define regDSCC2_DSCC_DISPCLK_TEST_DEBUG_DATA0 0x30fd 12288 #define regDSCC2_DSCC_DISPCLK_TEST_DEBUG_DATA0_BASE_IDX 2 12289 12290 12291 // addressBlock: dcn_dcec_dsc2_dispdec_dsccif_dispdec 12292 // base address: 0x2e0 12293 #define regDSCCIF2_DSCCIF_CONFIG0 0x30bd 12294 #define regDSCCIF2_DSCCIF_CONFIG0_BASE_IDX 2 12295 12296 12297 // addressBlock: dcn_dcec_dsc2_dispdec_dsc_top_dispdec 12298 // base address: 0x2e0 12299 #define regDSC_TOP2_DSC_TOP_CONTROL 0x30b8 12300 #define regDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX 2 12301 #define regDSC_TOP2_DSC_DEBUG_CONTROL 0x30b9 12302 #define regDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX 2 12303 #define regDSC_TOP2_DSC_SPARE_DEBUG 0x30ba 12304 #define regDSC_TOP2_DSC_SPARE_DEBUG_BASE_IDX 2 12305 #define regDSC_TOP2_DSC_TOP_TEST_DEBUG_INDEX 0x30bb 12306 #define regDSC_TOP2_DSC_TOP_TEST_DEBUG_INDEX_BASE_IDX 2 12307 #define regDSC_TOP2_DSC_TOP_TEST_DEBUG_DATA 0x30bc 12308 #define regDSC_TOP2_DSC_TOP_TEST_DEBUG_DATA_BASE_IDX 2 12309 12310 12311 // addressBlock: dcn_dcec_dsc3_dispdec_dscc_dispdec 12312 // base address: 0x450 12313 #define regDSCC3_DSCC_CONFIG0 0x311e 12314 #define regDSCC3_DSCC_CONFIG0_BASE_IDX 2 12315 #define regDSCC3_DSCC_CONFIG1 0x311f 12316 #define regDSCC3_DSCC_CONFIG1_BASE_IDX 2 12317 #define regDSCC3_DSCC_CONFIG2 0x3120 12318 #define regDSCC3_DSCC_CONFIG2_BASE_IDX 2 12319 #define regDSCC3_DSCC_STATUS 0x3121 12320 #define regDSCC3_DSCC_STATUS_BASE_IDX 2 12321 #define regDSCC3_DSCC_INTERRUPT_CONTROL0 0x3122 12322 #define regDSCC3_DSCC_INTERRUPT_CONTROL0_BASE_IDX 2 12323 #define regDSCC3_DSCC_INTERRUPT_CONTROL1 0x3123 12324 #define regDSCC3_DSCC_INTERRUPT_CONTROL1_BASE_IDX 2 12325 #define regDSCC3_DSCC_INTERRUPT_STATUS0 0x3124 12326 #define regDSCC3_DSCC_INTERRUPT_STATUS0_BASE_IDX 2 12327 #define regDSCC3_DSCC_INTERRUPT_STATUS1 0x3125 12328 #define regDSCC3_DSCC_INTERRUPT_STATUS1_BASE_IDX 2 12329 #define regDSCC3_DSCC_PPS_CONFIG0 0x3126 12330 #define regDSCC3_DSCC_PPS_CONFIG0_BASE_IDX 2 12331 #define regDSCC3_DSCC_PPS_CONFIG1 0x3127 12332 #define regDSCC3_DSCC_PPS_CONFIG1_BASE_IDX 2 12333 #define regDSCC3_DSCC_PPS_CONFIG2 0x3128 12334 #define regDSCC3_DSCC_PPS_CONFIG2_BASE_IDX 2 12335 #define regDSCC3_DSCC_PPS_CONFIG3 0x3129 12336 #define regDSCC3_DSCC_PPS_CONFIG3_BASE_IDX 2 12337 #define regDSCC3_DSCC_PPS_CONFIG4 0x312a 12338 #define regDSCC3_DSCC_PPS_CONFIG4_BASE_IDX 2 12339 #define regDSCC3_DSCC_PPS_CONFIG5 0x312b 12340 #define regDSCC3_DSCC_PPS_CONFIG5_BASE_IDX 2 12341 #define regDSCC3_DSCC_PPS_CONFIG6 0x312c 12342 #define regDSCC3_DSCC_PPS_CONFIG6_BASE_IDX 2 12343 #define regDSCC3_DSCC_PPS_CONFIG7 0x312d 12344 #define regDSCC3_DSCC_PPS_CONFIG7_BASE_IDX 2 12345 #define regDSCC3_DSCC_PPS_CONFIG8 0x312e 12346 #define regDSCC3_DSCC_PPS_CONFIG8_BASE_IDX 2 12347 #define regDSCC3_DSCC_PPS_CONFIG9 0x312f 12348 #define regDSCC3_DSCC_PPS_CONFIG9_BASE_IDX 2 12349 #define regDSCC3_DSCC_PPS_CONFIG10 0x3130 12350 #define regDSCC3_DSCC_PPS_CONFIG10_BASE_IDX 2 12351 #define regDSCC3_DSCC_PPS_CONFIG11 0x3131 12352 #define regDSCC3_DSCC_PPS_CONFIG11_BASE_IDX 2 12353 #define regDSCC3_DSCC_PPS_CONFIG12 0x3132 12354 #define regDSCC3_DSCC_PPS_CONFIG12_BASE_IDX 2 12355 #define regDSCC3_DSCC_PPS_CONFIG13 0x3133 12356 #define regDSCC3_DSCC_PPS_CONFIG13_BASE_IDX 2 12357 #define regDSCC3_DSCC_PPS_CONFIG14 0x3134 12358 #define regDSCC3_DSCC_PPS_CONFIG14_BASE_IDX 2 12359 #define regDSCC3_DSCC_PPS_CONFIG15 0x3135 12360 #define regDSCC3_DSCC_PPS_CONFIG15_BASE_IDX 2 12361 #define regDSCC3_DSCC_PPS_CONFIG16 0x3136 12362 #define regDSCC3_DSCC_PPS_CONFIG16_BASE_IDX 2 12363 #define regDSCC3_DSCC_PPS_CONFIG17 0x3137 12364 #define regDSCC3_DSCC_PPS_CONFIG17_BASE_IDX 2 12365 #define regDSCC3_DSCC_PPS_CONFIG18 0x3138 12366 #define regDSCC3_DSCC_PPS_CONFIG18_BASE_IDX 2 12367 #define regDSCC3_DSCC_PPS_CONFIG19 0x3139 12368 #define regDSCC3_DSCC_PPS_CONFIG19_BASE_IDX 2 12369 #define regDSCC3_DSCC_PPS_CONFIG20 0x313a 12370 #define regDSCC3_DSCC_PPS_CONFIG20_BASE_IDX 2 12371 #define regDSCC3_DSCC_PPS_CONFIG21 0x313b 12372 #define regDSCC3_DSCC_PPS_CONFIG21_BASE_IDX 2 12373 #define regDSCC3_DSCC_PPS_CONFIG22 0x313c 12374 #define regDSCC3_DSCC_PPS_CONFIG22_BASE_IDX 2 12375 #define regDSCC3_DSCC_MEM_POWER_CONTROL0 0x313d 12376 #define regDSCC3_DSCC_MEM_POWER_CONTROL0_BASE_IDX 2 12377 #define regDSCC3_DSCC_MEM_POWER_CONTROL1 0x313e 12378 #define regDSCC3_DSCC_MEM_POWER_CONTROL1_BASE_IDX 2 12379 #define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER 0x313f 12380 #define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 12381 #define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3140 12382 #define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 12383 #define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3141 12384 #define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 12385 #define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3142 12386 #define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 12387 #define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER 0x3143 12388 #define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 12389 #define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER 0x3144 12390 #define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 12391 #define regDSCC3_DSCC_MAX_ABS_ERROR0 0x3145 12392 #define regDSCC3_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 12393 #define regDSCC3_DSCC_MAX_ABS_ERROR1 0x3146 12394 #define regDSCC3_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 12395 #define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0 0x3147 12396 #define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_BASE_IDX 2 12397 #define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1 0x3148 12398 #define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_BASE_IDX 2 12399 #define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2 0x3149 12400 #define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_BASE_IDX 2 12401 #define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3 0x314a 12402 #define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_BASE_IDX 2 12403 #define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0 0x314b 12404 #define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_BASE_IDX 2 12405 #define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1 0x314c 12406 #define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_BASE_IDX 2 12407 #define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2 0x314d 12408 #define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_BASE_IDX 2 12409 #define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3 0x314e 12410 #define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_BASE_IDX 2 12411 #define regDSCC3_DSCC_TEST_DEBUG_INDEX0 0x314f 12412 #define regDSCC3_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2 12413 #define regDSCC3_DSCC_TEST_DEBUG_INDEX1 0x3150 12414 #define regDSCC3_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2 12415 #define regDSCC3_DSCC_TEST_DEBUG_INDEX2 0x3151 12416 #define regDSCC3_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2 12417 #define regDSCC3_DSCC_TEST_DEBUG_INDEX3 0x3152 12418 #define regDSCC3_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2 12419 #define regDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE 0x3153 12420 #define regDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 12421 #define regDSCC3_DSCC_TEST_DEBUG_DATA0 0x3154 12422 #define regDSCC3_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2 12423 #define regDSCC3_DSCC_TEST_DEBUG_DATA1 0x3155 12424 #define regDSCC3_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2 12425 #define regDSCC3_DSCC_TEST_DEBUG_DATA2 0x3156 12426 #define regDSCC3_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2 12427 #define regDSCC3_DSCC_TEST_DEBUG_DATA3 0x3157 12428 #define regDSCC3_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2 12429 #define regDSCC3_DSCC_DISPCLK_TEST_DEBUG_INDEX0 0x3158 12430 #define regDSCC3_DSCC_DISPCLK_TEST_DEBUG_INDEX0_BASE_IDX 2 12431 #define regDSCC3_DSCC_DISPCLK_TEST_DEBUG_DATA0 0x3159 12432 #define regDSCC3_DSCC_DISPCLK_TEST_DEBUG_DATA0_BASE_IDX 2 12433 12434 12435 // addressBlock: dcn_dcec_dsc3_dispdec_dsccif_dispdec 12436 // base address: 0x450 12437 #define regDSCCIF3_DSCCIF_CONFIG0 0x3119 12438 #define regDSCCIF3_DSCCIF_CONFIG0_BASE_IDX 2 12439 12440 12441 // addressBlock: dcn_dcec_dsc3_dispdec_dsc_top_dispdec 12442 // base address: 0x450 12443 #define regDSC_TOP3_DSC_TOP_CONTROL 0x3114 12444 #define regDSC_TOP3_DSC_TOP_CONTROL_BASE_IDX 2 12445 #define regDSC_TOP3_DSC_DEBUG_CONTROL 0x3115 12446 #define regDSC_TOP3_DSC_DEBUG_CONTROL_BASE_IDX 2 12447 #define regDSC_TOP3_DSC_SPARE_DEBUG 0x3116 12448 #define regDSC_TOP3_DSC_SPARE_DEBUG_BASE_IDX 2 12449 #define regDSC_TOP3_DSC_TOP_TEST_DEBUG_INDEX 0x3117 12450 #define regDSC_TOP3_DSC_TOP_TEST_DEBUG_INDEX_BASE_IDX 2 12451 #define regDSC_TOP3_DSC_TOP_TEST_DEBUG_DATA 0x3118 12452 #define regDSC_TOP3_DSC_TOP_TEST_DEBUG_DATA_BASE_IDX 2 12453 12454 12455 // addressBlock: dcn_dcec_dcoh_dcoh_top_dispdec 12456 // base address: 0x0 12457 #define regDCOH_TOP_CLOCK_CONTROL 0x17af 12458 #define regDCOH_TOP_CLOCK_CONTROL_BASE_IDX 2 12459 #define regDCOH_TOP_SPARE 0x17b3 12460 #define regDCOH_TOP_SPARE_BASE_IDX 2 12461 12462 12463 // addressBlock: dcn_dcec_dcoh_phy_mux0_dispdec 12464 // base address: 0x13168 12465 #define regPHY_MUX0_PHY_MUX_CONTROL 0x179a 12466 #define regPHY_MUX0_PHY_MUX_CONTROL_BASE_IDX 2 12467 #define regPHY_MUX0_PORT_TYPE 0x179b 12468 #define regPHY_MUX0_PORT_TYPE_BASE_IDX 2 12469 12470 12471 // addressBlock: dcn_dcec_dcoh_phy_mux1_dispdec 12472 // base address: 0x13174 12473 #define regPHY_MUX1_PHY_MUX_CONTROL 0x179d 12474 #define regPHY_MUX1_PHY_MUX_CONTROL_BASE_IDX 2 12475 #define regPHY_MUX1_PORT_TYPE 0x179e 12476 #define regPHY_MUX1_PORT_TYPE_BASE_IDX 2 12477 12478 12479 // addressBlock: dcn_dcec_dcoh_phy_mux2_dispdec 12480 // base address: 0x13180 12481 #define regPHY_MUX2_PHY_MUX_CONTROL 0x17a0 12482 #define regPHY_MUX2_PHY_MUX_CONTROL_BASE_IDX 2 12483 #define regPHY_MUX2_PORT_TYPE 0x17a1 12484 #define regPHY_MUX2_PORT_TYPE_BASE_IDX 2 12485 12486 12487 // addressBlock: dcn_dcec_dcoh_phy_mux3_dispdec 12488 // base address: 0x1318c 12489 #define regPHY_MUX3_PHY_MUX_CONTROL 0x17a3 12490 #define regPHY_MUX3_PHY_MUX_CONTROL_BASE_IDX 2 12491 #define regPHY_MUX3_PORT_TYPE 0x17a4 12492 #define regPHY_MUX3_PORT_TYPE_BASE_IDX 2 12493 12494 12495 // addressBlock: dcn_dcec_dcoh_dp_aux0_dispdec 12496 // base address: 0x0 12497 #define regDP_AUX0_AUX_CONTROL 0x16b2 12498 #define regDP_AUX0_AUX_CONTROL_BASE_IDX 2 12499 #define regDP_AUX0_AUX_SW_CONTROL 0x16b3 12500 #define regDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2 12501 #define regDP_AUX0_AUX_ARB_CONTROL 0x16b4 12502 #define regDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2 12503 #define regDP_AUX0_AUX_INTERRUPT_CONTROL 0x16b5 12504 #define regDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2 12505 #define regDP_AUX0_AUX_SW_STATUS 0x16b6 12506 #define regDP_AUX0_AUX_SW_STATUS_BASE_IDX 2 12507 #define regDP_AUX0_AUX_LS_STATUS 0x16b7 12508 #define regDP_AUX0_AUX_LS_STATUS_BASE_IDX 2 12509 #define regDP_AUX0_AUX_SW_DATA 0x16b8 12510 #define regDP_AUX0_AUX_SW_DATA_BASE_IDX 2 12511 #define regDP_AUX0_AUX_LS_DATA 0x16b9 12512 #define regDP_AUX0_AUX_LS_DATA_BASE_IDX 2 12513 #define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x16ba 12514 #define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 12515 #define regDP_AUX0_AUX_DPHY_TX_CONTROL 0x16bb 12516 #define regDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2 12517 #define regDP_AUX0_AUX_DPHY_RX_CONTROL0 0x16bc 12518 #define regDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 12519 #define regDP_AUX0_AUX_DPHY_RX_CONTROL1 0x16bd 12520 #define regDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 12521 #define regDP_AUX0_AUX_DPHY_TX_STATUS 0x16be 12522 #define regDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2 12523 #define regDP_AUX0_AUX_DPHY_RX_STATUS 0x16bf 12524 #define regDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2 12525 #define regDP_AUX0_AUX_PHY_WAKE_CNTL 0x16c1 12526 #define regDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX 2 12527 #define regDP_AUX0_AUX_PHY_WAKE_STATUS 0x16c2 12528 #define regDP_AUX0_AUX_PHY_WAKE_STATUS_BASE_IDX 2 12529 12530 12531 // addressBlock: dcn_dcec_dcoh_dp_aux1_dispdec 12532 // base address: 0x70 12533 #define regDP_AUX1_AUX_CONTROL 0x16ce 12534 #define regDP_AUX1_AUX_CONTROL_BASE_IDX 2 12535 #define regDP_AUX1_AUX_SW_CONTROL 0x16cf 12536 #define regDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2 12537 #define regDP_AUX1_AUX_ARB_CONTROL 0x16d0 12538 #define regDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2 12539 #define regDP_AUX1_AUX_INTERRUPT_CONTROL 0x16d1 12540 #define regDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2 12541 #define regDP_AUX1_AUX_SW_STATUS 0x16d2 12542 #define regDP_AUX1_AUX_SW_STATUS_BASE_IDX 2 12543 #define regDP_AUX1_AUX_LS_STATUS 0x16d3 12544 #define regDP_AUX1_AUX_LS_STATUS_BASE_IDX 2 12545 #define regDP_AUX1_AUX_SW_DATA 0x16d4 12546 #define regDP_AUX1_AUX_SW_DATA_BASE_IDX 2 12547 #define regDP_AUX1_AUX_LS_DATA 0x16d5 12548 #define regDP_AUX1_AUX_LS_DATA_BASE_IDX 2 12549 #define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x16d6 12550 #define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 12551 #define regDP_AUX1_AUX_DPHY_TX_CONTROL 0x16d7 12552 #define regDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2 12553 #define regDP_AUX1_AUX_DPHY_RX_CONTROL0 0x16d8 12554 #define regDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 12555 #define regDP_AUX1_AUX_DPHY_RX_CONTROL1 0x16d9 12556 #define regDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 12557 #define regDP_AUX1_AUX_DPHY_TX_STATUS 0x16da 12558 #define regDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2 12559 #define regDP_AUX1_AUX_DPHY_RX_STATUS 0x16db 12560 #define regDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2 12561 #define regDP_AUX1_AUX_PHY_WAKE_CNTL 0x16dd 12562 #define regDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX 2 12563 #define regDP_AUX1_AUX_PHY_WAKE_STATUS 0x16de 12564 #define regDP_AUX1_AUX_PHY_WAKE_STATUS_BASE_IDX 2 12565 12566 12567 // addressBlock: dcn_dcec_dcoh_dp_aux2_dispdec 12568 // base address: 0xe0 12569 #define regDP_AUX2_AUX_CONTROL 0x16ea 12570 #define regDP_AUX2_AUX_CONTROL_BASE_IDX 2 12571 #define regDP_AUX2_AUX_SW_CONTROL 0x16eb 12572 #define regDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2 12573 #define regDP_AUX2_AUX_ARB_CONTROL 0x16ec 12574 #define regDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2 12575 #define regDP_AUX2_AUX_INTERRUPT_CONTROL 0x16ed 12576 #define regDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2 12577 #define regDP_AUX2_AUX_SW_STATUS 0x16ee 12578 #define regDP_AUX2_AUX_SW_STATUS_BASE_IDX 2 12579 #define regDP_AUX2_AUX_LS_STATUS 0x16ef 12580 #define regDP_AUX2_AUX_LS_STATUS_BASE_IDX 2 12581 #define regDP_AUX2_AUX_SW_DATA 0x16f0 12582 #define regDP_AUX2_AUX_SW_DATA_BASE_IDX 2 12583 #define regDP_AUX2_AUX_LS_DATA 0x16f1 12584 #define regDP_AUX2_AUX_LS_DATA_BASE_IDX 2 12585 #define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x16f2 12586 #define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 12587 #define regDP_AUX2_AUX_DPHY_TX_CONTROL 0x16f3 12588 #define regDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2 12589 #define regDP_AUX2_AUX_DPHY_RX_CONTROL0 0x16f4 12590 #define regDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 12591 #define regDP_AUX2_AUX_DPHY_RX_CONTROL1 0x16f5 12592 #define regDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 12593 #define regDP_AUX2_AUX_DPHY_TX_STATUS 0x16f6 12594 #define regDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2 12595 #define regDP_AUX2_AUX_DPHY_RX_STATUS 0x16f7 12596 #define regDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2 12597 #define regDP_AUX2_AUX_PHY_WAKE_CNTL 0x16f9 12598 #define regDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX 2 12599 #define regDP_AUX2_AUX_PHY_WAKE_STATUS 0x16fa 12600 #define regDP_AUX2_AUX_PHY_WAKE_STATUS_BASE_IDX 2 12601 12602 12603 // addressBlock: dcn_dcec_dcoh_dp_aux3_dispdec 12604 // base address: 0x150 12605 #define regDP_AUX3_AUX_CONTROL 0x1706 12606 #define regDP_AUX3_AUX_CONTROL_BASE_IDX 2 12607 #define regDP_AUX3_AUX_SW_CONTROL 0x1707 12608 #define regDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2 12609 #define regDP_AUX3_AUX_ARB_CONTROL 0x1708 12610 #define regDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2 12611 #define regDP_AUX3_AUX_INTERRUPT_CONTROL 0x1709 12612 #define regDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2 12613 #define regDP_AUX3_AUX_SW_STATUS 0x170a 12614 #define regDP_AUX3_AUX_SW_STATUS_BASE_IDX 2 12615 #define regDP_AUX3_AUX_LS_STATUS 0x170b 12616 #define regDP_AUX3_AUX_LS_STATUS_BASE_IDX 2 12617 #define regDP_AUX3_AUX_SW_DATA 0x170c 12618 #define regDP_AUX3_AUX_SW_DATA_BASE_IDX 2 12619 #define regDP_AUX3_AUX_LS_DATA 0x170d 12620 #define regDP_AUX3_AUX_LS_DATA_BASE_IDX 2 12621 #define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x170e 12622 #define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 12623 #define regDP_AUX3_AUX_DPHY_TX_CONTROL 0x170f 12624 #define regDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2 12625 #define regDP_AUX3_AUX_DPHY_RX_CONTROL0 0x1710 12626 #define regDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 12627 #define regDP_AUX3_AUX_DPHY_RX_CONTROL1 0x1711 12628 #define regDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 12629 #define regDP_AUX3_AUX_DPHY_TX_STATUS 0x1712 12630 #define regDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2 12631 #define regDP_AUX3_AUX_DPHY_RX_STATUS 0x1713 12632 #define regDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2 12633 #define regDP_AUX3_AUX_PHY_WAKE_CNTL 0x1715 12634 #define regDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX 2 12635 #define regDP_AUX3_AUX_PHY_WAKE_STATUS 0x1716 12636 #define regDP_AUX3_AUX_PHY_WAKE_STATUS_BASE_IDX 2 12637 12638 12639 // addressBlock: dcn_dcec_dcoh_hpd0_dispdec 12640 // base address: 0x0 12641 #define regHPD0_DC_HPD_INT_STATUS 0x175a 12642 #define regHPD0_DC_HPD_INT_STATUS_BASE_IDX 2 12643 #define regHPD0_DC_HPD_INT_CONTROL 0x175b 12644 #define regHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2 12645 #define regHPD0_DC_HPD_CONTROL 0x175c 12646 #define regHPD0_DC_HPD_CONTROL_BASE_IDX 2 12647 #define regHPD0_DC_HPD_FAST_TRAIN_CNTL 0x175d 12648 #define regHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 12649 #define regHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x175e 12650 #define regHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 12651 12652 12653 // addressBlock: dcn_dcec_dcoh_hpd1_dispdec 12654 // base address: 0x20 12655 #define regHPD1_DC_HPD_INT_STATUS 0x1762 12656 #define regHPD1_DC_HPD_INT_STATUS_BASE_IDX 2 12657 #define regHPD1_DC_HPD_INT_CONTROL 0x1763 12658 #define regHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2 12659 #define regHPD1_DC_HPD_CONTROL 0x1764 12660 #define regHPD1_DC_HPD_CONTROL_BASE_IDX 2 12661 #define regHPD1_DC_HPD_FAST_TRAIN_CNTL 0x1765 12662 #define regHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 12663 #define regHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x1766 12664 #define regHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 12665 12666 12667 // addressBlock: dcn_dcec_dcoh_hpd2_dispdec 12668 // base address: 0x40 12669 #define regHPD2_DC_HPD_INT_STATUS 0x176a 12670 #define regHPD2_DC_HPD_INT_STATUS_BASE_IDX 2 12671 #define regHPD2_DC_HPD_INT_CONTROL 0x176b 12672 #define regHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2 12673 #define regHPD2_DC_HPD_CONTROL 0x176c 12674 #define regHPD2_DC_HPD_CONTROL_BASE_IDX 2 12675 #define regHPD2_DC_HPD_FAST_TRAIN_CNTL 0x176d 12676 #define regHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 12677 #define regHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x176e 12678 #define regHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 12679 12680 12681 // addressBlock: dcn_dcec_dcoh_hpd3_dispdec 12682 // base address: 0x60 12683 #define regHPD3_DC_HPD_INT_STATUS 0x1772 12684 #define regHPD3_DC_HPD_INT_STATUS_BASE_IDX 2 12685 #define regHPD3_DC_HPD_INT_CONTROL 0x1773 12686 #define regHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2 12687 #define regHPD3_DC_HPD_CONTROL 0x1774 12688 #define regHPD3_DC_HPD_CONTROL_BASE_IDX 2 12689 #define regHPD3_DC_HPD_FAST_TRAIN_CNTL 0x1775 12690 #define regHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 12691 #define regHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x1776 12692 #define regHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 12693 12694 12695 // addressBlock: dcn_dcec_hpo_hpo_top_dispdec 12696 // base address: 0x2790c 12697 #define regHPO_TOP_CLOCK_CONTROL 0x0e43 12698 #define regHPO_TOP_CLOCK_CONTROL_BASE_IDX 3 12699 #define regHPO_TOP_HW_CONTROL 0x0e44 12700 #define regHPO_TOP_HW_CONTROL_BASE_IDX 3 12701 12702 12703 // addressBlock: dcn_dcec_hpo_dp_stream_mapper_dispdec 12704 // base address: 0x27958 12705 #define regDP_STREAM_MAPPER_CONTROL0 0x0e56 12706 #define regDP_STREAM_MAPPER_CONTROL0_BASE_IDX 3 12707 #define regDP_STREAM_MAPPER_CONTROL1 0x0e57 12708 #define regDP_STREAM_MAPPER_CONTROL1_BASE_IDX 3 12709 #define regDP_STREAM_MAPPER_CONTROL2 0x0e58 12710 #define regDP_STREAM_MAPPER_CONTROL2_BASE_IDX 3 12711 #define regDP_STREAM_MAPPER_CONTROL3 0x0e59 12712 #define regDP_STREAM_MAPPER_CONTROL3_BASE_IDX 3 12713 #define regDP_STREAM_MAPPER_CONTROL4 0x0e5a 12714 #define regDP_STREAM_MAPPER_CONTROL4_BASE_IDX 3 12715 #define regDP_STREAM_MAPPER_CONTROL5 0x0e5b 12716 #define regDP_STREAM_MAPPER_CONTROL5_BASE_IDX 3 12717 12718 12719 // addressBlock: dcn_dcec_hpo_hdmi_link_enc0_dispdec 12720 // base address: 0x2656c 12721 #define regHDMI_LINK_ENC_CONTROL 0x095b 12722 #define regHDMI_LINK_ENC_CONTROL_BASE_IDX 3 12723 #define regHDMI_LINK_ENC_CLK_CTRL 0x095c 12724 #define regHDMI_LINK_ENC_CLK_CTRL_BASE_IDX 3 12725 12726 12727 // addressBlock: dcn_dcec_hpo_hdmi_frl_enc0_dispdec 12728 // base address: 0x26594 12729 #define regHDMI_FRL_ENC_CONFIG 0x0965 12730 #define regHDMI_FRL_ENC_CONFIG_BASE_IDX 3 12731 #define regHDMI_FRL_ENC_CONFIG2 0x0966 12732 #define regHDMI_FRL_ENC_CONFIG2_BASE_IDX 3 12733 #define regHDMI_FRL_ENC_METER_BUFFER_STATUS 0x0967 12734 #define regHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX 3 12735 #define regHDMI_FRL_ENC_MEM_CTRL 0x0968 12736 #define regHDMI_FRL_ENC_MEM_CTRL_BASE_IDX 3 12737 12738 12739 // addressBlock: dcn_dcec_hpo_hdmi_stream_enc0_dispdec 12740 // base address: 0x2634c 12741 #define regHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3 12742 #define regHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3 12743 #define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d5 12744 #define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3 12745 #define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d6 12746 #define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3 12747 #define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d7 12748 #define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3 12749 #define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d8 12750 #define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3 12751 12752 12753 // addressBlock: dcn_dcec_hpo_hdmi_stream_enc0_afmt_afmt_dispdec 12754 // base address: 0x2646c 12755 #define regAFMT4_AFMT_ACP 0x091b 12756 #define regAFMT4_AFMT_ACP_BASE_IDX 3 12757 #define regAFMT4_AFMT_VBI_PACKET_CONTROL 0x091c 12758 #define regAFMT4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 3 12759 #define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2 0x091d 12760 #define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 3 12761 #define regAFMT4_AFMT_AUDIO_INFO0 0x091e 12762 #define regAFMT4_AFMT_AUDIO_INFO0_BASE_IDX 3 12763 #define regAFMT4_AFMT_AUDIO_INFO1 0x091f 12764 #define regAFMT4_AFMT_AUDIO_INFO1_BASE_IDX 3 12765 #define regAFMT4_AFMT_60958_0 0x0920 12766 #define regAFMT4_AFMT_60958_0_BASE_IDX 3 12767 #define regAFMT4_AFMT_60958_1 0x0921 12768 #define regAFMT4_AFMT_60958_1_BASE_IDX 3 12769 #define regAFMT4_AFMT_AUDIO_CRC_CONTROL 0x0922 12770 #define regAFMT4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 3 12771 #define regAFMT4_AFMT_RAMP_CONTROL0 0x0923 12772 #define regAFMT4_AFMT_RAMP_CONTROL0_BASE_IDX 3 12773 #define regAFMT4_AFMT_RAMP_CONTROL1 0x0924 12774 #define regAFMT4_AFMT_RAMP_CONTROL1_BASE_IDX 3 12775 #define regAFMT4_AFMT_RAMP_CONTROL2 0x0925 12776 #define regAFMT4_AFMT_RAMP_CONTROL2_BASE_IDX 3 12777 #define regAFMT4_AFMT_RAMP_CONTROL3 0x0926 12778 #define regAFMT4_AFMT_RAMP_CONTROL3_BASE_IDX 3 12779 #define regAFMT4_AFMT_60958_2 0x0927 12780 #define regAFMT4_AFMT_60958_2_BASE_IDX 3 12781 #define regAFMT4_AFMT_AUDIO_CRC_RESULT 0x0928 12782 #define regAFMT4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 3 12783 #define regAFMT4_AFMT_STATUS 0x0929 12784 #define regAFMT4_AFMT_STATUS_BASE_IDX 3 12785 #define regAFMT4_AFMT_AUDIO_PACKET_CONTROL 0x092a 12786 #define regAFMT4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 3 12787 #define regAFMT4_AFMT_INFOFRAME_CONTROL0 0x092b 12788 #define regAFMT4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 3 12789 #define regAFMT4_AFMT_INTERRUPT_STATUS 0x092c 12790 #define regAFMT4_AFMT_INTERRUPT_STATUS_BASE_IDX 3 12791 #define regAFMT4_AFMT_AUDIO_SRC_CONTROL 0x092d 12792 #define regAFMT4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 3 12793 #define regAFMT4_AFMT_AUDIO_DBG_DTO_CNTL 0x092e 12794 #define regAFMT4_AFMT_AUDIO_DBG_DTO_CNTL_BASE_IDX 3 12795 #define regAFMT4_AFMT_MEM_PWR 0x092f 12796 #define regAFMT4_AFMT_MEM_PWR_BASE_IDX 3 12797 12798 12799 // addressBlock: dcn_dcec_hpo_hdmi_stream_enc0_dme_dme_dispdec 12800 // base address: 0x264f0 12801 #define regDME4_DME_CONTROL 0x093c 12802 #define regDME4_DME_CONTROL_BASE_IDX 3 12803 #define regDME4_DME_MEMORY_CONTROL 0x093d 12804 #define regDME4_DME_MEMORY_CONTROL_BASE_IDX 3 12805 12806 12807 // addressBlock: dcn_dcec_hpo_hdmi_stream_enc0_vpg_vpg_dispdec 12808 // base address: 0x264c4 12809 #define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL 0x0931 12810 #define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 3 12811 #define regVPG4_VPG_GENERIC_PACKET_DATA 0x0932 12812 #define regVPG4_VPG_GENERIC_PACKET_DATA_BASE_IDX 3 12813 #define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL 0x0933 12814 #define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 3 12815 #define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x0934 12816 #define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 3 12817 #define regVPG4_VPG_GENERIC_STATUS 0x0935 12818 #define regVPG4_VPG_GENERIC_STATUS_BASE_IDX 3 12819 #define regVPG4_VPG_MEM_PWR 0x0936 12820 #define regVPG4_VPG_MEM_PWR_BASE_IDX 3 12821 #define regVPG4_VPG_ISRC1_2_ACCESS_CTRL 0x0937 12822 #define regVPG4_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 3 12823 #define regVPG4_VPG_ISRC1_2_DATA 0x0938 12824 #define regVPG4_VPG_ISRC1_2_DATA_BASE_IDX 3 12825 #define regVPG4_VPG_MPEG_INFO0 0x0939 12826 #define regVPG4_VPG_MPEG_INFO0_BASE_IDX 3 12827 #define regVPG4_VPG_MPEG_INFO1 0x093a 12828 #define regVPG4_VPG_MPEG_INFO1_BASE_IDX 3 12829 12830 // addressBlock: dcn_dcec_hpo_hdmi_tb_enc0_dispdec 12831 // base address: 0x2637c 12832 #define regHDMI_TB_ENC_CONTROL 0x08df 12833 #define regHDMI_TB_ENC_CONTROL_BASE_IDX 3 12834 #define regHDMI_TB_ENC_PIXEL_FORMAT 0x08e0 12835 #define regHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX 3 12836 #define regHDMI_TB_ENC_PACKET_CONTROL 0x08e1 12837 #define regHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX 3 12838 #define regHDMI_TB_ENC_ACR_PACKET_CONTROL 0x08e2 12839 #define regHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX 3 12840 #define regHDMI_TB_ENC_VBI_PACKET_CONTROL1 0x08e3 12841 #define regHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX 3 12842 #define regHDMI_TB_ENC_VBI_PACKET_CONTROL2 0x08e4 12843 #define regHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX 3 12844 #define regHDMI_TB_ENC_GC_CONTROL 0x08e5 12845 #define regHDMI_TB_ENC_GC_CONTROL_BASE_IDX 3 12846 #define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0 0x08e6 12847 #define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX 3 12848 #define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1 0x08e7 12849 #define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX 3 12850 #define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2 0x08e8 12851 #define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX 3 12852 #define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE 0x08e9 12853 #define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX 3 12854 #define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE 0x08ea 12855 #define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX 3 12856 #define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE 0x08eb 12857 #define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX 3 12858 #define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE 0x08ec 12859 #define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX 3 12860 #define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE 0x08ed 12861 #define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX 3 12862 #define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE 0x08ee 12863 #define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX 3 12864 #define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE 0x08ef 12865 #define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX 3 12866 #define regHDMI_TB_ENC_GENERIC_PACKET14_LINE 0x08f0 12867 #define regHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX 3 12868 #define regHDMI_TB_ENC_DB_CONTROL 0x08f1 12869 #define regHDMI_TB_ENC_DB_CONTROL_BASE_IDX 3 12870 #define regHDMI_TB_ENC_ACR_32_0 0x08f2 12871 #define regHDMI_TB_ENC_ACR_32_0_BASE_IDX 3 12872 #define regHDMI_TB_ENC_ACR_32_1 0x08f3 12873 #define regHDMI_TB_ENC_ACR_32_1_BASE_IDX 3 12874 #define regHDMI_TB_ENC_ACR_44_0 0x08f4 12875 #define regHDMI_TB_ENC_ACR_44_0_BASE_IDX 3 12876 #define regHDMI_TB_ENC_ACR_44_1 0x08f5 12877 #define regHDMI_TB_ENC_ACR_44_1_BASE_IDX 3 12878 #define regHDMI_TB_ENC_ACR_48_0 0x08f6 12879 #define regHDMI_TB_ENC_ACR_48_0_BASE_IDX 3 12880 #define regHDMI_TB_ENC_ACR_48_1 0x08f7 12881 #define regHDMI_TB_ENC_ACR_48_1_BASE_IDX 3 12882 #define regHDMI_TB_ENC_ACR_STATUS_0 0x08f8 12883 #define regHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX 3 12884 #define regHDMI_TB_ENC_ACR_STATUS_1 0x08f9 12885 #define regHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX 3 12886 #define regHDMI_TB_ENC_BUFFER_CONTROL 0x08fb 12887 #define regHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX 3 12888 #define regHDMI_TB_ENC_MEM_CTRL 0x08fe 12889 #define regHDMI_TB_ENC_MEM_CTRL_BASE_IDX 3 12890 #define regHDMI_TB_ENC_METADATA_PACKET_CONTROL 0x08ff 12891 #define regHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX 3 12892 #define regHDMI_TB_ENC_H_ACTIVE_BLANK 0x0900 12893 #define regHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX 3 12894 #define regHDMI_TB_ENC_HC_ACTIVE_BLANK 0x0901 12895 #define regHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX 3 12896 #define regHDMI_TB_ENC_CRC_CNTL 0x0903 12897 #define regHDMI_TB_ENC_CRC_CNTL_BASE_IDX 3 12898 #define regHDMI_TB_ENC_CRC_RESULT_0 0x0904 12899 #define regHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX 3 12900 #define regHDMI_TB_ENC_ENCRYPTION_CONTROL 0x0907 12901 #define regHDMI_TB_ENC_ENCRYPTION_CONTROL_BASE_IDX 3 12902 #define regHDMI_TB_ENC_MODE 0x0908 12903 #define regHDMI_TB_ENC_MODE_BASE_IDX 3 12904 #define regHDMI_TB_ENC_INPUT_FIFO_STATUS 0x0909 12905 #define regHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX 3 12906 #define regHDMI_TB_ENC_CRC_RESULT_1 0x090a 12907 #define regHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX 3 12908 12909 12910 // addressBlock: dcn_dcec_hpo_dp_stream_enc0_dispdec 12911 // base address: 0x1ab8c 12912 #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL 0x3623 12913 #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 12914 #define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x3624 12915 #define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 12916 #define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL 0x3625 12917 #define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 12918 #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x3626 12919 #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 12920 #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x3627 12921 #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 12922 #define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE 0x3628 12923 #define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE_BASE_IDX 2 12924 12925 12926 // addressBlock: dcn_dcec_hpo_dp_stream_enc0_apg_apg_dispdec 12927 // base address: 0x1abc0 12928 #define regAPG0_APG_CONTROL 0x3630 12929 #define regAPG0_APG_CONTROL_BASE_IDX 2 12930 #define regAPG0_APG_CONTROL2 0x3631 12931 #define regAPG0_APG_CONTROL2_BASE_IDX 2 12932 #define regAPG0_APG_DBG_GEN_CONTROL 0x3632 12933 #define regAPG0_APG_DBG_GEN_CONTROL_BASE_IDX 2 12934 #define regAPG0_APG_PACKET_CONTROL 0x3633 12935 #define regAPG0_APG_PACKET_CONTROL_BASE_IDX 2 12936 #define regAPG0_APG_DBG_ACP 0x3634 12937 #define regAPG0_APG_DBG_ACP_BASE_IDX 2 12938 #define regAPG0_APG_AUDIO_INFO 0x3635 12939 #define regAPG0_APG_AUDIO_INFO_BASE_IDX 2 12940 #define regAPG0_APG_DBG_AUDIO_INFO 0x3636 12941 #define regAPG0_APG_DBG_AUDIO_INFO_BASE_IDX 2 12942 #define regAPG0_APG_DBG_60958_0 0x3637 12943 #define regAPG0_APG_DBG_60958_0_BASE_IDX 2 12944 #define regAPG0_APG_DBG_60958_1 0x3638 12945 #define regAPG0_APG_DBG_60958_1_BASE_IDX 2 12946 #define regAPG0_APG_DBG_60958_2 0x3639 12947 #define regAPG0_APG_DBG_60958_2_BASE_IDX 2 12948 #define regAPG0_APG_AUDIO_CRC_CONTROL 0x363a 12949 #define regAPG0_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 12950 #define regAPG0_APG_AUDIO_CRC_CONTROL2 0x363b 12951 #define regAPG0_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 12952 #define regAPG0_APG_AUDIO_CRC_RESULT 0x363c 12953 #define regAPG0_APG_AUDIO_CRC_RESULT_BASE_IDX 2 12954 #define regAPG0_APG_DBG_RAMP_CONTROL0 0x363d 12955 #define regAPG0_APG_DBG_RAMP_CONTROL0_BASE_IDX 2 12956 #define regAPG0_APG_DBG_RAMP_CONTROL1 0x363e 12957 #define regAPG0_APG_DBG_RAMP_CONTROL1_BASE_IDX 2 12958 #define regAPG0_APG_DBG_RAMP_CONTROL2 0x363f 12959 #define regAPG0_APG_DBG_RAMP_CONTROL2_BASE_IDX 2 12960 #define regAPG0_APG_DBG_RAMP_CONTROL3 0x3640 12961 #define regAPG0_APG_DBG_RAMP_CONTROL3_BASE_IDX 2 12962 #define regAPG0_APG_STATUS 0x3641 12963 #define regAPG0_APG_STATUS_BASE_IDX 2 12964 #define regAPG0_APG_STATUS2 0x3642 12965 #define regAPG0_APG_STATUS2_BASE_IDX 2 12966 #define regAPG0_APG_DBG_AUDIO_DTO_CNTL 0x3643 12967 #define regAPG0_APG_DBG_AUDIO_DTO_CNTL_BASE_IDX 2 12968 #define regAPG0_APG_MEM_PWR 0x3644 12969 #define regAPG0_APG_MEM_PWR_BASE_IDX 2 12970 #define regAPG0_APG_SPARE 0x3646 12971 #define regAPG0_APG_SPARE_BASE_IDX 2 12972 12973 12974 // addressBlock: dcn_dcec_hpo_dp_stream_enc0_dme_dme_dispdec 12975 // base address: 0x1ac38 12976 #define regDME5_DME_CONTROL 0x364e 12977 #define regDME5_DME_CONTROL_BASE_IDX 2 12978 #define regDME5_DME_MEMORY_CONTROL 0x364f 12979 #define regDME5_DME_MEMORY_CONTROL_BASE_IDX 2 12980 12981 12982 // addressBlock: dcn_dcec_hpo_dp_stream_enc0_vpg_vpg_dispdec 12983 // base address: 0x1ac44 12984 #define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL 0x3651 12985 #define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 12986 #define regVPG5_VPG_GENERIC_PACKET_DATA 0x3652 12987 #define regVPG5_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 12988 #define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL 0x3653 12989 #define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 12990 #define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x3654 12991 #define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 12992 #define regVPG5_VPG_GENERIC_STATUS 0x3655 12993 #define regVPG5_VPG_GENERIC_STATUS_BASE_IDX 2 12994 #define regVPG5_VPG_MEM_PWR 0x3656 12995 #define regVPG5_VPG_MEM_PWR_BASE_IDX 2 12996 #define regVPG5_VPG_ISRC1_2_ACCESS_CTRL 0x3657 12997 #define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 12998 #define regVPG5_VPG_ISRC1_2_DATA 0x3658 12999 #define regVPG5_VPG_ISRC1_2_DATA_BASE_IDX 2 13000 #define regVPG5_VPG_MPEG_INFO0 0x3659 13001 #define regVPG5_VPG_MPEG_INFO0_BASE_IDX 2 13002 #define regVPG5_VPG_MPEG_INFO1 0x365a 13003 #define regVPG5_VPG_MPEG_INFO1_BASE_IDX 2 13004 13005 13006 // addressBlock: dcn_dcec_hpo_dp_sym32_enc0_dispdec 13007 // base address: 0x1ac74 13008 #define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL 0x365d 13009 #define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL_BASE_IDX 2 13010 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL 0x365e 13011 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 13012 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x365f 13013 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13014 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3660 13015 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13016 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3661 13017 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 13018 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0 0x3662 13019 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 13020 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1 0x3663 13021 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 13022 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2 0x3664 13023 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 13024 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3 0x3665 13025 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 13026 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4 0x3666 13027 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 13028 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5 0x3667 13029 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 13030 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6 0x3668 13031 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 13032 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7 0x3669 13033 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 13034 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8 0x366a 13035 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 13036 #define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL 0x366b 13037 #define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 13038 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x366c 13039 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 13040 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x366d 13041 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 13042 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x366e 13043 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 13044 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x366f 13045 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 13046 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3670 13047 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 13048 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3671 13049 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 13050 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x3672 13051 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 13052 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x3673 13053 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 13054 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x3674 13055 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 13056 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x3675 13057 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 13058 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x3676 13059 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 13060 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x3677 13061 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 13062 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x3678 13063 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 13064 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x3679 13065 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 13066 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x367a 13067 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 13068 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL 0x367b 13069 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 13070 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x367c 13071 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 13072 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x367d 13073 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 13074 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x367e 13075 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 13076 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_FRAMING 0x367f 13077 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_FRAMING_BASE_IDX 2 13078 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_ATP_CONTROL0 0x3680 13079 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_ATP_CONTROL0_BASE_IDX 2 13080 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_ATP_CONTROL1 0x3681 13081 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_ATP_CONTROL1_BASE_IDX 2 13082 #define regDP_SYM32_ENC0_DP_SYM32_ENC_IDLE_PATTERN_CONTROL 0x3682 13083 #define regDP_SYM32_ENC0_DP_SYM32_ENC_IDLE_PATTERN_CONTROL_BASE_IDX 2 13084 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL 0x3683 13085 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 13086 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL 0x3684 13087 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 13088 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3685 13089 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 13090 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x3686 13091 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 13092 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL 0x3687 13093 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 13094 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0 0x3688 13095 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 13096 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1 0x3689 13097 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 13098 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS 0x368a 13099 #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 13100 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS 0x368b 13101 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX 2 13102 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL 0x368c 13103 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX 2 13104 #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL 0x368d 13105 #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL_BASE_IDX 2 13106 #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL 0x368e 13107 #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL_BASE_IDX 2 13108 #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_REQUEST_OFFSET 0x368f 13109 #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_REQUEST_OFFSET_BASE_IDX 2 13110 #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_READY_CONTROL 0x3690 13111 #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_READY_CONTROL_BASE_IDX 2 13112 #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL 0x3691 13113 #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL_BASE_IDX 2 13114 #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_STATUS 0x3692 13115 #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_STATUS_BASE_IDX 2 13116 #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_START_CONTROL 0x3693 13117 #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_START_CONTROL_BASE_IDX 2 13118 #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL 0x3694 13119 #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL_BASE_IDX 2 13120 #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS 0x3695 13121 #define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS_BASE_IDX 2 13122 #define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3696 13123 #define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 13124 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE 0x3697 13125 #define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE_BASE_IDX 2 13126 13127 13128 // addressBlock: dcn_dcec_hpo_dp_stream_enc1_dispdec 13129 // base address: 0x1aedc 13130 #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL 0x36f7 13131 #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 13132 #define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x36f8 13133 #define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 13134 #define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL 0x36f9 13135 #define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 13136 #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x36fa 13137 #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 13138 #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x36fb 13139 #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 13140 #define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE 0x36fc 13141 #define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE_BASE_IDX 2 13142 13143 13144 // addressBlock: dcn_dcec_hpo_dp_stream_enc1_apg_apg_dispdec 13145 // base address: 0x1af10 13146 #define regAPG1_APG_CONTROL 0x3704 13147 #define regAPG1_APG_CONTROL_BASE_IDX 2 13148 #define regAPG1_APG_CONTROL2 0x3705 13149 #define regAPG1_APG_CONTROL2_BASE_IDX 2 13150 #define regAPG1_APG_DBG_GEN_CONTROL 0x3706 13151 #define regAPG1_APG_DBG_GEN_CONTROL_BASE_IDX 2 13152 #define regAPG1_APG_PACKET_CONTROL 0x3707 13153 #define regAPG1_APG_PACKET_CONTROL_BASE_IDX 2 13154 #define regAPG1_APG_DBG_ACP 0x3708 13155 #define regAPG1_APG_DBG_ACP_BASE_IDX 2 13156 #define regAPG1_APG_AUDIO_INFO 0x3709 13157 #define regAPG1_APG_AUDIO_INFO_BASE_IDX 2 13158 #define regAPG1_APG_DBG_AUDIO_INFO 0x370a 13159 #define regAPG1_APG_DBG_AUDIO_INFO_BASE_IDX 2 13160 #define regAPG1_APG_DBG_60958_0 0x370b 13161 #define regAPG1_APG_DBG_60958_0_BASE_IDX 2 13162 #define regAPG1_APG_DBG_60958_1 0x370c 13163 #define regAPG1_APG_DBG_60958_1_BASE_IDX 2 13164 #define regAPG1_APG_DBG_60958_2 0x370d 13165 #define regAPG1_APG_DBG_60958_2_BASE_IDX 2 13166 #define regAPG1_APG_AUDIO_CRC_CONTROL 0x370e 13167 #define regAPG1_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 13168 #define regAPG1_APG_AUDIO_CRC_CONTROL2 0x370f 13169 #define regAPG1_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 13170 #define regAPG1_APG_AUDIO_CRC_RESULT 0x3710 13171 #define regAPG1_APG_AUDIO_CRC_RESULT_BASE_IDX 2 13172 #define regAPG1_APG_DBG_RAMP_CONTROL0 0x3711 13173 #define regAPG1_APG_DBG_RAMP_CONTROL0_BASE_IDX 2 13174 #define regAPG1_APG_DBG_RAMP_CONTROL1 0x3712 13175 #define regAPG1_APG_DBG_RAMP_CONTROL1_BASE_IDX 2 13176 #define regAPG1_APG_DBG_RAMP_CONTROL2 0x3713 13177 #define regAPG1_APG_DBG_RAMP_CONTROL2_BASE_IDX 2 13178 #define regAPG1_APG_DBG_RAMP_CONTROL3 0x3714 13179 #define regAPG1_APG_DBG_RAMP_CONTROL3_BASE_IDX 2 13180 #define regAPG1_APG_STATUS 0x3715 13181 #define regAPG1_APG_STATUS_BASE_IDX 2 13182 #define regAPG1_APG_STATUS2 0x3716 13183 #define regAPG1_APG_STATUS2_BASE_IDX 2 13184 #define regAPG1_APG_DBG_AUDIO_DTO_CNTL 0x3717 13185 #define regAPG1_APG_DBG_AUDIO_DTO_CNTL_BASE_IDX 2 13186 #define regAPG1_APG_MEM_PWR 0x3718 13187 #define regAPG1_APG_MEM_PWR_BASE_IDX 2 13188 #define regAPG1_APG_SPARE 0x371a 13189 #define regAPG1_APG_SPARE_BASE_IDX 2 13190 13191 13192 // addressBlock: dcn_dcec_hpo_dp_stream_enc1_dme_dme_dispdec 13193 // base address: 0x1af88 13194 #define regDME6_DME_CONTROL 0x3722 13195 #define regDME6_DME_CONTROL_BASE_IDX 2 13196 #define regDME6_DME_MEMORY_CONTROL 0x3723 13197 #define regDME6_DME_MEMORY_CONTROL_BASE_IDX 2 13198 13199 13200 // addressBlock: dcn_dcec_hpo_dp_stream_enc1_vpg_vpg_dispdec 13201 // base address: 0x1af94 13202 #define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL 0x3725 13203 #define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 13204 #define regVPG6_VPG_GENERIC_PACKET_DATA 0x3726 13205 #define regVPG6_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 13206 #define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL 0x3727 13207 #define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 13208 #define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x3728 13209 #define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 13210 #define regVPG6_VPG_GENERIC_STATUS 0x3729 13211 #define regVPG6_VPG_GENERIC_STATUS_BASE_IDX 2 13212 #define regVPG6_VPG_MEM_PWR 0x372a 13213 #define regVPG6_VPG_MEM_PWR_BASE_IDX 2 13214 #define regVPG6_VPG_ISRC1_2_ACCESS_CTRL 0x372b 13215 #define regVPG6_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 13216 #define regVPG6_VPG_ISRC1_2_DATA 0x372c 13217 #define regVPG6_VPG_ISRC1_2_DATA_BASE_IDX 2 13218 #define regVPG6_VPG_MPEG_INFO0 0x372d 13219 #define regVPG6_VPG_MPEG_INFO0_BASE_IDX 2 13220 #define regVPG6_VPG_MPEG_INFO1 0x372e 13221 #define regVPG6_VPG_MPEG_INFO1_BASE_IDX 2 13222 13223 13224 // addressBlock: dcn_dcec_hpo_dp_sym32_enc1_dispdec 13225 // base address: 0x1afc4 13226 #define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL 0x3731 13227 #define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL_BASE_IDX 2 13228 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL 0x3732 13229 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 13230 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x3733 13231 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13232 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3734 13233 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13234 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3735 13235 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 13236 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0 0x3736 13237 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 13238 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1 0x3737 13239 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 13240 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2 0x3738 13241 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 13242 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3 0x3739 13243 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 13244 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4 0x373a 13245 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 13246 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5 0x373b 13247 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 13248 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6 0x373c 13249 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 13250 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7 0x373d 13251 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 13252 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8 0x373e 13253 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 13254 #define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL 0x373f 13255 #define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 13256 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x3740 13257 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 13258 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x3741 13259 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 13260 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x3742 13261 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 13262 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x3743 13263 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 13264 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3744 13265 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 13266 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3745 13267 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 13268 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x3746 13269 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 13270 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x3747 13271 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 13272 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x3748 13273 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 13274 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x3749 13275 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 13276 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x374a 13277 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 13278 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x374b 13279 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 13280 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x374c 13281 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 13282 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x374d 13283 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 13284 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x374e 13285 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 13286 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL 0x374f 13287 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 13288 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x3750 13289 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 13290 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x3751 13291 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 13292 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x3752 13293 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 13294 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_FRAMING 0x3753 13295 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_FRAMING_BASE_IDX 2 13296 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_ATP_CONTROL0 0x3754 13297 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_ATP_CONTROL0_BASE_IDX 2 13298 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_ATP_CONTROL1 0x3755 13299 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_ATP_CONTROL1_BASE_IDX 2 13300 #define regDP_SYM32_ENC1_DP_SYM32_ENC_IDLE_PATTERN_CONTROL 0x3756 13301 #define regDP_SYM32_ENC1_DP_SYM32_ENC_IDLE_PATTERN_CONTROL_BASE_IDX 2 13302 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL 0x3757 13303 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 13304 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL 0x3758 13305 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 13306 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3759 13307 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 13308 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x375a 13309 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 13310 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL 0x375b 13311 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 13312 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0 0x375c 13313 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 13314 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1 0x375d 13315 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 13316 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS 0x375e 13317 #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 13318 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS 0x375f 13319 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX 2 13320 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL 0x3760 13321 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX 2 13322 #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL 0x3761 13323 #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL_BASE_IDX 2 13324 #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL 0x3762 13325 #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL_BASE_IDX 2 13326 #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_REQUEST_OFFSET 0x3763 13327 #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_REQUEST_OFFSET_BASE_IDX 2 13328 #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_READY_CONTROL 0x3764 13329 #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_READY_CONTROL_BASE_IDX 2 13330 #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL 0x3765 13331 #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL_BASE_IDX 2 13332 #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_STATUS 0x3766 13333 #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_STATUS_BASE_IDX 2 13334 #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_START_CONTROL 0x3767 13335 #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_START_CONTROL_BASE_IDX 2 13336 #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL 0x3768 13337 #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL_BASE_IDX 2 13338 #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS 0x3769 13339 #define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS_BASE_IDX 2 13340 #define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL 0x376a 13341 #define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 13342 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE 0x376b 13343 #define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE_BASE_IDX 2 13344 13345 13346 // addressBlock: dcn_dcec_hpo_dp_stream_enc2_dispdec 13347 // base address: 0x1b22c 13348 #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL 0x37cb 13349 #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 13350 #define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x37cc 13351 #define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 13352 #define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL 0x37cd 13353 #define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 13354 #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x37ce 13355 #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 13356 #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x37cf 13357 #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 13358 #define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE 0x37d0 13359 #define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE_BASE_IDX 2 13360 13361 13362 // addressBlock: dcn_dcec_hpo_dp_stream_enc2_apg_apg_dispdec 13363 // base address: 0x1b260 13364 #define regAPG2_APG_CONTROL 0x37d8 13365 #define regAPG2_APG_CONTROL_BASE_IDX 2 13366 #define regAPG2_APG_CONTROL2 0x37d9 13367 #define regAPG2_APG_CONTROL2_BASE_IDX 2 13368 #define regAPG2_APG_DBG_GEN_CONTROL 0x37da 13369 #define regAPG2_APG_DBG_GEN_CONTROL_BASE_IDX 2 13370 #define regAPG2_APG_PACKET_CONTROL 0x37db 13371 #define regAPG2_APG_PACKET_CONTROL_BASE_IDX 2 13372 #define regAPG2_APG_DBG_ACP 0x37dc 13373 #define regAPG2_APG_DBG_ACP_BASE_IDX 2 13374 #define regAPG2_APG_AUDIO_INFO 0x37dd 13375 #define regAPG2_APG_AUDIO_INFO_BASE_IDX 2 13376 #define regAPG2_APG_DBG_AUDIO_INFO 0x37de 13377 #define regAPG2_APG_DBG_AUDIO_INFO_BASE_IDX 2 13378 #define regAPG2_APG_DBG_60958_0 0x37df 13379 #define regAPG2_APG_DBG_60958_0_BASE_IDX 2 13380 #define regAPG2_APG_DBG_60958_1 0x37e0 13381 #define regAPG2_APG_DBG_60958_1_BASE_IDX 2 13382 #define regAPG2_APG_DBG_60958_2 0x37e1 13383 #define regAPG2_APG_DBG_60958_2_BASE_IDX 2 13384 #define regAPG2_APG_AUDIO_CRC_CONTROL 0x37e2 13385 #define regAPG2_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 13386 #define regAPG2_APG_AUDIO_CRC_CONTROL2 0x37e3 13387 #define regAPG2_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 13388 #define regAPG2_APG_AUDIO_CRC_RESULT 0x37e4 13389 #define regAPG2_APG_AUDIO_CRC_RESULT_BASE_IDX 2 13390 #define regAPG2_APG_DBG_RAMP_CONTROL0 0x37e5 13391 #define regAPG2_APG_DBG_RAMP_CONTROL0_BASE_IDX 2 13392 #define regAPG2_APG_DBG_RAMP_CONTROL1 0x37e6 13393 #define regAPG2_APG_DBG_RAMP_CONTROL1_BASE_IDX 2 13394 #define regAPG2_APG_DBG_RAMP_CONTROL2 0x37e7 13395 #define regAPG2_APG_DBG_RAMP_CONTROL2_BASE_IDX 2 13396 #define regAPG2_APG_DBG_RAMP_CONTROL3 0x37e8 13397 #define regAPG2_APG_DBG_RAMP_CONTROL3_BASE_IDX 2 13398 #define regAPG2_APG_STATUS 0x37e9 13399 #define regAPG2_APG_STATUS_BASE_IDX 2 13400 #define regAPG2_APG_STATUS2 0x37ea 13401 #define regAPG2_APG_STATUS2_BASE_IDX 2 13402 #define regAPG2_APG_DBG_AUDIO_DTO_CNTL 0x37eb 13403 #define regAPG2_APG_DBG_AUDIO_DTO_CNTL_BASE_IDX 2 13404 #define regAPG2_APG_MEM_PWR 0x37ec 13405 #define regAPG2_APG_MEM_PWR_BASE_IDX 2 13406 #define regAPG2_APG_SPARE 0x37ee 13407 #define regAPG2_APG_SPARE_BASE_IDX 2 13408 13409 13410 // addressBlock: dcn_dcec_hpo_dp_stream_enc2_dme_dme_dispdec 13411 // base address: 0x1b2d8 13412 #define regDME7_DME_CONTROL 0x37f6 13413 #define regDME7_DME_CONTROL_BASE_IDX 2 13414 #define regDME7_DME_MEMORY_CONTROL 0x37f7 13415 #define regDME7_DME_MEMORY_CONTROL_BASE_IDX 2 13416 13417 13418 // addressBlock: dcn_dcec_hpo_dp_stream_enc2_vpg_vpg_dispdec 13419 // base address: 0x1b2e4 13420 #define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL 0x37f9 13421 #define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 13422 #define regVPG7_VPG_GENERIC_PACKET_DATA 0x37fa 13423 #define regVPG7_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 13424 #define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL 0x37fb 13425 #define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 13426 #define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x37fc 13427 #define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 13428 #define regVPG7_VPG_GENERIC_STATUS 0x37fd 13429 #define regVPG7_VPG_GENERIC_STATUS_BASE_IDX 2 13430 #define regVPG7_VPG_MEM_PWR 0x37fe 13431 #define regVPG7_VPG_MEM_PWR_BASE_IDX 2 13432 #define regVPG7_VPG_ISRC1_2_ACCESS_CTRL 0x37ff 13433 #define regVPG7_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 13434 #define regVPG7_VPG_ISRC1_2_DATA 0x3800 13435 #define regVPG7_VPG_ISRC1_2_DATA_BASE_IDX 2 13436 #define regVPG7_VPG_MPEG_INFO0 0x3801 13437 #define regVPG7_VPG_MPEG_INFO0_BASE_IDX 2 13438 #define regVPG7_VPG_MPEG_INFO1 0x3802 13439 #define regVPG7_VPG_MPEG_INFO1_BASE_IDX 2 13440 13441 13442 // addressBlock: dcn_dcec_hpo_dp_sym32_enc2_dispdec 13443 // base address: 0x1b314 13444 #define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL 0x3805 13445 #define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL_BASE_IDX 2 13446 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL 0x3806 13447 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 13448 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x3807 13449 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13450 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3808 13451 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13452 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3809 13453 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 13454 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0 0x380a 13455 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 13456 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1 0x380b 13457 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 13458 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2 0x380c 13459 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 13460 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3 0x380d 13461 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 13462 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4 0x380e 13463 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 13464 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5 0x380f 13465 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 13466 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6 0x3810 13467 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 13468 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7 0x3811 13469 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 13470 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8 0x3812 13471 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 13472 #define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL 0x3813 13473 #define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 13474 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x3814 13475 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 13476 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x3815 13477 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 13478 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x3816 13479 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 13480 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x3817 13481 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 13482 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3818 13483 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 13484 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3819 13485 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 13486 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x381a 13487 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 13488 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x381b 13489 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 13490 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x381c 13491 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 13492 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x381d 13493 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 13494 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x381e 13495 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 13496 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x381f 13497 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 13498 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x3820 13499 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 13500 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x3821 13501 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 13502 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x3822 13503 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 13504 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL 0x3823 13505 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 13506 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x3824 13507 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 13508 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x3825 13509 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 13510 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x3826 13511 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 13512 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_FRAMING 0x3827 13513 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_FRAMING_BASE_IDX 2 13514 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_ATP_CONTROL0 0x3828 13515 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_ATP_CONTROL0_BASE_IDX 2 13516 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_ATP_CONTROL1 0x3829 13517 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_ATP_CONTROL1_BASE_IDX 2 13518 #define regDP_SYM32_ENC2_DP_SYM32_ENC_IDLE_PATTERN_CONTROL 0x382a 13519 #define regDP_SYM32_ENC2_DP_SYM32_ENC_IDLE_PATTERN_CONTROL_BASE_IDX 2 13520 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL 0x382b 13521 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 13522 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL 0x382c 13523 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 13524 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL 0x382d 13525 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 13526 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x382e 13527 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 13528 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL 0x382f 13529 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 13530 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0 0x3830 13531 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 13532 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1 0x3831 13533 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 13534 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS 0x3832 13535 #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 13536 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS 0x3833 13537 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX 2 13538 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL 0x3834 13539 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX 2 13540 #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL 0x3835 13541 #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL_BASE_IDX 2 13542 #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL 0x3836 13543 #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL_BASE_IDX 2 13544 #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_REQUEST_OFFSET 0x3837 13545 #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_REQUEST_OFFSET_BASE_IDX 2 13546 #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_READY_CONTROL 0x3838 13547 #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_READY_CONTROL_BASE_IDX 2 13548 #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL 0x3839 13549 #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL_BASE_IDX 2 13550 #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_STATUS 0x383a 13551 #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_STATUS_BASE_IDX 2 13552 #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_START_CONTROL 0x383b 13553 #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_START_CONTROL_BASE_IDX 2 13554 #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL 0x383c 13555 #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL_BASE_IDX 2 13556 #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS 0x383d 13557 #define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS_BASE_IDX 2 13558 #define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL 0x383e 13559 #define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 13560 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE 0x383f 13561 #define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE_BASE_IDX 2 13562 13563 13564 // addressBlock: dcn_dcec_hpo_dp_stream_enc3_dispdec 13565 // base address: 0x1b57c 13566 #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL 0x389f 13567 #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 13568 #define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x38a0 13569 #define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 13570 #define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL 0x38a1 13571 #define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 13572 #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x38a2 13573 #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 13574 #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x38a3 13575 #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 13576 #define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE 0x38a4 13577 #define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE_BASE_IDX 2 13578 13579 13580 // addressBlock: dcn_dcec_hpo_dp_stream_enc3_apg_apg_dispdec 13581 // base address: 0x1b5b0 13582 #define regAPG3_APG_CONTROL 0x38ac 13583 #define regAPG3_APG_CONTROL_BASE_IDX 2 13584 #define regAPG3_APG_CONTROL2 0x38ad 13585 #define regAPG3_APG_CONTROL2_BASE_IDX 2 13586 #define regAPG3_APG_DBG_GEN_CONTROL 0x38ae 13587 #define regAPG3_APG_DBG_GEN_CONTROL_BASE_IDX 2 13588 #define regAPG3_APG_PACKET_CONTROL 0x38af 13589 #define regAPG3_APG_PACKET_CONTROL_BASE_IDX 2 13590 #define regAPG3_APG_DBG_ACP 0x38b0 13591 #define regAPG3_APG_DBG_ACP_BASE_IDX 2 13592 #define regAPG3_APG_AUDIO_INFO 0x38b1 13593 #define regAPG3_APG_AUDIO_INFO_BASE_IDX 2 13594 #define regAPG3_APG_DBG_AUDIO_INFO 0x38b2 13595 #define regAPG3_APG_DBG_AUDIO_INFO_BASE_IDX 2 13596 #define regAPG3_APG_DBG_60958_0 0x38b3 13597 #define regAPG3_APG_DBG_60958_0_BASE_IDX 2 13598 #define regAPG3_APG_DBG_60958_1 0x38b4 13599 #define regAPG3_APG_DBG_60958_1_BASE_IDX 2 13600 #define regAPG3_APG_DBG_60958_2 0x38b5 13601 #define regAPG3_APG_DBG_60958_2_BASE_IDX 2 13602 #define regAPG3_APG_AUDIO_CRC_CONTROL 0x38b6 13603 #define regAPG3_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 13604 #define regAPG3_APG_AUDIO_CRC_CONTROL2 0x38b7 13605 #define regAPG3_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 13606 #define regAPG3_APG_AUDIO_CRC_RESULT 0x38b8 13607 #define regAPG3_APG_AUDIO_CRC_RESULT_BASE_IDX 2 13608 #define regAPG3_APG_DBG_RAMP_CONTROL0 0x38b9 13609 #define regAPG3_APG_DBG_RAMP_CONTROL0_BASE_IDX 2 13610 #define regAPG3_APG_DBG_RAMP_CONTROL1 0x38ba 13611 #define regAPG3_APG_DBG_RAMP_CONTROL1_BASE_IDX 2 13612 #define regAPG3_APG_DBG_RAMP_CONTROL2 0x38bb 13613 #define regAPG3_APG_DBG_RAMP_CONTROL2_BASE_IDX 2 13614 #define regAPG3_APG_DBG_RAMP_CONTROL3 0x38bc 13615 #define regAPG3_APG_DBG_RAMP_CONTROL3_BASE_IDX 2 13616 #define regAPG3_APG_STATUS 0x38bd 13617 #define regAPG3_APG_STATUS_BASE_IDX 2 13618 #define regAPG3_APG_STATUS2 0x38be 13619 #define regAPG3_APG_STATUS2_BASE_IDX 2 13620 #define regAPG3_APG_DBG_AUDIO_DTO_CNTL 0x38bf 13621 #define regAPG3_APG_DBG_AUDIO_DTO_CNTL_BASE_IDX 2 13622 #define regAPG3_APG_MEM_PWR 0x38c0 13623 #define regAPG3_APG_MEM_PWR_BASE_IDX 2 13624 #define regAPG3_APG_SPARE 0x38c2 13625 #define regAPG3_APG_SPARE_BASE_IDX 2 13626 13627 13628 // addressBlock: dcn_dcec_hpo_dp_stream_enc3_dme_dme_dispdec 13629 // base address: 0x1b628 13630 #define regDME8_DME_CONTROL 0x38ca 13631 #define regDME8_DME_CONTROL_BASE_IDX 2 13632 #define regDME8_DME_MEMORY_CONTROL 0x38cb 13633 #define regDME8_DME_MEMORY_CONTROL_BASE_IDX 2 13634 13635 13636 // addressBlock: dcn_dcec_hpo_dp_stream_enc3_vpg_vpg_dispdec 13637 // base address: 0x1b634 13638 #define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL 0x38cd 13639 #define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 13640 #define regVPG8_VPG_GENERIC_PACKET_DATA 0x38ce 13641 #define regVPG8_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 13642 #define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL 0x38cf 13643 #define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 13644 #define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x38d0 13645 #define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 13646 #define regVPG8_VPG_GENERIC_STATUS 0x38d1 13647 #define regVPG8_VPG_GENERIC_STATUS_BASE_IDX 2 13648 #define regVPG8_VPG_MEM_PWR 0x38d2 13649 #define regVPG8_VPG_MEM_PWR_BASE_IDX 2 13650 #define regVPG8_VPG_ISRC1_2_ACCESS_CTRL 0x38d3 13651 #define regVPG8_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 13652 #define regVPG8_VPG_ISRC1_2_DATA 0x38d4 13653 #define regVPG8_VPG_ISRC1_2_DATA_BASE_IDX 2 13654 #define regVPG8_VPG_MPEG_INFO0 0x38d5 13655 #define regVPG8_VPG_MPEG_INFO0_BASE_IDX 2 13656 #define regVPG8_VPG_MPEG_INFO1 0x38d6 13657 #define regVPG8_VPG_MPEG_INFO1_BASE_IDX 2 13658 13659 13660 // addressBlock: dcn_dcec_hpo_dp_sym32_enc3_dispdec 13661 // base address: 0x1b664 13662 #define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL 0x38d9 13663 #define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL_BASE_IDX 2 13664 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL 0x38da 13665 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 13666 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x38db 13667 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13668 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x38dc 13669 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 13670 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x38dd 13671 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 13672 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0 0x38de 13673 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 13674 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1 0x38df 13675 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 13676 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2 0x38e0 13677 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 13678 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3 0x38e1 13679 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 13680 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4 0x38e2 13681 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 13682 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5 0x38e3 13683 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 13684 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6 0x38e4 13685 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 13686 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7 0x38e5 13687 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 13688 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8 0x38e6 13689 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 13690 #define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL 0x38e7 13691 #define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 13692 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x38e8 13693 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 13694 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x38e9 13695 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 13696 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x38ea 13697 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 13698 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x38eb 13699 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 13700 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x38ec 13701 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 13702 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x38ed 13703 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 13704 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x38ee 13705 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 13706 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x38ef 13707 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 13708 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x38f0 13709 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 13710 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x38f1 13711 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 13712 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x38f2 13713 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 13714 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x38f3 13715 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 13716 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x38f4 13717 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 13718 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x38f5 13719 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 13720 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x38f6 13721 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 13722 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL 0x38f7 13723 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 13724 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x38f8 13725 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 13726 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x38f9 13727 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 13728 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x38fa 13729 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 13730 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_FRAMING 0x38fb 13731 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_FRAMING_BASE_IDX 2 13732 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_ATP_CONTROL0 0x38fc 13733 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_ATP_CONTROL0_BASE_IDX 2 13734 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_ATP_CONTROL1 0x38fd 13735 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_ATP_CONTROL1_BASE_IDX 2 13736 #define regDP_SYM32_ENC3_DP_SYM32_ENC_IDLE_PATTERN_CONTROL 0x38fe 13737 #define regDP_SYM32_ENC3_DP_SYM32_ENC_IDLE_PATTERN_CONTROL_BASE_IDX 2 13738 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL 0x38ff 13739 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 13740 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL 0x3900 13741 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 13742 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3901 13743 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 13744 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x3902 13745 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 13746 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL 0x3903 13747 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 13748 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0 0x3904 13749 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 13750 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1 0x3905 13751 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 13752 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS 0x3906 13753 #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 13754 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS 0x3907 13755 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX 2 13756 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL 0x3908 13757 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX 2 13758 #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL 0x3909 13759 #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL_BASE_IDX 2 13760 #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL 0x390a 13761 #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL_BASE_IDX 2 13762 #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_REQUEST_OFFSET 0x390b 13763 #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_REQUEST_OFFSET_BASE_IDX 2 13764 #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_READY_CONTROL 0x390c 13765 #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_READY_CONTROL_BASE_IDX 2 13766 #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL 0x390d 13767 #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL_BASE_IDX 2 13768 #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_STATUS 0x390e 13769 #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_STATUS_BASE_IDX 2 13770 #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_START_CONTROL 0x390f 13771 #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_START_CONTROL_BASE_IDX 2 13772 #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL 0x3910 13773 #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL_BASE_IDX 2 13774 #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS 0x3911 13775 #define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS_BASE_IDX 2 13776 #define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3912 13777 #define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 13778 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE 0x3913 13779 #define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE_BASE_IDX 2 13780 13781 13782 // addressBlock: dcn_dcec_hpo_dp_link_enc0_dispdec 13783 // base address: 0x1ad7c 13784 #define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL 0x369f 13785 #define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 13786 #define regDP_LINK_ENC0_DP_LINK_ENC_SPARE 0x36a0 13787 #define regDP_LINK_ENC0_DP_LINK_ENC_SPARE_BASE_IDX 2 13788 13789 13790 // addressBlock: dcn_dcec_hpo_dp_dphy_sym320_dispdec 13791 // base address: 0x1add0 13792 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL 0x36b4 13793 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 13794 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS 0x36b5 13795 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS_BASE_IDX 2 13796 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ENCRYPT_CONFIG0 0x36b6 13797 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ENCRYPT_CONFIG0_BASE_IDX 2 13798 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ENCRYPT_CONFIG1 0x36b7 13799 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ENCRYPT_CONFIG1_BASE_IDX 2 13800 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE 0x36b8 13801 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 13802 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0 0x36b9 13803 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 13804 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1 0x36ba 13805 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 13806 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2 0x36bb 13807 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 13808 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3 0x36bc 13809 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 13810 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL4 0x36bd 13811 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL4_BASE_IDX 2 13812 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL5 0x36be 13813 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL5_BASE_IDX 2 13814 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0 0x36bf 13815 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 13816 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1 0x36c0 13817 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 13818 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2 0x36c1 13819 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 13820 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3 0x36c2 13821 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 13822 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC4 0x36c3 13823 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC4_BASE_IDX 2 13824 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC5 0x36c4 13825 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC5_BASE_IDX 2 13826 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0 0x36c5 13827 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 13828 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1 0x36c6 13829 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 13830 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2 0x36c7 13831 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 13832 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3 0x36c8 13833 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 13834 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS4 0x36c9 13835 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS4_BASE_IDX 2 13836 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS5 0x36ca 13837 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS5_BASE_IDX 2 13838 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_CONFIG0 0x36cb 13839 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_CONFIG0_BASE_IDX 2 13840 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR0 0x36cc 13841 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR0_BASE_IDX 2 13842 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR1 0x36cd 13843 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR1_BASE_IDX 2 13844 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR2 0x36ce 13845 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR2_BASE_IDX 2 13846 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR3 0x36cf 13847 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR3_BASE_IDX 2 13848 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0 0x36d0 13849 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0_BASE_IDX 2 13850 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0 0x36d1 13851 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0_BASE_IDX 2 13852 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1 0x36d2 13853 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1_BASE_IDX 2 13854 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_CONTROL 0x36d3 13855 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_CONTROL_BASE_IDX 2 13856 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG 0x36d4 13857 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 13858 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0 0x36d5 13859 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 13860 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1 0x36d6 13861 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 13862 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2 0x36d7 13863 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 13864 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3 0x36d8 13865 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 13866 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE 0x36d9 13867 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 13868 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0 0x36da 13869 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 13870 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1 0x36db 13871 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 13872 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2 0x36dc 13873 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 13874 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3 0x36dd 13875 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 13876 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4 0x36de 13877 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 13878 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5 0x36df 13879 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 13880 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6 0x36e0 13881 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 13882 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7 0x36e1 13883 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 13884 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8 0x36e2 13885 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 13886 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9 0x36e3 13887 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 13888 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10 0x36e4 13889 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 13890 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS 0x36e5 13891 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 13892 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_DEFAULT_OVERRIDE0 0x36e6 13893 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_DEFAULT_OVERRIDE0_BASE_IDX 2 13894 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0 0x36e8 13895 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX 2 13896 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1 0x36e9 13897 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX 2 13898 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL 0x36ea 13899 #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX 2 13900 13901 13902 // addressBlock: dcn_dcec_hpo_dp_link_enc1_dispdec 13903 // base address: 0x1b0cc 13904 #define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL 0x3773 13905 #define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 13906 #define regDP_LINK_ENC1_DP_LINK_ENC_SPARE 0x3774 13907 #define regDP_LINK_ENC1_DP_LINK_ENC_SPARE_BASE_IDX 2 13908 13909 13910 // addressBlock: dcn_dcec_hpo_dp_dphy_sym321_dispdec 13911 // base address: 0x1b120 13912 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL 0x3788 13913 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 13914 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS 0x3789 13915 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS_BASE_IDX 2 13916 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ENCRYPT_CONFIG0 0x378a 13917 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ENCRYPT_CONFIG0_BASE_IDX 2 13918 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ENCRYPT_CONFIG1 0x378b 13919 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ENCRYPT_CONFIG1_BASE_IDX 2 13920 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE 0x378c 13921 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 13922 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0 0x378d 13923 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 13924 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1 0x378e 13925 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 13926 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2 0x378f 13927 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 13928 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3 0x3790 13929 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 13930 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL4 0x3791 13931 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL4_BASE_IDX 2 13932 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL5 0x3792 13933 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL5_BASE_IDX 2 13934 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0 0x3793 13935 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 13936 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1 0x3794 13937 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 13938 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2 0x3795 13939 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 13940 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3 0x3796 13941 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 13942 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC4 0x3797 13943 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC4_BASE_IDX 2 13944 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC5 0x3798 13945 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC5_BASE_IDX 2 13946 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0 0x3799 13947 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 13948 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1 0x379a 13949 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 13950 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2 0x379b 13951 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 13952 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3 0x379c 13953 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 13954 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS4 0x379d 13955 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS4_BASE_IDX 2 13956 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS5 0x379e 13957 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS5_BASE_IDX 2 13958 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_CONFIG0 0x379f 13959 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_CONFIG0_BASE_IDX 2 13960 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR0 0x37a0 13961 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR0_BASE_IDX 2 13962 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR1 0x37a1 13963 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR1_BASE_IDX 2 13964 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR2 0x37a2 13965 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR2_BASE_IDX 2 13966 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR3 0x37a3 13967 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR3_BASE_IDX 2 13968 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0 0x37a4 13969 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0_BASE_IDX 2 13970 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0 0x37a5 13971 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0_BASE_IDX 2 13972 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1 0x37a6 13973 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1_BASE_IDX 2 13974 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_CONTROL 0x37a7 13975 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_CONTROL_BASE_IDX 2 13976 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG 0x37a8 13977 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 13978 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0 0x37a9 13979 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 13980 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1 0x37aa 13981 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 13982 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2 0x37ab 13983 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 13984 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3 0x37ac 13985 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 13986 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE 0x37ad 13987 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 13988 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0 0x37ae 13989 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 13990 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1 0x37af 13991 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 13992 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2 0x37b0 13993 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 13994 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3 0x37b1 13995 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 13996 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4 0x37b2 13997 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 13998 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5 0x37b3 13999 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 14000 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6 0x37b4 14001 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 14002 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7 0x37b5 14003 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 14004 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8 0x37b6 14005 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 14006 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9 0x37b7 14007 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 14008 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10 0x37b8 14009 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 14010 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS 0x37b9 14011 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 14012 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_DEFAULT_OVERRIDE0 0x37ba 14013 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_DEFAULT_OVERRIDE0_BASE_IDX 2 14014 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0 0x37bc 14015 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX 2 14016 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1 0x37bd 14017 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX 2 14018 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL 0x37be 14019 #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX 2 14020 14021 14022 // addressBlock: dcn_dcec_hpo_dp_link_enc2_dispdec 14023 // base address: 0x1b41c 14024 #define regDP_LINK_ENC2_DP_LINK_ENC_CLOCK_CONTROL 0x3847 14025 #define regDP_LINK_ENC2_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 14026 #define regDP_LINK_ENC2_DP_LINK_ENC_SPARE 0x3848 14027 #define regDP_LINK_ENC2_DP_LINK_ENC_SPARE_BASE_IDX 2 14028 14029 14030 // addressBlock: dcn_dcec_hpo_dp_dphy_sym322_dispdec 14031 // base address: 0x1b470 14032 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL 0x385c 14033 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 14034 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_STATUS 0x385d 14035 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_STATUS_BASE_IDX 2 14036 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_ENCRYPT_CONFIG0 0x385e 14037 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_ENCRYPT_CONFIG0_BASE_IDX 2 14038 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_ENCRYPT_CONFIG1 0x385f 14039 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_ENCRYPT_CONFIG1_BASE_IDX 2 14040 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_UPDATE 0x3860 14041 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 14042 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL0 0x3861 14043 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 14044 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL1 0x3862 14045 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 14046 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL2 0x3863 14047 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 14048 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL3 0x3864 14049 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 14050 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL4 0x3865 14051 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL4_BASE_IDX 2 14052 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL5 0x3866 14053 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL5_BASE_IDX 2 14054 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC0 0x3867 14055 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 14056 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC1 0x3868 14057 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 14058 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC2 0x3869 14059 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 14060 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC3 0x386a 14061 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 14062 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC4 0x386b 14063 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC4_BASE_IDX 2 14064 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC5 0x386c 14065 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC5_BASE_IDX 2 14066 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS0 0x386d 14067 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 14068 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS1 0x386e 14069 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 14070 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS2 0x386f 14071 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 14072 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS3 0x3870 14073 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 14074 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS4 0x3871 14075 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS4_BASE_IDX 2 14076 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS5 0x3872 14077 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS5_BASE_IDX 2 14078 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_CONFIG0 0x3873 14079 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_CONFIG0_BASE_IDX 2 14080 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR0 0x3874 14081 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR0_BASE_IDX 2 14082 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR1 0x3875 14083 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR1_BASE_IDX 2 14084 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR2 0x3876 14085 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR2_BASE_IDX 2 14086 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR3 0x3877 14087 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR3_BASE_IDX 2 14088 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0 0x3878 14089 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0_BASE_IDX 2 14090 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0 0x3879 14091 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0_BASE_IDX 2 14092 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1 0x387a 14093 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1_BASE_IDX 2 14094 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_CONTROL 0x387b 14095 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_CONTROL_BASE_IDX 2 14096 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG 0x387c 14097 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 14098 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED0 0x387d 14099 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 14100 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED1 0x387e 14101 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 14102 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED2 0x387f 14103 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 14104 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED3 0x3880 14105 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 14106 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_SQ_PULSE 0x3881 14107 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 14108 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM0 0x3882 14109 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 14110 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM1 0x3883 14111 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 14112 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM2 0x3884 14113 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 14114 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM3 0x3885 14115 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 14116 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM4 0x3886 14117 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 14118 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM5 0x3887 14119 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 14120 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM6 0x3888 14121 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 14122 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM7 0x3889 14123 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 14124 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM8 0x388a 14125 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 14126 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM9 0x388b 14127 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 14128 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM10 0x388c 14129 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 14130 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS 0x388d 14131 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 14132 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_DEFAULT_OVERRIDE0 0x388e 14133 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_DEFAULT_OVERRIDE0_BASE_IDX 2 14134 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0 0x3890 14135 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX 2 14136 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1 0x3891 14137 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX 2 14138 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL 0x3892 14139 #define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX 2 14140 14141 14142 // addressBlock: dcn_dcec_hpo_dp_link_enc3_dispdec 14143 // base address: 0x1b76c 14144 #define regDP_LINK_ENC3_DP_LINK_ENC_CLOCK_CONTROL 0x391b 14145 #define regDP_LINK_ENC3_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 14146 #define regDP_LINK_ENC3_DP_LINK_ENC_SPARE 0x391c 14147 #define regDP_LINK_ENC3_DP_LINK_ENC_SPARE_BASE_IDX 2 14148 14149 14150 // addressBlock: dcn_dcec_hpo_dp_dphy_sym323_dispdec 14151 // base address: 0x1b7c0 14152 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL 0x3930 14153 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 14154 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_STATUS 0x3931 14155 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_STATUS_BASE_IDX 2 14156 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_ENCRYPT_CONFIG0 0x3932 14157 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_ENCRYPT_CONFIG0_BASE_IDX 2 14158 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_ENCRYPT_CONFIG1 0x3933 14159 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_ENCRYPT_CONFIG1_BASE_IDX 2 14160 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_UPDATE 0x3934 14161 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 14162 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL0 0x3935 14163 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 14164 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL1 0x3936 14165 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 14166 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL2 0x3937 14167 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 14168 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL3 0x3938 14169 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 14170 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL4 0x3939 14171 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL4_BASE_IDX 2 14172 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL5 0x393a 14173 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL5_BASE_IDX 2 14174 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC0 0x393b 14175 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 14176 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC1 0x393c 14177 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 14178 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC2 0x393d 14179 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 14180 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC3 0x393e 14181 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 14182 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC4 0x393f 14183 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC4_BASE_IDX 2 14184 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC5 0x3940 14185 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC5_BASE_IDX 2 14186 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS0 0x3941 14187 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 14188 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS1 0x3942 14189 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 14190 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS2 0x3943 14191 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 14192 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS3 0x3944 14193 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 14194 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS4 0x3945 14195 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS4_BASE_IDX 2 14196 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS5 0x3946 14197 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS5_BASE_IDX 2 14198 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_CONFIG0 0x3947 14199 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_CONFIG0_BASE_IDX 2 14200 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR0 0x3948 14201 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR0_BASE_IDX 2 14202 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR1 0x3949 14203 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR1_BASE_IDX 2 14204 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR2 0x394a 14205 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR2_BASE_IDX 2 14206 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR3 0x394b 14207 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR3_BASE_IDX 2 14208 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0 0x394c 14209 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0_BASE_IDX 2 14210 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0 0x394d 14211 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0_BASE_IDX 2 14212 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1 0x394e 14213 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_WAKE_CONFIG1_BASE_IDX 2 14214 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_CONTROL 0x394f 14215 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_CONTROL_BASE_IDX 2 14216 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG 0x3950 14217 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 14218 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED0 0x3951 14219 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 14220 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED1 0x3952 14221 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 14222 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED2 0x3953 14223 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 14224 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED3 0x3954 14225 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 14226 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_SQ_PULSE 0x3955 14227 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 14228 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM0 0x3956 14229 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 14230 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM1 0x3957 14231 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 14232 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM2 0x3958 14233 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 14234 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM3 0x3959 14235 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 14236 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM4 0x395a 14237 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 14238 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM5 0x395b 14239 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 14240 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM6 0x395c 14241 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 14242 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM7 0x395d 14243 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 14244 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM8 0x395e 14245 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 14246 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM9 0x395f 14247 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 14248 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM10 0x3960 14249 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 14250 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS 0x3961 14251 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 14252 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_DEFAULT_OVERRIDE0 0x3962 14253 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_DEFAULT_OVERRIDE0_BASE_IDX 2 14254 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0 0x3964 14255 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX 2 14256 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1 0x3965 14257 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX 2 14258 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL 0x3966 14259 #define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX 2 14260 14261 14262 // addressBlock: dcn_dcec_dlpc_dlpc_dispdec 14263 // base address: 0x0 14264 #define regDLPC_ENABLE 0x2fe8 14265 #define regDLPC_ENABLE_BASE_IDX 2 14266 #define regDLPC_CURRENT_COUNT 0x2fe9 14267 #define regDLPC_CURRENT_COUNT_BASE_IDX 2 14268 #define regDLPC_OPTC_SNAPSHOT 0x2fea 14269 #define regDLPC_OPTC_SNAPSHOT_BASE_IDX 2 14270 #define regDLPC_PWRUP 0x2feb 14271 #define regDLPC_PWRUP_BASE_IDX 2 14272 #define regDLPC_OTG_RESYNC 0x2fec 14273 #define regDLPC_OTG_RESYNC_BASE_IDX 2 14274 #define regDLPC_DCN_ZSC_LONO_PWRUP 0x2fed 14275 #define regDLPC_DCN_ZSC_LONO_PWRUP_BASE_IDX 2 14276 #define regDLPC_SPARE 0x2fee 14277 #define regDLPC_SPARE_BASE_IDX 2 14278 #define regDLPC_COUNTER_INIT_VALUE 0x2fef 14279 #define regDLPC_COUNTER_INIT_VALUE_BASE_IDX 2 14280 14281 14282 // addressBlock: dcn_dpcssys_dpcssys_cr0_dispdec 14283 // base address: 0x0 14284 #define regDPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934 14285 #define regDPCSSYS_CR0_DPCSSYS_CR_ADDR_BASE_IDX 2 14286 #define regDPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935 14287 #define regDPCSSYS_CR0_DPCSSYS_CR_DATA_BASE_IDX 2 14288 14289 14290 // addressBlock: dcn_dpcssys_dpcssys_cr1_dispdec 14291 // base address: 0x360 14292 #define regDPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c 14293 #define regDPCSSYS_CR1_DPCSSYS_CR_ADDR_BASE_IDX 2 14294 #define regDPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d 14295 #define regDPCSSYS_CR1_DPCSSYS_CR_DATA_BASE_IDX 2 14296 14297 14298 // addressBlock: dcn_dpcssys_dpcssys_cr2_dispdec 14299 // base address: 0x6c0 14300 #define regDPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4 14301 #define regDPCSSYS_CR2_DPCSSYS_CR_ADDR_BASE_IDX 2 14302 #define regDPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5 14303 #define regDPCSSYS_CR2_DPCSSYS_CR_DATA_BASE_IDX 2 14304 14305 14306 // addressBlock: dcn_dpcssys_dpcssys_cr3_dispdec 14307 // base address: 0xa20 14308 #define regDPCSSYS_CR3_DPCSSYS_CR_ADDR 0x2bbc 14309 #define regDPCSSYS_CR3_DPCSSYS_CR_ADDR_BASE_IDX 2 14310 #define regDPCSSYS_CR3_DPCSSYS_CR_DATA 0x2bbd 14311 #define regDPCSSYS_CR3_DPCSSYS_CR_DATA_BASE_IDX 2 14312 14313 14314 // addressBlock: dcn_dpcssys_dpcs0_rdpcstx0_dispdec 14315 // base address: 0x0 14316 #define regRDPCSTX0_RDPCSTX_CNTL 0x2930 14317 #define regRDPCSTX0_RDPCSTX_CNTL_BASE_IDX 2 14318 #define regRDPCSTX0_RDPCSTX_CLOCK_CNTL 0x2931 14319 #define regRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 14320 #define regRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL 0x2932 14321 #define regRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 14322 #define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA 0x2933 14323 #define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX 2 14324 #define regRDPCSTX0_RDPCS_TX_CR_ADDR 0x2934 14325 #define regRDPCSTX0_RDPCS_TX_CR_ADDR_BASE_IDX 2 14326 #define regRDPCSTX0_RDPCS_TX_CR_DATA 0x2935 14327 #define regRDPCSTX0_RDPCS_TX_CR_DATA_BASE_IDX 2 14328 #define regRDPCSTX0_RDPCS_TX_SRAM_CNTL 0x2936 14329 #define regRDPCSTX0_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 14330 #define regRDPCSTX0_RDPCSTX_SCRATCH0 0x2937 14331 #define regRDPCSTX0_RDPCSTX_SCRATCH0_BASE_IDX 2 14332 #define regRDPCSTX0_RDPCSTX_SPARE 0x2938 14333 #define regRDPCSTX0_RDPCSTX_SPARE_BASE_IDX 2 14334 #define regRDPCSTX0_RDPCSTX_CNTL2 0x2939 14335 #define regRDPCSTX0_RDPCSTX_CNTL2_BASE_IDX 2 14336 #define regRDPCSTX0_RDPCSTX_DPALT_CNTL_SPARE 0x293a 14337 #define regRDPCSTX0_RDPCSTX_DPALT_CNTL_SPARE_BASE_IDX 2 14338 #define regRDPCSTX0_RDPCSTX_PATTERN_DETECT_CTRL 0x293b 14339 #define regRDPCSTX0_RDPCSTX_PATTERN_DETECT_CTRL_BASE_IDX 2 14340 #define regRDPCSTX0_RDPCSTX_CNTL4 0x293c 14341 #define regRDPCSTX0_RDPCSTX_CNTL4_BASE_IDX 2 14342 #define regRDPCSTX0_RDPCSTX_DEBUG_CONFIG 0x293d 14343 #define regRDPCSTX0_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 14344 #define regRDPCSTX0_RDPCSTX_PHY_CNTL0 0x2940 14345 #define regRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX 2 14346 #define regRDPCSTX0_RDPCSTX_PHY_CNTL1 0x2941 14347 #define regRDPCSTX0_RDPCSTX_PHY_CNTL1_BASE_IDX 2 14348 #define regRDPCSTX0_RDPCSTX_PHY_CNTL2 0x2942 14349 #define regRDPCSTX0_RDPCSTX_PHY_CNTL2_BASE_IDX 2 14350 #define regRDPCSTX0_RDPCSTX_PHY_CNTL3 0x2943 14351 #define regRDPCSTX0_RDPCSTX_PHY_CNTL3_BASE_IDX 2 14352 #define regRDPCSTX0_RDPCSTX_PHY_CNTL4 0x2944 14353 #define regRDPCSTX0_RDPCSTX_PHY_CNTL4_BASE_IDX 2 14354 #define regRDPCSTX0_RDPCSTX_PHY_CNTL5 0x2945 14355 #define regRDPCSTX0_RDPCSTX_PHY_CNTL5_BASE_IDX 2 14356 #define regRDPCSTX0_RDPCSTX_PHY_CNTL6 0x2946 14357 #define regRDPCSTX0_RDPCSTX_PHY_CNTL6_BASE_IDX 2 14358 #define regRDPCSTX0_RDPCSTX_PHY_CNTL7 0x2947 14359 #define regRDPCSTX0_RDPCSTX_PHY_CNTL7_BASE_IDX 2 14360 #define regRDPCSTX0_RDPCSTX_PHY_CNTL8 0x2948 14361 #define regRDPCSTX0_RDPCSTX_PHY_CNTL8_BASE_IDX 2 14362 #define regRDPCSTX0_RDPCSTX_PHY_CNTL9 0x2949 14363 #define regRDPCSTX0_RDPCSTX_PHY_CNTL9_BASE_IDX 2 14364 #define regRDPCSTX0_RDPCSTX_PHY_CNTL10 0x294a 14365 #define regRDPCSTX0_RDPCSTX_PHY_CNTL10_BASE_IDX 2 14366 #define regRDPCSTX0_RDPCSTX_PHY_CNTL11 0x294b 14367 #define regRDPCSTX0_RDPCSTX_PHY_CNTL11_BASE_IDX 2 14368 #define regRDPCSTX0_RDPCSTX_PHY_CNTL12 0x294c 14369 #define regRDPCSTX0_RDPCSTX_PHY_CNTL12_BASE_IDX 2 14370 #define regRDPCSTX0_RDPCSTX_PHY_CNTL13 0x294d 14371 #define regRDPCSTX0_RDPCSTX_PHY_CNTL13_BASE_IDX 2 14372 #define regRDPCSTX0_RDPCSTX_PHY_CNTL14 0x294e 14373 #define regRDPCSTX0_RDPCSTX_PHY_CNTL14_BASE_IDX 2 14374 #define regRDPCSTX0_RDPCSTX_PHY_FUSE0 0x294f 14375 #define regRDPCSTX0_RDPCSTX_PHY_FUSE0_BASE_IDX 2 14376 #define regRDPCSTX0_RDPCSTX_PHY_FUSE1 0x2950 14377 #define regRDPCSTX0_RDPCSTX_PHY_FUSE1_BASE_IDX 2 14378 #define regRDPCSTX0_RDPCSTX_PHY_FUSE2 0x2951 14379 #define regRDPCSTX0_RDPCSTX_PHY_FUSE2_BASE_IDX 2 14380 #define regRDPCSTX0_RDPCSTX_PHY_FUSE3 0x2952 14381 #define regRDPCSTX0_RDPCSTX_PHY_FUSE3_BASE_IDX 2 14382 #define regRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL 0x2953 14383 #define regRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 14384 #define regRDPCSTX0_RDPCSTX_SCRATCH1 0x2954 14385 #define regRDPCSTX0_RDPCSTX_SCRATCH1_BASE_IDX 2 14386 #define regRDPCSTX0_RDPCSTX_SCRATCH2 0x2955 14387 #define regRDPCSTX0_RDPCSTX_SCRATCH2_BASE_IDX 2 14388 #define regRDPCSTX0_RDPCSTX_PHY_CNTL15 0x2958 14389 #define regRDPCSTX0_RDPCSTX_PHY_CNTL15_BASE_IDX 2 14390 #define regRDPCSTX0_RDPCSTX_PHY_CNTL16 0x2959 14391 #define regRDPCSTX0_RDPCSTX_PHY_CNTL16_BASE_IDX 2 14392 #define regRDPCSTX0_RDPCSTX_PHY_CNTL17 0x295a 14393 #define regRDPCSTX0_RDPCSTX_PHY_CNTL17_BASE_IDX 2 14394 #define regRDPCSTX0_RDPCSTX_DEBUG_CONFIG2 0x295b 14395 #define regRDPCSTX0_RDPCSTX_DEBUG_CONFIG2_BASE_IDX 2 14396 #define regRDPCSTX0_RDPCS_CNTL3 0x295c 14397 #define regRDPCSTX0_RDPCS_CNTL3_BASE_IDX 2 14398 #define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD 0x295d 14399 #define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX 2 14400 #define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD 0x295e 14401 #define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX 2 14402 14403 14404 // addressBlock: dcn_dpcssys_dpcs0_rdpcstx1_dispdec 14405 // base address: 0x360 14406 #define regRDPCSTX1_RDPCSTX_CNTL 0x2a08 14407 #define regRDPCSTX1_RDPCSTX_CNTL_BASE_IDX 2 14408 #define regRDPCSTX1_RDPCSTX_CLOCK_CNTL 0x2a09 14409 #define regRDPCSTX1_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 14410 #define regRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL 0x2a0a 14411 #define regRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 14412 #define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA 0x2a0b 14413 #define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX 2 14414 #define regRDPCSTX1_RDPCS_TX_CR_ADDR 0x2a0c 14415 #define regRDPCSTX1_RDPCS_TX_CR_ADDR_BASE_IDX 2 14416 #define regRDPCSTX1_RDPCS_TX_CR_DATA 0x2a0d 14417 #define regRDPCSTX1_RDPCS_TX_CR_DATA_BASE_IDX 2 14418 #define regRDPCSTX1_RDPCS_TX_SRAM_CNTL 0x2a0e 14419 #define regRDPCSTX1_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 14420 #define regRDPCSTX1_RDPCSTX_SCRATCH0 0x2a0f 14421 #define regRDPCSTX1_RDPCSTX_SCRATCH0_BASE_IDX 2 14422 #define regRDPCSTX1_RDPCSTX_SPARE 0x2a10 14423 #define regRDPCSTX1_RDPCSTX_SPARE_BASE_IDX 2 14424 #define regRDPCSTX1_RDPCSTX_CNTL2 0x2a11 14425 #define regRDPCSTX1_RDPCSTX_CNTL2_BASE_IDX 2 14426 #define regRDPCSTX1_RDPCSTX_DPALT_CNTL_SPARE 0x2a12 14427 #define regRDPCSTX1_RDPCSTX_DPALT_CNTL_SPARE_BASE_IDX 2 14428 #define regRDPCSTX1_RDPCSTX_PATTERN_DETECT_CTRL 0x2a13 14429 #define regRDPCSTX1_RDPCSTX_PATTERN_DETECT_CTRL_BASE_IDX 2 14430 #define regRDPCSTX1_RDPCSTX_CNTL4 0x2a14 14431 #define regRDPCSTX1_RDPCSTX_CNTL4_BASE_IDX 2 14432 #define regRDPCSTX1_RDPCSTX_DEBUG_CONFIG 0x2a15 14433 #define regRDPCSTX1_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 14434 #define regRDPCSTX1_RDPCSTX_PHY_CNTL0 0x2a18 14435 #define regRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX 2 14436 #define regRDPCSTX1_RDPCSTX_PHY_CNTL1 0x2a19 14437 #define regRDPCSTX1_RDPCSTX_PHY_CNTL1_BASE_IDX 2 14438 #define regRDPCSTX1_RDPCSTX_PHY_CNTL2 0x2a1a 14439 #define regRDPCSTX1_RDPCSTX_PHY_CNTL2_BASE_IDX 2 14440 #define regRDPCSTX1_RDPCSTX_PHY_CNTL3 0x2a1b 14441 #define regRDPCSTX1_RDPCSTX_PHY_CNTL3_BASE_IDX 2 14442 #define regRDPCSTX1_RDPCSTX_PHY_CNTL4 0x2a1c 14443 #define regRDPCSTX1_RDPCSTX_PHY_CNTL4_BASE_IDX 2 14444 #define regRDPCSTX1_RDPCSTX_PHY_CNTL5 0x2a1d 14445 #define regRDPCSTX1_RDPCSTX_PHY_CNTL5_BASE_IDX 2 14446 #define regRDPCSTX1_RDPCSTX_PHY_CNTL6 0x2a1e 14447 #define regRDPCSTX1_RDPCSTX_PHY_CNTL6_BASE_IDX 2 14448 #define regRDPCSTX1_RDPCSTX_PHY_CNTL7 0x2a1f 14449 #define regRDPCSTX1_RDPCSTX_PHY_CNTL7_BASE_IDX 2 14450 #define regRDPCSTX1_RDPCSTX_PHY_CNTL8 0x2a20 14451 #define regRDPCSTX1_RDPCSTX_PHY_CNTL8_BASE_IDX 2 14452 #define regRDPCSTX1_RDPCSTX_PHY_CNTL9 0x2a21 14453 #define regRDPCSTX1_RDPCSTX_PHY_CNTL9_BASE_IDX 2 14454 #define regRDPCSTX1_RDPCSTX_PHY_CNTL10 0x2a22 14455 #define regRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX 2 14456 #define regRDPCSTX1_RDPCSTX_PHY_CNTL11 0x2a23 14457 #define regRDPCSTX1_RDPCSTX_PHY_CNTL11_BASE_IDX 2 14458 #define regRDPCSTX1_RDPCSTX_PHY_CNTL12 0x2a24 14459 #define regRDPCSTX1_RDPCSTX_PHY_CNTL12_BASE_IDX 2 14460 #define regRDPCSTX1_RDPCSTX_PHY_CNTL13 0x2a25 14461 #define regRDPCSTX1_RDPCSTX_PHY_CNTL13_BASE_IDX 2 14462 #define regRDPCSTX1_RDPCSTX_PHY_CNTL14 0x2a26 14463 #define regRDPCSTX1_RDPCSTX_PHY_CNTL14_BASE_IDX 2 14464 #define regRDPCSTX1_RDPCSTX_PHY_FUSE0 0x2a27 14465 #define regRDPCSTX1_RDPCSTX_PHY_FUSE0_BASE_IDX 2 14466 #define regRDPCSTX1_RDPCSTX_PHY_FUSE1 0x2a28 14467 #define regRDPCSTX1_RDPCSTX_PHY_FUSE1_BASE_IDX 2 14468 #define regRDPCSTX1_RDPCSTX_PHY_FUSE2 0x2a29 14469 #define regRDPCSTX1_RDPCSTX_PHY_FUSE2_BASE_IDX 2 14470 #define regRDPCSTX1_RDPCSTX_PHY_FUSE3 0x2a2a 14471 #define regRDPCSTX1_RDPCSTX_PHY_FUSE3_BASE_IDX 2 14472 #define regRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL 0x2a2b 14473 #define regRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 14474 #define regRDPCSTX1_RDPCSTX_SCRATCH1 0x2a2c 14475 #define regRDPCSTX1_RDPCSTX_SCRATCH1_BASE_IDX 2 14476 #define regRDPCSTX1_RDPCSTX_SCRATCH2 0x2a2d 14477 #define regRDPCSTX1_RDPCSTX_SCRATCH2_BASE_IDX 2 14478 #define regRDPCSTX1_RDPCSTX_PHY_CNTL15 0x2a30 14479 #define regRDPCSTX1_RDPCSTX_PHY_CNTL15_BASE_IDX 2 14480 #define regRDPCSTX1_RDPCSTX_PHY_CNTL16 0x2a31 14481 #define regRDPCSTX1_RDPCSTX_PHY_CNTL16_BASE_IDX 2 14482 #define regRDPCSTX1_RDPCSTX_PHY_CNTL17 0x2a32 14483 #define regRDPCSTX1_RDPCSTX_PHY_CNTL17_BASE_IDX 2 14484 #define regRDPCSTX1_RDPCSTX_DEBUG_CONFIG2 0x2a33 14485 #define regRDPCSTX1_RDPCSTX_DEBUG_CONFIG2_BASE_IDX 2 14486 #define regRDPCSTX1_RDPCS_CNTL3 0x2a34 14487 #define regRDPCSTX1_RDPCS_CNTL3_BASE_IDX 2 14488 #define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD 0x2a35 14489 #define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX 2 14490 #define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD 0x2a36 14491 #define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX 2 14492 14493 14494 // addressBlock: dcn_dpcssys_dpcs0_rdpcstx2_dispdec 14495 // base address: 0x6c0 14496 #define regRDPCSTX2_RDPCSTX_CNTL 0x2ae0 14497 #define regRDPCSTX2_RDPCSTX_CNTL_BASE_IDX 2 14498 #define regRDPCSTX2_RDPCSTX_CLOCK_CNTL 0x2ae1 14499 #define regRDPCSTX2_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 14500 #define regRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL 0x2ae2 14501 #define regRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 14502 #define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA 0x2ae3 14503 #define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX 2 14504 #define regRDPCSTX2_RDPCS_TX_CR_ADDR 0x2ae4 14505 #define regRDPCSTX2_RDPCS_TX_CR_ADDR_BASE_IDX 2 14506 #define regRDPCSTX2_RDPCS_TX_CR_DATA 0x2ae5 14507 #define regRDPCSTX2_RDPCS_TX_CR_DATA_BASE_IDX 2 14508 #define regRDPCSTX2_RDPCS_TX_SRAM_CNTL 0x2ae6 14509 #define regRDPCSTX2_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 14510 #define regRDPCSTX2_RDPCSTX_SCRATCH0 0x2ae7 14511 #define regRDPCSTX2_RDPCSTX_SCRATCH0_BASE_IDX 2 14512 #define regRDPCSTX2_RDPCSTX_SPARE 0x2ae8 14513 #define regRDPCSTX2_RDPCSTX_SPARE_BASE_IDX 2 14514 #define regRDPCSTX2_RDPCSTX_CNTL2 0x2ae9 14515 #define regRDPCSTX2_RDPCSTX_CNTL2_BASE_IDX 2 14516 #define regRDPCSTX2_RDPCSTX_DPALT_CNTL_SPARE 0x2aea 14517 #define regRDPCSTX2_RDPCSTX_DPALT_CNTL_SPARE_BASE_IDX 2 14518 #define regRDPCSTX2_RDPCSTX_PATTERN_DETECT_CTRL 0x2aeb 14519 #define regRDPCSTX2_RDPCSTX_PATTERN_DETECT_CTRL_BASE_IDX 2 14520 #define regRDPCSTX2_RDPCSTX_CNTL4 0x2aec 14521 #define regRDPCSTX2_RDPCSTX_CNTL4_BASE_IDX 2 14522 #define regRDPCSTX2_RDPCSTX_DEBUG_CONFIG 0x2aed 14523 #define regRDPCSTX2_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 14524 #define regRDPCSTX2_RDPCSTX_PHY_CNTL0 0x2af0 14525 #define regRDPCSTX2_RDPCSTX_PHY_CNTL0_BASE_IDX 2 14526 #define regRDPCSTX2_RDPCSTX_PHY_CNTL1 0x2af1 14527 #define regRDPCSTX2_RDPCSTX_PHY_CNTL1_BASE_IDX 2 14528 #define regRDPCSTX2_RDPCSTX_PHY_CNTL2 0x2af2 14529 #define regRDPCSTX2_RDPCSTX_PHY_CNTL2_BASE_IDX 2 14530 #define regRDPCSTX2_RDPCSTX_PHY_CNTL3 0x2af3 14531 #define regRDPCSTX2_RDPCSTX_PHY_CNTL3_BASE_IDX 2 14532 #define regRDPCSTX2_RDPCSTX_PHY_CNTL4 0x2af4 14533 #define regRDPCSTX2_RDPCSTX_PHY_CNTL4_BASE_IDX 2 14534 #define regRDPCSTX2_RDPCSTX_PHY_CNTL5 0x2af5 14535 #define regRDPCSTX2_RDPCSTX_PHY_CNTL5_BASE_IDX 2 14536 #define regRDPCSTX2_RDPCSTX_PHY_CNTL6 0x2af6 14537 #define regRDPCSTX2_RDPCSTX_PHY_CNTL6_BASE_IDX 2 14538 #define regRDPCSTX2_RDPCSTX_PHY_CNTL7 0x2af7 14539 #define regRDPCSTX2_RDPCSTX_PHY_CNTL7_BASE_IDX 2 14540 #define regRDPCSTX2_RDPCSTX_PHY_CNTL8 0x2af8 14541 #define regRDPCSTX2_RDPCSTX_PHY_CNTL8_BASE_IDX 2 14542 #define regRDPCSTX2_RDPCSTX_PHY_CNTL9 0x2af9 14543 #define regRDPCSTX2_RDPCSTX_PHY_CNTL9_BASE_IDX 2 14544 #define regRDPCSTX2_RDPCSTX_PHY_CNTL10 0x2afa 14545 #define regRDPCSTX2_RDPCSTX_PHY_CNTL10_BASE_IDX 2 14546 #define regRDPCSTX2_RDPCSTX_PHY_CNTL11 0x2afb 14547 #define regRDPCSTX2_RDPCSTX_PHY_CNTL11_BASE_IDX 2 14548 #define regRDPCSTX2_RDPCSTX_PHY_CNTL12 0x2afc 14549 #define regRDPCSTX2_RDPCSTX_PHY_CNTL12_BASE_IDX 2 14550 #define regRDPCSTX2_RDPCSTX_PHY_CNTL13 0x2afd 14551 #define regRDPCSTX2_RDPCSTX_PHY_CNTL13_BASE_IDX 2 14552 #define regRDPCSTX2_RDPCSTX_PHY_CNTL14 0x2afe 14553 #define regRDPCSTX2_RDPCSTX_PHY_CNTL14_BASE_IDX 2 14554 #define regRDPCSTX2_RDPCSTX_PHY_FUSE0 0x2aff 14555 #define regRDPCSTX2_RDPCSTX_PHY_FUSE0_BASE_IDX 2 14556 #define regRDPCSTX2_RDPCSTX_PHY_FUSE1 0x2b00 14557 #define regRDPCSTX2_RDPCSTX_PHY_FUSE1_BASE_IDX 2 14558 #define regRDPCSTX2_RDPCSTX_PHY_FUSE2 0x2b01 14559 #define regRDPCSTX2_RDPCSTX_PHY_FUSE2_BASE_IDX 2 14560 #define regRDPCSTX2_RDPCSTX_PHY_FUSE3 0x2b02 14561 #define regRDPCSTX2_RDPCSTX_PHY_FUSE3_BASE_IDX 2 14562 #define regRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL 0x2b03 14563 #define regRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 14564 #define regRDPCSTX2_RDPCSTX_SCRATCH1 0x2b04 14565 #define regRDPCSTX2_RDPCSTX_SCRATCH1_BASE_IDX 2 14566 #define regRDPCSTX2_RDPCSTX_SCRATCH2 0x2b05 14567 #define regRDPCSTX2_RDPCSTX_SCRATCH2_BASE_IDX 2 14568 #define regRDPCSTX2_RDPCSTX_PHY_CNTL15 0x2b08 14569 #define regRDPCSTX2_RDPCSTX_PHY_CNTL15_BASE_IDX 2 14570 #define regRDPCSTX2_RDPCSTX_PHY_CNTL16 0x2b09 14571 #define regRDPCSTX2_RDPCSTX_PHY_CNTL16_BASE_IDX 2 14572 #define regRDPCSTX2_RDPCSTX_PHY_CNTL17 0x2b0a 14573 #define regRDPCSTX2_RDPCSTX_PHY_CNTL17_BASE_IDX 2 14574 #define regRDPCSTX2_RDPCSTX_DEBUG_CONFIG2 0x2b0b 14575 #define regRDPCSTX2_RDPCSTX_DEBUG_CONFIG2_BASE_IDX 2 14576 #define regRDPCSTX2_RDPCS_CNTL3 0x2b0c 14577 #define regRDPCSTX2_RDPCS_CNTL3_BASE_IDX 2 14578 #define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD 0x2b0d 14579 #define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX 2 14580 #define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD 0x2b0e 14581 #define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX 2 14582 14583 14584 // addressBlock: dcn_dpcssys_dpcs0_rdpcstx3_dispdec 14585 // base address: 0xa20 14586 #define regRDPCSTX3_RDPCSTX_CNTL 0x2bb8 14587 #define regRDPCSTX3_RDPCSTX_CNTL_BASE_IDX 2 14588 #define regRDPCSTX3_RDPCSTX_CLOCK_CNTL 0x2bb9 14589 #define regRDPCSTX3_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 14590 #define regRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL 0x2bba 14591 #define regRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 14592 #define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA 0x2bbb 14593 #define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX 2 14594 #define regRDPCSTX3_RDPCS_TX_CR_ADDR 0x2bbc 14595 #define regRDPCSTX3_RDPCS_TX_CR_ADDR_BASE_IDX 2 14596 #define regRDPCSTX3_RDPCS_TX_CR_DATA 0x2bbd 14597 #define regRDPCSTX3_RDPCS_TX_CR_DATA_BASE_IDX 2 14598 #define regRDPCSTX3_RDPCS_TX_SRAM_CNTL 0x2bbe 14599 #define regRDPCSTX3_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 14600 #define regRDPCSTX3_RDPCSTX_SCRATCH0 0x2bbf 14601 #define regRDPCSTX3_RDPCSTX_SCRATCH0_BASE_IDX 2 14602 #define regRDPCSTX3_RDPCSTX_SPARE 0x2bc0 14603 #define regRDPCSTX3_RDPCSTX_SPARE_BASE_IDX 2 14604 #define regRDPCSTX3_RDPCSTX_CNTL2 0x2bc1 14605 #define regRDPCSTX3_RDPCSTX_CNTL2_BASE_IDX 2 14606 #define regRDPCSTX3_RDPCSTX_DPALT_CNTL_SPARE 0x2bc2 14607 #define regRDPCSTX3_RDPCSTX_DPALT_CNTL_SPARE_BASE_IDX 2 14608 #define regRDPCSTX3_RDPCSTX_PATTERN_DETECT_CTRL 0x2bc3 14609 #define regRDPCSTX3_RDPCSTX_PATTERN_DETECT_CTRL_BASE_IDX 2 14610 #define regRDPCSTX3_RDPCSTX_CNTL4 0x2bc4 14611 #define regRDPCSTX3_RDPCSTX_CNTL4_BASE_IDX 2 14612 #define regRDPCSTX3_RDPCSTX_DEBUG_CONFIG 0x2bc5 14613 #define regRDPCSTX3_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 14614 #define regRDPCSTX3_RDPCSTX_PHY_CNTL0 0x2bc8 14615 #define regRDPCSTX3_RDPCSTX_PHY_CNTL0_BASE_IDX 2 14616 #define regRDPCSTX3_RDPCSTX_PHY_CNTL1 0x2bc9 14617 #define regRDPCSTX3_RDPCSTX_PHY_CNTL1_BASE_IDX 2 14618 #define regRDPCSTX3_RDPCSTX_PHY_CNTL2 0x2bca 14619 #define regRDPCSTX3_RDPCSTX_PHY_CNTL2_BASE_IDX 2 14620 #define regRDPCSTX3_RDPCSTX_PHY_CNTL3 0x2bcb 14621 #define regRDPCSTX3_RDPCSTX_PHY_CNTL3_BASE_IDX 2 14622 #define regRDPCSTX3_RDPCSTX_PHY_CNTL4 0x2bcc 14623 #define regRDPCSTX3_RDPCSTX_PHY_CNTL4_BASE_IDX 2 14624 #define regRDPCSTX3_RDPCSTX_PHY_CNTL5 0x2bcd 14625 #define regRDPCSTX3_RDPCSTX_PHY_CNTL5_BASE_IDX 2 14626 #define regRDPCSTX3_RDPCSTX_PHY_CNTL6 0x2bce 14627 #define regRDPCSTX3_RDPCSTX_PHY_CNTL6_BASE_IDX 2 14628 #define regRDPCSTX3_RDPCSTX_PHY_CNTL7 0x2bcf 14629 #define regRDPCSTX3_RDPCSTX_PHY_CNTL7_BASE_IDX 2 14630 #define regRDPCSTX3_RDPCSTX_PHY_CNTL8 0x2bd0 14631 #define regRDPCSTX3_RDPCSTX_PHY_CNTL8_BASE_IDX 2 14632 #define regRDPCSTX3_RDPCSTX_PHY_CNTL9 0x2bd1 14633 #define regRDPCSTX3_RDPCSTX_PHY_CNTL9_BASE_IDX 2 14634 #define regRDPCSTX3_RDPCSTX_PHY_CNTL10 0x2bd2 14635 #define regRDPCSTX3_RDPCSTX_PHY_CNTL10_BASE_IDX 2 14636 #define regRDPCSTX3_RDPCSTX_PHY_CNTL11 0x2bd3 14637 #define regRDPCSTX3_RDPCSTX_PHY_CNTL11_BASE_IDX 2 14638 #define regRDPCSTX3_RDPCSTX_PHY_CNTL12 0x2bd4 14639 #define regRDPCSTX3_RDPCSTX_PHY_CNTL12_BASE_IDX 2 14640 #define regRDPCSTX3_RDPCSTX_PHY_CNTL13 0x2bd5 14641 #define regRDPCSTX3_RDPCSTX_PHY_CNTL13_BASE_IDX 2 14642 #define regRDPCSTX3_RDPCSTX_PHY_CNTL14 0x2bd6 14643 #define regRDPCSTX3_RDPCSTX_PHY_CNTL14_BASE_IDX 2 14644 #define regRDPCSTX3_RDPCSTX_PHY_FUSE0 0x2bd7 14645 #define regRDPCSTX3_RDPCSTX_PHY_FUSE0_BASE_IDX 2 14646 #define regRDPCSTX3_RDPCSTX_PHY_FUSE1 0x2bd8 14647 #define regRDPCSTX3_RDPCSTX_PHY_FUSE1_BASE_IDX 2 14648 #define regRDPCSTX3_RDPCSTX_PHY_FUSE2 0x2bd9 14649 #define regRDPCSTX3_RDPCSTX_PHY_FUSE2_BASE_IDX 2 14650 #define regRDPCSTX3_RDPCSTX_PHY_FUSE3 0x2bda 14651 #define regRDPCSTX3_RDPCSTX_PHY_FUSE3_BASE_IDX 2 14652 #define regRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL 0x2bdb 14653 #define regRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 14654 #define regRDPCSTX3_RDPCSTX_SCRATCH1 0x2bdc 14655 #define regRDPCSTX3_RDPCSTX_SCRATCH1_BASE_IDX 2 14656 #define regRDPCSTX3_RDPCSTX_SCRATCH2 0x2bdd 14657 #define regRDPCSTX3_RDPCSTX_SCRATCH2_BASE_IDX 2 14658 #define regRDPCSTX3_RDPCSTX_PHY_CNTL15 0x2be0 14659 #define regRDPCSTX3_RDPCSTX_PHY_CNTL15_BASE_IDX 2 14660 #define regRDPCSTX3_RDPCSTX_PHY_CNTL16 0x2be1 14661 #define regRDPCSTX3_RDPCSTX_PHY_CNTL16_BASE_IDX 2 14662 #define regRDPCSTX3_RDPCSTX_PHY_CNTL17 0x2be2 14663 #define regRDPCSTX3_RDPCSTX_PHY_CNTL17_BASE_IDX 2 14664 #define regRDPCSTX3_RDPCSTX_DEBUG_CONFIG2 0x2be3 14665 #define regRDPCSTX3_RDPCSTX_DEBUG_CONFIG2_BASE_IDX 2 14666 #define regRDPCSTX3_RDPCS_CNTL3 0x2be4 14667 #define regRDPCSTX3_RDPCS_CNTL3_BASE_IDX 2 14668 #define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD 0x2be5 14669 #define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX 2 14670 #define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD 0x2be6 14671 #define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX 2 14672 14673 14674 // addressBlock: dcn_dcec_host_hda_azcontroller_azdec 14675 // base address: 0x0 14676 #define regAZCONTROLLER0_CORB_WRITE_POINTER 0x0000 14677 #define regAZCONTROLLER0_CORB_WRITE_POINTER_BASE_IDX 0 14678 #define regAZCONTROLLER0_CORB_READ_POINTER 0x0000 14679 #define regAZCONTROLLER0_CORB_READ_POINTER_BASE_IDX 0 14680 #define regAZCONTROLLER0_CORB_CONTROL 0x0001 14681 #define regAZCONTROLLER0_CORB_CONTROL_BASE_IDX 0 14682 #define regAZCONTROLLER0_CORB_STATUS 0x0001 14683 #define regAZCONTROLLER0_CORB_STATUS_BASE_IDX 0 14684 #define regAZCONTROLLER0_CORB_SIZE 0x0001 14685 #define regAZCONTROLLER0_CORB_SIZE_BASE_IDX 0 14686 #define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS 0x0002 14687 #define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS_BASE_IDX 0 14688 #define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS 0x0003 14689 #define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS_BASE_IDX 0 14690 #define regAZCONTROLLER0_RIRB_WRITE_POINTER 0x0004 14691 #define regAZCONTROLLER0_RIRB_WRITE_POINTER_BASE_IDX 0 14692 #define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT 0x0004 14693 #define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT_BASE_IDX 0 14694 #define regAZCONTROLLER0_RIRB_CONTROL 0x0005 14695 #define regAZCONTROLLER0_RIRB_CONTROL_BASE_IDX 0 14696 #define regAZCONTROLLER0_RIRB_STATUS 0x0005 14697 #define regAZCONTROLLER0_RIRB_STATUS_BASE_IDX 0 14698 #define regAZCONTROLLER0_RIRB_SIZE 0x0005 14699 #define regAZCONTROLLER0_RIRB_SIZE_BASE_IDX 0 14700 #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006 14701 #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0 14702 #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 14703 #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 14704 #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 14705 #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 14706 #define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007 14707 #define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0 14708 #define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS 0x0008 14709 #define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS_BASE_IDX 0 14710 #define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS 0x000a 14711 #define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0 14712 #define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS 0x000b 14713 #define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0 14714 #define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS 0x074c 14715 #define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1 14716 14717 14718 // addressBlock: dcn_dcec_host_hda_azendpoint_azdec 14719 // base address: 0x0 14720 #define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 14721 #define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 14722 #define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 14723 #define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 14724 14725 14726 // addressBlock: dcn_dcec_host_hda_azinputendpoint_azdec 14727 // base address: 0x0 14728 #define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006 14729 #define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0 14730 #define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006 14731 #define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0 14732 14733 14734 // addressBlock: dcn_dcec_host_hda_azroot_azdec 14735 // base address: 0x0 14736 #define regAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 14737 #define regAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 14738 #define regAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 14739 #define regAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 14740 14741 14742 // addressBlock: dcn_dcec_host_hda_azstream0_azdec 14743 // base address: 0x0 14744 #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x000e 14745 #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 14746 #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x000f 14747 #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 14748 #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0010 14749 #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 14750 #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0011 14751 #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 14752 #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0012 14753 #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 14754 #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0012 14755 #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 14756 #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0014 14757 #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 14758 #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0015 14759 #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 14760 #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0761 14761 #define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 14762 14763 14764 // addressBlock: dcn_dcec_host_hda_azstream1_azdec 14765 // base address: 0x20 14766 #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0016 14767 #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 14768 #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0017 14769 #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 14770 #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0018 14771 #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 14772 #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0019 14773 #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 14774 #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x001a 14775 #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 14776 #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x001a 14777 #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 14778 #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x001c 14779 #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 14780 #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x001d 14781 #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 14782 #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0769 14783 #define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 14784 14785 14786 // addressBlock: dcn_dcec_host_hda_azstream2_azdec 14787 // base address: 0x40 14788 #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x001e 14789 #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 14790 #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x001f 14791 #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 14792 #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0020 14793 #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 14794 #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0021 14795 #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 14796 #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0022 14797 #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 14798 #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0022 14799 #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 14800 #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0024 14801 #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 14802 #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0025 14803 #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 14804 #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0771 14805 #define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 14806 14807 14808 // addressBlock: dcn_dcec_host_hda_azstream3_azdec 14809 // base address: 0x60 14810 #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0026 14811 #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 14812 #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0027 14813 #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 14814 #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0028 14815 #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 14816 #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0029 14817 #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 14818 #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x002a 14819 #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 14820 #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x002a 14821 #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 14822 #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x002c 14823 #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 14824 #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x002d 14825 #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 14826 #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0779 14827 #define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 14828 14829 14830 // addressBlock: dcn_dcec_host_hda_azstream4_azdec 14831 // base address: 0x80 14832 #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x002e 14833 #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 14834 #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x002f 14835 #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 14836 #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0030 14837 #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 14838 #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0031 14839 #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 14840 #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0032 14841 #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 14842 #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0032 14843 #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 14844 #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0034 14845 #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 14846 #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0035 14847 #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 14848 #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0781 14849 #define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 14850 14851 14852 // addressBlock: dcn_dcec_host_hda_azstream5_azdec 14853 // base address: 0xa0 14854 #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0036 14855 #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 14856 #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0037 14857 #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 14858 #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0038 14859 #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 14860 #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0039 14861 #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 14862 #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x003a 14863 #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 14864 #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x003a 14865 #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 14866 #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x003c 14867 #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 14868 #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x003d 14869 #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 14870 #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0789 14871 #define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 14872 14873 14874 // addressBlock: dcn_dcec_host_hda_azstream6_azdec 14875 // base address: 0xc0 14876 #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x003e 14877 #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 14878 #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x003f 14879 #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 14880 #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0040 14881 #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 14882 #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0041 14883 #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 14884 #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0042 14885 #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 14886 #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0042 14887 #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 14888 #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0044 14889 #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 14890 #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0045 14891 #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 14892 #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0791 14893 #define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 14894 14895 14896 // addressBlock: dcn_dcec_host_hda_azstream7_azdec 14897 // base address: 0xe0 14898 #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0046 14899 #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 14900 #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0047 14901 #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 14902 #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0048 14903 #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 14904 #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0049 14905 #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 14906 #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x004a 14907 #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 14908 #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x004a 14909 #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 14910 #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x004c 14911 #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 14912 #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x004d 14913 #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 14914 #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0799 14915 #define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 14916 14917 14918 // addressBlock: dcn_dcec_hda_azcontroller_azdec 14919 // base address: 0x1300000 14920 #define regGLOBAL_CAPABILITIES 0x4b7000 14921 #define regGLOBAL_CAPABILITIES_BASE_IDX 3 14922 #define regMINOR_VERSION 0x4b7000 14923 #define regMINOR_VERSION_BASE_IDX 3 14924 #define regMAJOR_VERSION 0x4b7000 14925 #define regMAJOR_VERSION_BASE_IDX 3 14926 #define regOUTPUT_PAYLOAD_CAPABILITY 0x4b7001 14927 #define regOUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 3 14928 #define regINPUT_PAYLOAD_CAPABILITY 0x4b7001 14929 #define regINPUT_PAYLOAD_CAPABILITY_BASE_IDX 3 14930 #define regGLOBAL_CONTROL 0x4b7002 14931 #define regGLOBAL_CONTROL_BASE_IDX 3 14932 #define regWAKE_ENABLE 0x4b7003 14933 #define regWAKE_ENABLE_BASE_IDX 3 14934 #define regSTATE_CHANGE_STATUS 0x4b7003 14935 #define regSTATE_CHANGE_STATUS_BASE_IDX 3 14936 #define regGLOBAL_STATUS 0x4b7004 14937 #define regGLOBAL_STATUS_BASE_IDX 3 14938 #define regOUTPUT_STREAM_PAYLOAD_CAPABILITY 0x4b7006 14939 #define regOUTPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX 3 14940 #define regINPUT_STREAM_PAYLOAD_CAPABILITY 0x4b7006 14941 #define regINPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX 3 14942 #define regINTERRUPT_CONTROL 0x4b7008 14943 #define regINTERRUPT_CONTROL_BASE_IDX 3 14944 #define regINTERRUPT_STATUS 0x4b7009 14945 #define regINTERRUPT_STATUS_BASE_IDX 3 14946 #define regWALL_CLOCK_COUNTER 0x4b700c 14947 #define regWALL_CLOCK_COUNTER_BASE_IDX 3 14948 #define regSTREAM_SYNCHRONIZATION 0x4b700e 14949 #define regSTREAM_SYNCHRONIZATION_BASE_IDX 3 14950 #define regCORB_LOWER_BASE_ADDRESS 0x4b7010 14951 #define regCORB_LOWER_BASE_ADDRESS_BASE_IDX 3 14952 #define regCORB_UPPER_BASE_ADDRESS 0x4b7011 14953 #define regCORB_UPPER_BASE_ADDRESS_BASE_IDX 3 14954 #define regAZCONTROLLER1_CORB_WRITE_POINTER 0x4b7012 14955 #define regAZCONTROLLER1_CORB_WRITE_POINTER_BASE_IDX 3 14956 #define regAZCONTROLLER1_CORB_READ_POINTER 0x4b7012 14957 #define regAZCONTROLLER1_CORB_READ_POINTER_BASE_IDX 3 14958 #define regAZCONTROLLER1_CORB_CONTROL 0x4b7013 14959 #define regAZCONTROLLER1_CORB_CONTROL_BASE_IDX 3 14960 #define regAZCONTROLLER1_CORB_STATUS 0x4b7013 14961 #define regAZCONTROLLER1_CORB_STATUS_BASE_IDX 3 14962 #define regAZCONTROLLER1_CORB_SIZE 0x4b7013 14963 #define regAZCONTROLLER1_CORB_SIZE_BASE_IDX 3 14964 #define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS 0x4b7014 14965 #define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS_BASE_IDX 3 14966 #define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS 0x4b7015 14967 #define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS_BASE_IDX 3 14968 #define regAZCONTROLLER1_RIRB_WRITE_POINTER 0x4b7016 14969 #define regAZCONTROLLER1_RIRB_WRITE_POINTER_BASE_IDX 3 14970 #define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT 0x4b7016 14971 #define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT_BASE_IDX 3 14972 #define regAZCONTROLLER1_RIRB_CONTROL 0x4b7017 14973 #define regAZCONTROLLER1_RIRB_CONTROL_BASE_IDX 3 14974 #define regAZCONTROLLER1_RIRB_STATUS 0x4b7017 14975 #define regAZCONTROLLER1_RIRB_STATUS_BASE_IDX 3 14976 #define regAZCONTROLLER1_RIRB_SIZE 0x4b7017 14977 #define regAZCONTROLLER1_RIRB_SIZE_BASE_IDX 3 14978 #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x4b7018 14979 #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 3 14980 #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x4b7018 14981 #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 3 14982 #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x4b7018 14983 #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 3 14984 #define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE 0x4b7019 14985 #define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 3 14986 #define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS 0x4b701a 14987 #define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS_BASE_IDX 3 14988 #define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS 0x4b701c 14989 #define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 3 14990 #define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS 0x4b701d 14991 #define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 3 14992 #define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS 0x4b780c 14993 #define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX 3 14994 14995 14996 // addressBlock: dcn_dcec_hda_azendpoint_azdec 14997 // base address: 0x1300000 14998 #define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x4b7018 14999 #define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 3 15000 #define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x4b7018 15001 #define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 3 15002 15003 15004 // addressBlock: dcn_dcec_hda_azinputendpoint_azdec 15005 // base address: 0x1300000 15006 #define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x4b7018 15007 #define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 3 15008 #define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x4b7018 15009 #define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 3 15010 15011 15012 // addressBlock: dcn_dcec_hda_azroot_azdec 15013 // base address: 0x1300000 15014 #define regAZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x4b7018 15015 #define regAZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 3 15016 #define regAZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x4b7018 15017 #define regAZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 3 15018 15019 15020 // addressBlock: dcn_dcec_hda_azstream0_azdec 15021 // base address: 0x1300000 15022 #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7020 15023 #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3 15024 #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7021 15025 #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3 15026 #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b7022 15027 #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3 15028 #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b7023 15029 #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3 15030 #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b7024 15031 #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3 15032 #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b7024 15033 #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3 15034 #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b7026 15035 #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3 15036 #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b7027 15037 #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3 15038 #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7821 15039 #define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3 15040 15041 15042 // addressBlock: dcn_dcec_hda_azstream1_azdec 15043 // base address: 0x1300020 15044 #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7028 15045 #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3 15046 #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7029 15047 #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3 15048 #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b702a 15049 #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3 15050 #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b702b 15051 #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3 15052 #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b702c 15053 #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3 15054 #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b702c 15055 #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3 15056 #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b702e 15057 #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3 15058 #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b702f 15059 #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3 15060 #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7829 15061 #define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3 15062 15063 15064 // addressBlock: dcn_dcec_hda_azstream2_azdec 15065 // base address: 0x1300040 15066 #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7030 15067 #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3 15068 #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7031 15069 #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3 15070 #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b7032 15071 #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3 15072 #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b7033 15073 #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3 15074 #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b7034 15075 #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3 15076 #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b7034 15077 #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3 15078 #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b7036 15079 #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3 15080 #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b7037 15081 #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3 15082 #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7831 15083 #define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3 15084 15085 15086 // addressBlock: dcn_dcec_hda_azstream3_azdec 15087 // base address: 0x1300060 15088 #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7038 15089 #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3 15090 #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7039 15091 #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3 15092 #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b703a 15093 #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3 15094 #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b703b 15095 #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3 15096 #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b703c 15097 #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3 15098 #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b703c 15099 #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3 15100 #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b703e 15101 #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3 15102 #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b703f 15103 #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3 15104 #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7839 15105 #define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3 15106 15107 15108 // addressBlock: dcn_dcec_hda_azstream4_azdec 15109 // base address: 0x1300080 15110 #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7040 15111 #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3 15112 #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7041 15113 #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3 15114 #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b7042 15115 #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3 15116 #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b7043 15117 #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3 15118 #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b7044 15119 #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3 15120 #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b7044 15121 #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3 15122 #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b7046 15123 #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3 15124 #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b7047 15125 #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3 15126 #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7841 15127 #define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3 15128 15129 15130 // addressBlock: dcn_dcec_hda_azstream5_azdec 15131 // base address: 0x13000a0 15132 #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7048 15133 #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3 15134 #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7049 15135 #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3 15136 #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b704a 15137 #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3 15138 #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b704b 15139 #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3 15140 #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b704c 15141 #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3 15142 #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b704c 15143 #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3 15144 #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b704e 15145 #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3 15146 #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b704f 15147 #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3 15148 #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7849 15149 #define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3 15150 15151 15152 // addressBlock: dcn_dcec_hda_azstream6_azdec 15153 // base address: 0x13000c0 15154 #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7050 15155 #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3 15156 #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7051 15157 #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3 15158 #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b7052 15159 #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3 15160 #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b7053 15161 #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3 15162 #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b7054 15163 #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3 15164 #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b7054 15165 #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3 15166 #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b7056 15167 #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3 15168 #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b7057 15169 #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3 15170 #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7851 15171 #define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3 15172 15173 15174 // addressBlock: dcn_dcec_hda_azstream7_azdec 15175 // base address: 0x13000e0 15176 #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7058 15177 #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3 15178 #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7059 15179 #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3 15180 #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b705a 15181 #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3 15182 #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b705b 15183 #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3 15184 #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b705c 15185 #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3 15186 #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b705c 15187 #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3 15188 #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b705e 15189 #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3 15190 #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b705f 15191 #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3 15192 #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7859 15193 #define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3 15194 15195 15196 // addressBlock: dcn_dcec_dio_hdcp1kp_pkdbdec 15197 // base address: 0x32000000 15198 15199 15200 // addressBlock: cnvc_cfg_cnvc_cfgdebugind 15201 // base address: 0x0 15202 #define ixID2_CNVC_FLOW_CONTROL 0x0002 15203 #define ixID4_CNVC_FLOW_CONTROL_2 0x0004 15204 #define ixID5_CNVC_REG_TO_FP_INPUT 0x0005 15205 #define ixID6_CNVC_REG_TO_FP_OUTPUT_UPPER_0 0x0006 15206 #define ixID7_CNVC_REG_TO_FP_OUTPUT_LOWER_0 0x0007 15207 #define ixID8_CNVC_REG_TO_FP_OUTPUT_UPPER_1 0x0008 15208 #define ixID9_CNVC_REG_TO_FP_OUTPUT_LOWER_1 0x0009 15209 15210 15211 // addressBlock: cm_cmdebugind 15212 // base address: 0x0 15213 #define ixID1_CM_FLOW_CONTROL 0x0001 15214 #define ixID2_CM_BYPASS 0x0002 15215 #define ixID3_CM_REG_TO_FP_CSC_INPUT 0x0003 15216 #define ixID4_CM_REG_TO_FP_CSC_OUTPUT_UPPER_0 0x0004 15217 #define ixID5_CM_REG_TO_FP_CSC_OUTPUT_LOWER_0 0x0005 15218 #define ixID6_CM_REG_TO_FP_BIAS_INPUT 0x0006 15219 #define ixID7_CM_REG_TO_FP_BIAS_OUTPUT_UPPER_0 0x0007 15220 #define ixID8_CM_REG_TO_FP_BIAS_OUTPUT_LOWER_0 0x0008 15221 #define ixID9_CM_STATUS 0x0009 15222 #define ixIDA_CM_REG_TO_FP_CSC_OUTPUT_UPPER_1 0x000a 15223 #define ixIDB_CM_REG_TO_FP_CSC_OUTPUT_LOWER_1 0x000b 15224 #define ixIDC_CM_REG_TO_FP_BIAS_OUTPUT_UPPER_1 0x000c 15225 #define ixIDD_CM_REG_TO_FP_BIAS_OUTPUT_LOWER_1 0x000d 15226 15227 15228 // addressBlock: mcif_wb0_mcif_wbdebugind 15229 // base address: 0x0 15230 #define ixID01_WB_FMT_DBG 0x0001 15231 #define ixID02_WB_FMT_DBG 0x0002 15232 #define ixID03_WB_FMT_DBG 0x0003 15233 #define ixID04_WB_MGR_DBG 0x0004 15234 #define ixID05_WB_MGR_DBG 0x0005 15235 #define ixID06_WB_MGR_DBG 0x0006 15236 #define ixID07_WB_MGR_DBG 0x0007 15237 #define ixID08_WB_ARB_DBG 0x0008 15238 #define ixID09_WB_ARB_DBG 0x0009 15239 #define ixID0A_WB_ARB_DBG 0x000a 15240 #define ixID0B_WB_ARB_DBG 0x000b 15241 #define ixID0C_WB_ARB_DBG 0x000c 15242 #define ixID0D_WB_ARB_DBG 0x000d 15243 #define ixID0E_WB_ARB_DBG 0x000e 15244 #define ixID0F_P010_WB_FMT_DBG_Y 0x000f 15245 #define ixID10_P010_WB_FMT_DBG_C 0x0010 15246 #define ixID11_WB_ARB_P010_DBG 0x0011 15247 #define ixID12_WB_ARB_P010_DBG 0x0012 15248 15249 15250 // addressBlock: mpc_ocsc_mpc_ocscdebugind 15251 // base address: 0x0 15252 #define ixID1_MPC_OUT0_CSC_MODE_DB 0x0001 15253 #define ixID2_MPC_OUT1_CSC_MODE_DB 0x0002 15254 #define ixID3_MPC_OUT2_CSC_MODE_DB 0x0003 15255 #define ixID4_MPC_OUT3_CSC_MODE_DB 0x0004 15256 15257 15258 // addressBlock: mpcc0_mpccdebugind 15259 // base address: 0x0 15260 #define ixMPCC0_ID01_MPCC_SEL_DB 0x0001 15261 #define ixMPCC0_ID02_MPCC_TOP_GAIN_DB 0x0002 15262 #define ixMPCC0_ID03_MPCC_BOT_GAIN_INSIDE_DB 0x0003 15263 #define ixMPCC0_ID04_MPCC_BOT_GAIN_OUTSIDE_DB 0x0004 15264 #define ixMPCC0_ID05_MPCC_BG_R_CR_DB 0x0005 15265 #define ixMPCC0_ID06_MPCC_BG_G_Y_DB 0x0006 15266 #define ixMPCC0_ID07_MPCC_BG_B_CB_DB 0x0007 15267 #define ixMPCC0_ID08_MPCC_CONTROL_DB 0x0008 15268 #define ixMPCC0_ID09_MPCC_SM_CONTROL_DB 0x0009 15269 #define ixMPCC0_ID17_MPCC_TOP_PIX 0x0011 15270 #define ixMPCC0_ID18_MPCC_recout_start 0x0012 15271 #define ixMPCC0_ID19_MPCC_recout_size 0x0013 15272 #define ixMPCC0_ID20_MPCC_mpc_size 0x0014 15273 #define ixMPCC0_ID21_MPCC_TOP_sideband 0x0015 15274 #define ixMPCC0_ID22_MPCC_BOT_PIX 0x0016 15275 #define ixMPCC0_ID23_MPCC_BOT_sideband 0x0017 15276 #define ixMPCC0_ID24_MPCC_OPP_PIX 0x0018 15277 #define ixMPCC0_ID25_MPCC_OPP_sideband 0x0019 15278 15279 15280 // addressBlock: mpcc1_mpccdebugind 15281 // base address: 0x0 15282 #define ixMPCC1_ID01_MPCC_SEL_DB 0x0001 15283 #define ixMPCC1_ID02_MPCC_TOP_GAIN_DB 0x0002 15284 #define ixMPCC1_ID03_MPCC_BOT_GAIN_INSIDE_DB 0x0003 15285 #define ixMPCC1_ID04_MPCC_BOT_GAIN_OUTSIDE_DB 0x0004 15286 #define ixMPCC1_ID05_MPCC_BG_R_CR_DB 0x0005 15287 #define ixMPCC1_ID06_MPCC_BG_G_Y_DB 0x0006 15288 #define ixMPCC1_ID07_MPCC_BG_B_CB_DB 0x0007 15289 #define ixMPCC1_ID08_MPCC_CONTROL_DB 0x0008 15290 #define ixMPCC1_ID09_MPCC_SM_CONTROL_DB 0x0009 15291 #define ixMPCC1_ID17_MPCC_TOP_PIX 0x0011 15292 #define ixMPCC1_ID18_MPCC_recout_start 0x0012 15293 #define ixMPCC1_ID19_MPCC_recout_size 0x0013 15294 #define ixMPCC1_ID20_MPCC_mpc_size 0x0014 15295 #define ixMPCC1_ID21_MPCC_TOP_sideband 0x0015 15296 #define ixMPCC1_ID22_MPCC_BOT_PIX 0x0016 15297 #define ixMPCC1_ID23_MPCC_BOT_sideband 0x0017 15298 #define ixMPCC1_ID24_MPCC_OPP_PIX 0x0018 15299 #define ixMPCC1_ID25_MPCC_OPP_sideband 0x0019 15300 15301 15302 // addressBlock: mpcc2_mpccdebugind 15303 // base address: 0x0 15304 #define ixMPCC2_ID01_MPCC_SEL_DB 0x0001 15305 #define ixMPCC2_ID02_MPCC_TOP_GAIN_DB 0x0002 15306 #define ixMPCC2_ID03_MPCC_BOT_GAIN_INSIDE_DB 0x0003 15307 #define ixMPCC2_ID04_MPCC_BOT_GAIN_OUTSIDE_DB 0x0004 15308 #define ixMPCC2_ID05_MPCC_BG_R_CR_DB 0x0005 15309 #define ixMPCC2_ID06_MPCC_BG_G_Y_DB 0x0006 15310 #define ixMPCC2_ID07_MPCC_BG_B_CB_DB 0x0007 15311 #define ixMPCC2_ID08_MPCC_CONTROL_DB 0x0008 15312 #define ixMPCC2_ID09_MPCC_SM_CONTROL_DB 0x0009 15313 #define ixMPCC2_ID17_MPCC_TOP_PIX 0x0011 15314 #define ixMPCC2_ID18_MPCC_recout_start 0x0012 15315 #define ixMPCC2_ID19_MPCC_recout_size 0x0013 15316 #define ixMPCC2_ID20_MPCC_mpc_size 0x0014 15317 #define ixMPCC2_ID21_MPCC_TOP_sideband 0x0015 15318 #define ixMPCC2_ID22_MPCC_BOT_PIX 0x0016 15319 #define ixMPCC2_ID23_MPCC_BOT_sideband 0x0017 15320 #define ixMPCC2_ID24_MPCC_OPP_PIX 0x0018 15321 #define ixMPCC2_ID25_MPCC_OPP_sideband 0x0019 15322 15323 15324 // addressBlock: mpcc3_mpccdebugind 15325 // base address: 0x0 15326 #define ixMPCC3_ID01_MPCC_SEL_DB 0x0001 15327 #define ixMPCC3_ID02_MPCC_TOP_GAIN_DB 0x0002 15328 #define ixMPCC3_ID03_MPCC_BOT_GAIN_INSIDE_DB 0x0003 15329 #define ixMPCC3_ID04_MPCC_BOT_GAIN_OUTSIDE_DB 0x0004 15330 #define ixMPCC3_ID05_MPCC_BG_R_CR_DB 0x0005 15331 #define ixMPCC3_ID06_MPCC_BG_G_Y_DB 0x0006 15332 #define ixMPCC3_ID07_MPCC_BG_B_CB_DB 0x0007 15333 #define ixMPCC3_ID08_MPCC_CONTROL_DB 0x0008 15334 #define ixMPCC3_ID09_MPCC_SM_CONTROL_DB 0x0009 15335 #define ixMPCC3_ID17_MPCC_TOP_PIX 0x0011 15336 #define ixMPCC3_ID18_MPCC_recout_start 0x0012 15337 #define ixMPCC3_ID19_MPCC_recout_size 0x0013 15338 #define ixMPCC3_ID20_MPCC_mpc_size 0x0014 15339 #define ixMPCC3_ID21_MPCC_TOP_sideband 0x0015 15340 #define ixMPCC3_ID22_MPCC_BOT_PIX 0x0016 15341 #define ixMPCC3_ID23_MPCC_BOT_sideband 0x0017 15342 #define ixMPCC3_ID24_MPCC_OPP_PIX 0x0018 15343 #define ixMPCC3_ID25_MPCC_OPP_sideband 0x0019 15344 15345 15346 // addressBlock: mpcc_ogam0_mpcc_ogamdebugind 15347 // base address: 0x0 15348 #define ixMPCC_OGAM0_ID01_MPCC_OGAM_CONTROL 0x0001 15349 15350 15351 // addressBlock: mpcc_mcm0_mpcc_mcmdebugind 15352 // base address: 0x0 15353 #define ixMPCC_MCM0_ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER 0x0008 15354 #define ixMPCC_MCM0_ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER 0x0009 15355 #define ixMPCC_MCM0_ID10_MPCC_MCM_R2F_3DLUT 0x000a 15356 #define ixMPCC_MCM0_ID11_MPCC_MCM_FIRST_GAMUT_REMAP 0x000b 15357 #define ixMPCC_MCM0_ID12_MPCC_MCM_SECOND_GAMUT_REMAP 0x000c 15358 15359 15360 // addressBlock: mpcc_ogam1_mpcc_ogamdebugind 15361 // base address: 0x0 15362 #define ixMPCC_OGAM1_ID01_MPCC_OGAM_CONTROL 0x0001 15363 15364 15365 // addressBlock: mpcc_mcm1_mpcc_mcmdebugind 15366 // base address: 0x0 15367 #define ixMPCC_MCM1_ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER 0x0008 15368 #define ixMPCC_MCM1_ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER 0x0009 15369 #define ixMPCC_MCM1_ID10_MPCC_MCM_R2F_3DLUT 0x000a 15370 #define ixMPCC_MCM1_ID11_MPCC_MCM_FIRST_GAMUT_REMAP 0x000b 15371 #define ixMPCC_MCM1_ID12_MPCC_MCM_SECOND_GAMUT_REMAP 0x000c 15372 15373 15374 // addressBlock: mpcc_ogam2_mpcc_ogamdebugind 15375 // base address: 0x0 15376 #define ixMPCC_OGAM2_ID01_MPCC_OGAM_CONTROL 0x0001 15377 15378 15379 // addressBlock: mpcc_mcm2_mpcc_mcmdebugind 15380 // base address: 0x0 15381 #define ixMPCC_MCM2_ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER 0x0008 15382 #define ixMPCC_MCM2_ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER 0x0009 15383 #define ixMPCC_MCM2_ID10_MPCC_MCM_R2F_3DLUT 0x000a 15384 #define ixMPCC_MCM2_ID11_MPCC_MCM_FIRST_GAMUT_REMAP 0x000b 15385 #define ixMPCC_MCM2_ID12_MPCC_MCM_SECOND_GAMUT_REMAP 0x000c 15386 15387 15388 // addressBlock: mpcc_ogam3_mpcc_ogamdebugind 15389 // base address: 0x0 15390 #define ixMPCC_OGAM3_ID01_MPCC_OGAM_CONTROL 0x0001 15391 15392 15393 // addressBlock: mpcc_mcm3_mpcc_mcmdebugind 15394 // base address: 0x0 15395 #define ixMPCC_MCM3_ID8_MPCC_MCM_R2F_3DLUT_FP_TO_FP_UPPER 0x0008 15396 #define ixMPCC_MCM3_ID9_MPCC_MCM_R2F_3DLUT_FP_TO_FP_LOWER 0x0009 15397 #define ixMPCC_MCM3_ID10_MPCC_MCM_R2F_3DLUT 0x000a 15398 #define ixMPCC_MCM3_ID11_MPCC_MCM_FIRST_GAMUT_REMAP 0x000b 15399 #define ixMPCC_MCM3_ID12_MPCC_MCM_SECOND_GAMUT_REMAP 0x000c 15400 15401 // addressBlock: otg0_otgdebugind 15402 // base address: 0x0 15403 #define ixOTG0_OTG_DBG_DATA1 0x0001 15404 #define ixOTG0_OTG_DBG_DATA2 0x0002 15405 #define ixOTG0_OTG_DBG_DATA3 0x0003 15406 #define ixOTG0_OTG_DBG_DATA4 0x0004 15407 #define ixOTG0_OTG_DBG_DATA5 0x0005 15408 #define ixOTG0_OTG_DBG_DATA6 0x0006 15409 #define ixOTG0_OTG_DBG_DATA7 0x0007 15410 #define ixOTG0_OTG_DBG_DATA8 0x0008 15411 #define ixOTG0_OTG_DBG_DATA9 0x0009 15412 #define ixOTG0_OTG_DBG_DATA10 0x000a 15413 #define ixOTG0_OTG_SCL_INTERFACE 0x0042 15414 #define ixOTG0_OTG_DOUT_INTERFACE_01_A 0x0043 15415 #define ixOTG0_OTG_DOUT_INTERFACE_01_B 0x0044 15416 #define ixOTG0_OTG_DOUT_INTERFACE_02 0x0045 15417 15418 15419 // addressBlock: otg1_otgdebugind 15420 // base address: 0x0 15421 #define ixOTG1_OTG_DBG_DATA1 0x0001 15422 #define ixOTG1_OTG_DBG_DATA2 0x0002 15423 #define ixOTG1_OTG_DBG_DATA3 0x0003 15424 #define ixOTG1_OTG_DBG_DATA4 0x0004 15425 #define ixOTG1_OTG_DBG_DATA5 0x0005 15426 #define ixOTG1_OTG_DBG_DATA6 0x0006 15427 #define ixOTG1_OTG_DBG_DATA7 0x0007 15428 #define ixOTG1_OTG_DBG_DATA8 0x0008 15429 #define ixOTG1_OTG_DBG_DATA9 0x0009 15430 #define ixOTG1_OTG_DBG_DATA10 0x000a 15431 #define ixOTG1_OTG_SCL_INTERFACE 0x0042 15432 #define ixOTG1_OTG_DOUT_INTERFACE_01_A 0x0043 15433 #define ixOTG1_OTG_DOUT_INTERFACE_01_B 0x0044 15434 #define ixOTG1_OTG_DOUT_INTERFACE_02 0x0045 15435 15436 15437 // addressBlock: otg2_otgdebugind 15438 // base address: 0x0 15439 #define ixOTG2_OTG_DBG_DATA1 0x0001 15440 #define ixOTG2_OTG_DBG_DATA2 0x0002 15441 #define ixOTG2_OTG_DBG_DATA3 0x0003 15442 #define ixOTG2_OTG_DBG_DATA4 0x0004 15443 #define ixOTG2_OTG_DBG_DATA5 0x0005 15444 #define ixOTG2_OTG_DBG_DATA6 0x0006 15445 #define ixOTG2_OTG_DBG_DATA7 0x0007 15446 #define ixOTG2_OTG_DBG_DATA8 0x0008 15447 #define ixOTG2_OTG_DBG_DATA9 0x0009 15448 #define ixOTG2_OTG_DBG_DATA10 0x000a 15449 #define ixOTG2_OTG_SCL_INTERFACE 0x0042 15450 #define ixOTG2_OTG_DOUT_INTERFACE_01_A 0x0043 15451 #define ixOTG2_OTG_DOUT_INTERFACE_01_B 0x0044 15452 #define ixOTG2_OTG_DOUT_INTERFACE_02 0x0045 15453 #define ixDCIO_DEBUG_ID 0x0000 15454 #define ixDCIO_DEBUG1B 0x001b 15455 #define ixDCIO_DEBUG1C 0x001c 15456 #define ixDCIO_DEBUG1D 0x001d 15457 #define ixDCIO_DEBUG1E 0x001e 15458 #define ixDCIO_DEBUG1F 0x001f 15459 #define ixDCIO_DEBUG20 0x0020 15460 #define ixDCIO_DEBUG21 0x0021 15461 #define ixDCIO_DEBUG22 0x0022 15462 15463 15464 // addressBlock: otg3_otgdebugind 15465 // base address: 0x0 15466 #define ixOTG3_OTG_DBG_DATA1 0x0001 15467 #define ixOTG3_OTG_DBG_DATA2 0x0002 15468 #define ixOTG3_OTG_DBG_DATA3 0x0003 15469 #define ixOTG3_OTG_DBG_DATA4 0x0004 15470 #define ixOTG3_OTG_DBG_DATA5 0x0005 15471 #define ixOTG3_OTG_DBG_DATA6 0x0006 15472 #define ixOTG3_OTG_DBG_DATA7 0x0007 15473 #define ixOTG3_OTG_DBG_DATA8 0x0008 15474 #define ixOTG3_OTG_DBG_DATA9 0x0009 15475 #define ixOTG3_OTG_DBG_DATA10 0x000a 15476 #define ixOTG3_OTG_SCL_INTERFACE 0x0042 15477 #define ixOTG3_OTG_DOUT_INTERFACE_01_A 0x0043 15478 #define ixOTG3_OTG_DOUT_INTERFACE_01_B 0x0044 15479 #define ixOTG3_OTG_DOUT_INTERFACE_02 0x0045 15480 15481 // addressBlock: azendpoint_f2codecind 15482 // base address: 0x0 15483 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 15484 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 15485 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d 15486 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e 15487 #define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 15488 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e 15489 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 15490 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 15491 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a 15492 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b 15493 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 15494 #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 15495 #define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 15496 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 15497 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c 15498 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d 15499 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e 15500 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f 15501 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 15502 #define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 15503 #define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 15504 #define ixAZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX 0x3774 15505 #define ixAZALIA_F2_CODEC_PIN_CONTROL_ACP_DATA 0x3775 15506 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 15507 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 15508 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 15509 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 15510 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 15511 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a 15512 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b 15513 #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c 15514 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 15515 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 15516 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 15517 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 15518 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 15519 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 15520 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 15521 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a 15522 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b 15523 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c 15524 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d 15525 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e 15526 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f 15527 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 15528 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 15529 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 15530 #define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 15531 #define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 15532 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 15533 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 15534 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a 15535 #define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b 15536 #define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c 15537 #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d 15538 #define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e 15539 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 15540 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c 15541 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e 15542 15543 15544 // addressBlock: azendpoint_descriptorind 15545 // base address: 0x0 15546 #define ixAUDIO_DESCRIPTOR0 0x0001 15547 #define ixAUDIO_DESCRIPTOR1 0x0002 15548 #define ixAUDIO_DESCRIPTOR2 0x0003 15549 #define ixAUDIO_DESCRIPTOR3 0x0004 15550 #define ixAUDIO_DESCRIPTOR4 0x0005 15551 #define ixAUDIO_DESCRIPTOR5 0x0006 15552 #define ixAUDIO_DESCRIPTOR6 0x0007 15553 #define ixAUDIO_DESCRIPTOR7 0x0008 15554 #define ixAUDIO_DESCRIPTOR8 0x0009 15555 #define ixAUDIO_DESCRIPTOR9 0x000a 15556 #define ixAUDIO_DESCRIPTOR10 0x000b 15557 #define ixAUDIO_DESCRIPTOR11 0x000c 15558 #define ixAUDIO_DESCRIPTOR12 0x000d 15559 #define ixAUDIO_DESCRIPTOR13 0x000e 15560 15561 15562 // addressBlock: azendpoint_sinkinfoind 15563 // base address: 0x0 15564 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000 15565 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001 15566 #define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002 15567 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003 15568 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004 15569 #define ixSINK_DESCRIPTION0 0x0005 15570 #define ixSINK_DESCRIPTION1 0x0006 15571 #define ixSINK_DESCRIPTION2 0x0007 15572 #define ixSINK_DESCRIPTION3 0x0008 15573 #define ixSINK_DESCRIPTION4 0x0009 15574 #define ixSINK_DESCRIPTION5 0x000a 15575 #define ixSINK_DESCRIPTION6 0x000b 15576 #define ixSINK_DESCRIPTION7 0x000c 15577 #define ixSINK_DESCRIPTION8 0x000d 15578 #define ixSINK_DESCRIPTION9 0x000e 15579 #define ixSINK_DESCRIPTION10 0x000f 15580 #define ixSINK_DESCRIPTION11 0x0010 15581 #define ixSINK_DESCRIPTION12 0x0011 15582 #define ixSINK_DESCRIPTION13 0x0012 15583 #define ixSINK_DESCRIPTION14 0x0013 15584 #define ixSINK_DESCRIPTION15 0x0014 15585 #define ixSINK_DESCRIPTION16 0x0015 15586 #define ixSINK_DESCRIPTION17 0x0016 15587 15588 15589 // addressBlock: azf0controller_azinputcrc0resultind 15590 // base address: 0x0 15591 #define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000 15592 #define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001 15593 #define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002 15594 #define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003 15595 #define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004 15596 #define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005 15597 #define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006 15598 #define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007 15599 15600 15601 // addressBlock: azf0controller_azinputcrc1resultind 15602 // base address: 0x0 15603 #define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000 15604 #define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001 15605 #define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002 15606 #define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003 15607 #define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004 15608 #define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005 15609 #define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006 15610 #define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007 15611 15612 15613 // addressBlock: azf0controller_azcrc0resultind 15614 // base address: 0x0 15615 #define ixAZALIA_CRC0_CHANNEL0 0x0000 15616 #define ixAZALIA_CRC0_CHANNEL1 0x0001 15617 #define ixAZALIA_CRC0_CHANNEL2 0x0002 15618 #define ixAZALIA_CRC0_CHANNEL3 0x0003 15619 #define ixAZALIA_CRC0_CHANNEL4 0x0004 15620 #define ixAZALIA_CRC0_CHANNEL5 0x0005 15621 #define ixAZALIA_CRC0_CHANNEL6 0x0006 15622 #define ixAZALIA_CRC0_CHANNEL7 0x0007 15623 15624 15625 // addressBlock: azf0controller_azcrc1resultind 15626 // base address: 0x0 15627 #define ixAZALIA_CRC1_CHANNEL0 0x0000 15628 #define ixAZALIA_CRC1_CHANNEL1 0x0001 15629 #define ixAZALIA_CRC1_CHANNEL2 0x0002 15630 #define ixAZALIA_CRC1_CHANNEL3 0x0003 15631 #define ixAZALIA_CRC1_CHANNEL4 0x0004 15632 #define ixAZALIA_CRC1_CHANNEL5 0x0005 15633 #define ixAZALIA_CRC1_CHANNEL6 0x0006 15634 #define ixAZALIA_CRC1_CHANNEL7 0x0007 15635 15636 15637 // addressBlock: azinputendpoint_f2codecind 15638 // base address: 0x0 15639 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 15640 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 15641 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d 15642 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 15643 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a 15644 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b 15645 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 15646 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 15647 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 15648 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c 15649 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d 15650 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e 15651 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f 15652 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 15653 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 15654 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 15655 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 15656 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a 15657 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c 15658 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 15659 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 15660 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 15661 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 15662 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 15663 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 15664 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a 15665 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b 15666 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c 15667 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d 15668 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e 15669 #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 15670 #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c 15671 15672 15673 // addressBlock: azroot_f2codecind 15674 // base address: 0x0 15675 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00 15676 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02 15677 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04 15678 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 15679 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 15680 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 15681 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 15682 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 15683 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 15684 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff 15685 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 15686 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 15687 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a 15688 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b 15689 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f 15690 15691 15692 // addressBlock: azf0stream0_streamind 15693 // base address: 0x0 15694 #define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000 15695 #define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 15696 #define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 15697 #define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 15698 #define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 15699 15700 15701 // addressBlock: azf0stream1_streamind 15702 // base address: 0x0 15703 #define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000 15704 #define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 15705 #define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 15706 #define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 15707 #define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 15708 15709 15710 // addressBlock: azf0stream2_streamind 15711 // base address: 0x0 15712 #define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000 15713 #define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 15714 #define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 15715 #define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 15716 #define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 15717 15718 15719 // addressBlock: azf0stream3_streamind 15720 // base address: 0x0 15721 #define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000 15722 #define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 15723 #define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 15724 #define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 15725 #define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 15726 15727 15728 // addressBlock: azf0stream4_streamind 15729 // base address: 0x0 15730 #define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000 15731 #define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 15732 #define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 15733 #define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 15734 #define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 15735 15736 15737 // addressBlock: azf0stream5_streamind 15738 // base address: 0x0 15739 #define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000 15740 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 15741 #define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 15742 #define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 15743 #define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 15744 15745 15746 // addressBlock: azf0stream6_streamind 15747 // base address: 0x0 15748 #define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000 15749 #define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 15750 #define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 15751 #define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 15752 #define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 15753 15754 15755 // addressBlock: azf0stream7_streamind 15756 // base address: 0x0 15757 #define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000 15758 #define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 15759 #define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 15760 #define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 15761 #define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 15762 15763 15764 // addressBlock: azf0stream8_streamind 15765 // base address: 0x0 15766 #define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000 15767 #define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 15768 #define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 15769 #define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 15770 #define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 15771 15772 15773 // addressBlock: azf0stream9_streamind 15774 // base address: 0x0 15775 #define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000 15776 #define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 15777 #define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 15778 #define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 15779 #define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 15780 15781 15782 // addressBlock: azf0stream10_streamind 15783 // base address: 0x0 15784 #define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000 15785 #define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 15786 #define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 15787 #define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 15788 #define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 15789 15790 15791 // addressBlock: azf0stream11_streamind 15792 // base address: 0x0 15793 #define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000 15794 #define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 15795 #define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 15796 #define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 15797 #define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 15798 15799 15800 // addressBlock: azf0stream12_streamind 15801 // base address: 0x0 15802 #define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000 15803 #define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 15804 #define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 15805 #define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 15806 #define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 15807 15808 15809 // addressBlock: azf0stream13_streamind 15810 // base address: 0x0 15811 #define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000 15812 #define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 15813 #define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 15814 #define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 15815 #define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 15816 15817 15818 // addressBlock: azf0stream14_streamind 15819 // base address: 0x0 15820 #define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000 15821 #define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 15822 #define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 15823 #define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 15824 #define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 15825 15826 15827 // addressBlock: azf0stream15_streamind 15828 // base address: 0x0 15829 #define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000 15830 #define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 15831 #define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 15832 #define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 15833 #define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 15834 15835 15836 // addressBlock: azf0endpoint0_endpointind 15837 // base address: 0x0 15838 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15839 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15840 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15841 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15842 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15843 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15844 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 15845 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 15846 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15847 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 15848 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15849 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 15850 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 15851 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 15852 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA 0x0027 15853 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 15854 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 15855 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 15856 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 15857 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 15858 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 15859 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 15860 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 15861 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 15862 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 15863 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 15864 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 15865 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 15866 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 15867 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15868 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 15869 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 15870 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 15871 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 15872 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 15873 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 15874 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 15875 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 15876 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 15877 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 15878 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 15879 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15880 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15881 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15882 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 15883 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 15884 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 15885 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 15886 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 15887 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 15888 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 15889 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 15890 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 15891 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 15892 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 15893 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 15894 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 15895 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15896 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 15897 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15898 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 15899 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 15900 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 15901 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 15902 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 15903 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 15904 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 15905 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 15906 #define ixAZF0ENDPOINT0_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 15907 15908 15909 // addressBlock: azf0endpoint1_endpointind 15910 // base address: 0x0 15911 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15912 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15913 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15914 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15915 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15916 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15917 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 15918 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 15919 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15920 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 15921 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15922 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 15923 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 15924 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 15925 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA 0x0027 15926 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 15927 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 15928 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 15929 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 15930 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 15931 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 15932 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 15933 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 15934 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 15935 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 15936 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 15937 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 15938 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 15939 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 15940 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 15941 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 15942 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 15943 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 15944 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 15945 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 15946 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 15947 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 15948 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 15949 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 15950 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 15951 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 15952 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 15953 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 15954 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 15955 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 15956 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 15957 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 15958 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 15959 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 15960 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 15961 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 15962 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 15963 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 15964 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 15965 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 15966 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 15967 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 15968 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 15969 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 15970 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 15971 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 15972 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 15973 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 15974 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 15975 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 15976 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 15977 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 15978 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 15979 #define ixAZF0ENDPOINT1_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 15980 15981 15982 // addressBlock: azf0endpoint2_endpointind 15983 // base address: 0x0 15984 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 15985 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 15986 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 15987 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 15988 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 15989 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 15990 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 15991 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 15992 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 15993 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 15994 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 15995 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 15996 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 15997 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 15998 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA 0x0027 15999 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 16000 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 16001 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 16002 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 16003 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 16004 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 16005 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 16006 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 16007 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 16008 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 16009 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 16010 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 16011 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 16012 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 16013 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 16014 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 16015 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 16016 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 16017 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 16018 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 16019 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 16020 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 16021 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 16022 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 16023 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 16024 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 16025 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 16026 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 16027 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 16028 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 16029 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 16030 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 16031 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 16032 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 16033 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 16034 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 16035 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 16036 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 16037 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 16038 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 16039 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 16040 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 16041 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 16042 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 16043 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 16044 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 16045 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 16046 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 16047 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 16048 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 16049 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 16050 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 16051 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 16052 #define ixAZF0ENDPOINT2_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 16053 16054 16055 // addressBlock: azf0endpoint3_endpointind 16056 // base address: 0x0 16057 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 16058 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 16059 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 16060 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 16061 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 16062 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 16063 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 16064 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 16065 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 16066 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 16067 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 16068 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 16069 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 16070 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 16071 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA 0x0027 16072 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 16073 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 16074 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 16075 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 16076 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 16077 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 16078 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 16079 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 16080 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 16081 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 16082 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 16083 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 16084 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 16085 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 16086 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 16087 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 16088 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 16089 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 16090 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 16091 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 16092 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 16093 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 16094 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 16095 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 16096 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 16097 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 16098 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 16099 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 16100 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 16101 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 16102 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 16103 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 16104 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 16105 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 16106 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 16107 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 16108 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 16109 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 16110 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 16111 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 16112 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 16113 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 16114 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 16115 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 16116 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 16117 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 16118 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 16119 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 16120 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 16121 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 16122 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 16123 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 16124 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 16125 #define ixAZF0ENDPOINT3_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 16126 16127 16128 // addressBlock: azf0endpoint4_endpointind 16129 // base address: 0x0 16130 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 16131 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 16132 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 16133 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 16134 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 16135 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 16136 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 16137 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 16138 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 16139 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 16140 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 16141 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 16142 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 16143 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 16144 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA 0x0027 16145 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 16146 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 16147 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 16148 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 16149 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 16150 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 16151 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 16152 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 16153 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 16154 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 16155 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 16156 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 16157 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 16158 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 16159 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 16160 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 16161 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 16162 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 16163 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 16164 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 16165 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 16166 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 16167 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 16168 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 16169 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 16170 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 16171 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 16172 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 16173 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 16174 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 16175 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 16176 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 16177 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 16178 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 16179 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 16180 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 16181 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 16182 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 16183 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 16184 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 16185 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 16186 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 16187 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 16188 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 16189 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 16190 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 16191 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 16192 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 16193 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 16194 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 16195 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 16196 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 16197 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 16198 #define ixAZF0ENDPOINT4_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 16199 16200 16201 // addressBlock: azf0endpoint5_endpointind 16202 // base address: 0x0 16203 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 16204 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 16205 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 16206 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 16207 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 16208 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 16209 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 16210 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 16211 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 16212 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 16213 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 16214 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 16215 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 16216 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 16217 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA 0x0027 16218 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 16219 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 16220 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 16221 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 16222 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 16223 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 16224 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 16225 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 16226 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 16227 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 16228 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 16229 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 16230 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 16231 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 16232 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 16233 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 16234 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 16235 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 16236 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 16237 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 16238 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 16239 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 16240 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 16241 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 16242 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 16243 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 16244 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 16245 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 16246 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 16247 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 16248 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 16249 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 16250 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 16251 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 16252 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 16253 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 16254 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 16255 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 16256 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 16257 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 16258 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 16259 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 16260 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 16261 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 16262 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 16263 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 16264 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 16265 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 16266 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 16267 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 16268 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 16269 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 16270 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 16271 #define ixAZF0ENDPOINT5_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 16272 16273 16274 // addressBlock: azf0endpoint6_endpointind 16275 // base address: 0x0 16276 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 16277 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 16278 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 16279 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 16280 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 16281 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 16282 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 16283 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 16284 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 16285 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 16286 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 16287 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 16288 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 16289 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 16290 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA 0x0027 16291 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 16292 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 16293 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 16294 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 16295 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 16296 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 16297 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 16298 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 16299 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 16300 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 16301 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 16302 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 16303 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 16304 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 16305 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 16306 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 16307 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 16308 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 16309 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 16310 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 16311 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 16312 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 16313 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 16314 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 16315 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 16316 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 16317 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 16318 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 16319 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 16320 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 16321 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 16322 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 16323 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 16324 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 16325 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 16326 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 16327 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 16328 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 16329 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 16330 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 16331 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 16332 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 16333 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 16334 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 16335 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 16336 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 16337 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 16338 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 16339 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 16340 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 16341 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 16342 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 16343 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 16344 #define ixAZF0ENDPOINT6_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 16345 16346 16347 // addressBlock: azf0endpoint7_endpointind 16348 // base address: 0x0 16349 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 16350 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 16351 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 16352 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 16353 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 16354 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 16355 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 16356 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 16357 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 16358 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 16359 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 16360 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 16361 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 16362 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 16363 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA 0x0027 16364 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 16365 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 16366 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 16367 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 16368 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 16369 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 16370 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 16371 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 16372 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 16373 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 16374 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 16375 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 16376 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 16377 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 16378 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 16379 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 16380 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 16381 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 16382 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 16383 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 16384 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 16385 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 16386 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 16387 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 16388 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 16389 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 16390 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 16391 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 16392 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 16393 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 16394 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 16395 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 16396 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 16397 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 16398 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 16399 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 16400 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 16401 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 16402 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 16403 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 16404 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 16405 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 16406 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 16407 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 16408 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 16409 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 16410 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 16411 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 16412 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 16413 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 16414 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 16415 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 16416 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 16417 #define ixAZF0ENDPOINT7_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 16418 16419 16420 // addressBlock: azf0inputendpoint0_inputendpointind 16421 // base address: 0x0 16422 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 16423 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 16424 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 16425 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 16426 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 16427 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 16428 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 16429 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 16430 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 16431 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 16432 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 16433 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 16434 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 16435 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 16436 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 16437 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 16438 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 16439 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 16440 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 16441 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 16442 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 16443 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 16444 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 16445 16446 16447 // addressBlock: azf0inputendpoint1_inputendpointind 16448 // base address: 0x0 16449 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 16450 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 16451 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 16452 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 16453 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 16454 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 16455 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 16456 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 16457 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 16458 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 16459 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 16460 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 16461 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 16462 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 16463 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 16464 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 16465 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 16466 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 16467 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 16468 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 16469 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 16470 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 16471 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 16472 16473 16474 // addressBlock: azf0inputendpoint2_inputendpointind 16475 // base address: 0x0 16476 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 16477 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 16478 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 16479 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 16480 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 16481 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 16482 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 16483 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 16484 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 16485 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 16486 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 16487 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 16488 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 16489 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 16490 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 16491 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 16492 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 16493 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 16494 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 16495 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 16496 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 16497 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 16498 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 16499 16500 16501 // addressBlock: azf0inputendpoint3_inputendpointind 16502 // base address: 0x0 16503 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 16504 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 16505 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 16506 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 16507 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 16508 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 16509 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 16510 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 16511 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 16512 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 16513 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 16514 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 16515 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 16516 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 16517 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 16518 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 16519 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 16520 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 16521 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 16522 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 16523 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 16524 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 16525 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 16526 16527 16528 // addressBlock: azf0inputendpoint4_inputendpointind 16529 // base address: 0x0 16530 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 16531 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 16532 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 16533 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 16534 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 16535 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 16536 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 16537 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 16538 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 16539 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 16540 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 16541 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 16542 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 16543 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 16544 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 16545 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 16546 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 16547 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 16548 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 16549 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 16550 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 16551 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 16552 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 16553 16554 16555 // addressBlock: azf0inputendpoint5_inputendpointind 16556 // base address: 0x0 16557 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 16558 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 16559 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 16560 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 16561 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 16562 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 16563 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 16564 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 16565 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 16566 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 16567 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 16568 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 16569 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 16570 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 16571 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 16572 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 16573 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 16574 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 16575 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 16576 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 16577 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 16578 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 16579 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 16580 16581 16582 // addressBlock: azf0inputendpoint6_inputendpointind 16583 // base address: 0x0 16584 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 16585 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 16586 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 16587 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 16588 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 16589 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 16590 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 16591 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 16592 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 16593 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 16594 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 16595 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 16596 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 16597 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 16598 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 16599 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 16600 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 16601 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 16602 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 16603 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 16604 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 16605 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 16606 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 16607 16608 16609 // addressBlock: azf0inputendpoint7_inputendpointind 16610 // base address: 0x0 16611 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 16612 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 16613 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 16614 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 16615 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 16616 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 16617 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 16618 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 16619 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 16620 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 16621 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 16622 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 16623 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 16624 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 16625 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 16626 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 16627 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 16628 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 16629 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 16630 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 16631 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 16632 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 16633 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 16634 16635 16636 #endif 16637