1# SPDX-License-Identifier: CC0-1.0 2# Generator: x86-cpuid-db v3.0 3 4# 5# Auto-generated file. 6# Please submit all updates and bugfixes to https://x86-cpuid.org 7# 8 9# The basic row format is: 10# LEAF, SUBLEAVES, reg, bits, short_name , long_description 11 12# Leaf 0H 13# Maximum standard leaf + CPU vendor string 14 15 0x0, 0, eax, 31:0, max_std_leaf , Highest standard CPUID leaf 16 0x0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vendor ID string bytes 0 - 3 17 0x0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vendor ID string bytes 8 - 11 18 0x0, 0, edx, 31:0, cpu_vendorid_1 , CPU vendor ID string bytes 4 - 7 19 20# Leaf 1H 21# CPU FMS (Family/Model/Stepping) + standard feature flags 22 23 0x1, 0, eax, 3:0, stepping , Stepping ID 24 0x1, 0, eax, 7:4, base_model , Base CPU model ID 25 0x1, 0, eax, 11:8, base_family_id , Base CPU family ID 26 0x1, 0, eax, 13:12, cpu_type , CPU type 27 0x1, 0, eax, 19:16, ext_model , Extended CPU model ID 28 0x1, 0, eax, 27:20, ext_family , Extended CPU family ID 29 0x1, 0, ebx, 7:0, brand_id , Brand index 30 0x1, 0, ebx, 15:8, clflush_size , CLFLUSH instruction cache line size 31 0x1, 0, ebx, 23:16, n_logical_cpu , Logical CPU count 32 0x1, 0, ebx, 31:24, local_apic_id , Initial local APIC physical ID 33 0x1, 0, ecx, 0, pni , Streaming SIMD Extensions 3 (SSE3) 34 0x1, 0, ecx, 1, pclmulqdq , PCLMULQDQ instruction support 35 0x1, 0, ecx, 2, dtes64 , 64-bit DS save area 36 0x1, 0, ecx, 3, monitor , MONITOR/MWAIT support 37 0x1, 0, ecx, 4, ds_cpl , CPL Qualified Debug Store 38 0x1, 0, ecx, 5, vmx , Virtual Machine Extensions 39 0x1, 0, ecx, 6, smx , Safer Mode Extensions 40 0x1, 0, ecx, 7, est , Enhanced Intel SpeedStep 41 0x1, 0, ecx, 8, tm2 , Thermal Monitor 2 42 0x1, 0, ecx, 9, ssse3 , Supplemental SSE3 43 0x1, 0, ecx, 10, cid , L1 Context ID 44 0x1, 0, ecx, 11, sdbg , Silicon Debug 45 0x1, 0, ecx, 12, fma , FMA extensions using YMM state 46 0x1, 0, ecx, 13, cx16 , CMPXCHG16B instruction support 47 0x1, 0, ecx, 14, xtpr , xTPR Update Control 48 0x1, 0, ecx, 15, pdcm , Perfmon and Debug Capability 49 0x1, 0, ecx, 17, pcid , Process-context identifiers 50 0x1, 0, ecx, 18, dca , Direct Cache Access 51 0x1, 0, ecx, 19, sse4_1 , SSE4.1 52 0x1, 0, ecx, 20, sse4_2 , SSE4.2 53 0x1, 0, ecx, 21, x2apic , X2APIC support 54 0x1, 0, ecx, 22, movbe , MOVBE instruction support 55 0x1, 0, ecx, 23, popcnt , POPCNT instruction support 56 0x1, 0, ecx, 24, tsc_deadline_timer , APIC timer one-shot operation 57 0x1, 0, ecx, 25, aes , AES instructions 58 0x1, 0, ecx, 26, xsave , XSAVE (and related instructions) support 59 0x1, 0, ecx, 27, osxsave , XSAVE (and related instructions) are enabled by OS 60 0x1, 0, ecx, 28, avx , AVX instructions support 61 0x1, 0, ecx, 29, f16c , Half-precision floating-point conversion support 62 0x1, 0, ecx, 30, rdrand , RDRAND instruction support 63 0x1, 0, ecx, 31, guest_status , System is running as guest; (para-)virtualized system 64 0x1, 0, edx, 0, fpu , Floating-Point Unit on-chip (x87) 65 0x1, 0, edx, 1, vme , Virtual-8086 Mode Extensions 66 0x1, 0, edx, 2, de , Debugging Extensions 67 0x1, 0, edx, 3, pse , Page Size Extension 68 0x1, 0, edx, 4, tsc , Time Stamp Counter 69 0x1, 0, edx, 5, msr , Model-Specific Registers (RDMSR and WRMSR support) 70 0x1, 0, edx, 6, pae , Physical Address Extensions 71 0x1, 0, edx, 7, mce , Machine Check Exception 72 0x1, 0, edx, 8, cx8 , CMPXCHG8B instruction 73 0x1, 0, edx, 9, apic , APIC on-chip 74 0x1, 0, edx, 11, sep , SYSENTER, SYSEXIT, and associated MSRs 75 0x1, 0, edx, 12, mtrr , Memory Type Range Registers 76 0x1, 0, edx, 13, pge , Page Global Extensions 77 0x1, 0, edx, 14, mca , Machine Check Architecture 78 0x1, 0, edx, 15, cmov , Conditional Move Instruction 79 0x1, 0, edx, 16, pat , Page Attribute Table 80 0x1, 0, edx, 17, pse36 , Page Size Extension (36-bit) 81 0x1, 0, edx, 18, pn , Processor Serial Number 82 0x1, 0, edx, 19, clflush , CLFLUSH instruction 83 0x1, 0, edx, 21, dts , Debug Store 84 0x1, 0, edx, 22, acpi , Thermal monitor and clock control 85 0x1, 0, edx, 23, mmx , MMX instructions 86 0x1, 0, edx, 24, fxsr , FXSAVE and FXRSTOR instructions 87 0x1, 0, edx, 25, sse , SSE instructions 88 0x1, 0, edx, 26, sse2 , SSE2 instructions 89 0x1, 0, edx, 27, ss , Self Snoop 90 0x1, 0, edx, 28, ht , Hyper-threading 91 0x1, 0, edx, 29, tm , Thermal Monitor 92 0x1, 0, edx, 30, ia64 , Legacy IA-64 (Itanium) support bit, now reserved 93 0x1, 0, edx, 31, pbe , Pending Break Enable 94 95# Leaf 2H 96# Intel cache and TLB information one-byte descriptors 97 98 0x2, 0, eax, 7:0, iteration_count , Number of times this leaf must be queried 99 0x2, 0, eax, 15:8, desc1 , Descriptor #1 100 0x2, 0, eax, 23:16, desc2 , Descriptor #2 101 0x2, 0, eax, 30:24, desc3 , Descriptor #3 102 0x2, 0, eax, 31, eax_invalid , Descriptors 1-3 are invalid if set 103 0x2, 0, ebx, 7:0, desc4 , Descriptor #4 104 0x2, 0, ebx, 15:8, desc5 , Descriptor #5 105 0x2, 0, ebx, 23:16, desc6 , Descriptor #6 106 0x2, 0, ebx, 30:24, desc7 , Descriptor #7 107 0x2, 0, ebx, 31, ebx_invalid , Descriptors 4-7 are invalid if set 108 0x2, 0, ecx, 7:0, desc8 , Descriptor #8 109 0x2, 0, ecx, 15:8, desc9 , Descriptor #9 110 0x2, 0, ecx, 23:16, desc10 , Descriptor #10 111 0x2, 0, ecx, 30:24, desc11 , Descriptor #11 112 0x2, 0, ecx, 31, ecx_invalid , Descriptors 8-11 are invalid if set 113 0x2, 0, edx, 7:0, desc12 , Descriptor #12 114 0x2, 0, edx, 15:8, desc13 , Descriptor #13 115 0x2, 0, edx, 23:16, desc14 , Descriptor #14 116 0x2, 0, edx, 30:24, desc15 , Descriptor #15 117 0x2, 0, edx, 31, edx_invalid , Descriptors 12-15 are invalid if set 118 119# Leaf 4H 120# Intel deterministic cache parameters 121 122 0x4, 31:0, eax, 4:0, cache_type , Cache type field 123 0x4, 31:0, eax, 7:5, cache_level , Cache level (1-based) 124 0x4, 31:0, eax, 8, cache_self_init , Self-initializing cache level 125 0x4, 31:0, eax, 9, fully_associative , Fully-associative cache 126 0x4, 31:0, eax, 25:14, num_threads_sharing , Number logical CPUs sharing this cache 127 0x4, 31:0, eax, 31:26, num_cores_on_die , Number of cores in the physical package 128 0x4, 31:0, ebx, 11:0, cache_linesize , System coherency line size (0-based) 129 0x4, 31:0, ebx, 21:12, cache_npartitions , Physical line partitions (0-based) 130 0x4, 31:0, ebx, 31:22, cache_nways , Ways of associativity (0-based) 131 0x4, 31:0, ecx, 30:0, cache_nsets , Cache number of sets (0-based) 132 0x4, 31:0, edx, 0, wbinvd_rll_no_guarantee, WBINVD/INVD not guaranteed for Remote Lower-Level caches 133 0x4, 31:0, edx, 1, ll_inclusive , Cache is inclusive of Lower-Level caches 134 0x4, 31:0, edx, 2, complex_indexing , Not a direct-mapped cache (complex function) 135 136# Leaf 5H 137# MONITOR/MWAIT instructions 138 139 0x5, 0, eax, 15:0, min_mon_size , Smallest monitor-line size, in bytes 140 0x5, 0, ebx, 15:0, max_mon_size , Largest monitor-line size, in bytes 141 0x5, 0, ecx, 0, mwait_ext , MONITOR/MWAIT extensions 142 0x5, 0, ecx, 1, mwait_irq_break , Interrupts as a break event for MWAIT 143 0x5, 0, edx, 3:0, n_c0_substates , Number of C0 sub C-states 144 0x5, 0, edx, 7:4, n_c1_substates , Number of C1 sub C-states 145 0x5, 0, edx, 11:8, n_c2_substates , Number of C2 sub C-states 146 0x5, 0, edx, 15:12, n_c3_substates , Number of C3 sub C-states 147 0x5, 0, edx, 19:16, n_c4_substates , Number of C4 sub C-states 148 0x5, 0, edx, 23:20, n_c5_substates , Number of C5 sub C-states 149 0x5, 0, edx, 27:24, n_c6_substates , Number of C6 sub C-states 150 0x5, 0, edx, 31:28, n_c7_substates , Number of C7 sub C-states 151 152# Leaf 6H 153# Thermal and power management 154 155 0x6, 0, eax, 0, dtherm , Digital temperature sensor 156 0x6, 0, eax, 1, turbo_boost , Intel Turbo Boost 157 0x6, 0, eax, 2, arat , Always-Running APIC Timer (not affected by p-state) 158 0x6, 0, eax, 4, pln , Power Limit Notification (PLN) event 159 0x6, 0, eax, 5, ecmd , Clock modulation duty cycle extension 160 0x6, 0, eax, 6, pts , Package thermal management 161 0x6, 0, eax, 7, hwp , HWP (Hardware P-states) base registers 162 0x6, 0, eax, 8, hwp_notify , HWP notification (IA32_HWP_INTERRUPT MSR) 163 0x6, 0, eax, 9, hwp_act_window , HWP activity window (IA32_HWP_REQUEST[bits 41:32]) 164 0x6, 0, eax, 10, hwp_epp , HWP Energy Performance Preference 165 0x6, 0, eax, 11, hwp_pkg_req , HWP Package Level Request 166 0x6, 0, eax, 13, hdc_base_regs , HDC base registers 167 0x6, 0, eax, 14, turbo_boost_3_0 , Intel Turbo Boost Max 3.0 168 0x6, 0, eax, 15, hwp_capabilities , HWP Highest Performance change 169 0x6, 0, eax, 16, hwp_peci_override , HWP PECI override 170 0x6, 0, eax, 17, hwp_flexible , Flexible HWP 171 0x6, 0, eax, 18, hwp_fast , IA32_HWP_REQUEST MSR fast access mode 172 0x6, 0, eax, 19, hfi , HW_FEEDBACK MSRs 173 0x6, 0, eax, 20, hwp_ignore_idle , Ignoring idle logical CPU HWP request is supported 174 0x6, 0, eax, 22, hwp_ctl , IA32_HWP_CTL MSR 175 0x6, 0, eax, 23, thread_director , Intel thread director 176 0x6, 0, eax, 24, therm_interrupt_bit25 , IA32_THERM_INTERRUPT MSR bit 25 177 0x6, 0, ebx, 3:0, n_therm_thresholds , Digital thermometer thresholds 178 0x6, 0, ecx, 0, aperfmperf , MPERF/APERF MSRs (effective frequency interface) 179 0x6, 0, ecx, 3, epb , IA32_ENERGY_PERF_BIAS MSR 180 0x6, 0, ecx, 15:8, thrd_director_nclasses , Number of classes, Intel thread director 181 0x6, 0, edx, 0, perfcap_reporting , Performance capability reporting 182 0x6, 0, edx, 1, encap_reporting , Energy efficiency capability reporting 183 0x6, 0, edx, 11:8, feedback_sz , Feedback interface structure size, in 4K pages 184 0x6, 0, edx, 31:16, this_lcpu_hwfdbk_idx , This logical CPU hardware feedback interface index 185 186# Leaf 7H 187# Extended CPU features 188 189 0x7, 0, eax, 31:0, leaf7_n_subleaves , Number of leaf 0x7 subleaves 190 0x7, 0, ebx, 0, fsgsbase , FSBASE/GSBASE read/write 191 0x7, 0, ebx, 1, tsc_adjust , IA32_TSC_ADJUST MSR 192 0x7, 0, ebx, 2, sgx , Intel SGX (Software Guard Extensions) 193 0x7, 0, ebx, 3, bmi1 , Bit manipulation extensions group 1 194 0x7, 0, ebx, 4, hle , Hardware Lock Elision 195 0x7, 0, ebx, 5, avx2 , AVX2 instruction set 196 0x7, 0, ebx, 6, fdp_excptn_only , FPU Data Pointer updated only on x87 exceptions 197 0x7, 0, ebx, 7, smep , Supervisor Mode Execution Protection 198 0x7, 0, ebx, 8, bmi2 , Bit manipulation extensions group 2 199 0x7, 0, ebx, 9, erms , Enhanced REP MOVSB/STOSB 200 0x7, 0, ebx, 10, invpcid , INVPCID instruction (Invalidate Processor Context ID) 201 0x7, 0, ebx, 11, rtm , Intel restricted transactional memory 202 0x7, 0, ebx, 12, cqm , Intel RDT-CMT / AMD Platform-QoS cache monitoring 203 0x7, 0, ebx, 13, zero_fcs_fds , Deprecated FPU CS/DS (stored as zero) 204 0x7, 0, ebx, 14, mpx , Intel memory protection extensions 205 0x7, 0, ebx, 15, rdt_a , Intel RDT / AMD Platform-QoS Enforcement 206 0x7, 0, ebx, 16, avx512f , AVX-512 foundation instructions 207 0x7, 0, ebx, 17, avx512dq , AVX-512 double/quadword instructions 208 0x7, 0, ebx, 18, rdseed , RDSEED instruction 209 0x7, 0, ebx, 19, adx , ADCX/ADOX instructions 210 0x7, 0, ebx, 20, smap , Supervisor mode access prevention 211 0x7, 0, ebx, 21, avx512ifma , AVX-512 integer fused multiply add 212 0x7, 0, ebx, 23, clflushopt , CLFLUSHOPT instruction 213 0x7, 0, ebx, 24, clwb , CLWB instruction 214 0x7, 0, ebx, 25, intel_pt , Intel processor trace 215 0x7, 0, ebx, 26, avx512pf , AVX-512 prefetch instructions 216 0x7, 0, ebx, 27, avx512er , AVX-512 exponent/reciprocal instructions 217 0x7, 0, ebx, 28, avx512cd , AVX-512 conflict detection instructions 218 0x7, 0, ebx, 29, sha_ni , SHA/SHA256 instructions 219 0x7, 0, ebx, 30, avx512bw , AVX-512 byte/word instructions 220 0x7, 0, ebx, 31, avx512vl , AVX-512 VL (128/256 vector length) extensions 221 0x7, 0, ecx, 0, prefetchwt1 , PREFETCHWT1 (Intel Xeon Phi only) 222 0x7, 0, ecx, 1, avx512vbmi , AVX-512 Vector byte manipulation instructions 223 0x7, 0, ecx, 2, umip , User mode instruction protection 224 0x7, 0, ecx, 3, pku , Protection keys for user-space 225 0x7, 0, ecx, 4, ospke , OS protection keys enable 226 0x7, 0, ecx, 5, waitpkg , WAITPKG instructions 227 0x7, 0, ecx, 6, avx512_vbmi2 , AVX-512 vector byte manipulation instructions group 2 228 0x7, 0, ecx, 7, cet_ss , CET shadow stack features 229 0x7, 0, ecx, 8, gfni , Galois field new instructions 230 0x7, 0, ecx, 9, vaes , Vector AES instructions 231 0x7, 0, ecx, 10, vpclmulqdq , VPCLMULQDQ 256-bit instruction 232 0x7, 0, ecx, 11, avx512_vnni , Vector neural network instructions 233 0x7, 0, ecx, 12, avx512_bitalg , AVX-512 bitwise algorithms 234 0x7, 0, ecx, 13, tme , Intel total memory encryption 235 0x7, 0, ecx, 14, avx512_vpopcntdq , AVX-512: POPCNT for vectors of DWORD/QWORD 236 0x7, 0, ecx, 16, la57 , 57-bit linear addresses (five-level paging) 237 0x7, 0, ecx, 21:17, mawau_val_lm , BNDLDX/BNDSTX MAWAU value in 64-bit mode 238 0x7, 0, ecx, 22, rdpid , RDPID instruction 239 0x7, 0, ecx, 23, key_locker , Intel key locker 240 0x7, 0, ecx, 24, bus_lock_detect , OS bus-lock detection 241 0x7, 0, ecx, 25, cldemote , CLDEMOTE instruction 242 0x7, 0, ecx, 27, movdiri , MOVDIRI instruction 243 0x7, 0, ecx, 28, movdir64b , MOVDIR64B instruction 244 0x7, 0, ecx, 29, enqcmd , Enqueue stores (ENQCMD{,S}) 245 0x7, 0, ecx, 30, sgx_lc , Intel SGX launch configuration 246 0x7, 0, ecx, 31, pks , Protection keys for supervisor-mode pages 247 0x7, 0, edx, 1, sgx_keys , Intel SGX attestation services 248 0x7, 0, edx, 2, avx512_4vnniw , AVX-512 neural network instructions 249 0x7, 0, edx, 3, avx512_4fmaps , AVX-512 multiply accumulation single precision 250 0x7, 0, edx, 4, fsrm , Fast short REP MOV 251 0x7, 0, edx, 5, uintr , User interrupts 252 0x7, 0, edx, 8, avx512_vp2intersect , VP2INTERSECT{D,Q} instructions 253 0x7, 0, edx, 9, srdbs_ctrl , SRBDS mitigation MSR 254 0x7, 0, edx, 10, md_clear , VERW MD_CLEAR microcode 255 0x7, 0, edx, 11, rtm_always_abort , XBEGIN (RTM transaction) always aborts 256 0x7, 0, edx, 13, tsx_force_abort , MSR TSX_FORCE_ABORT, RTM_ABORT bit 257 0x7, 0, edx, 14, serialize , SERIALIZE instruction 258 0x7, 0, edx, 15, hybrid_cpu , The CPU is identified as a 'hybrid part' 259 0x7, 0, edx, 16, tsxldtrk , TSX suspend/resume load address tracking 260 0x7, 0, edx, 18, pconfig , PCONFIG instruction 261 0x7, 0, edx, 19, arch_lbr , Intel architectural LBRs 262 0x7, 0, edx, 20, ibt , CET indirect branch tracking 263 0x7, 0, edx, 22, amx_bf16 , AMX-BF16: tile bfloat16 264 0x7, 0, edx, 23, avx512_fp16 , AVX-512 FP16 instructions 265 0x7, 0, edx, 24, amx_tile , AMX-TILE: tile architecture 266 0x7, 0, edx, 25, amx_int8 , AMX-INT8: tile 8-bit integer 267 0x7, 0, edx, 26, spec_ctrl , Speculation Control (IBRS/IBPB: indirect branch restrictions) 268 0x7, 0, edx, 27, intel_stibp , Single thread indirect branch predictors 269 0x7, 0, edx, 28, flush_l1d , FLUSH L1D cache: IA32_FLUSH_CMD MSR 270 0x7, 0, edx, 29, arch_capabilities , Intel IA32_ARCH_CAPABILITIES MSR 271 0x7, 0, edx, 30, core_capabilities , IA32_CORE_CAPABILITIES MSR 272 0x7, 0, edx, 31, spec_ctrl_ssbd , Speculative store bypass disable 273 0x7, 1, eax, 4, avx_vnni , AVX-VNNI instructions 274 0x7, 1, eax, 5, avx512_bf16 , AVX-512 bfloat16 instructions 275 0x7, 1, eax, 6, lass , Linear address space separation 276 0x7, 1, eax, 7, cmpccxadd , CMPccXADD instructions 277 0x7, 1, eax, 8, arch_perfmon_ext , ArchPerfmonExt: leaf 0x23 278 0x7, 1, eax, 10, fzrm , Fast zero-length REP MOVSB 279 0x7, 1, eax, 11, fsrs , Fast short REP STOSB 280 0x7, 1, eax, 12, fsrc , Fast Short REP CMPSB/SCASB 281 0x7, 1, eax, 17, fred , FRED: Flexible return and event delivery transitions 282 0x7, 1, eax, 18, lkgs , LKGS: Load 'kernel' (userspace) GS 283 0x7, 1, eax, 19, wrmsrns , WRMSRNS instruction (WRMSR-non-serializing) 284 0x7, 1, eax, 20, nmi_src , NMI-source reporting with FRED event data 285 0x7, 1, eax, 21, amx_fp16 , AMX-FP16: FP16 tile operations 286 0x7, 1, eax, 22, hreset , HRESET (Thread director history reset) 287 0x7, 1, eax, 23, avx_ifma , Integer fused multiply add 288 0x7, 1, eax, 26, lam , Linear address masking 289 0x7, 1, eax, 27, rd_wr_msrlist , RDMSRLIST/WRMSRLIST instructions 290 0x7, 1, ebx, 0, intel_ppin , Protected processor inventory number (PPIN{,_CTL} MSRs) 291 0x7, 1, edx, 4, avx_vnni_int8 , AVX-VNNI-INT8 instructions 292 0x7, 1, edx, 5, avx_ne_convert , AVX-NE-CONVERT instructions 293 0x7, 1, edx, 8, amx_complex , AMX-COMPLEX instructions (starting from Granite Rapids) 294 0x7, 1, edx, 14, prefetchit_0_1 , PREFETCHIT0/1 instructions 295 0x7, 1, edx, 18, cet_sss , CET supervisor shadow stacks safe to use 296 0x7, 2, edx, 0, intel_psfd , Intel predictive store forward disable 297 0x7, 2, edx, 1, ipred_ctrl , MSR bits IA32_SPEC_CTRL.IPRED_DIS_{U,S} 298 0x7, 2, edx, 2, rrsba_ctrl , MSR bits IA32_SPEC_CTRL.RRSBA_DIS_{U,S} 299 0x7, 2, edx, 3, ddp_ctrl , MSR bit IA32_SPEC_CTRL.DDPD_U 300 0x7, 2, edx, 4, bhi_ctrl , MSR bit IA32_SPEC_CTRL.BHI_DIS_S 301 0x7, 2, edx, 5, mcdt_no , MCDT mitigation not needed 302 0x7, 2, edx, 6, uclock_disable , UC-lock disable 303 304# Leaf 9H 305# Intel DCA (Direct Cache Access) 306 307 0x9, 0, eax, 0, dca_enabled_in_bios , DCA is enabled in BIOS 308 309# Leaf AH 310# Intel PMU (Performance Monitoring Unit) 311 312 0xa, 0, eax, 7:0, pmu_version , Performance monitoring unit version ID 313 0xa, 0, eax, 15:8, num_counters_gp , Number of general-purpose PMU counters per logical CPU 314 0xa, 0, eax, 23:16, bit_width_gp , Bitwidth of PMU general-purpose counters 315 0xa, 0, eax, 31:24, events_mask_len , Length of CPUID(0xa).EBX bit vector 316 0xa, 0, ebx, 0, no_core_cycle , Core cycle event not available 317 0xa, 0, ebx, 1, no_instruction_retired , Instruction retired event not available 318 0xa, 0, ebx, 2, no_reference_cycles , Reference cycles event not available 319 0xa, 0, ebx, 3, no_llc_reference , LLC-reference event not available 320 0xa, 0, ebx, 4, no_llc_misses , LLC-misses event not available 321 0xa, 0, ebx, 5, no_br_insn_retired , Branch instruction retired event not available 322 0xa, 0, ebx, 6, no_br_misses_retired , Branch mispredict retired event not available 323 0xa, 0, ebx, 7, no_topdown_slots , Topdown slots event not available 324 0xa, 0, ebx, 8, no_backend_bound , Topdown backend bound not available 325 0xa, 0, ebx, 9, no_bad_speculation , Topdown bad speculation not available 326 0xa, 0, ebx, 10, no_frontend_bound , Topdown frontend bound not available 327 0xa, 0, ebx, 11, no_retiring , Topdown retiring not available 328 0xa, 0, ebx, 12, no_lbr_inserts , LBR inserts not available 329 0xa, 0, ecx, 31:0, pmu_fcounters_bitmap , Fixed-function PMU counters support bitmap 330 0xa, 0, edx, 4:0, num_counters_fixed , Number of fixed PMU counters 331 0xa, 0, edx, 12:5, bitwidth_fixed , Bitwidth of PMU fixed counters 332 0xa, 0, edx, 15, anythread_deprecation , AnyThread mode deprecation 333 334# Leaf BH 335# CPU extended topology v1 336 337 0xb, 1:0, eax, 4:0, x2apic_id_shift , Bit width of this level (previous levels inclusive) 338 0xb, 1:0, ebx, 15:0, domain_lcpus_count , Logical CPUs count across all instances of this domain 339 0xb, 1:0, ecx, 7:0, domain_nr , This domain level (subleaf ID) 340 0xb, 1:0, ecx, 15:8, domain_type , This domain type 341 0xb, 1:0, edx, 31:0, x2apic_id , x2APIC ID of current logical CPU 342 343# Leaf DH 344# CPU extended state 345 346 0xd, 0, eax, 0, xcr0_x87 , XCR0.X87 347 0xd, 0, eax, 1, xcr0_sse , XCR0.SSE 348 0xd, 0, eax, 2, xcr0_avx , XCR0.AVX 349 0xd, 0, eax, 3, xcr0_mpx_bndregs , XCR0.BNDREGS: MPX BND0-BND3 registers 350 0xd, 0, eax, 4, xcr0_mpx_bndcsr , XCR0.BNDCSR: MPX BNDCFGU/BNDSTATUS registers 351 0xd, 0, eax, 5, xcr0_avx512_opmask , XCR0.OPMASK: AVX-512 k0-k7 registers 352 0xd, 0, eax, 6, xcr0_avx512_zmm_hi256 , XCR0.ZMM_Hi256: AVX-512 ZMM0->ZMM7/15 registers 353 0xd, 0, eax, 7, xcr0_avx512_hi16_zmm , XCR0.HI16_ZMM: AVX-512 ZMM16->ZMM31 registers 354 0xd, 0, eax, 9, xcr0_pkru , XCR0.PKRU: XSAVE PKRU registers 355 0xd, 0, eax, 11, xcr0_cet_u , XCR0.CET_U: CET user state 356 0xd, 0, eax, 12, xcr0_cet_s , XCR0.CET_S: CET supervisor state 357 0xd, 0, eax, 17, xcr0_tileconfig , XCR0.TILECONFIG: AMX can manage TILECONFIG 358 0xd, 0, eax, 18, xcr0_tiledata , XCR0.TILEDATA: AMX can manage TILEDATA 359 0xd, 0, ebx, 31:0, xsave_sz_xcr0 , XSAVE/XRSTOR area byte size, for XCR0 enabled features 360 0xd, 0, ecx, 31:0, xsave_sz_max , XSAVE/XRSTOR area max byte size, all CPU features 361 0xd, 0, edx, 30, xcr0_lwp , AMD XCR0.LWP: Light-weight Profiling 362 0xd, 1, eax, 0, xsaveopt , XSAVEOPT instruction 363 0xd, 1, eax, 1, xsavec , XSAVEC instruction 364 0xd, 1, eax, 2, xgetbv1 , XGETBV instruction with ECX = 1 365 0xd, 1, eax, 3, xsaves , XSAVES/XRSTORS instructions (and XSS MSR) 366 0xd, 1, eax, 4, xfd , Extended feature disable 367 0xd, 1, ebx, 31:0, xsave_sz_xcr0_xss , XSAVES/XSAVEC area byte size, for XCR0|XSS enabled features 368 0xd, 1, ecx, 8, xss_pt , PT state 369 0xd, 1, ecx, 10, xss_pasid , PASID state 370 0xd, 1, ecx, 11, xss_cet_u , CET user state 371 0xd, 1, ecx, 12, xss_cet_p , CET supervisor state 372 0xd, 1, ecx, 13, xss_hdc , HDC state 373 0xd, 1, ecx, 14, xss_uintr , UINTR state 374 0xd, 1, ecx, 15, xss_lbr , LBR state 375 0xd, 1, ecx, 16, xss_hwp , HWP state 376 0xd, 63:2, eax, 31:0, xsave_sz , Subleaf-N feature save area size, in bytes 377 0xd, 63:2, ebx, 31:0, xsave_offset , Subleaf-N feature save area offset, in bytes 378 0xd, 63:2, ecx, 0, is_xss_bit , Subleaf N describes an XSS bit (otherwise XCR0) 379 0xd, 63:2, ecx, 1, compacted_xsave_64byte_aligned, When compacted, subleaf-N XSAVE area is 64-byte aligned 380 381# Leaf FH 382# Intel RDT / AMD PQoS resource monitoring 383 384 0xf, 0, ebx, 31:0, core_rmid_max , RMID max within this core (0-based) 385 0xf, 0, edx, 1, cqm_llc , LLC QoS-monitoring 386 0xf, 1, eax, 7:0, l3c_qm_bitwidth , L3 QoS-monitoring counter bitwidth (24-based) 387 0xf, 1, eax, 8, l3c_qm_overflow_bit , QM_CTR MSR bit 61 is an overflow bit 388 0xf, 1, eax, 9, io_rdt_cmt , non-CPU agent supporting Intel RDT CMT present 389 0xf, 1, eax, 10, io_rdt_mbm , non-CPU agent supporting Intel RDT MBM present 390 0xf, 1, ebx, 31:0, l3c_qm_conver_factor , QM_CTR MSR conversion factor to bytes 391 0xf, 1, ecx, 31:0, l3c_qm_rmid_max , L3 QoS-monitoring max RMID 392 0xf, 1, edx, 0, cqm_occup_llc , L3 QoS occupancy monitoring 393 0xf, 1, edx, 1, cqm_mbm_total , L3 QoS total bandwidth monitoring 394 0xf, 1, edx, 2, cqm_mbm_local , L3 QoS local bandwidth monitoring 395 396# Leaf 10H 397# Intel RDT / AMD PQoS allocation 398 399 0x10, 0, ebx, 1, cat_l3 , L3 Cache Allocation Technology 400 0x10, 0, ebx, 2, cat_l2 , L2 Cache Allocation Technology 401 0x10, 0, ebx, 3, mba , Memory Bandwidth Allocation 402 0x10, 2:1, eax, 4:0, cat_cbm_len , L3/L2_CAT capacity bitmask length, minus-one notation 403 0x10, 2:1, ebx, 31:0, cat_units_bitmap , L3/L2_CAT allocation units bitmap 404 0x10, 2:1, ecx, 1, l3_cat_cos_infreq_updates, L3_CAT COS updates should be infrequent 405 0x10, 2:1, ecx, 2, cdp_l3 , L3/L2_CAT Code and Data Prioritization 406 0x10, 2:1, ecx, 3, cat_sparse_1s , L3/L2_CAT non-contiguous 1s value 407 0x10, 2:1, edx, 15:0, cat_cos_max , L3/L2_CAT max Class of Service 408 0x10, 3, eax, 11:0, mba_max_delay , Max MBA throttling value; minus-one notation 409 0x10, 3, ecx, 0, per_thread_mba , Per-thread MBA controls 410 0x10, 3, ecx, 2, mba_delay_linear , Delay values are linear 411 0x10, 3, edx, 15:0, mba_cos_max , MBA max Class of Service 412 413# Leaf 12H 414# Intel SGX (Software Guard Extensions) 415 416 0x12, 0, eax, 0, sgx1 , SGX1 leaf functions 417 0x12, 0, eax, 1, sgx2 , SGX2 leaf functions 418 0x12, 0, eax, 5, enclv_leaves , ENCLV leaves 419 0x12, 0, eax, 6, encls_leaves , ENCLS leaves 420 0x12, 0, eax, 7, enclu_everifyreport2 , ENCLU leaf EVERIFYREPORT2 421 0x12, 0, eax, 10, encls_eupdatesvn , ENCLS leaf EUPDATESVN 422 0x12, 0, eax, 11, sgx_edeccssa , ENCLU leaf EDECCSSA 423 0x12, 0, ebx, 0, miscselect_exinfo , SSA.MISC frame: Enclave #PF and #GP reporting 424 0x12, 0, ebx, 1, miscselect_cpinfo , SSA.MISC frame: Enclave #CP reporting 425 0x12, 0, edx, 7:0, max_enclave_sz_not64 , Maximum enclave size in non-64-bit mode (log2) 426 0x12, 0, edx, 15:8, max_enclave_sz_64 , Maximum enclave size in 64-bit mode (log2) 427 0x12, 1, eax, 0, secs_attr_init , Enclave initialized by EINIT 428 0x12, 1, eax, 1, secs_attr_debug , Enclave permits debugger read/write 429 0x12, 1, eax, 2, secs_attr_mode64bit , Enclave runs in 64-bit mode 430 0x12, 1, eax, 4, secs_attr_provisionkey , Provisioning key 431 0x12, 1, eax, 5, secs_attr_einittoken_key, EINIT token key 432 0x12, 1, eax, 6, secs_attr_cet , CET attributes 433 0x12, 1, eax, 7, secs_attr_kss , Key Separation and Sharing 434 0x12, 1, eax, 10, secs_attr_aexnotify , Enclave threads: AEX notifications 435 0x12, 1, ecx, 0, xfrm_x87 , Enclave XFRM.X87 436 0x12, 1, ecx, 1, xfrm_sse , Enclave XFRM.SEE 437 0x12, 1, ecx, 2, xfrm_avx , Enclave XFRM.AVX 438 0x12, 1, ecx, 3, xfrm_mpx_bndregs , Enclave XFRM.BNDREGS (MPX BND0-BND3 registers) 439 0x12, 1, ecx, 4, xfrm_mpx_bndcsr , Enclave XFRM.BNDCSR (MPX BNDCFGU/BNDSTATUS registers) 440 0x12, 1, ecx, 5, xfrm_avx512_opmask , Enclave XFRM.OPMASK (AVX-512 k0-k7 registers) 441 0x12, 1, ecx, 6, xfrm_avx512_zmm_hi256 , Enclave XFRM.ZMM_Hi256 (AVX-512 ZMM0->ZMM7/15 registers) 442 0x12, 1, ecx, 7, xfrm_avx512_hi16_zmm , Enclave XFRM.HI16_ZMM (AVX-512 ZMM16->ZMM31 registers) 443 0x12, 1, ecx, 9, xfrm_pkru , Enclave XFRM.PKRU (XSAVE PKRU registers) 444 0x12, 1, ecx, 17, xfrm_tileconfig , Enclave XFRM.TILECONFIG (AMX can manage TILECONFIG) 445 0x12, 1, ecx, 18, xfrm_tiledata , Enclave XFRM.TILEDATA (AMX can manage TILEDATA) 446 0x12, 31:2, eax, 3:0, subleaf_type , Subleaf type 447 0x12, 31:2, eax, 31:12, epc_sec_base_addr_0 , EPC section base address, bits[12:31] 448 0x12, 31:2, ebx, 19:0, epc_sec_base_addr_1 , EPC section base address, bits[32:51] 449 0x12, 31:2, ecx, 3:0, epc_sec_type , EPC section type / property encoding 450 0x12, 31:2, ecx, 31:12, epc_sec_size_0 , EPC section size, bits[12:31] 451 0x12, 31:2, edx, 19:0, epc_sec_size_1 , EPC section size, bits[32:51] 452 453# Leaf 14H 454# Intel Processor Trace 455 456 0x14, 0, eax, 31:0, pt_max_subleaf , Maximum leaf 0x14 subleaf 457 0x14, 0, ebx, 0, cr3_filtering , IA32_RTIT_CR3_MATCH is accessible 458 0x14, 0, ebx, 1, psb_cyc , Configurable PSB and cycle-accurate mode 459 0x14, 0, ebx, 2, ip_filtering , IP/TraceStop filtering; Warm-reset PT MSRs preservation 460 0x14, 0, ebx, 3, mtc_timing , MTC timing packet; COFI-based packets suppression 461 0x14, 0, ebx, 4, ptwrite , PTWRITE instruction 462 0x14, 0, ebx, 5, power_event_trace , Power Event Trace 463 0x14, 0, ebx, 6, psb_pmi_preserve , PSB and PMI preservation 464 0x14, 0, ebx, 7, event_trace , Event Trace packet generation 465 0x14, 0, ebx, 8, tnt_disable , TNT packet generation disable 466 0x14, 0, ecx, 0, topa_output , ToPA output scheme 467 0x14, 0, ecx, 1, topa_multiple_entries , ToPA tables can hold multiple entries 468 0x14, 0, ecx, 2, single_range_output , Single-range output 469 0x14, 0, ecx, 3, trance_transport_output, Trace Transport subsystem output 470 0x14, 0, ecx, 31, ip_payloads_lip , IP payloads have LIP values (CS base included) 471 0x14, 1, eax, 2:0, num_address_ranges , Number of configurable Address Ranges 472 0x14, 1, eax, 31:16, mtc_periods_bmp , MTC period encodings bitmap 473 0x14, 1, ebx, 15:0, cycle_thresholds_bmp , Cycle Threshold encodings bitmap 474 0x14, 1, ebx, 31:16, psb_periods_bmp , Configurable PSB frequency encodings bitmap 475 476# Leaf 15H 477# Intel TSC (Time Stamp Counter) 478 479 0x15, 0, eax, 31:0, tsc_denominator , Denominator of the TSC/'core crystal clock' ratio 480 0x15, 0, ebx, 31:0, tsc_numerator , Numerator of the TSC/'core crystal clock' ratio 481 0x15, 0, ecx, 31:0, cpu_crystal_hz , Core crystal clock nominal frequency, in Hz 482 483# Leaf 16H 484# Intel processor frequency 485 486 0x16, 0, eax, 15:0, cpu_base_mhz , Processor base frequency, in MHz 487 0x16, 0, ebx, 15:0, cpu_max_mhz , Processor max frequency, in MHz 488 0x16, 0, ecx, 15:0, bus_mhz , Bus reference frequency, in MHz 489 490# Leaf 17H 491# Intel SoC vendor attributes 492 493 0x17, 0, eax, 31:0, soc_max_subleaf , Maximum leaf 0x17 subleaf 494 0x17, 0, ebx, 15:0, soc_vendor_id , SoC vendor ID 495 0x17, 0, ebx, 16, is_vendor_scheme , Assigned by industry enumeration scheme (not Intel) 496 0x17, 0, ecx, 31:0, soc_proj_id , SoC project ID, assigned by vendor 497 0x17, 0, edx, 31:0, soc_stepping_id , Soc project stepping ID, assigned by vendor 498 0x17, 3:1, eax, 31:0, vendor_brand_a , Vendor Brand ID string, bytes subleaf_nr * (0 -> 3) 499 0x17, 3:1, ebx, 31:0, vendor_brand_b , Vendor Brand ID string, bytes subleaf_nr * (4 -> 7) 500 0x17, 3:1, ecx, 31:0, vendor_brand_c , Vendor Brand ID string, bytes subleaf_nr * (8 -> 11) 501 0x17, 3:1, edx, 31:0, vendor_brand_d , Vendor Brand ID string, bytes subleaf_nr * (12 -> 15) 502 503# Leaf 18H 504# Intel deterministic address translation (TLB) parameters 505 506 0x18, 31:0, eax, 31:0, tlb_max_subleaf , Maximum leaf 0x18 subleaf 507 0x18, 31:0, ebx, 0, tlb_4k_page , TLB supports 4KB-page entries 508 0x18, 31:0, ebx, 1, tlb_2m_page , TLB supports 2MB-page entries 509 0x18, 31:0, ebx, 2, tlb_4m_page , TLB supports 4MB-page entries 510 0x18, 31:0, ebx, 3, tlb_1g_page , TLB supports 1GB-page entries 511 0x18, 31:0, ebx, 10:8, hard_partitioning , Partitioning between logical CPUs 512 0x18, 31:0, ebx, 31:16, n_way_associative , Ways of associativity 513 0x18, 31:0, ecx, 31:0, n_sets , Number of sets 514 0x18, 31:0, edx, 4:0, tlb_type , Translation cache type (TLB type) 515 0x18, 31:0, edx, 7:5, tlb_cache_level , Translation cache level (1-based) 516 0x18, 31:0, edx, 8, is_fully_associative , Fully-associative 517 0x18, 31:0, edx, 25:14, tlb_max_addressible_ids, Max number of addressable IDs - 1 518 519# Leaf 19H 520# Intel key locker 521 522 0x19, 0, eax, 0, kl_cpl0_only , CPL0-only key Locker restriction 523 0x19, 0, eax, 1, kl_no_encrypt , No-encrypt key locker restriction 524 0x19, 0, eax, 2, kl_no_decrypt , No-decrypt key locker restriction 525 0x19, 0, ebx, 0, aes_keylocker , AES key locker instructions 526 0x19, 0, ebx, 2, aes_keylocker_wide , AES wide key locker instructions 527 0x19, 0, ebx, 4, kl_msr_iwkey , Key locker MSRs and IWKEY backups 528 0x19, 0, ecx, 0, loadiwkey_no_backup , LOADIWKEY NoBackup parameter 529 0x19, 0, ecx, 1, iwkey_rand , IWKEY randomization 530 531# Leaf 1AH 532# Intel hybrid CPUs identification (e.g. Atom, Core) 533 534 0x1a, 0, eax, 23:0, core_native_model , This core's native model ID 535 0x1a, 0, eax, 31:24, core_type , This core's type 536 537# Leaf 1BH 538# Intel PCONFIG (Platform configuration) 539 540 0x1b, 31:0, eax, 11:0, pconfig_subleaf_type , CPUID 0x1b subleaf type 541 0x1b, 31:0, ebx, 31:0, pconfig_target_id_x , A supported PCONFIG target ID 542 0x1b, 31:0, ecx, 31:0, pconfig_target_id_y , A supported PCONFIG target ID 543 0x1b, 31:0, edx, 31:0, pconfig_target_id_z , A supported PCONFIG target ID 544 545# Leaf 1CH 546# Intel LBR (Last Branch Record) 547 548 0x1c, 0, eax, 7:0, lbr_depth_mask , Max LBR stack depth bitmask 549 0x1c, 0, eax, 30, lbr_deep_c_reset , LBRs maybe cleared on MWAIT C-state > C1 550 0x1c, 0, eax, 31, lbr_ip_is_lip , LBR IP contain Last IP (otherwise effective IP) 551 0x1c, 0, ebx, 0, lbr_cpl , CPL filtering 552 0x1c, 0, ebx, 1, lbr_branch_filter , Branch filtering 553 0x1c, 0, ebx, 2, lbr_call_stack , Call-stack mode 554 0x1c, 0, ecx, 0, lbr_mispredict , Branch misprediction bit 555 0x1c, 0, ecx, 1, lbr_timed_lbr , Timed LBRs (CPU cycles since last LBR entry) 556 0x1c, 0, ecx, 2, lbr_branch_type , Branch type field 557 0x1c, 0, ecx, 19:16, lbr_events_gpc_bmp , PMU-events logging support 558 559# Leaf 1DH 560# Intel AMX (Advanced Matrix Extensions) tile information 561 562 0x1d, 0, eax, 31:0, amx_max_palette , Highest palette ID / subleaf ID 563 0x1d, 1, eax, 15:0, amx_palette_size , AMX palette total tiles size, in bytes 564 0x1d, 1, eax, 31:16, amx_tile_size , AMX single tile's size, in bytes 565 0x1d, 1, ebx, 15:0, amx_tile_row_size , AMX tile single row's size, in bytes 566 0x1d, 1, ebx, 31:16, amx_palette_nr_tiles , AMX palette number of tiles 567 0x1d, 1, ecx, 15:0, amx_tile_nr_rows , AMX tile max number of rows 568 569# Leaf 1EH 570# Intel TMUL (Tile-matrix Multiply) 571 572 0x1e, 0, ebx, 7:0, tmul_maxk , TMUL unit maximum height, K (rows or columns) 573 0x1e, 0, ebx, 23:8, tmul_maxn , TMUL unit maximum SIMD dimension, N (column bytes) 574 575# Leaf 1FH 576# Intel extended topology v2 577 578 0x1f, 5:0, eax, 4:0, x2apic_id_shift , Bit width of this level (previous levels inclusive) 579 0x1f, 5:0, ebx, 15:0, domain_lcpus_count , Logical CPUs count across all instances of this domain 580 0x1f, 5:0, ecx, 7:0, domain_level , This domain level (subleaf ID) 581 0x1f, 5:0, ecx, 15:8, domain_type , This domain type 582 0x1f, 5:0, edx, 31:0, x2apic_id , x2APIC ID of current logical CPU 583 584# Leaf 20H 585# Intel HRESET (History Reset) 586 587 0x20, 0, eax, 31:0, hreset_nr_subleaves , CPUID 0x20 max subleaf + 1 588 0x20, 0, ebx, 0, hreset_thread_director , Intel thread director HRESET 589 590# Leaf 21H 591# Intel TD (Trust Domain) 592 593 0x21, 0, ebx, 31:0, tdx_vendorid_0 , TDX vendor ID string bytes 0 - 3 594 0x21, 0, ecx, 31:0, tdx_vendorid_2 , CPU vendor ID string bytes 8 - 11 595 0x21, 0, edx, 31:0, tdx_vendorid_1 , CPU vendor ID string bytes 4 - 7 596 597# Leaf 23H 598# Intel Architectural Performance Monitoring Extended (ArchPerfmonExt) 599 600 0x23, 0, eax, 0, subleaf_0 , Subleaf 0, this subleaf 601 0x23, 0, eax, 1, counters_subleaf , Subleaf 1, PMU counter bitmaps 602 0x23, 0, eax, 2, acr_subleaf , Subleaf 2, Auto Counter Reload bitmaps 603 0x23, 0, eax, 3, events_subleaf , Subleaf 3, PMU event bitmaps 604 0x23, 0, eax, 4, pebs_caps_subleaf , Subleaf 4, PEBS capabilities 605 0x23, 0, eax, 5, pebs_subleaf , Subleaf 5, Arch PEBS bitmaps 606 0x23, 0, ebx, 0, unitmask2 , IA32_PERFEVTSELx MSRs UnitMask2 bit 607 0x23, 0, ebx, 1, eq , IA32_PERFEVTSELx MSRs EQ bit 608 0x23, 0, ebx, 2, rdpmc_user_disable , RDPMC userspace disable 609 0x23, 1, eax, 31:0, gp_counters , Bitmap of general-purpose PMU counters 610 0x23, 1, ebx, 31:0, fixed_counters , Bitmap of fixed PMU counters 611 0x23, 2, eax, 31:0, acr_gp_reload , Bitmap of general-purpose counters that can be reloaded 612 0x23, 2, ebx, 31:0, acr_fixed_reload , Bitmap of fixed counters that can be reloaded 613 0x23, 2, ecx, 31:0, acr_gp_trigger , Bitmap of general-purpose counters that can trigger reloads 614 0x23, 2, edx, 31:0, acr_fixed_trigger , Bitmap of fixed counters that can trigger reloads 615 0x23, 3, eax, 0, core_cycles_evt , Core cycles event 616 0x23, 3, eax, 1, insn_retired_evt , Instructions retired event 617 0x23, 3, eax, 2, ref_cycles_evt , Reference cycles event 618 0x23, 3, eax, 3, llc_refs_evt , Last-level cache references event 619 0x23, 3, eax, 4, llc_misses_evt , Last-level cache misses event 620 0x23, 3, eax, 5, br_insn_ret_evt , Branch instruction retired event 621 0x23, 3, eax, 6, br_mispr_evt , Branch mispredict retired event 622 0x23, 3, eax, 7, td_slots_evt , Topdown slots event 623 0x23, 3, eax, 8, td_backend_bound_evt , Topdown backend bound event 624 0x23, 3, eax, 9, td_bad_spec_evt , Topdown bad speculation event 625 0x23, 3, eax, 10, td_frontend_bound_evt , Topdown frontend bound event 626 0x23, 3, eax, 11, td_retiring_evt , Topdown retiring event 627 0x23, 4, ebx, 3, allow_in_record , ALLOW_IN_RECORD bit in MSRs 628 0x23, 4, ebx, 4, counters_gp , Counters group sub-group general-purpose counters 629 0x23, 4, ebx, 5, counters_fixed , Counters group sub-group fixed-function counters 630 0x23, 4, ebx, 6, counters_metrics , Counters group sub-group performance metrics 631 0x23, 4, ebx, 9:8, lbr , LBR group 632 0x23, 4, ebx, 23:16, xer , XER group 633 0x23, 4, ebx, 29, gpr , GPR group 634 0x23, 4, ebx, 30, aux , AUX group 635 0x23, 5, eax, 31:0, pebs_gp , Architectural PEBS general-purpose counters 636 0x23, 5, ebx, 31:0, pebs_pdist_gp , Architectural PEBS PDIST general-purpose counters 637 0x23, 5, ecx, 31:0, pebs_fixed , Architectural PEBS fixed counters 638 0x23, 5, edx, 31:0, pebs_pdist_fixed , Architectural PEBS PDIST fixed counters 639 640# Leaf 40000000H 641# Maximum hypervisor leaf + hypervisor vendor string 642 6430x40000000, 0, eax, 31:0, max_hyp_leaf , Maximum hypervisor leaf 6440x40000000, 0, ebx, 31:0, hypervisor_id_0 , Hypervisor ID string bytes 0 - 3 6450x40000000, 0, ecx, 31:0, hypervisor_id_1 , Hypervisor ID string bytes 4 - 7 6460x40000000, 0, edx, 31:0, hypervisor_id_2 , Hypervisor ID string bytes 8 - 11 647 648# Leaf 80000000H 649# Maximum extended leaf + CPU vendor string 650 6510x80000000, 0, eax, 31:0, max_ext_leaf , Maximum extended CPUID leaf 6520x80000000, 0, ebx, 31:0, cpu_vendorid_0 , Vendor ID string bytes 0 - 3 6530x80000000, 0, ecx, 31:0, cpu_vendorid_2 , Vendor ID string bytes 8 - 11 6540x80000000, 0, edx, 31:0, cpu_vendorid_1 , Vendor ID string bytes 4 - 7 655 656# Leaf 80000001H 657# Extended CPU features 658 6590x80000001, 0, eax, 3:0, e_stepping_id , Stepping ID 6600x80000001, 0, eax, 7:4, e_base_model , Base processor model 6610x80000001, 0, eax, 11:8, e_base_family , Base processor family 6620x80000001, 0, eax, 13:12, e_base_type , Base processor type (Transmeta) 6630x80000001, 0, eax, 19:16, e_ext_model , Extended processor model 6640x80000001, 0, eax, 27:20, e_ext_family , Extended processor family 6650x80000001, 0, ebx, 15:0, brand_id , Brand ID 6660x80000001, 0, ebx, 31:28, pkg_type , Package type 6670x80000001, 0, ecx, 0, lahf_lm , LAHF and SAHF in 64-bit mode 6680x80000001, 0, ecx, 1, cmp_legacy , Multi-processing legacy mode (No HT) 6690x80000001, 0, ecx, 2, svm , Secure Virtual Machine 6700x80000001, 0, ecx, 3, extapic , Extended APIC space 6710x80000001, 0, ecx, 4, cr8_legacy , LOCK MOV CR0 means MOV CR8 6720x80000001, 0, ecx, 5, abm , LZCNT advanced bit manipulation 6730x80000001, 0, ecx, 6, sse4a , SSE4A support 6740x80000001, 0, ecx, 7, misalignsse , Misaligned SSE mode 6750x80000001, 0, ecx, 8, 3dnowprefetch , 3DNow PREFETCH/PREFETCHW support 6760x80000001, 0, ecx, 9, osvw , OS visible workaround 6770x80000001, 0, ecx, 10, ibs , Instruction based sampling 6780x80000001, 0, ecx, 11, xop , XOP: extended operation (AVX instructions) 6790x80000001, 0, ecx, 12, skinit , SKINIT/STGI support 6800x80000001, 0, ecx, 13, wdt , Watchdog timer support 6810x80000001, 0, ecx, 15, lwp , Lightweight profiling 6820x80000001, 0, ecx, 16, fma4 , 4-operand FMA instruction 6830x80000001, 0, ecx, 17, tce , Translation cache extension 6840x80000001, 0, ecx, 19, nodeid_msr , NodeId MSR (0xc001100c) 6850x80000001, 0, ecx, 21, tbm , Trailing bit manipulations 6860x80000001, 0, ecx, 22, topoext , Topology Extensions (leaf 0x8000001d) 6870x80000001, 0, ecx, 23, perfctr_core , Core performance counter extensions 6880x80000001, 0, ecx, 24, perfctr_nb , NB/DF performance counter extensions 6890x80000001, 0, ecx, 26, bpext , Data access breakpoint extension 6900x80000001, 0, ecx, 27, ptsc , Performance time-stamp counter 6910x80000001, 0, ecx, 28, perfctr_llc , LLC (L3) performance counter extensions 6920x80000001, 0, ecx, 29, mwaitx , MWAITX/MONITORX support 6930x80000001, 0, ecx, 30, addr_mask_ext , Breakpoint address mask extension (to bit 31) 6940x80000001, 0, edx, 0, e_fpu , Floating-Point Unit on-chip (x87) 6950x80000001, 0, edx, 1, e_vme , Virtual-8086 Mode Extensions 6960x80000001, 0, edx, 2, e_de , Debugging Extensions 6970x80000001, 0, edx, 3, e_pse , Page Size Extension 6980x80000001, 0, edx, 4, e_tsc , Time Stamp Counter 6990x80000001, 0, edx, 5, e_msr , Model-Specific Registers (RDMSR and WRMSR support) 7000x80000001, 0, edx, 6, pae , Physical Address Extensions 7010x80000001, 0, edx, 7, mce , Machine Check Exception 7020x80000001, 0, edx, 8, cx8 , CMPXCHG8B instruction 7030x80000001, 0, edx, 9, apic , APIC on-chip 7040x80000001, 0, edx, 11, syscall , SYSCALL and SYSRET instructions 7050x80000001, 0, edx, 12, mtrr , Memory Type Range Registers 7060x80000001, 0, edx, 13, pge , Page Global Extensions 7070x80000001, 0, edx, 14, mca , Machine Check Architecture 7080x80000001, 0, edx, 15, cmov , Conditional Move Instruction 7090x80000001, 0, edx, 16, pat , Page Attribute Table 7100x80000001, 0, edx, 17, pse36 , Page Size Extension (36-bit) 7110x80000001, 0, edx, 19, mp , Out-of-spec AMD Multiprocessing bit 7120x80000001, 0, edx, 20, nx , No-execute page protection 7130x80000001, 0, edx, 22, mmxext , AMD MMX extensions 7140x80000001, 0, edx, 23, e_mmx , MMX instructions 7150x80000001, 0, edx, 24, e_fxsr , FXSAVE and FXRSTOR instructions 7160x80000001, 0, edx, 25, fxsr_opt , FXSAVE and FXRSTOR optimizations 7170x80000001, 0, edx, 26, pdpe1gb , 1-GB large page support 7180x80000001, 0, edx, 27, rdtscp , RDTSCP instruction 7190x80000001, 0, edx, 29, lm , Long mode (x86-64, 64-bit support) 7200x80000001, 0, edx, 30, 3dnowext , AMD 3DNow extensions 7210x80000001, 0, edx, 31, 3dnow , 3DNow instructions 722 723# Leaf 80000002H 724# CPU brand ID string, bytes 0 - 15 725 7260x80000002, 0, eax, 31:0, cpu_brandid_0 , CPU brand ID string, bytes 0 - 3 7270x80000002, 0, ebx, 31:0, cpu_brandid_1 , CPU brand ID string, bytes 4 - 7 7280x80000002, 0, ecx, 31:0, cpu_brandid_2 , CPU brand ID string, bytes 8 - 11 7290x80000002, 0, edx, 31:0, cpu_brandid_3 , CPU brand ID string, bytes 12 - 15 730 731# Leaf 80000003H 732# CPU brand ID string, bytes 16 - 31 733 7340x80000003, 0, eax, 31:0, cpu_brandid_4 , CPU brand ID string bytes, 16 - 19 7350x80000003, 0, ebx, 31:0, cpu_brandid_5 , CPU brand ID string bytes, 20 - 23 7360x80000003, 0, ecx, 31:0, cpu_brandid_6 , CPU brand ID string bytes, 24 - 27 7370x80000003, 0, edx, 31:0, cpu_brandid_7 , CPU brand ID string bytes, 28 - 31 738 739# Leaf 80000004H 740# CPU brand ID string, bytes 32 - 47 741 7420x80000004, 0, eax, 31:0, cpu_brandid_8 , CPU brand ID string, bytes 32 - 35 7430x80000004, 0, ebx, 31:0, cpu_brandid_9 , CPU brand ID string, bytes 36 - 39 7440x80000004, 0, ecx, 31:0, cpu_brandid_10 , CPU brand ID string, bytes 40 - 43 7450x80000004, 0, edx, 31:0, cpu_brandid_11 , CPU brand ID string, bytes 44 - 47 746 747# Leaf 80000005H 748# AMD/Transmeta L1 cache and TLB 749 7500x80000005, 0, eax, 7:0, l1_itlb_2m_4m_nentries , L1 ITLB #entries, 2M and 4M pages 7510x80000005, 0, eax, 15:8, l1_itlb_2m_4m_assoc , L1 ITLB associativity, 2M and 4M pages 7520x80000005, 0, eax, 23:16, l1_dtlb_2m_4m_nentries , L1 DTLB #entries, 2M and 4M pages 7530x80000005, 0, eax, 31:24, l1_dtlb_2m_4m_assoc , L1 DTLB associativity, 2M and 4M pages 7540x80000005, 0, ebx, 7:0, l1_itlb_4k_nentries , L1 ITLB #entries, 4K pages 7550x80000005, 0, ebx, 15:8, l1_itlb_4k_assoc , L1 ITLB associativity, 4K pages 7560x80000005, 0, ebx, 23:16, l1_dtlb_4k_nentries , L1 DTLB #entries, 4K pages 7570x80000005, 0, ebx, 31:24, l1_dtlb_4k_assoc , L1 DTLB associativity, 4K pages 7580x80000005, 0, ecx, 7:0, l1_dcache_line_size , L1 dcache line size, in bytes 7590x80000005, 0, ecx, 15:8, l1_dcache_nlines , L1 dcache lines per tag 7600x80000005, 0, ecx, 23:16, l1_dcache_assoc , L1 dcache associativity 7610x80000005, 0, ecx, 31:24, l1_dcache_size_kb , L1 dcache size, in KB 7620x80000005, 0, edx, 7:0, l1_icache_line_size , L1 icache line size, in bytes 7630x80000005, 0, edx, 15:8, l1_icache_nlines , L1 icache lines per tag 7640x80000005, 0, edx, 23:16, l1_icache_assoc , L1 icache associativity 7650x80000005, 0, edx, 31:24, l1_icache_size_kb , L1 icache size, in KB 766 767# Leaf 80000006H 768# (Mostly AMD) L2/L3 cache and TLB 769 7700x80000006, 0, eax, 11:0, l2_itlb_2m_4m_nentries , L2 iTLB #entries, 2M and 4M pages 7710x80000006, 0, eax, 15:12, l2_itlb_2m_4m_assoc , L2 iTLB associativity, 2M and 4M pages 7720x80000006, 0, eax, 27:16, l2_dtlb_2m_4m_nentries , L2 dTLB #entries, 2M and 4M pages 7730x80000006, 0, eax, 31:28, l2_dtlb_2m_4m_assoc , L2 dTLB associativity, 2M and 4M pages 7740x80000006, 0, ebx, 11:0, l2_itlb_4k_nentries , L2 iTLB #entries, 4K pages 7750x80000006, 0, ebx, 15:12, l2_itlb_4k_assoc , L2 iTLB associativity, 4K pages 7760x80000006, 0, ebx, 27:16, l2_dtlb_4k_nentries , L2 dTLB #entries, 4K pages 7770x80000006, 0, ebx, 31:28, l2_dtlb_4k_assoc , L2 dTLB associativity, 4K pages 7780x80000006, 0, ecx, 7:0, l2_line_size , L2 cache line size, in bytes 7790x80000006, 0, ecx, 11:8, l2_nlines , L2 cache number of lines per tag 7800x80000006, 0, ecx, 15:12, l2_assoc , L2 cache associativity 7810x80000006, 0, ecx, 31:16, l2_size_kb , L2 cache size, in KB 7820x80000006, 0, edx, 7:0, l3_line_size , L3 cache line size, in bytes 7830x80000006, 0, edx, 11:8, l3_nlines , L3 cache number of lines per tag 7840x80000006, 0, edx, 15:12, l3_assoc , L3 cache associativity 7850x80000006, 0, edx, 31:18, l3_size_range , L3 cache size range 786 787# Leaf 80000007H 788# CPU power management (mostly AMD) and AMD RAS 789 7900x80000007, 0, ebx, 0, overflow_recov , MCA overflow conditions not fatal 7910x80000007, 0, ebx, 1, succor , Software containment of uncorrectable errors 7920x80000007, 0, ebx, 2, hw_assert , Hardware assert MSRs 7930x80000007, 0, ebx, 3, smca , Scalable MCA (MCAX MSRs) 7940x80000007, 0, ecx, 31:0, cpu_pwr_sample_ratio , CPU power sample time ratio 7950x80000007, 0, edx, 0, digital_temp , Digital temperature sensor 7960x80000007, 0, edx, 1, powernow_freq_id , PowerNOW! frequency scaling 7970x80000007, 0, edx, 2, powernow_volt_id , PowerNOW! voltage scaling 7980x80000007, 0, edx, 3, thermal_trip , THERMTRIP (Thermal Trip) 7990x80000007, 0, edx, 4, hw_thermal_control , Hardware thermal control 8000x80000007, 0, edx, 5, sw_thermal_control , Software thermal control 8010x80000007, 0, edx, 6, 100mhz_steps , 100 MHz multiplier control 8020x80000007, 0, edx, 7, hw_pstate , Hardware P-state control 8030x80000007, 0, edx, 8, constant_tsc , TSC ticks at constant rate across all P and C states 8040x80000007, 0, edx, 9, cpb , Core performance boost 8050x80000007, 0, edx, 10, eff_freq_ro , Read-only effective frequency interface 8060x80000007, 0, edx, 11, proc_feedback , Processor feedback interface (deprecated) 8070x80000007, 0, edx, 12, acc_power , Processor power reporting interface 8080x80000007, 0, edx, 13, connected_standby , CPU Connected Standby support 8090x80000007, 0, edx, 14, rapl , Runtime Average Power Limit interface 810 811# Leaf 80000008H 812# CPU capacity parameters and extended feature flags (mostly AMD) 813 8140x80000008, 0, eax, 7:0, phys_addr_bits , Max physical address bits 8150x80000008, 0, eax, 15:8, virt_addr_bits , Max virtual address bits 8160x80000008, 0, eax, 23:16, guest_phys_addr_bits , Max nested-paging guest physical address bits 8170x80000008, 0, ebx, 0, clzero , CLZERO instruction 8180x80000008, 0, ebx, 1, irperf , Instruction retired counter MSR 8190x80000008, 0, ebx, 2, xsaveerptr , XSAVE/XRSTOR always saves/restores FPU error pointers 8200x80000008, 0, ebx, 3, invlpgb , INVLPGB broadcasts a TLB invalidate 8210x80000008, 0, ebx, 4, rdpru , RDPRU (Read Processor Register at User level) 8220x80000008, 0, ebx, 6, mba , Memory Bandwidth Allocation (AMD bit) 8230x80000008, 0, ebx, 8, mcommit , MCOMMIT instruction 8240x80000008, 0, ebx, 9, wbnoinvd , WBNOINVD instruction 8250x80000008, 0, ebx, 12, amd_ibpb , Indirect Branch Prediction Barrier 8260x80000008, 0, ebx, 13, wbinvd_int , Interruptible WBINVD/WBNOINVD 8270x80000008, 0, ebx, 14, amd_ibrs , Indirect Branch Restricted Speculation 8280x80000008, 0, ebx, 15, amd_stibp , Single Thread Indirect Branch Prediction mode 8290x80000008, 0, ebx, 16, ibrs_always_on , IBRS always-on preferred 8300x80000008, 0, ebx, 17, amd_stibp_always_on , STIBP always-on preferred 8310x80000008, 0, ebx, 18, ibrs_fast , IBRS is preferred over software solution 8320x80000008, 0, ebx, 19, ibrs_same_mode , IBRS provides same mode protection 8330x80000008, 0, ebx, 20, no_efer_lmsle , Long-Mode Segment Limit Enable unsupported 8340x80000008, 0, ebx, 21, tlb_flush_nested , INVLPGB RAX[5] bit can be set 8350x80000008, 0, ebx, 23, amd_ppin , Protected Processor Inventory Number 8360x80000008, 0, ebx, 24, amd_ssbd , Speculative Store Bypass Disable 8370x80000008, 0, ebx, 25, virt_ssbd , virtualized SSBD (Speculative Store Bypass Disable) 8380x80000008, 0, ebx, 26, amd_ssb_no , SSBD is not needed (fixed in hardware) 8390x80000008, 0, ebx, 27, cppc , Collaborative Processor Performance Control 8400x80000008, 0, ebx, 28, amd_psfd , Predictive Store Forward Disable 8410x80000008, 0, ebx, 29, btc_no , CPU not affected by Branch Type Confusion 8420x80000008, 0, ebx, 30, ibpb_ret , IBPB clears RSB/RAS too 8430x80000008, 0, ebx, 31, brs , Branch Sampling 8440x80000008, 0, ecx, 7:0, cpu_nthreads , Number of physical threads - 1 8450x80000008, 0, ecx, 15:12, apicid_coreid_len , Number of thread core ID bits (shift) in APIC ID 8460x80000008, 0, ecx, 17:16, perf_tsc_len , Performance time-stamp counter size 8470x80000008, 0, edx, 15:0, invlpgb_max_pages , INVLPGB maximum page count 8480x80000008, 0, edx, 31:16, rdpru_max_reg_id , RDPRU max register ID (ECX input) 849 850# Leaf 8000000AH 851# AMD SVM (Secure Virtual Machine) 852 8530x8000000a, 0, eax, 7:0, svm_version , SVM revision number 8540x8000000a, 0, ebx, 31:0, svm_nasid , Number of address space identifiers (ASID) 8550x8000000a, 0, ecx, 4, pml , Page Modification Logging (PML) 8560x8000000a, 0, edx, 0, npt , Nested paging 8570x8000000a, 0, edx, 1, lbrv , LBR virtualization 8580x8000000a, 0, edx, 2, svm_lock , SVM lock 8590x8000000a, 0, edx, 3, nrip_save , NRIP save support on #VMEXIT 8600x8000000a, 0, edx, 4, tsc_scale , MSR based TSC rate control 8610x8000000a, 0, edx, 5, vmcb_clean , VMCB clean bits support 8620x8000000a, 0, edx, 6, flushbyasid , Flush by ASID + Extended VMCB TLB_Control 8630x8000000a, 0, edx, 7, decodeassists , Decode Assists support 8640x8000000a, 0, edx, 10, pausefilter , Pause intercept filter 8650x8000000a, 0, edx, 12, pfthreshold , Pause filter threshold 8660x8000000a, 0, edx, 13, avic , Advanced virtual interrupt controller 8670x8000000a, 0, edx, 15, v_vmsave_vmload , Virtual VMSAVE/VMLOAD (nested virtualization) 8680x8000000a, 0, edx, 16, vgif , Virtualize the Global Interrupt Flag 8690x8000000a, 0, edx, 17, gmet , Guest mode execution trap 8700x8000000a, 0, edx, 18, x2avic , Virtual x2APIC 8710x8000000a, 0, edx, 19, sss_check , Supervisor Shadow Stack restrictions 8720x8000000a, 0, edx, 20, v_spec_ctrl , Virtual SPEC_CTRL 8730x8000000a, 0, edx, 21, ro_gpt , Read-Only guest page table support 8740x8000000a, 0, edx, 23, h_mce_override , Host MCE override 8750x8000000a, 0, edx, 24, tlbsync_int , TLBSYNC intercept + INVLPGB/TLBSYNC in VMCB 8760x8000000a, 0, edx, 25, vnmi , NMI virtualization 8770x8000000a, 0, edx, 26, ibs_virt , IBS Virtualization 8780x8000000a, 0, edx, 27, ext_lvt_off_chg , Extended LVT offset fault change 8790x8000000a, 0, edx, 28, svme_addr_chk , Guest SVME address check 880 881# Leaf 80000019H 882# AMD TLB characteristics for 1GB pages 883 8840x80000019, 0, eax, 11:0, l1_itlb_1g_nentries , L1 iTLB #entries, 1G pages 8850x80000019, 0, eax, 15:12, l1_itlb_1g_assoc , L1 iTLB associativity, 1G pages 8860x80000019, 0, eax, 27:16, l1_dtlb_1g_nentries , L1 dTLB #entries, 1G pages 8870x80000019, 0, eax, 31:28, l1_dtlb_1g_assoc , L1 dTLB associativity, 1G pages 8880x80000019, 0, ebx, 11:0, l2_itlb_1g_nentries , L2 iTLB #entries, 1G pages 8890x80000019, 0, ebx, 15:12, l2_itlb_1g_assoc , L2 iTLB associativity, 1G pages 8900x80000019, 0, ebx, 27:16, l2_dtlb_1g_nentries , L2 dTLB #entries, 1G pages 8910x80000019, 0, ebx, 31:28, l2_dtlb_1g_assoc , L2 dTLB associativity, 1G pages 892 893# Leaf 8000001AH 894# AMD instruction optimizations 895 8960x8000001a, 0, eax, 0, fp_128 , Internal FP/SIMD exec data path is 128-bits wide 8970x8000001a, 0, eax, 1, movu_preferred , SSE: MOVU* better than MOVL*/MOVH* 8980x8000001a, 0, eax, 2, fp_256 , internal FP/SSE exec data path is 256-bits wide 899 900# Leaf 8000001BH 901# AMD IBS (Instruction-Based Sampling) 902 9030x8000001b, 0, eax, 0, ibs_flags , IBS feature flags 9040x8000001b, 0, eax, 1, ibs_fetch_sampling , IBS fetch sampling 9050x8000001b, 0, eax, 2, ibs_op_sampling , IBS execution sampling 9060x8000001b, 0, eax, 3, ibs_rdwr_op_counter , IBS read/write of op counter 9070x8000001b, 0, eax, 4, ibs_op_count , IBS OP counting mode 9080x8000001b, 0, eax, 5, ibs_branch_target , IBS branch target address reporting 9090x8000001b, 0, eax, 6, ibs_op_counters_ext , IBS IbsOpCurCnt/IbsOpMaxCnt extend by 7 bits 9100x8000001b, 0, eax, 7, ibs_rip_invalid_chk , IBS invalid RIP indication 9110x8000001b, 0, eax, 8, ibs_op_branch_fuse , IBS fused branch micro-op indication 9120x8000001b, 0, eax, 9, ibs_fetch_ctl_ext , IBS Fetch Control Extended MSR 9130x8000001b, 0, eax, 10, ibs_op_data_4 , IBS op data 4 MSR 9140x8000001b, 0, eax, 11, ibs_l3_miss_filter , IBS L3-miss filtering (Zen4+) 915 916# Leaf 8000001CH 917# AMD LWP (Lightweight Profiling) 918 9190x8000001c, 0, eax, 0, os_lwp_avail , OS: LWP is available to application programs 9200x8000001c, 0, eax, 1, os_lpwval , OS: LWPVAL instruction 9210x8000001c, 0, eax, 2, os_lwp_ire , OS: Instructions Retired Event 9220x8000001c, 0, eax, 3, os_lwp_bre , OS: Branch Retired Event 9230x8000001c, 0, eax, 4, os_lwp_dme , OS: Dcache Miss Event 9240x8000001c, 0, eax, 5, os_lwp_cnh , OS: CPU Clocks Not Halted event 9250x8000001c, 0, eax, 6, os_lwp_rnh , OS: CPU Reference clocks Not Halted event 9260x8000001c, 0, eax, 29, os_lwp_cont , OS: LWP sampling in continuous mode 9270x8000001c, 0, eax, 30, os_lwp_ptsc , OS: Performance Time Stamp Counter in event records 9280x8000001c, 0, eax, 31, os_lwp_int , OS: Interrupt on threshold overflow 9290x8000001c, 0, ebx, 7:0, lwp_lwpcb_sz , Control Block size, in quadwords 9300x8000001c, 0, ebx, 15:8, lwp_event_sz , Event record size, in bytes 9310x8000001c, 0, ebx, 23:16, lwp_max_events , Max EventID supported 9320x8000001c, 0, ebx, 31:24, lwp_event_offset , Control Block events area offset 9330x8000001c, 0, ecx, 4:0, lwp_latency_max , Cache latency counters number of bits 9340x8000001c, 0, ecx, 5, lwp_data_addr , Cache miss events report data cache address 9350x8000001c, 0, ecx, 8:6, lwp_latency_rnd , Cache latency rounding amount 9360x8000001c, 0, ecx, 15:9, lwp_version , LWP version 9370x8000001c, 0, ecx, 23:16, lwp_buf_min_sz , LWP event ring buffer min size, 32 event records units 9380x8000001c, 0, ecx, 28, lwp_branch_predict , Branches Retired events can be filtered 9390x8000001c, 0, ecx, 29, lwp_ip_filtering , IP filtering (IPI, IPF, BaseIP, and LimitIP @ LWPCP) 9400x8000001c, 0, ecx, 30, lwp_cache_levels , Cache-related events: filter by cache level 9410x8000001c, 0, ecx, 31, lwp_cache_latency , Cache-related events: filter by latency 9420x8000001c, 0, edx, 0, hw_lwp_avail , HW: LWP available 9430x8000001c, 0, edx, 1, hw_lpwval , HW: LWPVAL available 9440x8000001c, 0, edx, 2, hw_lwp_ire , HW: Instructions Retired Event 9450x8000001c, 0, edx, 3, hw_lwp_bre , HW: Branch Retired Event 9460x8000001c, 0, edx, 4, hw_lwp_dme , HW: Dcache Miss Event 9470x8000001c, 0, edx, 5, hw_lwp_cnh , HW: Clocks Not Halted event 9480x8000001c, 0, edx, 6, hw_lwp_rnh , HW: Reference clocks Not Halted event 9490x8000001c, 0, edx, 29, hw_lwp_cont , HW: LWP sampling in continuous mode 9500x8000001c, 0, edx, 30, hw_lwp_ptsc , HW: Performance Time Stamp Counter in event records 9510x8000001c, 0, edx, 31, hw_lwp_int , HW: Interrupt on threshold overflow 952 953# Leaf 8000001DH 954# AMD deterministic cache parameters 955 9560x8000001d, 31:0, eax, 4:0, cache_type , Cache type field 9570x8000001d, 31:0, eax, 7:5, cache_level , Cache level (1-based) 9580x8000001d, 31:0, eax, 8, cache_self_init , Self-initializing cache level 9590x8000001d, 31:0, eax, 9, fully_associative , Fully-associative cache 9600x8000001d, 31:0, eax, 25:14, num_threads_sharing , Number of logical CPUs sharing cache 9610x8000001d, 31:0, ebx, 11:0, cache_linesize , System coherency line size (0-based) 9620x8000001d, 31:0, ebx, 21:12, cache_npartitions , Physical line partitions (0-based) 9630x8000001d, 31:0, ebx, 31:22, cache_nways , Ways of associativity (0-based) 9640x8000001d, 31:0, ecx, 30:0, cache_nsets , Cache number of sets (0-based) 9650x8000001d, 31:0, edx, 0, wbinvd_rll_no_guarantee, WBINVD/INVD not guaranteed for Remote Lower-Level caches 9660x8000001d, 31:0, edx, 1, ll_inclusive , Cache is inclusive of Lower-Level caches 967 968# Leaf 8000001EH 969# AMD CPU topology 970 9710x8000001e, 0, eax, 31:0, ext_apic_id , Extended APIC ID 9720x8000001e, 0, ebx, 7:0, core_id , Unique per-socket logical core unit ID 9730x8000001e, 0, ebx, 15:8, core_nthreads , #Threads per core (zero-based) 9740x8000001e, 0, ecx, 7:0, node_id , Node (die) ID of invoking logical CPU 9750x8000001e, 0, ecx, 10:8, nnodes_per_socket , #nodes in invoking logical CPU's package/socket 976 977# Leaf 8000001FH 978# AMD encrypted memory capabilities (SME/SEV) 979 9800x8000001f, 0, eax, 0, sme , Secure Memory Encryption 9810x8000001f, 0, eax, 1, sev , Secure Encrypted Virtualization 9820x8000001f, 0, eax, 2, vm_page_flush , VM Page Flush MSR 9830x8000001f, 0, eax, 3, sev_es , SEV Encrypted State 9840x8000001f, 0, eax, 4, sev_nested_paging , SEV secure nested paging 9850x8000001f, 0, eax, 5, vm_permission_levels , VMPL 9860x8000001f, 0, eax, 6, rpmquery , RPMQUERY instruction 9870x8000001f, 0, eax, 7, vmpl_sss , VMPL supervisor shadow stack 9880x8000001f, 0, eax, 8, secure_tsc , Secure TSC 9890x8000001f, 0, eax, 9, v_tsc_aux , Hardware virtualizes TSC_AUX 9900x8000001f, 0, eax, 10, sme_coherent , Cache coherency enforcement across encryption domains 9910x8000001f, 0, eax, 11, req_64bit_hypervisor , SEV guest mandates 64-bit hypervisor 9920x8000001f, 0, eax, 12, restricted_injection , Restricted Injection supported 9930x8000001f, 0, eax, 13, alternate_injection , Alternate Injection supported 9940x8000001f, 0, eax, 14, debug_swap , SEV-ES: Full debug state swap 9950x8000001f, 0, eax, 15, disallow_host_ibs , SEV-ES: Disallowing IBS use by the host 9960x8000001f, 0, eax, 16, virt_transparent_enc , Virtual Transparent Encryption 9970x8000001f, 0, eax, 17, vmgexit_parameter , SEV_FEATURES: VmgexitParameter 9980x8000001f, 0, eax, 18, virt_tom_msr , Virtual TOM MSR 9990x8000001f, 0, eax, 19, virt_ibs , SEV-ES guests: IBS state virtualization 10000x8000001f, 0, eax, 24, vmsa_reg_protection , VMSA register protection 10010x8000001f, 0, eax, 25, smt_protection , SMT protection 10020x8000001f, 0, eax, 28, svsm_page_msr , SVSM communication page MSR 10030x8000001f, 0, eax, 29, nested_virt_snp_msr , VIRT_RMPUPDATE/VIRT_PSMASH MSRs 10040x8000001f, 0, ebx, 5:0, pte_cbit_pos , PTE bit number to enable memory encryption 10050x8000001f, 0, ebx, 11:6, phys_addr_reduction_nbits, Reduction of phys address space in bits 10060x8000001f, 0, ebx, 15:12, vmpl_count , Number of VM permission levels (VMPL) 10070x8000001f, 0, ecx, 31:0, enc_guests_max , Max number of simultaneous encrypted guests 10080x8000001f, 0, edx, 31:0, min_sev_asid_no_sev_es , Minimum ASID for SEV-enabled SEV-ES-disabled guest 1009 1010# Leaf 80000020H 1011# AMD PQoS (Platform QoS) extended features 1012 10130x80000020, 0, ebx, 1, mba , Memory Bandwidth Allocation support 10140x80000020, 0, ebx, 2, smba , Slow Memory Bandwidth Allocation support 10150x80000020, 0, ebx, 3, bmec , Bandwidth Monitoring Event Configuration support 10160x80000020, 0, ebx, 4, l3rr , L3 Range Reservation support 10170x80000020, 0, ebx, 5, abmc , Assignable Bandwidth Monitoring Counters 10180x80000020, 0, ebx, 6, sdciae , Smart Data Cache Injection (SDCI) Allocation Enforcement 10190x80000020, 1, eax, 31:0, mba_limit_len , MBA enforcement limit size 10200x80000020, 1, edx, 31:0, mba_cos_max , MBA max Class of Service number (zero-based) 10210x80000020, 2, eax, 31:0, smba_limit_len , SMBA enforcement limit size 10220x80000020, 2, edx, 31:0, smba_cos_max , SMBA max Class of Service number (zero-based) 10230x80000020, 3, ebx, 7:0, bmec_num_events , BMEC number of bandwidth events available 10240x80000020, 3, ecx, 0, bmec_local_reads , Local NUMA reads can be tracked 10250x80000020, 3, ecx, 1, bmec_remote_reads , Remote NUMA reads can be tracked 10260x80000020, 3, ecx, 2, bmec_local_nontemp_wr , Local NUMA non-temporal writes can be tracked 10270x80000020, 3, ecx, 3, bmec_remote_nontemp_wr , Remote NUMA non-temporal writes can be tracked 10280x80000020, 3, ecx, 4, bmec_local_slow_mem_rd , Local NUMA slow-memory reads can be tracked 10290x80000020, 3, ecx, 5, bmec_remote_slow_mem_rd, Remote NUMA slow-memory reads can be tracked 10300x80000020, 3, ecx, 6, bmec_all_dirty_victims , Dirty QoS victims to all types of memory can be tracked 1031 1032# Leaf 80000021H 1033# AMD extended CPU features 2 1034 10350x80000021, 0, eax, 0, no_nested_data_bp , No nested data breakpoints 10360x80000021, 0, eax, 1, fsgs_non_serializing , WRMSR to {FS,GS,KERNEL_GS}_BASE is non-serializing 10370x80000021, 0, eax, 2, lfence_rdtsc , LFENCE always serializing / synchronizes RDTSC 10380x80000021, 0, eax, 3, smm_page_cfg_lock , SMM paging configuration lock 10390x80000021, 0, eax, 6, null_sel_clr_base , Null selector clears base 10400x80000021, 0, eax, 7, upper_addr_ignore , EFER MSR Upper Address Ignore 10410x80000021, 0, eax, 8, autoibrs , EFER MSR Automatic IBRS 10420x80000021, 0, eax, 9, no_smm_ctl_msr , SMM_CTL MSR not available 10430x80000021, 0, eax, 10, fsrs , Fast Short Rep STOSB 10440x80000021, 0, eax, 11, fsrc , Fast Short Rep CMPSB 10450x80000021, 0, eax, 13, prefetch_ctl_msr , Prefetch control MSR 10460x80000021, 0, eax, 16, opcode_reclaim , Reserves opcode space 10470x80000021, 0, eax, 17, user_cpuid_disable , #GP when executing CPUID at CPL > 0 10480x80000021, 0, eax, 18, epsf , Enhanced Predictive Store Forwarding 10490x80000021, 0, eax, 22, wl_feedback , Workload-based heuristic feedback to OS 10500x80000021, 0, eax, 24, eraps , Enhanced Return Address Predictor Security 10510x80000021, 0, eax, 27, sbpb , Selective Branch Predictor Barrier 10520x80000021, 0, eax, 28, ibpb_brtype , Branch predictions flushed from CPU branch predictor 10530x80000021, 0, eax, 29, srso_no , No SRSO vulnerability 10540x80000021, 0, eax, 30, srso_uk_no , No SRSO at user-kernel boundary 10550x80000021, 0, eax, 31, srso_msr_fix , MSR BP_CFG[BpSpecReduce] SRSO mitigation 10560x80000021, 0, ebx, 15:0, microcode_patch_size , Microcode patch size, in 16-byte units 10570x80000021, 0, ebx, 23:16, rap_size , Return Address Predictor size 1058 1059# Leaf 80000022H 1060# AMD extended performance monitoring 1061 10620x80000022, 0, eax, 0, perfmon_v2 , Performance monitoring v2 10630x80000022, 0, eax, 1, lbr_v2 , Last Branch Record v2 extensions (LBR Stack) 10640x80000022, 0, eax, 2, lbr_pmc_freeze , Freezing core performance counters / LBR Stack 10650x80000022, 0, ebx, 3:0, n_pmc_core , Number of core performance counters 10660x80000022, 0, ebx, 9:4, lbr_v2_stack_size , Number of LBR stack entries 10670x80000022, 0, ebx, 15:10, n_pmc_northbridge , Number of northbridge performance counters 10680x80000022, 0, ebx, 21:16, n_pmc_umc , Number of UMC performance counters 10690x80000022, 0, ecx, 31:0, active_umc_bitmask , Active UMCs bitmask 1070 1071# Leaf 80000023H 1072# AMD multi-key encrypted memory 1073 10740x80000023, 0, eax, 0, mem_hmk_mode , MEM-HMK encryption mode 10750x80000023, 0, ebx, 15:0, mem_hmk_avail_keys , Total number of available encryption keys 1076 1077# Leaf 80000026H 1078# AMD extended CPU topology 1079 10800x80000026, 3:0, eax, 4:0, x2apic_id_shift , Bit width of this level (previous levels inclusive) 10810x80000026, 3:0, eax, 29, core_has_pwreff_ranking, This core has a power efficiency ranking 10820x80000026, 3:0, eax, 30, domain_has_hybrid_cores, This domain level has hybrid (E, P) cores 10830x80000026, 3:0, eax, 31, domain_core_count_asymm, The 'Core' domain has asymmetric cores count 10840x80000026, 3:0, ebx, 15:0, domain_lcpus_count , Number of logical CPUs at this domain instance 10850x80000026, 3:0, ebx, 23:16, core_pwreff_ranking , This core's static power efficiency ranking 10860x80000026, 3:0, ebx, 27:24, core_native_model_id , This core's native model ID 10870x80000026, 3:0, ebx, 31:28, core_type , This core's type 10880x80000026, 3:0, ecx, 7:0, domain_level , This domain level (subleaf ID) 10890x80000026, 3:0, ecx, 15:8, domain_type , This domain type 10900x80000026, 3:0, edx, 31:0, x2apic_id , x2APIC ID of current logical CPU 1091 1092# Leaf 80860000H 1093# Maximum Transmeta leaf + CPU vendor string 1094 10950x80860000, 0, eax, 31:0, max_tra_leaf , Maximum Transmeta leaf 10960x80860000, 0, ebx, 31:0, cpu_vendorid_0 , Transmeta Vendor ID string bytes 0 - 3 10970x80860000, 0, ecx, 31:0, cpu_vendorid_2 , Transmeta Vendor ID string bytes 8 - 11 10980x80860000, 0, edx, 31:0, cpu_vendorid_1 , Transmeta Vendor ID string bytes 4 - 7 1099 1100# Leaf 80860001H 1101# Transmeta extended CPU features 1102 11030x80860001, 0, eax, 3:0, stepping , Stepping ID 11040x80860001, 0, eax, 7:4, base_model , Base CPU model ID 11050x80860001, 0, eax, 11:8, base_family_id , Base CPU family ID 11060x80860001, 0, eax, 13:12, cpu_type , CPU type 11070x80860001, 0, ebx, 7:0, cpu_rev_mask_minor , CPU revision ID, mask minor 11080x80860001, 0, ebx, 15:8, cpu_rev_mask_major , CPU revision ID, mask major 11090x80860001, 0, ebx, 23:16, cpu_rev_minor , CPU revision ID, minor 11100x80860001, 0, ebx, 31:24, cpu_rev_major , CPU revision ID, major 11110x80860001, 0, ecx, 31:0, cpu_base_mhz , CPU nominal frequency, in MHz 11120x80860001, 0, edx, 0, recovery , Recovery CMS is active (after bad flush) 11130x80860001, 0, edx, 1, longrun , LongRun power management capabilities 11140x80860001, 0, edx, 3, lrti , LongRun Table Interface 1115 1116# Leaf 80860002H 1117# Transmeta CMS (Code Morphing Software) 1118 11190x80860002, 0, eax, 31:0, cpu_rev_id , CPU revision ID 11200x80860002, 0, ebx, 7:0, cms_rev_mask_2 , CMS revision ID, mask component 2 11210x80860002, 0, ebx, 15:8, cms_rev_mask_1 , CMS revision ID, mask component 1 11220x80860002, 0, ebx, 23:16, cms_rev_minor , CMS revision ID, minor 11230x80860002, 0, ebx, 31:24, cms_rev_major , CMS revision ID, major 11240x80860002, 0, ecx, 31:0, cms_rev_mask_3 , CMS revision ID, mask component 3 1125 1126# Leaf 80860003H 1127# Transmeta CPU information string, bytes 0 - 15 1128 11290x80860003, 0, eax, 31:0, cpu_info_0 , CPU info string bytes 0 - 3 11300x80860003, 0, ebx, 31:0, cpu_info_1 , CPU info string bytes 4 - 7 11310x80860003, 0, ecx, 31:0, cpu_info_2 , CPU info string bytes 8 - 11 11320x80860003, 0, edx, 31:0, cpu_info_3 , CPU info string bytes 12 - 15 1133 1134# Leaf 80860004H 1135# Transmeta CPU information string, bytes 16 - 31 1136 11370x80860004, 0, eax, 31:0, cpu_info_4 , CPU info string bytes 16 - 19 11380x80860004, 0, ebx, 31:0, cpu_info_5 , CPU info string bytes 20 - 23 11390x80860004, 0, ecx, 31:0, cpu_info_6 , CPU info string bytes 24 - 27 11400x80860004, 0, edx, 31:0, cpu_info_7 , CPU info string bytes 28 - 31 1141 1142# Leaf 80860005H 1143# Transmeta CPU information string, bytes 32 - 47 1144 11450x80860005, 0, eax, 31:0, cpu_info_8 , CPU info string bytes 32 - 35 11460x80860005, 0, ebx, 31:0, cpu_info_9 , CPU info string bytes 36 - 39 11470x80860005, 0, ecx, 31:0, cpu_info_10 , CPU info string bytes 40 - 43 11480x80860005, 0, edx, 31:0, cpu_info_11 , CPU info string bytes 44 - 47 1149 1150# Leaf 80860006H 1151# Transmeta CPU information string, bytes 48 - 63 1152 11530x80860006, 0, eax, 31:0, cpu_info_12 , CPU info string bytes 48 - 51 11540x80860006, 0, ebx, 31:0, cpu_info_13 , CPU info string bytes 52 - 55 11550x80860006, 0, ecx, 31:0, cpu_info_14 , CPU info string bytes 56 - 59 11560x80860006, 0, edx, 31:0, cpu_info_15 , CPU info string bytes 60 - 63 1157 1158# Leaf 80860007H 1159# Transmeta live CPU information 1160 11610x80860007, 0, eax, 31:0, cpu_cur_mhz , Current CPU frequency, in MHz 11620x80860007, 0, ebx, 31:0, cpu_cur_voltage , Current CPU voltage, in millivolts 11630x80860007, 0, ecx, 31:0, cpu_cur_perf_pctg , Current CPU performance percentage, 0 - 100 11640x80860007, 0, edx, 31:0, cpu_cur_gate_delay , Current CPU gate delay, in femtoseconds 1165 1166# Leaf C0000000H 1167# Maximum Centaur/Zhaoxin leaf 1168 11690xc0000000, 0, eax, 31:0, max_cntr_leaf , Maximum Centaur/Zhaoxin leaf 1170 1171# Leaf C0000001H 1172# Centaur/Zhaoxin extended CPU features 1173 11740xc0000001, 0, edx, 0, ccs_sm2 , CCS SM2 instructions 11750xc0000001, 0, edx, 1, ccs_sm2_en , CCS SM2 enabled 11760xc0000001, 0, edx, 2, xstore , Random Number Generator 11770xc0000001, 0, edx, 3, xstore_en , RNG enabled 11780xc0000001, 0, edx, 4, ccs_sm3_sm4 , CCS SM3 and SM4 instructions 11790xc0000001, 0, edx, 5, ccs_sm3_sm4_en , CCS SM3/SM4 enabled 11800xc0000001, 0, edx, 6, ace , Advanced Cryptography Engine 11810xc0000001, 0, edx, 7, ace_en , ACE enabled 11820xc0000001, 0, edx, 8, ace2 , Advanced Cryptography Engine v2 11830xc0000001, 0, edx, 9, ace2_en , ACE v2 enabled 11840xc0000001, 0, edx, 10, phe , PadLock Hash Engine 11850xc0000001, 0, edx, 11, phe_en , PHE enabled 11860xc0000001, 0, edx, 12, pmm , PadLock Montgomery Multiplier 11870xc0000001, 0, edx, 13, pmm_en , PMM enabled 11880xc0000001, 0, edx, 16, parallax , Parallax auto adjust processor voltage 11890xc0000001, 0, edx, 17, parallax_en , Parallax enabled 11900xc0000001, 0, edx, 20, tm3 , Thermal Monitor v3 11910xc0000001, 0, edx, 21, tm3_en , TM v3 enabled 11920xc0000001, 0, edx, 25, phe2 , PadLock Hash Engine v2 (SHA384/SHA512) 11930xc0000001, 0, edx, 26, phe2_en , PHE v2 enabled 11940xc0000001, 0, edx, 27, rsa , RSA instructions (XMODEXP/MONTMUL2) 11950xc0000001, 0, edx, 28, rsa_en , RSA instructions enabled 1196