1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * CPPC (Collaborative Processor Performance Control) methods used by CPUfreq drivers.
4 *
5 * (C) Copyright 2014, 2015 Linaro Ltd.
6 * Author: Ashwin Chaugule <ashwin.chaugule@linaro.org>
7 *
8 * CPPC describes a few methods for controlling CPU performance using
9 * information from a per CPU table called CPC. This table is described in
10 * the ACPI v5.0+ specification. The table consists of a list of
11 * registers which may be memory mapped or hardware registers and also may
12 * include some static integer values.
13 *
14 * CPU performance is on an abstract continuous scale as against a discretized
15 * P-state scale which is tied to CPU frequency only. In brief, the basic
16 * operation involves:
17 *
18 * - OS makes a CPU performance request. (Can provide min and max bounds)
19 *
20 * - Platform (such as BMC) is free to optimize request within requested bounds
21 * depending on power/thermal budgets etc.
22 *
23 * - Platform conveys its decision back to OS
24 *
25 * The communication between OS and platform occurs through another medium
26 * called (PCC) Platform Communication Channel. This is a generic mailbox like
27 * mechanism which includes doorbell semantics to indicate register updates.
28 * See drivers/mailbox/pcc.c for details on PCC.
29 *
30 * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and
31 * above specifications.
32 */
33
34 #define pr_fmt(fmt) "ACPI CPPC: " fmt
35
36 #include <linux/delay.h>
37 #include <linux/iopoll.h>
38 #include <linux/ktime.h>
39 #include <linux/rwsem.h>
40 #include <linux/wait.h>
41 #include <linux/topology.h>
42 #include <linux/dmi.h>
43 #include <linux/units.h>
44 #include <linux/unaligned.h>
45
46 #include <acpi/cppc_acpi.h>
47
48 struct cppc_pcc_data {
49 struct pcc_mbox_chan *pcc_channel;
50 bool pcc_channel_acquired;
51 unsigned int deadline_us;
52 unsigned int pcc_mpar, pcc_mrtt, pcc_nominal;
53
54 bool pending_pcc_write_cmd; /* Any pending/batched PCC write cmds? */
55 bool platform_owns_pcc; /* Ownership of PCC subspace */
56 unsigned int pcc_write_cnt; /* Running count of PCC write commands */
57
58 /*
59 * Lock to provide controlled access to the PCC channel.
60 *
61 * For performance critical usecases(currently cppc_set_perf)
62 * We need to take read_lock and check if channel belongs to OSPM
63 * before reading or writing to PCC subspace
64 * We need to take write_lock before transferring the channel
65 * ownership to the platform via a Doorbell
66 * This allows us to batch a number of CPPC requests if they happen
67 * to originate in about the same time
68 *
69 * For non-performance critical usecases(init)
70 * Take write_lock for all purposes which gives exclusive access
71 */
72 struct rw_semaphore pcc_lock;
73
74 /* Wait queue for CPUs whose requests were batched */
75 wait_queue_head_t pcc_write_wait_q;
76 ktime_t last_cmd_cmpl_time;
77 ktime_t last_mpar_reset;
78 int mpar_count;
79 int refcount;
80 };
81
82 /* Array to represent the PCC channel per subspace ID */
83 static struct cppc_pcc_data *pcc_data[MAX_PCC_SUBSPACES];
84 /* The cpu_pcc_subspace_idx contains per CPU subspace ID */
85 static DEFINE_PER_CPU(int, cpu_pcc_subspace_idx);
86
87 /*
88 * The cpc_desc structure contains the ACPI register details
89 * as described in the per CPU _CPC tables. The details
90 * include the type of register (e.g. PCC, System IO, FFH etc.)
91 * and destination addresses which lets us READ/WRITE CPU performance
92 * information using the appropriate I/O methods.
93 */
94 static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
95
96 /* pcc mapped address + header size + offset within PCC subspace */
97 #define GET_PCC_VADDR(offs, pcc_ss_id) (pcc_data[pcc_ss_id]->pcc_channel->shmem + \
98 0x8 + (offs))
99
100 /* Check if a CPC register is in PCC */
101 #define CPC_IN_PCC(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
102 (cpc)->cpc_entry.reg.space_id == \
103 ACPI_ADR_SPACE_PLATFORM_COMM)
104
105 /* Check if a CPC register is in FFH */
106 #define CPC_IN_FFH(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
107 (cpc)->cpc_entry.reg.space_id == \
108 ACPI_ADR_SPACE_FIXED_HARDWARE)
109
110 /* Check if a CPC register is in SystemMemory */
111 #define CPC_IN_SYSTEM_MEMORY(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
112 (cpc)->cpc_entry.reg.space_id == \
113 ACPI_ADR_SPACE_SYSTEM_MEMORY)
114
115 /* Check if a CPC register is in SystemIo */
116 #define CPC_IN_SYSTEM_IO(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
117 (cpc)->cpc_entry.reg.space_id == \
118 ACPI_ADR_SPACE_SYSTEM_IO)
119
120 /* Evaluates to True if reg is a NULL register descriptor */
121 #define IS_NULL_REG(reg) ((reg)->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY && \
122 (reg)->address == 0 && \
123 (reg)->bit_width == 0 && \
124 (reg)->bit_offset == 0 && \
125 (reg)->access_width == 0)
126
127 /* Evaluates to True if an optional cpc field is supported */
128 #define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ? \
129 !!(cpc)->cpc_entry.int_value : \
130 !IS_NULL_REG(&(cpc)->cpc_entry.reg))
131
132 /*
133 * Each bit indicates the optionality of the register in per-cpu
134 * cpc_regs[] with the corresponding index. 0 means mandatory and 1
135 * means optional.
136 */
137 #define REG_OPTIONAL (0x1FC7D0)
138
139 /*
140 * Use the index of the register in per-cpu cpc_regs[] to check if
141 * it's an optional one.
142 */
143 #define IS_OPTIONAL_CPC_REG(reg_idx) (REG_OPTIONAL & (1U << (reg_idx)))
144
145 /*
146 * Arbitrary Retries in case the remote processor is slow to respond
147 * to PCC commands. Keeping it high enough to cover emulators where
148 * the processors run painfully slow.
149 */
150 #define NUM_RETRIES 500ULL
151
152 #define OVER_16BTS_MASK ~0xFFFFULL
153
154 #define define_one_cppc_ro(_name) \
155 static struct kobj_attribute _name = \
156 __ATTR(_name, 0444, show_##_name, NULL)
157
158 #define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj)
159
160 #define show_cppc_data(access_fn, struct_name, member_name) \
161 static ssize_t show_##member_name(struct kobject *kobj, \
162 struct kobj_attribute *attr, char *buf) \
163 { \
164 struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); \
165 struct struct_name st_name = {0}; \
166 int ret; \
167 \
168 ret = access_fn(cpc_ptr->cpu_id, &st_name); \
169 if (ret) \
170 return ret; \
171 \
172 return sysfs_emit(buf, "%llu\n", \
173 (u64)st_name.member_name); \
174 } \
175 define_one_cppc_ro(member_name)
176
177 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, highest_perf);
178 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_perf);
179 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_perf);
180 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf);
181 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, guaranteed_perf);
182 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_freq);
183 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq);
184
185 show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf);
186 show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time);
187
188 /* Check for valid access_width, otherwise, fallback to using bit_width */
189 #define GET_BIT_WIDTH(reg) ((reg)->access_width ? (8 << ((reg)->access_width - 1)) : (reg)->bit_width)
190
191 /* Shift and apply the mask for CPC reads/writes */
192 #define MASK_VAL_READ(reg, val) (((val) >> (reg)->bit_offset) & \
193 GENMASK(((reg)->bit_width) - 1, 0))
194 #define MASK_VAL_WRITE(reg, prev_val, val) \
195 ((((val) & GENMASK(((reg)->bit_width) - 1, 0)) << (reg)->bit_offset) | \
196 ((prev_val) & ~(GENMASK(((reg)->bit_width) - 1, 0) << (reg)->bit_offset))) \
197
show_feedback_ctrs(struct kobject * kobj,struct kobj_attribute * attr,char * buf)198 static ssize_t show_feedback_ctrs(struct kobject *kobj,
199 struct kobj_attribute *attr, char *buf)
200 {
201 struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);
202 struct cppc_perf_fb_ctrs fb_ctrs = {0};
203 int ret;
204
205 ret = cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs);
206 if (ret)
207 return ret;
208
209 return sysfs_emit(buf, "ref:%llu del:%llu\n",
210 fb_ctrs.reference, fb_ctrs.delivered);
211 }
212 define_one_cppc_ro(feedback_ctrs);
213
214 static struct attribute *cppc_attrs[] = {
215 &feedback_ctrs.attr,
216 &reference_perf.attr,
217 &wraparound_time.attr,
218 &highest_perf.attr,
219 &lowest_perf.attr,
220 &lowest_nonlinear_perf.attr,
221 &guaranteed_perf.attr,
222 &nominal_perf.attr,
223 &nominal_freq.attr,
224 &lowest_freq.attr,
225 NULL
226 };
227 ATTRIBUTE_GROUPS(cppc);
228
229 static const struct kobj_type cppc_ktype = {
230 .sysfs_ops = &kobj_sysfs_ops,
231 .default_groups = cppc_groups,
232 };
233
check_pcc_chan(int pcc_ss_id,bool chk_err_bit)234 static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit)
235 {
236 int ret, status;
237 struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
238 struct acpi_pcct_shared_memory __iomem *generic_comm_base =
239 pcc_ss_data->pcc_channel->shmem;
240
241 if (!pcc_ss_data->platform_owns_pcc)
242 return 0;
243
244 /*
245 * Poll PCC status register every 3us(delay_us) for maximum of
246 * deadline_us(timeout_us) until PCC command complete bit is set(cond)
247 */
248 ret = readw_relaxed_poll_timeout(&generic_comm_base->status, status,
249 status & PCC_CMD_COMPLETE_MASK, 3,
250 pcc_ss_data->deadline_us);
251
252 if (likely(!ret)) {
253 pcc_ss_data->platform_owns_pcc = false;
254 if (chk_err_bit && (status & PCC_ERROR_MASK))
255 ret = -EIO;
256 }
257
258 if (unlikely(ret))
259 pr_err("PCC check channel failed for ss: %d. ret=%d\n",
260 pcc_ss_id, ret);
261
262 return ret;
263 }
264
265 /*
266 * This function transfers the ownership of the PCC to the platform
267 * So it must be called while holding write_lock(pcc_lock)
268 */
send_pcc_cmd(int pcc_ss_id,u16 cmd)269 static int send_pcc_cmd(int pcc_ss_id, u16 cmd)
270 {
271 int ret = -EIO, i;
272 struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
273 struct acpi_pcct_shared_memory __iomem *generic_comm_base =
274 pcc_ss_data->pcc_channel->shmem;
275 unsigned int time_delta;
276
277 /*
278 * For CMD_WRITE we know for a fact the caller should have checked
279 * the channel before writing to PCC space
280 */
281 if (cmd == CMD_READ) {
282 /*
283 * If there are pending cpc_writes, then we stole the channel
284 * before write completion, so first send a WRITE command to
285 * platform
286 */
287 if (pcc_ss_data->pending_pcc_write_cmd)
288 send_pcc_cmd(pcc_ss_id, CMD_WRITE);
289
290 ret = check_pcc_chan(pcc_ss_id, false);
291 if (ret)
292 goto end;
293 } else /* CMD_WRITE */
294 pcc_ss_data->pending_pcc_write_cmd = FALSE;
295
296 /*
297 * Handle the Minimum Request Turnaround Time(MRTT)
298 * "The minimum amount of time that OSPM must wait after the completion
299 * of a command before issuing the next command, in microseconds"
300 */
301 if (pcc_ss_data->pcc_mrtt) {
302 time_delta = ktime_us_delta(ktime_get(),
303 pcc_ss_data->last_cmd_cmpl_time);
304 if (pcc_ss_data->pcc_mrtt > time_delta)
305 udelay(pcc_ss_data->pcc_mrtt - time_delta);
306 }
307
308 /*
309 * Handle the non-zero Maximum Periodic Access Rate(MPAR)
310 * "The maximum number of periodic requests that the subspace channel can
311 * support, reported in commands per minute. 0 indicates no limitation."
312 *
313 * This parameter should be ideally zero or large enough so that it can
314 * handle maximum number of requests that all the cores in the system can
315 * collectively generate. If it is not, we will follow the spec and just
316 * not send the request to the platform after hitting the MPAR limit in
317 * any 60s window
318 */
319 if (pcc_ss_data->pcc_mpar) {
320 if (pcc_ss_data->mpar_count == 0) {
321 time_delta = ktime_ms_delta(ktime_get(),
322 pcc_ss_data->last_mpar_reset);
323 if ((time_delta < 60 * MSEC_PER_SEC) && pcc_ss_data->last_mpar_reset) {
324 pr_debug("PCC cmd for subspace %d not sent due to MPAR limit",
325 pcc_ss_id);
326 ret = -EIO;
327 goto end;
328 }
329 pcc_ss_data->last_mpar_reset = ktime_get();
330 pcc_ss_data->mpar_count = pcc_ss_data->pcc_mpar;
331 }
332 pcc_ss_data->mpar_count--;
333 }
334
335 /* Write to the shared comm region. */
336 writew_relaxed(cmd, &generic_comm_base->command);
337
338 /* Flip CMD COMPLETE bit */
339 writew_relaxed(0, &generic_comm_base->status);
340
341 pcc_ss_data->platform_owns_pcc = true;
342
343 /* Ring doorbell */
344 ret = mbox_send_message(pcc_ss_data->pcc_channel->mchan, &cmd);
345 if (ret < 0) {
346 pr_err("Err sending PCC mbox message. ss: %d cmd:%d, ret:%d\n",
347 pcc_ss_id, cmd, ret);
348 goto end;
349 }
350
351 /* wait for completion and check for PCC error bit */
352 ret = check_pcc_chan(pcc_ss_id, true);
353
354 if (pcc_ss_data->pcc_mrtt)
355 pcc_ss_data->last_cmd_cmpl_time = ktime_get();
356
357 if (pcc_ss_data->pcc_channel->mchan->mbox->txdone_irq)
358 mbox_chan_txdone(pcc_ss_data->pcc_channel->mchan, ret);
359 else
360 mbox_client_txdone(pcc_ss_data->pcc_channel->mchan, ret);
361
362 end:
363 if (cmd == CMD_WRITE) {
364 if (unlikely(ret)) {
365 for_each_possible_cpu(i) {
366 struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i);
367
368 if (!desc)
369 continue;
370
371 if (desc->write_cmd_id == pcc_ss_data->pcc_write_cnt)
372 desc->write_cmd_status = ret;
373 }
374 }
375 pcc_ss_data->pcc_write_cnt++;
376 wake_up_all(&pcc_ss_data->pcc_write_wait_q);
377 }
378
379 return ret;
380 }
381
cppc_chan_tx_done(struct mbox_client * cl,void * msg,int ret)382 static void cppc_chan_tx_done(struct mbox_client *cl, void *msg, int ret)
383 {
384 if (ret < 0)
385 pr_debug("TX did not complete: CMD sent:%x, ret:%d\n",
386 *(u16 *)msg, ret);
387 else
388 pr_debug("TX completed. CMD sent:%x, ret:%d\n",
389 *(u16 *)msg, ret);
390 }
391
392 static struct mbox_client cppc_mbox_cl = {
393 .tx_done = cppc_chan_tx_done,
394 .knows_txdone = true,
395 };
396
acpi_get_psd(struct cpc_desc * cpc_ptr,acpi_handle handle)397 static int acpi_get_psd(struct cpc_desc *cpc_ptr, acpi_handle handle)
398 {
399 int result = -EFAULT;
400 acpi_status status = AE_OK;
401 struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL};
402 struct acpi_buffer format = {sizeof("NNNNN"), "NNNNN"};
403 struct acpi_buffer state = {0, NULL};
404 union acpi_object *psd = NULL;
405 struct acpi_psd_package *pdomain;
406
407 status = acpi_evaluate_object_typed(handle, "_PSD", NULL,
408 &buffer, ACPI_TYPE_PACKAGE);
409 if (status == AE_NOT_FOUND) /* _PSD is optional */
410 return 0;
411 if (ACPI_FAILURE(status))
412 return -ENODEV;
413
414 psd = buffer.pointer;
415 if (!psd || psd->package.count != 1) {
416 pr_debug("Invalid _PSD data\n");
417 goto end;
418 }
419
420 pdomain = &(cpc_ptr->domain_info);
421
422 state.length = sizeof(struct acpi_psd_package);
423 state.pointer = pdomain;
424
425 status = acpi_extract_package(&(psd->package.elements[0]),
426 &format, &state);
427 if (ACPI_FAILURE(status)) {
428 pr_debug("Invalid _PSD data for CPU:%d\n", cpc_ptr->cpu_id);
429 goto end;
430 }
431
432 if (pdomain->num_entries != ACPI_PSD_REV0_ENTRIES) {
433 pr_debug("Unknown _PSD:num_entries for CPU:%d\n", cpc_ptr->cpu_id);
434 goto end;
435 }
436
437 if (pdomain->revision != ACPI_PSD_REV0_REVISION) {
438 pr_debug("Unknown _PSD:revision for CPU: %d\n", cpc_ptr->cpu_id);
439 goto end;
440 }
441
442 if (pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ALL &&
443 pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ANY &&
444 pdomain->coord_type != DOMAIN_COORD_TYPE_HW_ALL) {
445 pr_debug("Invalid _PSD:coord_type for CPU:%d\n", cpc_ptr->cpu_id);
446 goto end;
447 }
448
449 result = 0;
450 end:
451 kfree(buffer.pointer);
452 return result;
453 }
454
acpi_cpc_valid(void)455 bool acpi_cpc_valid(void)
456 {
457 struct cpc_desc *cpc_ptr;
458 int cpu;
459
460 if (acpi_disabled)
461 return false;
462
463 for_each_present_cpu(cpu) {
464 cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
465 if (!cpc_ptr)
466 return false;
467 }
468
469 return true;
470 }
471 EXPORT_SYMBOL_GPL(acpi_cpc_valid);
472
cppc_allow_fast_switch(void)473 bool cppc_allow_fast_switch(void)
474 {
475 struct cpc_register_resource *desired_reg;
476 struct cpc_desc *cpc_ptr;
477 int cpu;
478
479 for_each_present_cpu(cpu) {
480 cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
481 desired_reg = &cpc_ptr->cpc_regs[DESIRED_PERF];
482 if (!CPC_IN_SYSTEM_MEMORY(desired_reg) &&
483 !CPC_IN_SYSTEM_IO(desired_reg))
484 return false;
485 }
486
487 return true;
488 }
489 EXPORT_SYMBOL_GPL(cppc_allow_fast_switch);
490
491 /**
492 * acpi_get_psd_map - Map the CPUs in the freq domain of a given cpu
493 * @cpu: Find all CPUs that share a domain with cpu.
494 * @cpu_data: Pointer to CPU specific CPPC data including PSD info.
495 *
496 * Return: 0 for success or negative value for err.
497 */
acpi_get_psd_map(unsigned int cpu,struct cppc_cpudata * cpu_data)498 int acpi_get_psd_map(unsigned int cpu, struct cppc_cpudata *cpu_data)
499 {
500 struct cpc_desc *cpc_ptr, *match_cpc_ptr;
501 struct acpi_psd_package *match_pdomain;
502 struct acpi_psd_package *pdomain;
503 int count_target, i;
504
505 /*
506 * Now that we have _PSD data from all CPUs, let's setup P-state
507 * domain info.
508 */
509 cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
510 if (!cpc_ptr)
511 return -EFAULT;
512
513 pdomain = &(cpc_ptr->domain_info);
514 cpumask_set_cpu(cpu, cpu_data->shared_cpu_map);
515 if (pdomain->num_processors <= 1)
516 return 0;
517
518 /* Validate the Domain info */
519 count_target = pdomain->num_processors;
520 if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL)
521 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ALL;
522 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL)
523 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_HW;
524 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY)
525 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ANY;
526
527 for_each_possible_cpu(i) {
528 if (i == cpu)
529 continue;
530
531 match_cpc_ptr = per_cpu(cpc_desc_ptr, i);
532 if (!match_cpc_ptr)
533 goto err_fault;
534
535 match_pdomain = &(match_cpc_ptr->domain_info);
536 if (match_pdomain->domain != pdomain->domain)
537 continue;
538
539 /* Here i and cpu are in the same domain */
540 if (match_pdomain->num_processors != count_target)
541 goto err_fault;
542
543 if (pdomain->coord_type != match_pdomain->coord_type)
544 goto err_fault;
545
546 cpumask_set_cpu(i, cpu_data->shared_cpu_map);
547 }
548
549 return 0;
550
551 err_fault:
552 /* Assume no coordination on any error parsing domain info */
553 cpumask_clear(cpu_data->shared_cpu_map);
554 cpumask_set_cpu(cpu, cpu_data->shared_cpu_map);
555 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_NONE;
556
557 return -EFAULT;
558 }
559 EXPORT_SYMBOL_GPL(acpi_get_psd_map);
560
register_pcc_channel(int pcc_ss_idx)561 static int register_pcc_channel(int pcc_ss_idx)
562 {
563 struct pcc_mbox_chan *pcc_chan;
564 u64 usecs_lat;
565
566 if (pcc_ss_idx >= 0) {
567 pcc_chan = pcc_mbox_request_channel(&cppc_mbox_cl, pcc_ss_idx);
568
569 if (IS_ERR(pcc_chan)) {
570 pr_err("Failed to find PCC channel for subspace %d\n",
571 pcc_ss_idx);
572 return -ENODEV;
573 }
574
575 pcc_data[pcc_ss_idx]->pcc_channel = pcc_chan;
576 /*
577 * cppc_ss->latency is just a Nominal value. In reality
578 * the remote processor could be much slower to reply.
579 * So add an arbitrary amount of wait on top of Nominal.
580 */
581 usecs_lat = NUM_RETRIES * pcc_chan->latency;
582 pcc_data[pcc_ss_idx]->deadline_us = usecs_lat;
583 pcc_data[pcc_ss_idx]->pcc_mrtt = pcc_chan->min_turnaround_time;
584 pcc_data[pcc_ss_idx]->pcc_mpar = pcc_chan->max_access_rate;
585 pcc_data[pcc_ss_idx]->pcc_nominal = pcc_chan->latency;
586
587 /* Set flag so that we don't come here for each CPU. */
588 pcc_data[pcc_ss_idx]->pcc_channel_acquired = true;
589 }
590
591 return 0;
592 }
593
594 /**
595 * cpc_ffh_supported() - check if FFH reading supported
596 *
597 * Check if the architecture has support for functional fixed hardware
598 * read/write capability.
599 *
600 * Return: true for supported, false for not supported
601 */
cpc_ffh_supported(void)602 bool __weak cpc_ffh_supported(void)
603 {
604 return false;
605 }
606
607 /**
608 * cpc_supported_by_cpu() - check if CPPC is supported by CPU
609 *
610 * Check if the architectural support for CPPC is present even
611 * if the _OSC hasn't prescribed it
612 *
613 * Return: true for supported, false for not supported
614 */
cpc_supported_by_cpu(void)615 bool __weak cpc_supported_by_cpu(void)
616 {
617 return false;
618 }
619
620 /**
621 * pcc_data_alloc() - Allocate the pcc_data memory for pcc subspace
622 * @pcc_ss_id: PCC Subspace index as in the PCC client ACPI package.
623 *
624 * Check and allocate the cppc_pcc_data memory.
625 * In some processor configurations it is possible that same subspace
626 * is shared between multiple CPUs. This is seen especially in CPUs
627 * with hardware multi-threading support.
628 *
629 * Return: 0 for success, errno for failure
630 */
pcc_data_alloc(int pcc_ss_id)631 static int pcc_data_alloc(int pcc_ss_id)
632 {
633 if (pcc_ss_id < 0 || pcc_ss_id >= MAX_PCC_SUBSPACES)
634 return -EINVAL;
635
636 if (pcc_data[pcc_ss_id]) {
637 pcc_data[pcc_ss_id]->refcount++;
638 } else {
639 pcc_data[pcc_ss_id] = kzalloc(sizeof(struct cppc_pcc_data),
640 GFP_KERNEL);
641 if (!pcc_data[pcc_ss_id])
642 return -ENOMEM;
643 pcc_data[pcc_ss_id]->refcount++;
644 }
645
646 return 0;
647 }
648
649 /*
650 * An example CPC table looks like the following.
651 *
652 * Name (_CPC, Package() {
653 * 17, // NumEntries
654 * 1, // Revision
655 * ResourceTemplate() {Register(PCC, 32, 0, 0x120, 2)}, // Highest Performance
656 * ResourceTemplate() {Register(PCC, 32, 0, 0x124, 2)}, // Nominal Performance
657 * ResourceTemplate() {Register(PCC, 32, 0, 0x128, 2)}, // Lowest Nonlinear Performance
658 * ResourceTemplate() {Register(PCC, 32, 0, 0x12C, 2)}, // Lowest Performance
659 * ResourceTemplate() {Register(PCC, 32, 0, 0x130, 2)}, // Guaranteed Performance Register
660 * ResourceTemplate() {Register(PCC, 32, 0, 0x110, 2)}, // Desired Performance Register
661 * ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)},
662 * ...
663 * ...
664 * ...
665 * }
666 * Each Register() encodes how to access that specific register.
667 * e.g. a sample PCC entry has the following encoding:
668 *
669 * Register (
670 * PCC, // AddressSpaceKeyword
671 * 8, // RegisterBitWidth
672 * 8, // RegisterBitOffset
673 * 0x30, // RegisterAddress
674 * 9, // AccessSize (subspace ID)
675 * )
676 */
677
678 /**
679 * acpi_cppc_processor_probe - Search for per CPU _CPC objects.
680 * @pr: Ptr to acpi_processor containing this CPU's logical ID.
681 *
682 * Return: 0 for success or negative value for err.
683 */
acpi_cppc_processor_probe(struct acpi_processor * pr)684 int acpi_cppc_processor_probe(struct acpi_processor *pr)
685 {
686 struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL};
687 union acpi_object *out_obj, *cpc_obj;
688 struct cpc_desc *cpc_ptr;
689 struct cpc_reg *gas_t;
690 struct device *cpu_dev;
691 acpi_handle handle = pr->handle;
692 unsigned int num_ent, i, cpc_rev;
693 int pcc_subspace_id = -1;
694 acpi_status status;
695 int ret = -ENODATA;
696
697 if (!osc_sb_cppc2_support_acked) {
698 pr_debug("CPPC v2 _OSC not acked\n");
699 if (!cpc_supported_by_cpu()) {
700 pr_debug("CPPC is not supported by the CPU\n");
701 return -ENODEV;
702 }
703 }
704
705 /* Parse the ACPI _CPC table for this CPU. */
706 status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output,
707 ACPI_TYPE_PACKAGE);
708 if (ACPI_FAILURE(status)) {
709 ret = -ENODEV;
710 goto out_buf_free;
711 }
712
713 out_obj = (union acpi_object *) output.pointer;
714
715 cpc_ptr = kzalloc(sizeof(struct cpc_desc), GFP_KERNEL);
716 if (!cpc_ptr) {
717 ret = -ENOMEM;
718 goto out_buf_free;
719 }
720
721 /* First entry is NumEntries. */
722 cpc_obj = &out_obj->package.elements[0];
723 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
724 num_ent = cpc_obj->integer.value;
725 if (num_ent <= 1) {
726 pr_debug("Unexpected _CPC NumEntries value (%d) for CPU:%d\n",
727 num_ent, pr->id);
728 goto out_free;
729 }
730 } else {
731 pr_debug("Unexpected _CPC NumEntries entry type (%d) for CPU:%d\n",
732 cpc_obj->type, pr->id);
733 goto out_free;
734 }
735
736 /* Second entry should be revision. */
737 cpc_obj = &out_obj->package.elements[1];
738 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
739 cpc_rev = cpc_obj->integer.value;
740 } else {
741 pr_debug("Unexpected _CPC Revision entry type (%d) for CPU:%d\n",
742 cpc_obj->type, pr->id);
743 goto out_free;
744 }
745
746 if (cpc_rev < CPPC_V2_REV) {
747 pr_debug("Unsupported _CPC Revision (%d) for CPU:%d\n", cpc_rev,
748 pr->id);
749 goto out_free;
750 }
751
752 /*
753 * Disregard _CPC if the number of entries in the return pachage is not
754 * as expected, but support future revisions being proper supersets of
755 * the v3 and only causing more entries to be returned by _CPC.
756 */
757 if ((cpc_rev == CPPC_V2_REV && num_ent != CPPC_V2_NUM_ENT) ||
758 (cpc_rev == CPPC_V3_REV && num_ent != CPPC_V3_NUM_ENT) ||
759 (cpc_rev > CPPC_V3_REV && num_ent <= CPPC_V3_NUM_ENT)) {
760 pr_debug("Unexpected number of _CPC return package entries (%d) for CPU:%d\n",
761 num_ent, pr->id);
762 goto out_free;
763 }
764 if (cpc_rev > CPPC_V3_REV) {
765 num_ent = CPPC_V3_NUM_ENT;
766 cpc_rev = CPPC_V3_REV;
767 }
768
769 cpc_ptr->num_entries = num_ent;
770 cpc_ptr->version = cpc_rev;
771
772 /* Iterate through remaining entries in _CPC */
773 for (i = 2; i < num_ent; i++) {
774 cpc_obj = &out_obj->package.elements[i];
775
776 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
777 cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER;
778 cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value;
779 } else if (cpc_obj->type == ACPI_TYPE_BUFFER) {
780 gas_t = (struct cpc_reg *)
781 cpc_obj->buffer.pointer;
782
783 /*
784 * The PCC Subspace index is encoded inside
785 * the CPC table entries. The same PCC index
786 * will be used for all the PCC entries,
787 * so extract it only once.
788 */
789 if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
790 if (pcc_subspace_id < 0) {
791 pcc_subspace_id = gas_t->access_width;
792 if (pcc_data_alloc(pcc_subspace_id))
793 goto out_free;
794 } else if (pcc_subspace_id != gas_t->access_width) {
795 pr_debug("Mismatched PCC ids in _CPC for CPU:%d\n",
796 pr->id);
797 goto out_free;
798 }
799 } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
800 if (gas_t->address) {
801 void __iomem *addr;
802 size_t access_width;
803
804 if (!osc_cpc_flexible_adr_space_confirmed) {
805 pr_debug("Flexible address space capability not supported\n");
806 if (!cpc_supported_by_cpu())
807 goto out_free;
808 }
809
810 access_width = GET_BIT_WIDTH(gas_t) / 8;
811 addr = ioremap(gas_t->address, access_width);
812 if (!addr)
813 goto out_free;
814 cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr;
815 }
816 } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
817 if (gas_t->access_width < 1 || gas_t->access_width > 3) {
818 /*
819 * 1 = 8-bit, 2 = 16-bit, and 3 = 32-bit.
820 * SystemIO doesn't implement 64-bit
821 * registers.
822 */
823 pr_debug("Invalid access width %d for SystemIO register in _CPC\n",
824 gas_t->access_width);
825 goto out_free;
826 }
827 if (gas_t->address & OVER_16BTS_MASK) {
828 /* SystemIO registers use 16-bit integer addresses */
829 pr_debug("Invalid IO port %llu for SystemIO register in _CPC\n",
830 gas_t->address);
831 goto out_free;
832 }
833 if (!osc_cpc_flexible_adr_space_confirmed) {
834 pr_debug("Flexible address space capability not supported\n");
835 if (!cpc_supported_by_cpu())
836 goto out_free;
837 }
838 } else {
839 if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) {
840 /* Support only PCC, SystemMemory, SystemIO, and FFH type regs. */
841 pr_debug("Unsupported register type (%d) in _CPC\n",
842 gas_t->space_id);
843 goto out_free;
844 }
845 }
846
847 cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER;
848 memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t));
849 } else {
850 pr_debug("Invalid entry type (%d) in _CPC for CPU:%d\n",
851 i, pr->id);
852 goto out_free;
853 }
854 }
855 per_cpu(cpu_pcc_subspace_idx, pr->id) = pcc_subspace_id;
856
857 /*
858 * Initialize the remaining cpc_regs as unsupported.
859 * Example: In case FW exposes CPPC v2, the below loop will initialize
860 * LOWEST_FREQ and NOMINAL_FREQ regs as unsupported
861 */
862 for (i = num_ent - 2; i < MAX_CPC_REG_ENT; i++) {
863 cpc_ptr->cpc_regs[i].type = ACPI_TYPE_INTEGER;
864 cpc_ptr->cpc_regs[i].cpc_entry.int_value = 0;
865 }
866
867
868 /* Store CPU Logical ID */
869 cpc_ptr->cpu_id = pr->id;
870 raw_spin_lock_init(&cpc_ptr->rmw_lock);
871
872 /* Parse PSD data for this CPU */
873 ret = acpi_get_psd(cpc_ptr, handle);
874 if (ret)
875 goto out_free;
876
877 /* Register PCC channel once for all PCC subspace ID. */
878 if (pcc_subspace_id >= 0 && !pcc_data[pcc_subspace_id]->pcc_channel_acquired) {
879 ret = register_pcc_channel(pcc_subspace_id);
880 if (ret)
881 goto out_free;
882
883 init_rwsem(&pcc_data[pcc_subspace_id]->pcc_lock);
884 init_waitqueue_head(&pcc_data[pcc_subspace_id]->pcc_write_wait_q);
885 }
886
887 /* Everything looks okay */
888 pr_debug("Parsed CPC struct for CPU: %d\n", pr->id);
889
890 /* Add per logical CPU nodes for reading its feedback counters. */
891 cpu_dev = get_cpu_device(pr->id);
892 if (!cpu_dev) {
893 ret = -EINVAL;
894 goto out_free;
895 }
896
897 /* Plug PSD data into this CPU's CPC descriptor. */
898 per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr;
899
900 ret = kobject_init_and_add(&cpc_ptr->kobj, &cppc_ktype, &cpu_dev->kobj,
901 "acpi_cppc");
902 if (ret) {
903 per_cpu(cpc_desc_ptr, pr->id) = NULL;
904 kobject_put(&cpc_ptr->kobj);
905 goto out_free;
906 }
907
908 kfree(output.pointer);
909 return 0;
910
911 out_free:
912 /* Free all the mapped sys mem areas for this CPU */
913 for (i = 2; i < cpc_ptr->num_entries; i++) {
914 void __iomem *addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
915
916 if (addr)
917 iounmap(addr);
918 }
919 kfree(cpc_ptr);
920
921 out_buf_free:
922 kfree(output.pointer);
923 return ret;
924 }
925 EXPORT_SYMBOL_GPL(acpi_cppc_processor_probe);
926
927 /**
928 * acpi_cppc_processor_exit - Cleanup CPC structs.
929 * @pr: Ptr to acpi_processor containing this CPU's logical ID.
930 *
931 * Return: Void
932 */
acpi_cppc_processor_exit(struct acpi_processor * pr)933 void acpi_cppc_processor_exit(struct acpi_processor *pr)
934 {
935 struct cpc_desc *cpc_ptr;
936 unsigned int i;
937 void __iomem *addr;
938 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, pr->id);
939
940 if (pcc_ss_id >= 0 && pcc_data[pcc_ss_id]) {
941 if (pcc_data[pcc_ss_id]->pcc_channel_acquired) {
942 pcc_data[pcc_ss_id]->refcount--;
943 if (!pcc_data[pcc_ss_id]->refcount) {
944 pcc_mbox_free_channel(pcc_data[pcc_ss_id]->pcc_channel);
945 kfree(pcc_data[pcc_ss_id]);
946 pcc_data[pcc_ss_id] = NULL;
947 }
948 }
949 }
950
951 cpc_ptr = per_cpu(cpc_desc_ptr, pr->id);
952 if (!cpc_ptr)
953 return;
954
955 /* Free all the mapped sys mem areas for this CPU */
956 for (i = 2; i < cpc_ptr->num_entries; i++) {
957 addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
958 if (addr)
959 iounmap(addr);
960 }
961
962 kobject_put(&cpc_ptr->kobj);
963 kfree(cpc_ptr);
964 }
965 EXPORT_SYMBOL_GPL(acpi_cppc_processor_exit);
966
967 /**
968 * cpc_read_ffh() - Read FFH register
969 * @cpunum: CPU number to read
970 * @reg: cppc register information
971 * @val: place holder for return value
972 *
973 * Read bit_width bits from a specified address and bit_offset
974 *
975 * Return: 0 for success and error code
976 */
cpc_read_ffh(int cpunum,struct cpc_reg * reg,u64 * val)977 int __weak cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val)
978 {
979 return -ENOTSUPP;
980 }
981
982 /**
983 * cpc_write_ffh() - Write FFH register
984 * @cpunum: CPU number to write
985 * @reg: cppc register information
986 * @val: value to write
987 *
988 * Write value of bit_width bits to a specified address and bit_offset
989 *
990 * Return: 0 for success and error code
991 */
cpc_write_ffh(int cpunum,struct cpc_reg * reg,u64 val)992 int __weak cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)
993 {
994 return -ENOTSUPP;
995 }
996
997 /*
998 * Since cpc_read and cpc_write are called while holding pcc_lock, it should be
999 * as fast as possible. We have already mapped the PCC subspace during init, so
1000 * we can directly write to it.
1001 */
1002
cpc_read(int cpu,struct cpc_register_resource * reg_res,u64 * val)1003 static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
1004 {
1005 void __iomem *vaddr = NULL;
1006 int size;
1007 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1008 struct cpc_reg *reg = ®_res->cpc_entry.reg;
1009
1010 if (reg_res->type == ACPI_TYPE_INTEGER) {
1011 *val = reg_res->cpc_entry.int_value;
1012 return 0;
1013 }
1014
1015 *val = 0;
1016 size = GET_BIT_WIDTH(reg);
1017
1018 if (IS_ENABLED(CONFIG_HAS_IOPORT) &&
1019 reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
1020 u32 val_u32;
1021 acpi_status status;
1022
1023 status = acpi_os_read_port((acpi_io_address)reg->address,
1024 &val_u32, size);
1025 if (ACPI_FAILURE(status)) {
1026 pr_debug("Error: Failed to read SystemIO port %llx\n",
1027 reg->address);
1028 return -EFAULT;
1029 }
1030
1031 *val = val_u32;
1032 return 0;
1033 } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) {
1034 /*
1035 * For registers in PCC space, the register size is determined
1036 * by the bit width field; the access size is used to indicate
1037 * the PCC subspace id.
1038 */
1039 size = reg->bit_width;
1040 vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
1041 }
1042 else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
1043 vaddr = reg_res->sys_mem_vaddr;
1044 else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
1045 return cpc_read_ffh(cpu, reg, val);
1046 else
1047 return acpi_os_read_memory((acpi_physical_address)reg->address,
1048 val, size);
1049
1050 switch (size) {
1051 case 8:
1052 *val = readb_relaxed(vaddr);
1053 break;
1054 case 16:
1055 *val = readw_relaxed(vaddr);
1056 break;
1057 case 32:
1058 *val = readl_relaxed(vaddr);
1059 break;
1060 case 64:
1061 *val = readq_relaxed(vaddr);
1062 break;
1063 default:
1064 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
1065 pr_debug("Error: Cannot read %u bit width from system memory: 0x%llx\n",
1066 size, reg->address);
1067 } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
1068 pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n",
1069 size, pcc_ss_id);
1070 }
1071 return -EFAULT;
1072 }
1073
1074 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
1075 *val = MASK_VAL_READ(reg, *val);
1076
1077 return 0;
1078 }
1079
cpc_write(int cpu,struct cpc_register_resource * reg_res,u64 val)1080 static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
1081 {
1082 int ret_val = 0;
1083 int size;
1084 u64 prev_val;
1085 void __iomem *vaddr = NULL;
1086 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1087 struct cpc_reg *reg = ®_res->cpc_entry.reg;
1088 struct cpc_desc *cpc_desc;
1089 unsigned long flags;
1090
1091 size = GET_BIT_WIDTH(reg);
1092
1093 if (IS_ENABLED(CONFIG_HAS_IOPORT) &&
1094 reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
1095 acpi_status status;
1096
1097 status = acpi_os_write_port((acpi_io_address)reg->address,
1098 (u32)val, size);
1099 if (ACPI_FAILURE(status)) {
1100 pr_debug("Error: Failed to write SystemIO port %llx\n",
1101 reg->address);
1102 return -EFAULT;
1103 }
1104
1105 return 0;
1106 } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) {
1107 /*
1108 * For registers in PCC space, the register size is determined
1109 * by the bit width field; the access size is used to indicate
1110 * the PCC subspace id.
1111 */
1112 size = reg->bit_width;
1113 vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
1114 }
1115 else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
1116 vaddr = reg_res->sys_mem_vaddr;
1117 else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
1118 return cpc_write_ffh(cpu, reg, val);
1119 else
1120 return acpi_os_write_memory((acpi_physical_address)reg->address,
1121 val, size);
1122
1123 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
1124 cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1125 if (!cpc_desc) {
1126 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1127 return -ENODEV;
1128 }
1129
1130 raw_spin_lock_irqsave(&cpc_desc->rmw_lock, flags);
1131 switch (size) {
1132 case 8:
1133 prev_val = readb_relaxed(vaddr);
1134 break;
1135 case 16:
1136 prev_val = readw_relaxed(vaddr);
1137 break;
1138 case 32:
1139 prev_val = readl_relaxed(vaddr);
1140 break;
1141 case 64:
1142 prev_val = readq_relaxed(vaddr);
1143 break;
1144 default:
1145 raw_spin_unlock_irqrestore(&cpc_desc->rmw_lock, flags);
1146 return -EFAULT;
1147 }
1148 val = MASK_VAL_WRITE(reg, prev_val, val);
1149 }
1150
1151 switch (size) {
1152 case 8:
1153 writeb_relaxed(val, vaddr);
1154 break;
1155 case 16:
1156 writew_relaxed(val, vaddr);
1157 break;
1158 case 32:
1159 writel_relaxed(val, vaddr);
1160 break;
1161 case 64:
1162 writeq_relaxed(val, vaddr);
1163 break;
1164 default:
1165 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
1166 pr_debug("Error: Cannot write %u bit width to system memory: 0x%llx\n",
1167 size, reg->address);
1168 } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
1169 pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n",
1170 size, pcc_ss_id);
1171 }
1172 ret_val = -EFAULT;
1173 break;
1174 }
1175
1176 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
1177 raw_spin_unlock_irqrestore(&cpc_desc->rmw_lock, flags);
1178
1179 return ret_val;
1180 }
1181
cppc_get_reg_val_in_pcc(int cpu,struct cpc_register_resource * reg,u64 * val)1182 static int cppc_get_reg_val_in_pcc(int cpu, struct cpc_register_resource *reg, u64 *val)
1183 {
1184 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1185 struct cppc_pcc_data *pcc_ss_data = NULL;
1186 int ret;
1187
1188 if (pcc_ss_id < 0) {
1189 pr_debug("Invalid pcc_ss_id\n");
1190 return -ENODEV;
1191 }
1192
1193 pcc_ss_data = pcc_data[pcc_ss_id];
1194
1195 down_write(&pcc_ss_data->pcc_lock);
1196
1197 if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0)
1198 ret = cpc_read(cpu, reg, val);
1199 else
1200 ret = -EIO;
1201
1202 up_write(&pcc_ss_data->pcc_lock);
1203
1204 return ret;
1205 }
1206
cppc_get_reg_val(int cpu,enum cppc_regs reg_idx,u64 * val)1207 static int cppc_get_reg_val(int cpu, enum cppc_regs reg_idx, u64 *val)
1208 {
1209 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1210 struct cpc_register_resource *reg;
1211
1212 if (val == NULL)
1213 return -EINVAL;
1214
1215 if (!cpc_desc) {
1216 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1217 return -ENODEV;
1218 }
1219
1220 reg = &cpc_desc->cpc_regs[reg_idx];
1221
1222 if ((reg->type == ACPI_TYPE_INTEGER && IS_OPTIONAL_CPC_REG(reg_idx) &&
1223 !reg->cpc_entry.int_value) || (reg->type != ACPI_TYPE_INTEGER &&
1224 IS_NULL_REG(®->cpc_entry.reg))) {
1225 pr_debug("CPC register is not supported\n");
1226 return -EOPNOTSUPP;
1227 }
1228
1229 if (CPC_IN_PCC(reg))
1230 return cppc_get_reg_val_in_pcc(cpu, reg, val);
1231
1232 return cpc_read(cpu, reg, val);
1233 }
1234
cppc_set_reg_val_in_pcc(int cpu,struct cpc_register_resource * reg,u64 val)1235 static int cppc_set_reg_val_in_pcc(int cpu, struct cpc_register_resource *reg, u64 val)
1236 {
1237 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1238 struct cppc_pcc_data *pcc_ss_data = NULL;
1239 int ret;
1240
1241 if (pcc_ss_id < 0) {
1242 pr_debug("Invalid pcc_ss_id\n");
1243 return -ENODEV;
1244 }
1245
1246 ret = cpc_write(cpu, reg, val);
1247 if (ret)
1248 return ret;
1249
1250 pcc_ss_data = pcc_data[pcc_ss_id];
1251
1252 down_write(&pcc_ss_data->pcc_lock);
1253 /* after writing CPC, transfer the ownership of PCC to platform */
1254 ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
1255 up_write(&pcc_ss_data->pcc_lock);
1256
1257 return ret;
1258 }
1259
cppc_set_reg_val(int cpu,enum cppc_regs reg_idx,u64 val)1260 static int cppc_set_reg_val(int cpu, enum cppc_regs reg_idx, u64 val)
1261 {
1262 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1263 struct cpc_register_resource *reg;
1264
1265 if (!cpc_desc) {
1266 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1267 return -ENODEV;
1268 }
1269
1270 reg = &cpc_desc->cpc_regs[reg_idx];
1271
1272 /* if a register is writeable, it must be a buffer and not null */
1273 if ((reg->type != ACPI_TYPE_BUFFER) || IS_NULL_REG(®->cpc_entry.reg)) {
1274 pr_debug("CPC register is not supported\n");
1275 return -EOPNOTSUPP;
1276 }
1277
1278 if (CPC_IN_PCC(reg))
1279 return cppc_set_reg_val_in_pcc(cpu, reg, val);
1280
1281 return cpc_write(cpu, reg, val);
1282 }
1283
1284 /**
1285 * cppc_get_desired_perf - Get the desired performance register value.
1286 * @cpunum: CPU from which to get desired performance.
1287 * @desired_perf: Return address.
1288 *
1289 * Return: 0 for success, -EIO otherwise.
1290 */
cppc_get_desired_perf(int cpunum,u64 * desired_perf)1291 int cppc_get_desired_perf(int cpunum, u64 *desired_perf)
1292 {
1293 return cppc_get_reg_val(cpunum, DESIRED_PERF, desired_perf);
1294 }
1295 EXPORT_SYMBOL_GPL(cppc_get_desired_perf);
1296
1297 /**
1298 * cppc_get_nominal_perf - Get the nominal performance register value.
1299 * @cpunum: CPU from which to get nominal performance.
1300 * @nominal_perf: Return address.
1301 *
1302 * Return: 0 for success, -EIO otherwise.
1303 */
cppc_get_nominal_perf(int cpunum,u64 * nominal_perf)1304 int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf)
1305 {
1306 return cppc_get_reg_val(cpunum, NOMINAL_PERF, nominal_perf);
1307 }
1308
1309 /**
1310 * cppc_get_highest_perf - Get the highest performance register value.
1311 * @cpunum: CPU from which to get highest performance.
1312 * @highest_perf: Return address.
1313 *
1314 * Return: 0 for success, -EIO otherwise.
1315 */
cppc_get_highest_perf(int cpunum,u64 * highest_perf)1316 int cppc_get_highest_perf(int cpunum, u64 *highest_perf)
1317 {
1318 return cppc_get_reg_val(cpunum, HIGHEST_PERF, highest_perf);
1319 }
1320 EXPORT_SYMBOL_GPL(cppc_get_highest_perf);
1321
1322 /**
1323 * cppc_get_epp_perf - Get the epp register value.
1324 * @cpunum: CPU from which to get epp preference value.
1325 * @epp_perf: Return address.
1326 *
1327 * Return: 0 for success, -EIO otherwise.
1328 */
cppc_get_epp_perf(int cpunum,u64 * epp_perf)1329 int cppc_get_epp_perf(int cpunum, u64 *epp_perf)
1330 {
1331 return cppc_get_reg_val(cpunum, ENERGY_PERF, epp_perf);
1332 }
1333 EXPORT_SYMBOL_GPL(cppc_get_epp_perf);
1334
1335 /**
1336 * cppc_get_perf_caps - Get a CPU's performance capabilities.
1337 * @cpunum: CPU from which to get capabilities info.
1338 * @perf_caps: ptr to cppc_perf_caps. See cppc_acpi.h
1339 *
1340 * Return: 0 for success with perf_caps populated else -ERRNO.
1341 */
cppc_get_perf_caps(int cpunum,struct cppc_perf_caps * perf_caps)1342 int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
1343 {
1344 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1345 struct cpc_register_resource *highest_reg, *lowest_reg,
1346 *lowest_non_linear_reg, *nominal_reg, *guaranteed_reg,
1347 *low_freq_reg = NULL, *nom_freq_reg = NULL;
1348 u64 high, low, guaranteed, nom, min_nonlinear, low_f = 0, nom_f = 0;
1349 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1350 struct cppc_pcc_data *pcc_ss_data = NULL;
1351 int ret = 0, regs_in_pcc = 0;
1352
1353 if (!cpc_desc) {
1354 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1355 return -ENODEV;
1356 }
1357
1358 highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF];
1359 lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF];
1360 lowest_non_linear_reg = &cpc_desc->cpc_regs[LOW_NON_LINEAR_PERF];
1361 nominal_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1362 low_freq_reg = &cpc_desc->cpc_regs[LOWEST_FREQ];
1363 nom_freq_reg = &cpc_desc->cpc_regs[NOMINAL_FREQ];
1364 guaranteed_reg = &cpc_desc->cpc_regs[GUARANTEED_PERF];
1365
1366 /* Are any of the regs PCC ?*/
1367 if (CPC_IN_PCC(highest_reg) || CPC_IN_PCC(lowest_reg) ||
1368 CPC_IN_PCC(lowest_non_linear_reg) || CPC_IN_PCC(nominal_reg) ||
1369 CPC_IN_PCC(low_freq_reg) || CPC_IN_PCC(nom_freq_reg)) {
1370 if (pcc_ss_id < 0) {
1371 pr_debug("Invalid pcc_ss_id\n");
1372 return -ENODEV;
1373 }
1374 pcc_ss_data = pcc_data[pcc_ss_id];
1375 regs_in_pcc = 1;
1376 down_write(&pcc_ss_data->pcc_lock);
1377 /* Ring doorbell once to update PCC subspace */
1378 if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
1379 ret = -EIO;
1380 goto out_err;
1381 }
1382 }
1383
1384 cpc_read(cpunum, highest_reg, &high);
1385 perf_caps->highest_perf = high;
1386
1387 cpc_read(cpunum, lowest_reg, &low);
1388 perf_caps->lowest_perf = low;
1389
1390 cpc_read(cpunum, nominal_reg, &nom);
1391 perf_caps->nominal_perf = nom;
1392
1393 if (guaranteed_reg->type != ACPI_TYPE_BUFFER ||
1394 IS_NULL_REG(&guaranteed_reg->cpc_entry.reg)) {
1395 perf_caps->guaranteed_perf = 0;
1396 } else {
1397 cpc_read(cpunum, guaranteed_reg, &guaranteed);
1398 perf_caps->guaranteed_perf = guaranteed;
1399 }
1400
1401 cpc_read(cpunum, lowest_non_linear_reg, &min_nonlinear);
1402 perf_caps->lowest_nonlinear_perf = min_nonlinear;
1403
1404 if (!high || !low || !nom || !min_nonlinear)
1405 ret = -EFAULT;
1406
1407 /* Read optional lowest and nominal frequencies if present */
1408 if (CPC_SUPPORTED(low_freq_reg))
1409 cpc_read(cpunum, low_freq_reg, &low_f);
1410
1411 if (CPC_SUPPORTED(nom_freq_reg))
1412 cpc_read(cpunum, nom_freq_reg, &nom_f);
1413
1414 perf_caps->lowest_freq = low_f;
1415 perf_caps->nominal_freq = nom_f;
1416
1417
1418 out_err:
1419 if (regs_in_pcc)
1420 up_write(&pcc_ss_data->pcc_lock);
1421 return ret;
1422 }
1423 EXPORT_SYMBOL_GPL(cppc_get_perf_caps);
1424
1425 /**
1426 * cppc_perf_ctrs_in_pcc - Check if any perf counters are in a PCC region.
1427 *
1428 * CPPC has flexibility about how CPU performance counters are accessed.
1429 * One of the choices is PCC regions, which can have a high access latency. This
1430 * routine allows callers of cppc_get_perf_ctrs() to know this ahead of time.
1431 *
1432 * Return: true if any of the counters are in PCC regions, false otherwise
1433 */
cppc_perf_ctrs_in_pcc(void)1434 bool cppc_perf_ctrs_in_pcc(void)
1435 {
1436 int cpu;
1437
1438 for_each_present_cpu(cpu) {
1439 struct cpc_register_resource *ref_perf_reg;
1440 struct cpc_desc *cpc_desc;
1441
1442 cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1443
1444 if (CPC_IN_PCC(&cpc_desc->cpc_regs[DELIVERED_CTR]) ||
1445 CPC_IN_PCC(&cpc_desc->cpc_regs[REFERENCE_CTR]) ||
1446 CPC_IN_PCC(&cpc_desc->cpc_regs[CTR_WRAP_TIME]))
1447 return true;
1448
1449
1450 ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF];
1451
1452 /*
1453 * If reference perf register is not supported then we should
1454 * use the nominal perf value
1455 */
1456 if (!CPC_SUPPORTED(ref_perf_reg))
1457 ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1458
1459 if (CPC_IN_PCC(ref_perf_reg))
1460 return true;
1461 }
1462
1463 return false;
1464 }
1465 EXPORT_SYMBOL_GPL(cppc_perf_ctrs_in_pcc);
1466
1467 /**
1468 * cppc_get_perf_ctrs - Read a CPU's performance feedback counters.
1469 * @cpunum: CPU from which to read counters.
1470 * @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h
1471 *
1472 * Return: 0 for success with perf_fb_ctrs populated else -ERRNO.
1473 */
cppc_get_perf_ctrs(int cpunum,struct cppc_perf_fb_ctrs * perf_fb_ctrs)1474 int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
1475 {
1476 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1477 struct cpc_register_resource *delivered_reg, *reference_reg,
1478 *ref_perf_reg, *ctr_wrap_reg;
1479 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1480 struct cppc_pcc_data *pcc_ss_data = NULL;
1481 u64 delivered, reference, ref_perf, ctr_wrap_time;
1482 int ret = 0, regs_in_pcc = 0;
1483
1484 if (!cpc_desc) {
1485 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1486 return -ENODEV;
1487 }
1488
1489 delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR];
1490 reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR];
1491 ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF];
1492 ctr_wrap_reg = &cpc_desc->cpc_regs[CTR_WRAP_TIME];
1493
1494 /*
1495 * If reference perf register is not supported then we should
1496 * use the nominal perf value
1497 */
1498 if (!CPC_SUPPORTED(ref_perf_reg))
1499 ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1500
1501 /* Are any of the regs PCC ?*/
1502 if (CPC_IN_PCC(delivered_reg) || CPC_IN_PCC(reference_reg) ||
1503 CPC_IN_PCC(ctr_wrap_reg) || CPC_IN_PCC(ref_perf_reg)) {
1504 if (pcc_ss_id < 0) {
1505 pr_debug("Invalid pcc_ss_id\n");
1506 return -ENODEV;
1507 }
1508 pcc_ss_data = pcc_data[pcc_ss_id];
1509 down_write(&pcc_ss_data->pcc_lock);
1510 regs_in_pcc = 1;
1511 /* Ring doorbell once to update PCC subspace */
1512 if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
1513 ret = -EIO;
1514 goto out_err;
1515 }
1516 }
1517
1518 cpc_read(cpunum, delivered_reg, &delivered);
1519 cpc_read(cpunum, reference_reg, &reference);
1520 cpc_read(cpunum, ref_perf_reg, &ref_perf);
1521
1522 /*
1523 * Per spec, if ctr_wrap_time optional register is unsupported, then the
1524 * performance counters are assumed to never wrap during the lifetime of
1525 * platform
1526 */
1527 ctr_wrap_time = (u64)(~((u64)0));
1528 if (CPC_SUPPORTED(ctr_wrap_reg))
1529 cpc_read(cpunum, ctr_wrap_reg, &ctr_wrap_time);
1530
1531 if (!delivered || !reference || !ref_perf) {
1532 ret = -EFAULT;
1533 goto out_err;
1534 }
1535
1536 perf_fb_ctrs->delivered = delivered;
1537 perf_fb_ctrs->reference = reference;
1538 perf_fb_ctrs->reference_perf = ref_perf;
1539 perf_fb_ctrs->wraparound_time = ctr_wrap_time;
1540 out_err:
1541 if (regs_in_pcc)
1542 up_write(&pcc_ss_data->pcc_lock);
1543 return ret;
1544 }
1545 EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
1546
1547 /*
1548 * Set Energy Performance Preference Register value through
1549 * Performance Controls Interface
1550 */
cppc_set_epp_perf(int cpu,struct cppc_perf_ctrls * perf_ctrls,bool enable)1551 int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable)
1552 {
1553 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1554 struct cpc_register_resource *epp_set_reg;
1555 struct cpc_register_resource *auto_sel_reg;
1556 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1557 struct cppc_pcc_data *pcc_ss_data = NULL;
1558 int ret;
1559
1560 if (!cpc_desc) {
1561 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1562 return -ENODEV;
1563 }
1564
1565 auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
1566 epp_set_reg = &cpc_desc->cpc_regs[ENERGY_PERF];
1567
1568 if (CPC_IN_PCC(epp_set_reg) || CPC_IN_PCC(auto_sel_reg)) {
1569 if (pcc_ss_id < 0) {
1570 pr_debug("Invalid pcc_ss_id for CPU:%d\n", cpu);
1571 return -ENODEV;
1572 }
1573
1574 if (CPC_SUPPORTED(auto_sel_reg)) {
1575 ret = cpc_write(cpu, auto_sel_reg, enable);
1576 if (ret)
1577 return ret;
1578 }
1579
1580 if (CPC_SUPPORTED(epp_set_reg)) {
1581 ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf);
1582 if (ret)
1583 return ret;
1584 }
1585
1586 pcc_ss_data = pcc_data[pcc_ss_id];
1587
1588 down_write(&pcc_ss_data->pcc_lock);
1589 /* after writing CPC, transfer the ownership of PCC to platform */
1590 ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
1591 up_write(&pcc_ss_data->pcc_lock);
1592 } else if (osc_cpc_flexible_adr_space_confirmed &&
1593 CPC_SUPPORTED(epp_set_reg) && CPC_IN_FFH(epp_set_reg)) {
1594 ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf);
1595 } else {
1596 ret = -ENOTSUPP;
1597 pr_debug("_CPC in PCC and _CPC in FFH are not supported\n");
1598 }
1599
1600 return ret;
1601 }
1602 EXPORT_SYMBOL_GPL(cppc_set_epp_perf);
1603
1604 /**
1605 * cppc_set_epp() - Write the EPP register.
1606 * @cpu: CPU on which to write register.
1607 * @epp_val: Value to write to the EPP register.
1608 */
cppc_set_epp(int cpu,u64 epp_val)1609 int cppc_set_epp(int cpu, u64 epp_val)
1610 {
1611 if (epp_val > CPPC_ENERGY_PERF_MAX)
1612 return -EINVAL;
1613
1614 return cppc_set_reg_val(cpu, ENERGY_PERF, epp_val);
1615 }
1616 EXPORT_SYMBOL_GPL(cppc_set_epp);
1617
1618 /**
1619 * cppc_get_auto_act_window() - Read autonomous activity window register.
1620 * @cpu: CPU from which to read register.
1621 * @auto_act_window: Return address.
1622 *
1623 * According to ACPI 6.5, s8.4.6.1.6, the value read from the autonomous
1624 * activity window register consists of two parts: a 7 bits value indicate
1625 * significand and a 3 bits value indicate exponent.
1626 */
cppc_get_auto_act_window(int cpu,u64 * auto_act_window)1627 int cppc_get_auto_act_window(int cpu, u64 *auto_act_window)
1628 {
1629 unsigned int exp;
1630 u64 val, sig;
1631 int ret;
1632
1633 if (auto_act_window == NULL)
1634 return -EINVAL;
1635
1636 ret = cppc_get_reg_val(cpu, AUTO_ACT_WINDOW, &val);
1637 if (ret)
1638 return ret;
1639
1640 sig = val & CPPC_AUTO_ACT_WINDOW_MAX_SIG;
1641 exp = (val >> CPPC_AUTO_ACT_WINDOW_SIG_BIT_SIZE) & CPPC_AUTO_ACT_WINDOW_MAX_EXP;
1642 *auto_act_window = sig * int_pow(10, exp);
1643
1644 return 0;
1645 }
1646 EXPORT_SYMBOL_GPL(cppc_get_auto_act_window);
1647
1648 /**
1649 * cppc_set_auto_act_window() - Write autonomous activity window register.
1650 * @cpu: CPU on which to write register.
1651 * @auto_act_window: usec value to write to the autonomous activity window register.
1652 *
1653 * According to ACPI 6.5, s8.4.6.1.6, the value to write to the autonomous
1654 * activity window register consists of two parts: a 7 bits value indicate
1655 * significand and a 3 bits value indicate exponent.
1656 */
cppc_set_auto_act_window(int cpu,u64 auto_act_window)1657 int cppc_set_auto_act_window(int cpu, u64 auto_act_window)
1658 {
1659 /* The max value to store is 1270000000 */
1660 u64 max_val = CPPC_AUTO_ACT_WINDOW_MAX_SIG * int_pow(10, CPPC_AUTO_ACT_WINDOW_MAX_EXP);
1661 int exp = 0;
1662 u64 val;
1663
1664 if (auto_act_window > max_val)
1665 return -EINVAL;
1666
1667 /*
1668 * The max significand is 127, when auto_act_window is larger than
1669 * 129, discard the precision of the last digit and increase the
1670 * exponent by 1.
1671 */
1672 while (auto_act_window > CPPC_AUTO_ACT_WINDOW_SIG_CARRY_THRESH) {
1673 auto_act_window /= 10;
1674 exp += 1;
1675 }
1676
1677 /* For 128 and 129, cut it to 127. */
1678 if (auto_act_window > CPPC_AUTO_ACT_WINDOW_MAX_SIG)
1679 auto_act_window = CPPC_AUTO_ACT_WINDOW_MAX_SIG;
1680
1681 val = (exp << CPPC_AUTO_ACT_WINDOW_SIG_BIT_SIZE) + auto_act_window;
1682
1683 return cppc_set_reg_val(cpu, AUTO_ACT_WINDOW, val);
1684 }
1685 EXPORT_SYMBOL_GPL(cppc_set_auto_act_window);
1686
1687 /**
1688 * cppc_get_auto_sel() - Read autonomous selection register.
1689 * @cpu: CPU from which to read register.
1690 * @enable: Return address.
1691 */
cppc_get_auto_sel(int cpu,bool * enable)1692 int cppc_get_auto_sel(int cpu, bool *enable)
1693 {
1694 u64 auto_sel;
1695 int ret;
1696
1697 if (enable == NULL)
1698 return -EINVAL;
1699
1700 ret = cppc_get_reg_val(cpu, AUTO_SEL_ENABLE, &auto_sel);
1701 if (ret)
1702 return ret;
1703
1704 *enable = (bool)auto_sel;
1705
1706 return 0;
1707 }
1708 EXPORT_SYMBOL_GPL(cppc_get_auto_sel);
1709
1710 /**
1711 * cppc_set_auto_sel - Write autonomous selection register.
1712 * @cpu : CPU to which to write register.
1713 * @enable : the desired value of autonomous selection resiter to be updated.
1714 */
cppc_set_auto_sel(int cpu,bool enable)1715 int cppc_set_auto_sel(int cpu, bool enable)
1716 {
1717 return cppc_set_reg_val(cpu, AUTO_SEL_ENABLE, enable);
1718 }
1719 EXPORT_SYMBOL_GPL(cppc_set_auto_sel);
1720
1721 /**
1722 * cppc_set_enable - Set to enable CPPC on the processor by writing the
1723 * Continuous Performance Control package EnableRegister field.
1724 * @cpu: CPU for which to enable CPPC register.
1725 * @enable: 0 - disable, 1 - enable CPPC feature on the processor.
1726 *
1727 * Return: 0 for success, -ERRNO or -EIO otherwise.
1728 */
cppc_set_enable(int cpu,bool enable)1729 int cppc_set_enable(int cpu, bool enable)
1730 {
1731 return cppc_set_reg_val(cpu, ENABLE, enable);
1732 }
1733 EXPORT_SYMBOL_GPL(cppc_set_enable);
1734
1735 /**
1736 * cppc_set_perf - Set a CPU's performance controls.
1737 * @cpu: CPU for which to set performance controls.
1738 * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h
1739 *
1740 * Return: 0 for success, -ERRNO otherwise.
1741 */
cppc_set_perf(int cpu,struct cppc_perf_ctrls * perf_ctrls)1742 int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
1743 {
1744 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1745 struct cpc_register_resource *desired_reg, *min_perf_reg, *max_perf_reg;
1746 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1747 struct cppc_pcc_data *pcc_ss_data = NULL;
1748 int ret = 0;
1749
1750 if (!cpc_desc) {
1751 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1752 return -ENODEV;
1753 }
1754
1755 desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
1756 min_perf_reg = &cpc_desc->cpc_regs[MIN_PERF];
1757 max_perf_reg = &cpc_desc->cpc_regs[MAX_PERF];
1758
1759 /*
1760 * This is Phase-I where we want to write to CPC registers
1761 * -> We want all CPUs to be able to execute this phase in parallel
1762 *
1763 * Since read_lock can be acquired by multiple CPUs simultaneously we
1764 * achieve that goal here
1765 */
1766 if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg)) {
1767 if (pcc_ss_id < 0) {
1768 pr_debug("Invalid pcc_ss_id\n");
1769 return -ENODEV;
1770 }
1771 pcc_ss_data = pcc_data[pcc_ss_id];
1772 down_read(&pcc_ss_data->pcc_lock); /* BEGIN Phase-I */
1773 if (pcc_ss_data->platform_owns_pcc) {
1774 ret = check_pcc_chan(pcc_ss_id, false);
1775 if (ret) {
1776 up_read(&pcc_ss_data->pcc_lock);
1777 return ret;
1778 }
1779 }
1780 /*
1781 * Update the pending_write to make sure a PCC CMD_READ will not
1782 * arrive and steal the channel during the switch to write lock
1783 */
1784 pcc_ss_data->pending_pcc_write_cmd = true;
1785 cpc_desc->write_cmd_id = pcc_ss_data->pcc_write_cnt;
1786 cpc_desc->write_cmd_status = 0;
1787 }
1788
1789 cpc_write(cpu, desired_reg, perf_ctrls->desired_perf);
1790
1791 /*
1792 * Only write if min_perf and max_perf not zero. Some drivers pass zero
1793 * value to min and max perf, but they don't mean to set the zero value,
1794 * they just don't want to write to those registers.
1795 */
1796 if (perf_ctrls->min_perf)
1797 cpc_write(cpu, min_perf_reg, perf_ctrls->min_perf);
1798 if (perf_ctrls->max_perf)
1799 cpc_write(cpu, max_perf_reg, perf_ctrls->max_perf);
1800
1801 if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg))
1802 up_read(&pcc_ss_data->pcc_lock); /* END Phase-I */
1803 /*
1804 * This is Phase-II where we transfer the ownership of PCC to Platform
1805 *
1806 * Short Summary: Basically if we think of a group of cppc_set_perf
1807 * requests that happened in short overlapping interval. The last CPU to
1808 * come out of Phase-I will enter Phase-II and ring the doorbell.
1809 *
1810 * We have the following requirements for Phase-II:
1811 * 1. We want to execute Phase-II only when there are no CPUs
1812 * currently executing in Phase-I
1813 * 2. Once we start Phase-II we want to avoid all other CPUs from
1814 * entering Phase-I.
1815 * 3. We want only one CPU among all those who went through Phase-I
1816 * to run phase-II
1817 *
1818 * If write_trylock fails to get the lock and doesn't transfer the
1819 * PCC ownership to the platform, then one of the following will be TRUE
1820 * 1. There is at-least one CPU in Phase-I which will later execute
1821 * write_trylock, so the CPUs in Phase-I will be responsible for
1822 * executing the Phase-II.
1823 * 2. Some other CPU has beaten this CPU to successfully execute the
1824 * write_trylock and has already acquired the write_lock. We know for a
1825 * fact it (other CPU acquiring the write_lock) couldn't have happened
1826 * before this CPU's Phase-I as we held the read_lock.
1827 * 3. Some other CPU executing pcc CMD_READ has stolen the
1828 * down_write, in which case, send_pcc_cmd will check for pending
1829 * CMD_WRITE commands by checking the pending_pcc_write_cmd.
1830 * So this CPU can be certain that its request will be delivered
1831 * So in all cases, this CPU knows that its request will be delivered
1832 * by another CPU and can return
1833 *
1834 * After getting the down_write we still need to check for
1835 * pending_pcc_write_cmd to take care of the following scenario
1836 * The thread running this code could be scheduled out between
1837 * Phase-I and Phase-II. Before it is scheduled back on, another CPU
1838 * could have delivered the request to Platform by triggering the
1839 * doorbell and transferred the ownership of PCC to platform. So this
1840 * avoids triggering an unnecessary doorbell and more importantly before
1841 * triggering the doorbell it makes sure that the PCC channel ownership
1842 * is still with OSPM.
1843 * pending_pcc_write_cmd can also be cleared by a different CPU, if
1844 * there was a pcc CMD_READ waiting on down_write and it steals the lock
1845 * before the pcc CMD_WRITE is completed. send_pcc_cmd checks for this
1846 * case during a CMD_READ and if there are pending writes it delivers
1847 * the write command before servicing the read command
1848 */
1849 if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg)) {
1850 if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */
1851 /* Update only if there are pending write commands */
1852 if (pcc_ss_data->pending_pcc_write_cmd)
1853 send_pcc_cmd(pcc_ss_id, CMD_WRITE);
1854 up_write(&pcc_ss_data->pcc_lock); /* END Phase-II */
1855 } else
1856 /* Wait until pcc_write_cnt is updated by send_pcc_cmd */
1857 wait_event(pcc_ss_data->pcc_write_wait_q,
1858 cpc_desc->write_cmd_id != pcc_ss_data->pcc_write_cnt);
1859
1860 /* send_pcc_cmd updates the status in case of failure */
1861 ret = cpc_desc->write_cmd_status;
1862 }
1863 return ret;
1864 }
1865 EXPORT_SYMBOL_GPL(cppc_set_perf);
1866
1867 /**
1868 * cppc_get_transition_latency - returns frequency transition latency in ns
1869 * @cpu_num: CPU number for per_cpu().
1870 *
1871 * ACPI CPPC does not explicitly specify how a platform can specify the
1872 * transition latency for performance change requests. The closest we have
1873 * is the timing information from the PCCT tables which provides the info
1874 * on the number and frequency of PCC commands the platform can handle.
1875 *
1876 * If desired_reg is in the SystemMemory or SystemIo ACPI address space,
1877 * then assume there is no latency.
1878 */
cppc_get_transition_latency(int cpu_num)1879 unsigned int cppc_get_transition_latency(int cpu_num)
1880 {
1881 /*
1882 * Expected transition latency is based on the PCCT timing values
1883 * Below are definition from ACPI spec:
1884 * pcc_nominal- Expected latency to process a command, in microseconds
1885 * pcc_mpar - The maximum number of periodic requests that the subspace
1886 * channel can support, reported in commands per minute. 0
1887 * indicates no limitation.
1888 * pcc_mrtt - The minimum amount of time that OSPM must wait after the
1889 * completion of a command before issuing the next command,
1890 * in microseconds.
1891 */
1892 unsigned int latency_ns = 0;
1893 struct cpc_desc *cpc_desc;
1894 struct cpc_register_resource *desired_reg;
1895 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu_num);
1896 struct cppc_pcc_data *pcc_ss_data;
1897
1898 cpc_desc = per_cpu(cpc_desc_ptr, cpu_num);
1899 if (!cpc_desc)
1900 return CPUFREQ_ETERNAL;
1901
1902 desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
1903 if (CPC_IN_SYSTEM_MEMORY(desired_reg) || CPC_IN_SYSTEM_IO(desired_reg))
1904 return 0;
1905 else if (!CPC_IN_PCC(desired_reg))
1906 return CPUFREQ_ETERNAL;
1907
1908 if (pcc_ss_id < 0)
1909 return CPUFREQ_ETERNAL;
1910
1911 pcc_ss_data = pcc_data[pcc_ss_id];
1912 if (pcc_ss_data->pcc_mpar)
1913 latency_ns = 60 * (1000 * 1000 * 1000 / pcc_ss_data->pcc_mpar);
1914
1915 latency_ns = max(latency_ns, pcc_ss_data->pcc_nominal * 1000);
1916 latency_ns = max(latency_ns, pcc_ss_data->pcc_mrtt * 1000);
1917
1918 return latency_ns;
1919 }
1920 EXPORT_SYMBOL_GPL(cppc_get_transition_latency);
1921
1922 /* Minimum struct length needed for the DMI processor entry we want */
1923 #define DMI_ENTRY_PROCESSOR_MIN_LENGTH 48
1924
1925 /* Offset in the DMI processor structure for the max frequency */
1926 #define DMI_PROCESSOR_MAX_SPEED 0x14
1927
1928 /* Callback function used to retrieve the max frequency from DMI */
cppc_find_dmi_mhz(const struct dmi_header * dm,void * private)1929 static void cppc_find_dmi_mhz(const struct dmi_header *dm, void *private)
1930 {
1931 const u8 *dmi_data = (const u8 *)dm;
1932 u16 *mhz = (u16 *)private;
1933
1934 if (dm->type == DMI_ENTRY_PROCESSOR &&
1935 dm->length >= DMI_ENTRY_PROCESSOR_MIN_LENGTH) {
1936 u16 val = (u16)get_unaligned((const u16 *)
1937 (dmi_data + DMI_PROCESSOR_MAX_SPEED));
1938 *mhz = umax(val, *mhz);
1939 }
1940 }
1941
1942 /* Look up the max frequency in DMI */
cppc_get_dmi_max_khz(void)1943 static u64 cppc_get_dmi_max_khz(void)
1944 {
1945 u16 mhz = 0;
1946
1947 dmi_walk(cppc_find_dmi_mhz, &mhz);
1948
1949 /*
1950 * Real stupid fallback value, just in case there is no
1951 * actual value set.
1952 */
1953 mhz = mhz ? mhz : 1;
1954
1955 return KHZ_PER_MHZ * mhz;
1956 }
1957
1958 /*
1959 * If CPPC lowest_freq and nominal_freq registers are exposed then we can
1960 * use them to convert perf to freq and vice versa. The conversion is
1961 * extrapolated as an affine function passing by the 2 points:
1962 * - (Low perf, Low freq)
1963 * - (Nominal perf, Nominal freq)
1964 */
cppc_perf_to_khz(struct cppc_perf_caps * caps,unsigned int perf)1965 unsigned int cppc_perf_to_khz(struct cppc_perf_caps *caps, unsigned int perf)
1966 {
1967 s64 retval, offset = 0;
1968 static u64 max_khz;
1969 u64 mul, div;
1970
1971 if (caps->lowest_freq && caps->nominal_freq) {
1972 /* Avoid special case when nominal_freq is equal to lowest_freq */
1973 if (caps->lowest_freq == caps->nominal_freq) {
1974 mul = caps->nominal_freq;
1975 div = caps->nominal_perf;
1976 } else {
1977 mul = caps->nominal_freq - caps->lowest_freq;
1978 div = caps->nominal_perf - caps->lowest_perf;
1979 }
1980 mul *= KHZ_PER_MHZ;
1981 offset = caps->nominal_freq * KHZ_PER_MHZ -
1982 div64_u64(caps->nominal_perf * mul, div);
1983 } else {
1984 if (!max_khz)
1985 max_khz = cppc_get_dmi_max_khz();
1986 mul = max_khz;
1987 div = caps->highest_perf;
1988 }
1989
1990 retval = offset + div64_u64(perf * mul, div);
1991 if (retval >= 0)
1992 return retval;
1993 return 0;
1994 }
1995 EXPORT_SYMBOL_GPL(cppc_perf_to_khz);
1996
cppc_khz_to_perf(struct cppc_perf_caps * caps,unsigned int freq)1997 unsigned int cppc_khz_to_perf(struct cppc_perf_caps *caps, unsigned int freq)
1998 {
1999 s64 retval, offset = 0;
2000 static u64 max_khz;
2001 u64 mul, div;
2002
2003 if (caps->lowest_freq && caps->nominal_freq) {
2004 /* Avoid special case when nominal_freq is equal to lowest_freq */
2005 if (caps->lowest_freq == caps->nominal_freq) {
2006 mul = caps->nominal_perf;
2007 div = caps->nominal_freq;
2008 } else {
2009 mul = caps->nominal_perf - caps->lowest_perf;
2010 div = caps->nominal_freq - caps->lowest_freq;
2011 }
2012 /*
2013 * We don't need to convert to kHz for computing offset and can
2014 * directly use nominal_freq and lowest_freq as the div64_u64
2015 * will remove the frequency unit.
2016 */
2017 offset = caps->nominal_perf -
2018 div64_u64(caps->nominal_freq * mul, div);
2019 /* But we need it for computing the perf level. */
2020 div *= KHZ_PER_MHZ;
2021 } else {
2022 if (!max_khz)
2023 max_khz = cppc_get_dmi_max_khz();
2024 mul = caps->highest_perf;
2025 div = max_khz;
2026 }
2027
2028 retval = offset + div64_u64(freq * mul, div);
2029 if (retval >= 0)
2030 return retval;
2031 return 0;
2032 }
2033 EXPORT_SYMBOL_GPL(cppc_khz_to_perf);
2034