1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Motorola CPCAP PMIC regulator driver 4 * 5 * Based on cpcap-regulator.c from Motorola Linux kernel tree 6 * Copyright (C) 2009-2011 Motorola, Inc. 7 * 8 * Rewritten for mainline kernel to use device tree and regmap 9 * Copyright (C) 2017 Tony Lindgren <tony@atomide.com> 10 */ 11 12 #include <linux/err.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/platform_device.h> 16 #include <linux/regmap.h> 17 #include <linux/regulator/driver.h> 18 #include <linux/regulator/machine.h> 19 #include <linux/regulator/of_regulator.h> 20 #include <linux/mfd/motorola-cpcap.h> 21 22 /* 23 * Resource assignment register bits. These seem to control the state 24 * idle modes adn are used at least for omap4. 25 */ 26 27 /* CPCAP_REG_ASSIGN2 bits - Resource Assignment 2 */ 28 #define CPCAP_BIT_VSDIO_SEL BIT(15) 29 #define CPCAP_BIT_VDIG_SEL BIT(14) 30 #define CPCAP_BIT_VCAM_SEL BIT(13) 31 #define CPCAP_BIT_SW6_SEL BIT(12) 32 #define CPCAP_BIT_SW5_SEL BIT(11) 33 #define CPCAP_BIT_SW4_SEL BIT(10) 34 #define CPCAP_BIT_SW3_SEL BIT(9) 35 #define CPCAP_BIT_SW2_SEL BIT(8) 36 #define CPCAP_BIT_SW1_SEL BIT(7) 37 38 /* CPCAP_REG_ASSIGN3 bits - Resource Assignment 3 */ 39 #define CPCAP_BIT_VUSBINT2_SEL BIT(15) 40 #define CPCAP_BIT_VUSBINT1_SEL BIT(14) 41 #define CPCAP_BIT_VVIB_SEL BIT(13) 42 #define CPCAP_BIT_VWLAN1_SEL BIT(12) 43 #define CPCAP_BIT_VRF1_SEL BIT(11) 44 #define CPCAP_BIT_VHVIO_SEL BIT(10) 45 #define CPCAP_BIT_VDAC_SEL BIT(9) 46 #define CPCAP_BIT_VUSB_SEL BIT(8) 47 #define CPCAP_BIT_VSIM_SEL BIT(7) 48 #define CPCAP_BIT_VRFREF_SEL BIT(6) 49 #define CPCAP_BIT_VPLL_SEL BIT(5) 50 #define CPCAP_BIT_VFUSE_SEL BIT(4) 51 #define CPCAP_BIT_VCSI_SEL BIT(3) 52 #define CPCAP_BIT_SPARE_14_2 BIT(2) 53 #define CPCAP_BIT_VWLAN2_SEL BIT(1) 54 #define CPCAP_BIT_VRF2_SEL BIT(0) 55 56 /* CPCAP_REG_ASSIGN4 bits - Resource Assignment 4 */ 57 #define CPCAP_BIT_VAUDIO_SEL BIT(0) 58 59 /* 60 * Enable register bits. At least CPCAP_BIT_AUDIO_LOW_PWR is generic, 61 * and not limited to audio regulator. Let's use the Motorola kernel 62 * naming for now until we have a better understanding of the other 63 * enable register bits. No idea why BIT(3) is not defined. 64 */ 65 #define CPCAP_BIT_AUDIO_LOW_PWR BIT(6) 66 #define CPCAP_BIT_AUD_LOWPWR_SPEED BIT(5) 67 #define CPCAP_BIT_VAUDIOPRISTBY BIT(4) 68 #define CPCAP_BIT_VAUDIO_MODE1 BIT(2) 69 #define CPCAP_BIT_VAUDIO_MODE0 BIT(1) 70 #define CPCAP_BIT_V_AUDIO_EN BIT(0) 71 72 #define CPCAP_BIT_AUDIO_NORMAL_MODE 0x00 73 74 /* 75 * Off mode configuration bit. Used currently only by SW5 on omap4. There's 76 * the following comment in Motorola Linux kernel tree for it: 77 * 78 * When set in the regulator mode, the regulator assignment will be changed 79 * to secondary when the regulator is disabled. The mode will be set back to 80 * primary when the regulator is turned on. 81 */ 82 #define CPCAP_REG_OFF_MODE_SEC BIT(15) 83 84 /* 85 * SoC specific configuration for CPCAP regulator. There are at least three 86 * different SoCs each with their own parameters: omap3, omap4 and tegra2. 87 * 88 * The assign_reg and assign_mask seem to allow toggling between primary 89 * and secondary mode that at least omap4 uses for off mode. 90 */ 91 struct cpcap_regulator { 92 struct regulator_desc rdesc; 93 const u16 assign_reg; 94 const u16 assign_mask; 95 }; 96 97 #define CPCAP_REG(_ID, reg, assignment_reg, assignment_mask, val_tbl, \ 98 mode_mask, volt_mask, mode_val, off_val, \ 99 volt_trans_time) { \ 100 .rdesc = { \ 101 .name = #_ID, \ 102 .of_match = of_match_ptr(#_ID), \ 103 .ops = &cpcap_regulator_ops, \ 104 .regulators_node = of_match_ptr("regulators"), \ 105 .type = REGULATOR_VOLTAGE, \ 106 .id = CPCAP_##_ID, \ 107 .owner = THIS_MODULE, \ 108 .n_voltages = ARRAY_SIZE(val_tbl), \ 109 .volt_table = (val_tbl), \ 110 .vsel_reg = (reg), \ 111 .vsel_mask = (volt_mask), \ 112 .enable_reg = (reg), \ 113 .enable_mask = (mode_mask), \ 114 .enable_val = (mode_val), \ 115 .disable_val = (off_val), \ 116 .ramp_delay = (volt_trans_time), \ 117 .of_map_mode = cpcap_map_mode, \ 118 }, \ 119 .assign_reg = (assignment_reg), \ 120 .assign_mask = (assignment_mask), \ 121 } 122 123 struct cpcap_ddata { 124 struct regmap *reg; 125 struct device *dev; 126 const struct cpcap_regulator *soc; 127 }; 128 129 enum cpcap_regulator_id { 130 CPCAP_SW1, 131 CPCAP_SW2, 132 CPCAP_SW3, 133 CPCAP_SW4, 134 CPCAP_SW5, 135 CPCAP_SW6, 136 CPCAP_VCAM, 137 CPCAP_VCSI, 138 CPCAP_VDAC, 139 CPCAP_VDIG, 140 CPCAP_VFUSE, 141 CPCAP_VHVIO, 142 CPCAP_VSDIO, 143 CPCAP_VPLL, 144 CPCAP_VRF1, 145 CPCAP_VRF2, 146 CPCAP_VRFREF, 147 CPCAP_VWLAN1, 148 CPCAP_VWLAN2, 149 CPCAP_VSIM, 150 CPCAP_VSIMCARD, 151 CPCAP_VVIB, 152 CPCAP_VUSB, 153 CPCAP_VAUDIO, 154 CPCAP_NR_REGULATORS, 155 }; 156 157 /* 158 * We need to also configure regulator idle mode for SoC off mode if 159 * CPCAP_REG_OFF_MODE_SEC is set. 160 */ 161 static int cpcap_regulator_enable(struct regulator_dev *rdev) 162 { 163 struct cpcap_regulator *regulator = rdev_get_drvdata(rdev); 164 int error; 165 166 error = regulator_enable_regmap(rdev); 167 if (error) 168 return error; 169 170 if (rdev->desc->enable_val & CPCAP_REG_OFF_MODE_SEC) { 171 error = regmap_update_bits(rdev->regmap, regulator->assign_reg, 172 regulator->assign_mask, 173 regulator->assign_mask); 174 if (error) 175 regulator_disable_regmap(rdev); 176 } 177 178 return error; 179 } 180 181 /* 182 * We need to also configure regulator idle mode for SoC off mode if 183 * CPCAP_REG_OFF_MODE_SEC is set. 184 */ 185 static int cpcap_regulator_disable(struct regulator_dev *rdev) 186 { 187 struct cpcap_regulator *regulator = rdev_get_drvdata(rdev); 188 int error; 189 190 if (rdev->desc->enable_val & CPCAP_REG_OFF_MODE_SEC) { 191 error = regmap_update_bits(rdev->regmap, regulator->assign_reg, 192 regulator->assign_mask, 0); 193 if (error) 194 return error; 195 } 196 197 error = regulator_disable_regmap(rdev); 198 if (error && (rdev->desc->enable_val & CPCAP_REG_OFF_MODE_SEC)) { 199 regmap_update_bits(rdev->regmap, regulator->assign_reg, 200 regulator->assign_mask, 201 regulator->assign_mask); 202 } 203 204 return error; 205 } 206 207 static unsigned int cpcap_map_mode(unsigned int mode) 208 { 209 switch (mode) { 210 case CPCAP_BIT_AUDIO_NORMAL_MODE: 211 return REGULATOR_MODE_NORMAL; 212 case CPCAP_BIT_AUDIO_LOW_PWR: 213 return REGULATOR_MODE_STANDBY; 214 default: 215 return REGULATOR_MODE_INVALID; 216 } 217 } 218 219 static unsigned int cpcap_regulator_get_mode(struct regulator_dev *rdev) 220 { 221 int value; 222 223 regmap_read(rdev->regmap, rdev->desc->enable_reg, &value); 224 225 if (value & CPCAP_BIT_AUDIO_LOW_PWR) 226 return REGULATOR_MODE_STANDBY; 227 228 return REGULATOR_MODE_NORMAL; 229 } 230 231 static int cpcap_regulator_set_mode(struct regulator_dev *rdev, 232 unsigned int mode) 233 { 234 int value; 235 236 switch (mode) { 237 case REGULATOR_MODE_NORMAL: 238 value = CPCAP_BIT_AUDIO_NORMAL_MODE; 239 break; 240 case REGULATOR_MODE_STANDBY: 241 value = CPCAP_BIT_AUDIO_LOW_PWR; 242 break; 243 default: 244 return -EINVAL; 245 } 246 247 return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, 248 CPCAP_BIT_AUDIO_LOW_PWR, value); 249 } 250 251 static const struct regulator_ops cpcap_regulator_ops = { 252 .enable = cpcap_regulator_enable, 253 .disable = cpcap_regulator_disable, 254 .is_enabled = regulator_is_enabled_regmap, 255 .list_voltage = regulator_list_voltage_table, 256 .map_voltage = regulator_map_voltage_iterate, 257 .get_voltage_sel = regulator_get_voltage_sel_regmap, 258 .set_voltage_sel = regulator_set_voltage_sel_regmap, 259 .get_mode = cpcap_regulator_get_mode, 260 .set_mode = cpcap_regulator_set_mode, 261 }; 262 263 static const unsigned int unknown_val_tbl[] = { 0, }; 264 static const unsigned int sw_mot_val_tbl[] = { 600000, 612500, 625000, 265 637500, 650000, 662500, 266 675000, 687500, 700000, 267 712500, 725000, 737500, 268 750000, 762500, 775000, 269 787500, 800000, 812500, 270 825000, 837500, 850000, 271 862500, 875000, 887500, 272 900000, 912500, 925000, 273 937500, 950000, 962500, 274 975000, 987500, 1000000, 275 1012500, 1025000, 1037500, 276 1050000, 1062500, 1075000, 277 1087500, 1100000, 1112500, 278 1125000, 1137500, 1150000, 279 1162500, 1175000, 1187500, 280 1200000, 1212500, 1225000, 281 1237500, 1250000, 1262500, 282 1275000, 1287500, 1300000, 283 1312500, 1325000, 1337500, 284 1350000, 1362500, 1375000, 285 1387500, 1400000, 1412500, 286 1425000, 1437500, 1450000, 287 1462500, 1475000, }; 288 static const unsigned int sw2_sw4_val_tbl[] = { 612500, 625000, 637500, 289 650000, 662500, 675000, 290 687500, 700000, 712500, 291 725000, 737500, 750000, 292 762500, 775000, 787500, 293 800000, 812500, 825000, 294 837500, 850000, 862500, 295 875000, 887500, 900000, 296 912500, 925000, 937500, 297 950000, 962500, 975000, 298 987500, 1000000, 1012500, 299 1025000, 1037500, 1050000, 300 1062500, 1075000, 1087500, 301 1100000, 1112500, 1125000, 302 1137500, 1150000, 1162500, 303 1175000, 1187500, 1200000, 304 1212500, 1225000, 1237500, 305 1250000, 1262500, 1275000, 306 1287500, 1300000, 1312500, 307 1325000, 1337500, 1350000, 308 1362500, 1375000, 1387500, 309 1400000, 1412500, 1425000, 310 1437500, 1450000, 1462500, }; 311 static const unsigned int sw3_val_tbl[] = { 1350000, 1800000, 1850000, 1875000, }; 312 static const unsigned int sw5_val_tbl[] = { 0, 5050000, }; 313 static const unsigned int vcam_val_tbl[] = { 2600000, 2700000, 2800000, 314 2900000, }; 315 static const unsigned int vcsi_val_tbl[] = { 1200000, 1800000, }; 316 static const unsigned int vdac_val_tbl[] = { 1200000, 1500000, 1800000, 317 2500000,}; 318 static const unsigned int vdig_val_tbl[] = { 1200000, 1350000, 1500000, 319 1875000, }; 320 static const unsigned int vfuse_val_tbl[] = { 1500000, 1600000, 1700000, 321 1800000, 1900000, 2000000, 322 2100000, 2200000, 2300000, 323 2400000, 2500000, 2600000, 324 2700000, 3150000, }; 325 static const unsigned int vhvio_val_tbl[] = { 2775000, }; 326 static const unsigned int vsdio_val_tbl[] = { 1500000, 1600000, 1800000, 327 2600000, 2700000, 2800000, 328 2900000, 3000000, }; 329 static const unsigned int vpll_val_tbl[] = { 1200000, 1300000, 1400000, 330 1800000, }; 331 /* Quirk: 2775000 is before 2500000 for vrf1 regulator */ 332 static const unsigned int vrf1_val_tbl[] = { 2775000, 2500000, }; 333 static const unsigned int vrf2_val_tbl[] = { 0, 2775000, }; 334 static const unsigned int vrfref_val_tbl[] = { 2500000, 2775000, }; 335 static const unsigned int vwlan1_val_tbl[] = { 1800000, 1900000, }; 336 static const unsigned int vwlan2_val_tbl[] = { 2775000, 3000000, 3300000, 337 3300000, }; 338 static const unsigned int vsim_val_tbl[] = { 1800000, 2900000, }; 339 static const unsigned int vsimcard_val_tbl[] = { 1800000, 2900000, }; 340 static const unsigned int vvib_val_tbl[] = { 1300000, 1800000, 2000000, 341 3000000, }; 342 static const unsigned int vusb_val_tbl[] = { 0, 3300000, }; 343 static const unsigned int vaudio_val_tbl[] = { 0, 2775000, }; 344 345 /* 346 * SoC specific configuration for omap4. The data below is comes from Motorola 347 * Linux kernel tree. It's basically the values of cpcap_regltr_data, 348 * cpcap_regulator_mode_values and cpcap_regulator_off_mode_values, see 349 * CPCAP_REG macro above. 350 * 351 * SW1 to SW4 and SW6 seems to be unused for mapphone. Note that VSIM and 352 * VSIMCARD have a shared resource assignment bit. 353 */ 354 static const struct cpcap_regulator omap4_regulators[] = { 355 CPCAP_REG(SW1, CPCAP_REG_S1C1, CPCAP_REG_ASSIGN2, 356 CPCAP_BIT_SW1_SEL, unknown_val_tbl, 357 0, 0, 0, 0, 0), 358 CPCAP_REG(SW2, CPCAP_REG_S2C1, CPCAP_REG_ASSIGN2, 359 CPCAP_BIT_SW2_SEL, unknown_val_tbl, 360 0, 0, 0, 0, 0), 361 CPCAP_REG(SW3, CPCAP_REG_S3C, CPCAP_REG_ASSIGN2, 362 CPCAP_BIT_SW3_SEL, unknown_val_tbl, 363 0, 0, 0, 0, 0), 364 CPCAP_REG(SW4, CPCAP_REG_S4C1, CPCAP_REG_ASSIGN2, 365 CPCAP_BIT_SW4_SEL, unknown_val_tbl, 366 0, 0, 0, 0, 0), 367 CPCAP_REG(SW5, CPCAP_REG_S5C, CPCAP_REG_ASSIGN2, 368 CPCAP_BIT_SW5_SEL, sw5_val_tbl, 369 0x28, 0, 0x20 | CPCAP_REG_OFF_MODE_SEC, 0, 0), 370 CPCAP_REG(SW6, CPCAP_REG_S6C, CPCAP_REG_ASSIGN2, 371 CPCAP_BIT_SW6_SEL, unknown_val_tbl, 372 0, 0, 0, 0, 0), 373 CPCAP_REG(VCAM, CPCAP_REG_VCAMC, CPCAP_REG_ASSIGN2, 374 CPCAP_BIT_VCAM_SEL, vcam_val_tbl, 375 0x87, 0x30, 0x3, 0, 420), 376 CPCAP_REG(VCSI, CPCAP_REG_VCSIC, CPCAP_REG_ASSIGN3, 377 CPCAP_BIT_VCSI_SEL, vcsi_val_tbl, 378 0x47, 0x10, 0x43, 0x41, 350), 379 CPCAP_REG(VDAC, CPCAP_REG_VDACC, CPCAP_REG_ASSIGN3, 380 CPCAP_BIT_VDAC_SEL, vdac_val_tbl, 381 0x87, 0x30, 0x3, 0, 420), 382 CPCAP_REG(VDIG, CPCAP_REG_VDIGC, CPCAP_REG_ASSIGN2, 383 CPCAP_BIT_VDIG_SEL, vdig_val_tbl, 384 0x87, 0x30, 0x82, 0, 420), 385 CPCAP_REG(VFUSE, CPCAP_REG_VFUSEC, CPCAP_REG_ASSIGN3, 386 CPCAP_BIT_VFUSE_SEL, vfuse_val_tbl, 387 0x80, 0xf, 0x80, 0, 420), 388 CPCAP_REG(VHVIO, CPCAP_REG_VHVIOC, CPCAP_REG_ASSIGN3, 389 CPCAP_BIT_VHVIO_SEL, vhvio_val_tbl, 390 0x17, 0, 0, 0x12, 0), 391 CPCAP_REG(VSDIO, CPCAP_REG_VSDIOC, CPCAP_REG_ASSIGN2, 392 CPCAP_BIT_VSDIO_SEL, vsdio_val_tbl, 393 0x87, 0x38, 0x82, 0, 420), 394 CPCAP_REG(VPLL, CPCAP_REG_VPLLC, CPCAP_REG_ASSIGN3, 395 CPCAP_BIT_VPLL_SEL, vpll_val_tbl, 396 0x43, 0x18, 0x2, 0, 420), 397 CPCAP_REG(VRF1, CPCAP_REG_VRF1C, CPCAP_REG_ASSIGN3, 398 CPCAP_BIT_VRF1_SEL, vrf1_val_tbl, 399 0xac, 0x2, 0x4, 0, 10), 400 CPCAP_REG(VRF2, CPCAP_REG_VRF2C, CPCAP_REG_ASSIGN3, 401 CPCAP_BIT_VRF2_SEL, vrf2_val_tbl, 402 0x23, 0x8, 0, 0, 10), 403 CPCAP_REG(VRFREF, CPCAP_REG_VRFREFC, CPCAP_REG_ASSIGN3, 404 CPCAP_BIT_VRFREF_SEL, vrfref_val_tbl, 405 0x23, 0x8, 0, 0, 420), 406 CPCAP_REG(VWLAN1, CPCAP_REG_VWLAN1C, CPCAP_REG_ASSIGN3, 407 CPCAP_BIT_VWLAN1_SEL, vwlan1_val_tbl, 408 0x47, 0x10, 0, 0, 420), 409 CPCAP_REG(VWLAN2, CPCAP_REG_VWLAN2C, CPCAP_REG_ASSIGN3, 410 CPCAP_BIT_VWLAN2_SEL, vwlan2_val_tbl, 411 0x20c, 0xc0, 0x20c, 0, 420), 412 CPCAP_REG(VSIM, CPCAP_REG_VSIMC, CPCAP_REG_ASSIGN3, 413 0xffff, vsim_val_tbl, 414 0x23, 0x8, 0x3, 0, 420), 415 CPCAP_REG(VSIMCARD, CPCAP_REG_VSIMC, CPCAP_REG_ASSIGN3, 416 0xffff, vsimcard_val_tbl, 417 0x1e80, 0x8, 0x1e00, 0, 420), 418 CPCAP_REG(VVIB, CPCAP_REG_VVIBC, CPCAP_REG_ASSIGN3, 419 CPCAP_BIT_VVIB_SEL, vvib_val_tbl, 420 0x1, 0xc, 0x1, 0, 500), 421 CPCAP_REG(VUSB, CPCAP_REG_VUSBC, CPCAP_REG_ASSIGN3, 422 CPCAP_BIT_VUSB_SEL, vusb_val_tbl, 423 0x11c, 0x40, 0xc, 0, 0), 424 CPCAP_REG(VAUDIO, CPCAP_REG_VAUDIOC, CPCAP_REG_ASSIGN4, 425 CPCAP_BIT_VAUDIO_SEL, vaudio_val_tbl, 426 0x16, 0x1, 0x4, 0, 0), 427 { /* sentinel */ }, 428 }; 429 430 static const struct cpcap_regulator mot_regulators[] = { 431 CPCAP_REG(SW1, CPCAP_REG_S1C1, CPCAP_REG_ASSIGN2, 432 CPCAP_BIT_SW1_SEL, sw_mot_val_tbl, 433 0x6f00, 0x7f, 0x6800, 0, 0), 434 CPCAP_REG(SW2, CPCAP_REG_S2C1, CPCAP_REG_ASSIGN2, 435 CPCAP_BIT_SW2_SEL, sw_mot_val_tbl, 436 0x6f00, 0x7f, 0x4804, 0, 0), 437 CPCAP_REG(SW3, CPCAP_REG_S3C, CPCAP_REG_ASSIGN2, 438 CPCAP_BIT_SW3_SEL, sw3_val_tbl, 439 0x578, 0x3, 0x043c, 0, 0), 440 CPCAP_REG(SW4, CPCAP_REG_S4C1, CPCAP_REG_ASSIGN2, 441 CPCAP_BIT_SW4_SEL, sw_mot_val_tbl, 442 0x6f00, 0x7f, 0x4909, 0, 0), 443 CPCAP_REG(SW5, CPCAP_REG_S5C, CPCAP_REG_ASSIGN2, 444 CPCAP_BIT_SW5_SEL, sw5_val_tbl, 445 0x28, 0, 0x20, 0, 0), 446 CPCAP_REG(SW6, CPCAP_REG_S6C, CPCAP_REG_ASSIGN2, 447 CPCAP_BIT_SW6_SEL, unknown_val_tbl, 448 0, 0, 0, 0, 0), 449 CPCAP_REG(VCAM, CPCAP_REG_VCAMC, CPCAP_REG_ASSIGN2, 450 CPCAP_BIT_VCAM_SEL, vcam_val_tbl, 451 0x87, 0x30, 0x7, 0, 420), 452 CPCAP_REG(VCSI, CPCAP_REG_VCSIC, CPCAP_REG_ASSIGN3, 453 CPCAP_BIT_VCSI_SEL, vcsi_val_tbl, 454 0x47, 0x10, 0x7, 0, 350), 455 CPCAP_REG(VDAC, CPCAP_REG_VDACC, CPCAP_REG_ASSIGN3, 456 CPCAP_BIT_VDAC_SEL, vdac_val_tbl, 457 0x87, 0x30, 0x0, 0, 420), 458 CPCAP_REG(VDIG, CPCAP_REG_VDIGC, CPCAP_REG_ASSIGN2, 459 CPCAP_BIT_VDIG_SEL, vdig_val_tbl, 460 0x87, 0x30, 0x0, 0, 420), 461 CPCAP_REG(VFUSE, CPCAP_REG_VFUSEC, CPCAP_REG_ASSIGN3, 462 CPCAP_BIT_VFUSE_SEL, vfuse_val_tbl, 463 0xa0, 0xf, 0x0, 0, 420), 464 CPCAP_REG(VHVIO, CPCAP_REG_VHVIOC, CPCAP_REG_ASSIGN3, 465 CPCAP_BIT_VHVIO_SEL, vhvio_val_tbl, 466 0x17, 0, 0x2, 0, 0), 467 CPCAP_REG(VSDIO, CPCAP_REG_VSDIOC, CPCAP_REG_ASSIGN2, 468 CPCAP_BIT_VSDIO_SEL, vsdio_val_tbl, 469 0x87, 0x38, 0x2, 0, 420), 470 CPCAP_REG(VPLL, CPCAP_REG_VPLLC, CPCAP_REG_ASSIGN3, 471 CPCAP_BIT_VPLL_SEL, vpll_val_tbl, 472 0x47, 0x18, 0x1, 0, 420), 473 CPCAP_REG(VRF1, CPCAP_REG_VRF1C, CPCAP_REG_ASSIGN3, 474 CPCAP_BIT_VRF1_SEL, vrf1_val_tbl, 475 0xac, 0x2, 0, 0, 10), 476 CPCAP_REG(VRF2, CPCAP_REG_VRF2C, CPCAP_REG_ASSIGN3, 477 CPCAP_BIT_VRF2_SEL, vrf2_val_tbl, 478 0x23, 0x8, 0, 0, 10), 479 CPCAP_REG(VRFREF, CPCAP_REG_VRFREFC, CPCAP_REG_ASSIGN3, 480 CPCAP_BIT_VRFREF_SEL, vrfref_val_tbl, 481 0x23, 0x8, 0, 0, 420), 482 CPCAP_REG(VWLAN1, CPCAP_REG_VWLAN1C, CPCAP_REG_ASSIGN3, 483 CPCAP_BIT_VWLAN1_SEL, vwlan1_val_tbl, 484 0x47, 0x10, 0x5, 0, 420), 485 CPCAP_REG(VWLAN2, CPCAP_REG_VWLAN2C, CPCAP_REG_ASSIGN3, 486 CPCAP_BIT_VWLAN2_SEL, vwlan2_val_tbl, 487 0x20c, 0xc0, 0xd, 0, 420), 488 CPCAP_REG(VSIM, CPCAP_REG_VSIMC, CPCAP_REG_ASSIGN3, 489 0xffff, vsim_val_tbl, 490 0x23, 0x8, 0, 0, 420), 491 CPCAP_REG(VSIMCARD, CPCAP_REG_VSIMC, CPCAP_REG_ASSIGN3, 492 0xffff, vsimcard_val_tbl, 493 0x1e80, 0x8, 0x1e00, 0, 420), 494 CPCAP_REG(VVIB, CPCAP_REG_VVIBC, CPCAP_REG_ASSIGN3, 495 CPCAP_BIT_VVIB_SEL, vvib_val_tbl, 496 0x1, 0xc, 0x1, 0, 500), 497 CPCAP_REG(VUSB, CPCAP_REG_VUSBC, CPCAP_REG_ASSIGN3, 498 CPCAP_BIT_VUSB_SEL, vusb_val_tbl, 499 0x11c, 0x40, 0xc, 0, 0), 500 CPCAP_REG(VAUDIO, CPCAP_REG_VAUDIOC, CPCAP_REG_ASSIGN4, 501 CPCAP_BIT_VAUDIO_SEL, vaudio_val_tbl, 502 0x16, 0x1, 0x5, 0, 0), 503 { /* sentinel */ } 504 }; 505 506 static const struct cpcap_regulator xoom_regulators[] = { 507 CPCAP_REG(SW1, CPCAP_REG_S1C1, CPCAP_REG_ASSIGN2, 508 CPCAP_BIT_SW1_SEL, unknown_val_tbl, 509 0, 0, 0, 0, 0), 510 CPCAP_REG(SW2, CPCAP_REG_S2C1, CPCAP_REG_ASSIGN2, 511 CPCAP_BIT_SW2_SEL, sw2_sw4_val_tbl, 512 0xf00, 0x7f, 0x800, 0, 120), 513 CPCAP_REG(SW3, CPCAP_REG_S3C, CPCAP_REG_ASSIGN2, 514 CPCAP_BIT_SW3_SEL, unknown_val_tbl, 515 0, 0, 0, 0, 0), 516 CPCAP_REG(SW4, CPCAP_REG_S4C1, CPCAP_REG_ASSIGN2, 517 CPCAP_BIT_SW4_SEL, sw2_sw4_val_tbl, 518 0xf00, 0x7f, 0x900, 0, 100), 519 CPCAP_REG(SW5, CPCAP_REG_S5C, CPCAP_REG_ASSIGN2, 520 CPCAP_BIT_SW5_SEL, sw5_val_tbl, 521 0x2a, 0, 0x22, 0, 0), 522 CPCAP_REG(SW6, CPCAP_REG_S6C, CPCAP_REG_ASSIGN2, 523 CPCAP_BIT_SW6_SEL, unknown_val_tbl, 524 0, 0, 0, 0, 0), 525 CPCAP_REG(VCAM, CPCAP_REG_VCAMC, CPCAP_REG_ASSIGN2, 526 CPCAP_BIT_VCAM_SEL, vcam_val_tbl, 527 0x87, 0x30, 0x7, 0, 420), 528 CPCAP_REG(VCSI, CPCAP_REG_VCSIC, CPCAP_REG_ASSIGN3, 529 CPCAP_BIT_VCSI_SEL, vcsi_val_tbl, 530 0x47, 0x10, 0x7, 0, 350), 531 CPCAP_REG(VDAC, CPCAP_REG_VDACC, CPCAP_REG_ASSIGN3, 532 CPCAP_BIT_VDAC_SEL, vdac_val_tbl, 533 0x87, 0x30, 0x3, 0, 420), 534 CPCAP_REG(VDIG, CPCAP_REG_VDIGC, CPCAP_REG_ASSIGN2, 535 CPCAP_BIT_VDIG_SEL, vdig_val_tbl, 536 0x87, 0x30, 0x5, 0, 420), 537 CPCAP_REG(VFUSE, CPCAP_REG_VFUSEC, CPCAP_REG_ASSIGN3, 538 CPCAP_BIT_VFUSE_SEL, vfuse_val_tbl, 539 0x80, 0xf, 0x80, 0, 420), 540 CPCAP_REG(VHVIO, CPCAP_REG_VHVIOC, CPCAP_REG_ASSIGN3, 541 CPCAP_BIT_VHVIO_SEL, vhvio_val_tbl, 542 0x17, 0, 0x2, 0, 0), 543 CPCAP_REG(VSDIO, CPCAP_REG_VSDIOC, CPCAP_REG_ASSIGN2, 544 CPCAP_BIT_VSDIO_SEL, vsdio_val_tbl, 545 0x87, 0x38, 0x2, 0, 420), 546 CPCAP_REG(VPLL, CPCAP_REG_VPLLC, CPCAP_REG_ASSIGN3, 547 CPCAP_BIT_VPLL_SEL, vpll_val_tbl, 548 0x43, 0x18, 0x1, 0, 420), 549 CPCAP_REG(VRF1, CPCAP_REG_VRF1C, CPCAP_REG_ASSIGN3, 550 CPCAP_BIT_VRF1_SEL, vrf1_val_tbl, 551 0xac, 0x2, 0xc, 0, 10), 552 CPCAP_REG(VRF2, CPCAP_REG_VRF2C, CPCAP_REG_ASSIGN3, 553 CPCAP_BIT_VRF2_SEL, vrf2_val_tbl, 554 0x23, 0x8, 0x3, 0, 10), 555 CPCAP_REG(VRFREF, CPCAP_REG_VRFREFC, CPCAP_REG_ASSIGN3, 556 CPCAP_BIT_VRFREF_SEL, vrfref_val_tbl, 557 0x23, 0x8, 0x3, 0, 420), 558 CPCAP_REG(VWLAN1, CPCAP_REG_VWLAN1C, CPCAP_REG_ASSIGN3, 559 CPCAP_BIT_VWLAN1_SEL, vwlan1_val_tbl, 560 0x47, 0x10, 0x5, 0, 420), 561 CPCAP_REG(VWLAN2, CPCAP_REG_VWLAN2C, CPCAP_REG_ASSIGN3, 562 CPCAP_BIT_VWLAN2_SEL, vwlan2_val_tbl, 563 0x20c, 0xc0, 0x8, 0, 420), 564 CPCAP_REG(VSIM, CPCAP_REG_VSIMC, CPCAP_REG_ASSIGN3, 565 0xffff, vsim_val_tbl, 566 0x23, 0x8, 0x3, 0, 420), 567 CPCAP_REG(VSIMCARD, CPCAP_REG_VSIMC, CPCAP_REG_ASSIGN3, 568 0xffff, vsimcard_val_tbl, 569 0x1e80, 0x8, 0x1e00, 0, 420), 570 CPCAP_REG(VVIB, CPCAP_REG_VVIBC, CPCAP_REG_ASSIGN3, 571 CPCAP_BIT_VVIB_SEL, vvib_val_tbl, 572 0x1, 0xc, 0, 0x1, 500), 573 CPCAP_REG(VUSB, CPCAP_REG_VUSBC, CPCAP_REG_ASSIGN3, 574 CPCAP_BIT_VUSB_SEL, vusb_val_tbl, 575 0x11c, 0x40, 0xc, 0, 0), 576 CPCAP_REG(VAUDIO, CPCAP_REG_VAUDIOC, CPCAP_REG_ASSIGN4, 577 CPCAP_BIT_VAUDIO_SEL, vaudio_val_tbl, 578 0x16, 0x1, 0x4, 0, 0), 579 { /* sentinel */ }, 580 }; 581 582 static const struct of_device_id cpcap_regulator_id_table[] = { 583 { 584 .compatible = "motorola,cpcap-regulator", 585 }, 586 { 587 .compatible = "motorola,mapphone-cpcap-regulator", 588 .data = omap4_regulators, 589 }, 590 { 591 .compatible = "motorola,mot-cpcap-regulator", 592 .data = mot_regulators, 593 }, 594 { 595 .compatible = "motorola,xoom-cpcap-regulator", 596 .data = xoom_regulators, 597 }, 598 {}, 599 }; 600 MODULE_DEVICE_TABLE(of, cpcap_regulator_id_table); 601 602 static int cpcap_regulator_probe(struct platform_device *pdev) 603 { 604 struct cpcap_ddata *ddata; 605 const struct cpcap_regulator *match_data; 606 struct regulator_config config; 607 int i; 608 609 match_data = of_device_get_match_data(&pdev->dev); 610 if (!match_data) { 611 dev_err(&pdev->dev, "no configuration data found\n"); 612 613 return -ENODEV; 614 } 615 616 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL); 617 if (!ddata) 618 return -ENOMEM; 619 620 ddata->reg = dev_get_regmap(pdev->dev.parent, NULL); 621 if (!ddata->reg) 622 return -ENODEV; 623 624 ddata->dev = &pdev->dev; 625 ddata->soc = match_data; 626 platform_set_drvdata(pdev, ddata); 627 628 memset(&config, 0, sizeof(config)); 629 config.dev = &pdev->dev; 630 config.regmap = ddata->reg; 631 632 for (i = 0; i < CPCAP_NR_REGULATORS; i++) { 633 const struct cpcap_regulator *regulator = &ddata->soc[i]; 634 struct regulator_dev *rdev; 635 636 if (!regulator->rdesc.name) 637 break; 638 639 if (regulator->rdesc.volt_table == unknown_val_tbl) 640 continue; 641 642 config.driver_data = (void *)regulator; 643 rdev = devm_regulator_register(&pdev->dev, 644 ®ulator->rdesc, 645 &config); 646 if (IS_ERR(rdev)) { 647 dev_err(&pdev->dev, "failed to register regulator %s\n", 648 regulator->rdesc.name); 649 650 return PTR_ERR(rdev); 651 } 652 } 653 654 return 0; 655 } 656 657 static struct platform_driver cpcap_regulator_driver = { 658 .probe = cpcap_regulator_probe, 659 .driver = { 660 .name = "cpcap-regulator", 661 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 662 .of_match_table = of_match_ptr(cpcap_regulator_id_table), 663 }, 664 }; 665 666 module_platform_driver(cpcap_regulator_driver); 667 668 MODULE_ALIAS("platform:cpcap-regulator"); 669 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>"); 670 MODULE_DESCRIPTION("CPCAP regulator driver"); 671 MODULE_LICENSE("GPL v2"); 672