1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * This contains all required hardware related helper functions for 4 * Trace Buffer Extension (TRBE) driver in the coresight framework. 5 * 6 * Copyright (C) 2020 ARM Ltd. 7 * 8 * Author: Anshuman Khandual <anshuman.khandual@arm.com> 9 */ 10 #include <linux/acpi.h> 11 #include <linux/coresight.h> 12 #include <linux/device.h> 13 #include <linux/irq.h> 14 #include <linux/kernel.h> 15 #include <linux/of.h> 16 #include <linux/perf/arm_pmu.h> 17 #include <linux/platform_device.h> 18 #include <linux/smp.h> 19 20 #include "coresight-etm-perf.h" 21 is_trbe_available(void)22static inline bool is_trbe_available(void) 23 { 24 u64 aa64dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1); 25 unsigned int trbe = cpuid_feature_extract_unsigned_field(aa64dfr0, 26 ID_AA64DFR0_EL1_TraceBuffer_SHIFT); 27 28 return trbe >= ID_AA64DFR0_EL1_TraceBuffer_IMP; 29 } 30 is_trbe_enabled(void)31static inline bool is_trbe_enabled(void) 32 { 33 u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1); 34 35 return trblimitr & TRBLIMITR_EL1_E; 36 } 37 38 #define TRBE_EC_OTHERS 0 39 #define TRBE_EC_STAGE1_ABORT 36 40 #define TRBE_EC_STAGE2_ABORT 37 41 get_trbe_ec(u64 trbsr)42static inline int get_trbe_ec(u64 trbsr) 43 { 44 return (trbsr & TRBSR_EL1_EC_MASK) >> TRBSR_EL1_EC_SHIFT; 45 } 46 47 #define TRBE_BSC_NOT_STOPPED 0 48 #define TRBE_BSC_FILLED 1 49 #define TRBE_BSC_TRIGGERED 2 50 get_trbe_bsc(u64 trbsr)51static inline int get_trbe_bsc(u64 trbsr) 52 { 53 return (trbsr & TRBSR_EL1_BSC_MASK) >> TRBSR_EL1_BSC_SHIFT; 54 } 55 clr_trbe_irq(void)56static inline void clr_trbe_irq(void) 57 { 58 u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1); 59 60 trbsr &= ~TRBSR_EL1_IRQ; 61 write_sysreg_s(trbsr, SYS_TRBSR_EL1); 62 } 63 is_trbe_irq(u64 trbsr)64static inline bool is_trbe_irq(u64 trbsr) 65 { 66 return trbsr & TRBSR_EL1_IRQ; 67 } 68 is_trbe_trg(u64 trbsr)69static inline bool is_trbe_trg(u64 trbsr) 70 { 71 return trbsr & TRBSR_EL1_TRG; 72 } 73 is_trbe_wrap(u64 trbsr)74static inline bool is_trbe_wrap(u64 trbsr) 75 { 76 return trbsr & TRBSR_EL1_WRAP; 77 } 78 is_trbe_abort(u64 trbsr)79static inline bool is_trbe_abort(u64 trbsr) 80 { 81 return trbsr & TRBSR_EL1_EA; 82 } 83 is_trbe_running(u64 trbsr)84static inline bool is_trbe_running(u64 trbsr) 85 { 86 return !(trbsr & TRBSR_EL1_S); 87 } 88 get_trbe_flag_update(u64 trbidr)89static inline bool get_trbe_flag_update(u64 trbidr) 90 { 91 return trbidr & TRBIDR_EL1_F; 92 } 93 is_trbe_programmable(u64 trbidr)94static inline bool is_trbe_programmable(u64 trbidr) 95 { 96 return !(trbidr & TRBIDR_EL1_P); 97 } 98 get_trbe_address_align(u64 trbidr)99static inline int get_trbe_address_align(u64 trbidr) 100 { 101 return (trbidr & TRBIDR_EL1_Align_MASK) >> TRBIDR_EL1_Align_SHIFT; 102 } 103 get_trbe_write_pointer(void)104static inline unsigned long get_trbe_write_pointer(void) 105 { 106 return read_sysreg_s(SYS_TRBPTR_EL1); 107 } 108 set_trbe_write_pointer(unsigned long addr)109static inline void set_trbe_write_pointer(unsigned long addr) 110 { 111 WARN_ON(is_trbe_enabled()); 112 write_sysreg_s(addr, SYS_TRBPTR_EL1); 113 } 114 get_trbe_limit_pointer(void)115static inline unsigned long get_trbe_limit_pointer(void) 116 { 117 u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1); 118 unsigned long addr = trblimitr & TRBLIMITR_EL1_LIMIT_MASK; 119 120 WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE)); 121 return addr; 122 } 123 get_trbe_base_pointer(void)124static inline unsigned long get_trbe_base_pointer(void) 125 { 126 u64 trbbaser = read_sysreg_s(SYS_TRBBASER_EL1); 127 unsigned long addr = trbbaser & TRBBASER_EL1_BASE_MASK; 128 129 WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE)); 130 return addr; 131 } 132 set_trbe_base_pointer(unsigned long addr)133static inline void set_trbe_base_pointer(unsigned long addr) 134 { 135 WARN_ON(is_trbe_enabled()); 136 WARN_ON(!IS_ALIGNED(addr, (1UL << TRBBASER_EL1_BASE_SHIFT))); 137 WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE)); 138 write_sysreg_s(addr, SYS_TRBBASER_EL1); 139 } 140