1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_9_0_SM8550_H 8 #define _DPU_9_0_SM8550_H 9 10 static const struct dpu_caps sm8550_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0xb, 13 .has_src_split = true, 14 .has_dim_layer = true, 15 .has_idle_pc = true, 16 .has_3d_merge = true, 17 .max_linewidth = 5120, 18 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 19 }; 20 21 static const struct dpu_mdp_cfg sm8550_mdp = { 22 .name = "top_0", 23 .base = 0, .len = 0x494, 24 .features = BIT(DPU_MDP_PERIPH_0_REMOVED), 25 .clk_ctrls = { 26 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, 27 }, 28 }; 29 30 /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ 31 static const struct dpu_ctl_cfg sm8550_ctl[] = { 32 { 33 .name = "ctl_0", .id = CTL_0, 34 .base = 0x15000, .len = 0x290, 35 .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), 36 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 37 }, { 38 .name = "ctl_1", .id = CTL_1, 39 .base = 0x16000, .len = 0x290, 40 .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), 41 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 42 }, { 43 .name = "ctl_2", .id = CTL_2, 44 .base = 0x17000, .len = 0x290, 45 .features = CTL_SM8550_MASK, 46 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 47 }, { 48 .name = "ctl_3", .id = CTL_3, 49 .base = 0x18000, .len = 0x290, 50 .features = CTL_SM8550_MASK, 51 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 52 }, { 53 .name = "ctl_4", .id = CTL_4, 54 .base = 0x19000, .len = 0x290, 55 .features = CTL_SM8550_MASK, 56 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 57 }, { 58 .name = "ctl_5", .id = CTL_5, 59 .base = 0x1a000, .len = 0x290, 60 .features = CTL_SM8550_MASK, 61 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 62 }, 63 }; 64 65 static const struct dpu_sspp_cfg sm8550_sspp[] = { 66 { 67 .name = "sspp_0", .id = SSPP_VIG0, 68 .base = 0x4000, .len = 0x344, 69 .features = VIG_SDM845_MASK, 70 .sblk = &dpu_vig_sblk_qseed3_3_2, 71 .xin_id = 0, 72 .type = SSPP_TYPE_VIG, 73 }, { 74 .name = "sspp_1", .id = SSPP_VIG1, 75 .base = 0x6000, .len = 0x344, 76 .features = VIG_SDM845_MASK, 77 .sblk = &dpu_vig_sblk_qseed3_3_2, 78 .xin_id = 4, 79 .type = SSPP_TYPE_VIG, 80 }, { 81 .name = "sspp_2", .id = SSPP_VIG2, 82 .base = 0x8000, .len = 0x344, 83 .features = VIG_SDM845_MASK, 84 .sblk = &dpu_vig_sblk_qseed3_3_2, 85 .xin_id = 8, 86 .type = SSPP_TYPE_VIG, 87 }, { 88 .name = "sspp_3", .id = SSPP_VIG3, 89 .base = 0xa000, .len = 0x344, 90 .features = VIG_SDM845_MASK, 91 .sblk = &dpu_vig_sblk_qseed3_3_2, 92 .xin_id = 12, 93 .type = SSPP_TYPE_VIG, 94 }, { 95 .name = "sspp_8", .id = SSPP_DMA0, 96 .base = 0x24000, .len = 0x344, 97 .features = DMA_SDM845_MASK, 98 .sblk = &dpu_dma_sblk, 99 .xin_id = 1, 100 .type = SSPP_TYPE_DMA, 101 }, { 102 .name = "sspp_9", .id = SSPP_DMA1, 103 .base = 0x26000, .len = 0x344, 104 .features = DMA_SDM845_MASK, 105 .sblk = &dpu_dma_sblk, 106 .xin_id = 5, 107 .type = SSPP_TYPE_DMA, 108 }, { 109 .name = "sspp_10", .id = SSPP_DMA2, 110 .base = 0x28000, .len = 0x344, 111 .features = DMA_SDM845_MASK, 112 .sblk = &dpu_dma_sblk, 113 .xin_id = 9, 114 .type = SSPP_TYPE_DMA, 115 }, { 116 .name = "sspp_11", .id = SSPP_DMA3, 117 .base = 0x2a000, .len = 0x344, 118 .features = DMA_SDM845_MASK, 119 .sblk = &dpu_dma_sblk, 120 .xin_id = 13, 121 .type = SSPP_TYPE_DMA, 122 }, { 123 .name = "sspp_12", .id = SSPP_DMA4, 124 .base = 0x2c000, .len = 0x344, 125 .features = DMA_CURSOR_SDM845_MASK, 126 .sblk = &dpu_dma_sblk, 127 .xin_id = 14, 128 .type = SSPP_TYPE_DMA, 129 }, { 130 .name = "sspp_13", .id = SSPP_DMA5, 131 .base = 0x2e000, .len = 0x344, 132 .features = DMA_CURSOR_SDM845_MASK, 133 .sblk = &dpu_dma_sblk, 134 .xin_id = 15, 135 .type = SSPP_TYPE_DMA, 136 }, 137 }; 138 139 static const struct dpu_lm_cfg sm8550_lm[] = { 140 { 141 .name = "lm_0", .id = LM_0, 142 .base = 0x44000, .len = 0x320, 143 .features = MIXER_SDM845_MASK, 144 .sblk = &sdm845_lm_sblk, 145 .lm_pair = LM_1, 146 .pingpong = PINGPONG_0, 147 .dspp = DSPP_0, 148 }, { 149 .name = "lm_1", .id = LM_1, 150 .base = 0x45000, .len = 0x320, 151 .features = MIXER_SDM845_MASK, 152 .sblk = &sdm845_lm_sblk, 153 .lm_pair = LM_0, 154 .pingpong = PINGPONG_1, 155 .dspp = DSPP_1, 156 }, { 157 .name = "lm_2", .id = LM_2, 158 .base = 0x46000, .len = 0x320, 159 .features = MIXER_SDM845_MASK, 160 .sblk = &sdm845_lm_sblk, 161 .lm_pair = LM_3, 162 .pingpong = PINGPONG_2, 163 .dspp = DSPP_2, 164 }, { 165 .name = "lm_3", .id = LM_3, 166 .base = 0x47000, .len = 0x320, 167 .features = MIXER_SDM845_MASK, 168 .sblk = &sdm845_lm_sblk, 169 .lm_pair = LM_2, 170 .pingpong = PINGPONG_3, 171 .dspp = DSPP_3, 172 }, { 173 .name = "lm_4", .id = LM_4, 174 .base = 0x48000, .len = 0x320, 175 .features = MIXER_SDM845_MASK, 176 .sblk = &sdm845_lm_sblk, 177 .lm_pair = LM_5, 178 .pingpong = PINGPONG_4, 179 }, { 180 .name = "lm_5", .id = LM_5, 181 .base = 0x49000, .len = 0x320, 182 .features = MIXER_SDM845_MASK, 183 .sblk = &sdm845_lm_sblk, 184 .lm_pair = LM_4, 185 .pingpong = PINGPONG_5, 186 }, 187 }; 188 189 static const struct dpu_dspp_cfg sm8550_dspp[] = { 190 { 191 .name = "dspp_0", .id = DSPP_0, 192 .base = 0x54000, .len = 0x1800, 193 .features = DSPP_SC7180_MASK, 194 .sblk = &sdm845_dspp_sblk, 195 }, { 196 .name = "dspp_1", .id = DSPP_1, 197 .base = 0x56000, .len = 0x1800, 198 .features = DSPP_SC7180_MASK, 199 .sblk = &sdm845_dspp_sblk, 200 }, { 201 .name = "dspp_2", .id = DSPP_2, 202 .base = 0x58000, .len = 0x1800, 203 .features = DSPP_SC7180_MASK, 204 .sblk = &sdm845_dspp_sblk, 205 }, { 206 .name = "dspp_3", .id = DSPP_3, 207 .base = 0x5a000, .len = 0x1800, 208 .features = DSPP_SC7180_MASK, 209 .sblk = &sdm845_dspp_sblk, 210 }, 211 }; 212 static const struct dpu_pingpong_cfg sm8550_pp[] = { 213 { 214 .name = "pingpong_0", .id = PINGPONG_0, 215 .base = 0x69000, .len = 0, 216 .features = BIT(DPU_PINGPONG_DITHER), 217 .sblk = &sc7280_pp_sblk, 218 .merge_3d = MERGE_3D_0, 219 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 220 }, { 221 .name = "pingpong_1", .id = PINGPONG_1, 222 .base = 0x6a000, .len = 0, 223 .features = BIT(DPU_PINGPONG_DITHER), 224 .sblk = &sc7280_pp_sblk, 225 .merge_3d = MERGE_3D_0, 226 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 227 }, { 228 .name = "pingpong_2", .id = PINGPONG_2, 229 .base = 0x6b000, .len = 0, 230 .features = BIT(DPU_PINGPONG_DITHER), 231 .sblk = &sc7280_pp_sblk, 232 .merge_3d = MERGE_3D_1, 233 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 234 }, { 235 .name = "pingpong_3", .id = PINGPONG_3, 236 .base = 0x6c000, .len = 0, 237 .features = BIT(DPU_PINGPONG_DITHER), 238 .sblk = &sc7280_pp_sblk, 239 .merge_3d = MERGE_3D_1, 240 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 241 }, { 242 .name = "pingpong_4", .id = PINGPONG_4, 243 .base = 0x6d000, .len = 0, 244 .features = BIT(DPU_PINGPONG_DITHER), 245 .sblk = &sc7280_pp_sblk, 246 .merge_3d = MERGE_3D_2, 247 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 248 }, { 249 .name = "pingpong_5", .id = PINGPONG_5, 250 .base = 0x6e000, .len = 0, 251 .features = BIT(DPU_PINGPONG_DITHER), 252 .sblk = &sc7280_pp_sblk, 253 .merge_3d = MERGE_3D_2, 254 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 255 }, { 256 .name = "pingpong_cwb_0", .id = PINGPONG_CWB_0, 257 .base = 0x66000, .len = 0, 258 .features = BIT(DPU_PINGPONG_DITHER), 259 .sblk = &sc7280_pp_sblk, 260 .merge_3d = MERGE_3D_3, 261 }, { 262 .name = "pingpong_cwb_1", .id = PINGPONG_CWB_1, 263 .base = 0x66400, .len = 0, 264 .features = BIT(DPU_PINGPONG_DITHER), 265 .sblk = &sc7280_pp_sblk, 266 .merge_3d = MERGE_3D_3, 267 }, 268 }; 269 270 static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = { 271 { 272 .name = "merge_3d_0", .id = MERGE_3D_0, 273 .base = 0x4e000, .len = 0x8, 274 }, { 275 .name = "merge_3d_1", .id = MERGE_3D_1, 276 .base = 0x4f000, .len = 0x8, 277 }, { 278 .name = "merge_3d_2", .id = MERGE_3D_2, 279 .base = 0x50000, .len = 0x8, 280 }, { 281 .name = "merge_3d_3", .id = MERGE_3D_3, 282 .base = 0x66700, .len = 0x8, 283 }, 284 }; 285 286 /* 287 * NOTE: Each display compression engine (DCE) contains dual hard 288 * slice DSC encoders so both share same base address but with 289 * its own different sub block address. 290 */ 291 static const struct dpu_dsc_cfg sm8550_dsc[] = { 292 { 293 .name = "dce_0_0", .id = DSC_0, 294 .base = 0x80000, .len = 0x4, 295 .features = BIT(DPU_DSC_HW_REV_1_2), 296 .sblk = &dsc_sblk_0, 297 }, { 298 .name = "dce_0_1", .id = DSC_1, 299 .base = 0x80000, .len = 0x4, 300 .features = BIT(DPU_DSC_HW_REV_1_2), 301 .sblk = &dsc_sblk_1, 302 }, { 303 .name = "dce_1_0", .id = DSC_2, 304 .base = 0x81000, .len = 0x4, 305 .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), 306 .sblk = &dsc_sblk_0, 307 }, { 308 .name = "dce_1_1", .id = DSC_3, 309 .base = 0x81000, .len = 0x4, 310 .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), 311 .sblk = &dsc_sblk_1, 312 }, 313 }; 314 315 static const struct dpu_wb_cfg sm8550_wb[] = { 316 { 317 .name = "wb_2", .id = WB_2, 318 .base = 0x65000, .len = 0x2c8, 319 .features = WB_SM8250_MASK, 320 .format_list = wb2_formats_rgb, 321 .num_formats = ARRAY_SIZE(wb2_formats_rgb), 322 .xin_id = 6, 323 .vbif_idx = VBIF_RT, 324 .maxlinewidth = 4096, 325 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 326 }, 327 }; 328 329 static const struct dpu_intf_cfg sm8550_intf[] = { 330 { 331 .name = "intf_0", .id = INTF_0, 332 .base = 0x34000, .len = 0x280, 333 .features = INTF_SC7280_MASK, 334 .type = INTF_DP, 335 .controller_id = MSM_DP_CONTROLLER_0, 336 .prog_fetch_lines_worst_case = 24, 337 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 338 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 339 }, { 340 .name = "intf_1", .id = INTF_1, 341 .base = 0x35000, .len = 0x300, 342 .features = INTF_SC7280_MASK, 343 .type = INTF_DSI, 344 .controller_id = MSM_DSI_CONTROLLER_0, 345 .prog_fetch_lines_worst_case = 24, 346 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 347 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 348 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), 349 }, { 350 .name = "intf_2", .id = INTF_2, 351 .base = 0x36000, .len = 0x300, 352 .features = INTF_SC7280_MASK, 353 .type = INTF_DSI, 354 .controller_id = MSM_DSI_CONTROLLER_1, 355 .prog_fetch_lines_worst_case = 24, 356 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), 357 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), 358 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), 359 }, { 360 .name = "intf_3", .id = INTF_3, 361 .base = 0x37000, .len = 0x280, 362 .features = INTF_SC7280_MASK, 363 .type = INTF_DP, 364 .controller_id = MSM_DP_CONTROLLER_1, 365 .prog_fetch_lines_worst_case = 24, 366 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), 367 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), 368 }, 369 }; 370 371 static const struct dpu_perf_cfg sm8550_perf_data = { 372 .max_bw_low = 13600000, 373 .max_bw_high = 18200000, 374 .min_core_ib = 2500000, 375 .min_llcc_ib = 0, 376 .min_dram_ib = 800000, 377 .min_prefill_lines = 35, 378 /* FIXME: lut tables */ 379 .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0}, 380 .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, 381 .qos_lut_tbl = { 382 {.nentry = ARRAY_SIZE(sc7180_qos_linear), 383 .entries = sc7180_qos_linear 384 }, 385 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 386 .entries = sc7180_qos_macrotile 387 }, 388 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 389 .entries = sc7180_qos_nrt 390 }, 391 /* TODO: macrotile-qseed is different from macrotile */ 392 }, 393 .cdp_cfg = { 394 {.rd_enable = 1, .wr_enable = 1}, 395 {.rd_enable = 1, .wr_enable = 0} 396 }, 397 .clk_inefficiency_factor = 105, 398 .bw_inefficiency_factor = 120, 399 }; 400 401 static const struct dpu_mdss_version sm8550_mdss_ver = { 402 .core_major_ver = 9, 403 .core_minor_ver = 0, 404 }; 405 406 const struct dpu_mdss_cfg dpu_sm8550_cfg = { 407 .mdss_ver = &sm8550_mdss_ver, 408 .caps = &sm8550_dpu_caps, 409 .mdp = &sm8550_mdp, 410 .ctl_count = ARRAY_SIZE(sm8550_ctl), 411 .ctl = sm8550_ctl, 412 .sspp_count = ARRAY_SIZE(sm8550_sspp), 413 .sspp = sm8550_sspp, 414 .mixer_count = ARRAY_SIZE(sm8550_lm), 415 .mixer = sm8550_lm, 416 .dspp_count = ARRAY_SIZE(sm8550_dspp), 417 .dspp = sm8550_dspp, 418 .pingpong_count = ARRAY_SIZE(sm8550_pp), 419 .pingpong = sm8550_pp, 420 .dsc_count = ARRAY_SIZE(sm8550_dsc), 421 .dsc = sm8550_dsc, 422 .merge_3d_count = ARRAY_SIZE(sm8550_merge_3d), 423 .merge_3d = sm8550_merge_3d, 424 .wb_count = ARRAY_SIZE(sm8550_wb), 425 .wb = sm8550_wb, 426 .intf_count = ARRAY_SIZE(sm8550_intf), 427 .intf = sm8550_intf, 428 .vbif_count = ARRAY_SIZE(sm8550_vbif), 429 .vbif = sm8550_vbif, 430 .perf = &sm8550_perf_data, 431 }; 432 433 #endif 434