1 /* SPDX-License-Identifier: MIT */ 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 #ifndef __DML_DML_DCN42_SOC_BB__ 6 #define __DML_DML_DCN42_SOC_BB__ 7 8 #include "dml_top_soc_parameter_types.h" 9 10 static const struct dml2_soc_qos_parameters dml_dcn42_variant_a_soc_qos_params = { 11 .derate_table = { 12 .system_active_urgent = { 13 .dram_derate_percent_pixel = 65, 14 .dram_derate_percent_vm = 30, 15 .dram_derate_percent_pixel_and_vm = 60, 16 .fclk_derate_percent = 80, 17 .dcfclk_derate_percent = 80, 18 }, 19 .system_active_average = { 20 .dram_derate_percent_pixel = 30, 21 .dram_derate_percent_vm = 30, 22 .dram_derate_percent_pixel_and_vm = 30, 23 .fclk_derate_percent = 60, 24 .dcfclk_derate_percent = 60, 25 }, 26 .dcn_mall_prefetch_urgent = { 27 .dram_derate_percent_pixel = 65, 28 .dram_derate_percent_vm = 30, 29 .dram_derate_percent_pixel_and_vm = 60, 30 .fclk_derate_percent = 80, 31 .dcfclk_derate_percent = 80, 32 }, 33 .dcn_mall_prefetch_average = { 34 .dram_derate_percent_pixel = 30, 35 .dram_derate_percent_vm = 30, 36 .dram_derate_percent_pixel_and_vm = 30, 37 .fclk_derate_percent = 60, 38 .dcfclk_derate_percent = 60, 39 }, 40 .system_idle_average = { 41 .dram_derate_percent_pixel = 30, 42 .dram_derate_percent_vm = 30, 43 .dram_derate_percent_pixel_and_vm = 30, 44 .fclk_derate_percent = 60, 45 .dcfclk_derate_percent = 60, 46 }, 47 }, 48 .writeback = { 49 .base_latency_us = 12, 50 .scaling_factor_us = 0, 51 .scaling_factor_mhz = 0, 52 }, 53 .qos_params = { 54 .dcn32x = { 55 .loaded_round_trip_latency_fclk_cycles = 106, 56 .urgent_latency_us = { 57 .base_latency_us = 4, 58 .base_latency_pixel_vm_us = 4, 59 .base_latency_vm_us = 4, 60 .scaling_factor_fclk_us = 0, 61 .scaling_factor_mhz = 0, 62 }, 63 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 64 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 65 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 66 }, 67 }, 68 .qos_type = dml2_qos_param_type_dcn3, 69 }; 70 71 /* Default SOC bounding box for DCN42 based on LPDDR5/LPCAMM2 latencies*/ 72 static const struct dml2_soc_bb dml2_socbb_dcn42 = { 73 .clk_table = { 74 .wck_ratio = { 75 .clk_values_khz = {2}, 76 }, 77 .uclk = { 78 .clk_values_khz = {400000}, 79 .num_clk_values = 1, 80 }, 81 .fclk = { 82 .clk_values_khz = {400000}, 83 .num_clk_values = 1, 84 }, 85 .dcfclk = { 86 .clk_values_khz = {200000}, 87 .num_clk_values = 1, 88 }, 89 .dispclk = { 90 .clk_values_khz = {1500000}, 91 .num_clk_values = 1, 92 }, 93 .dppclk = { 94 .clk_values_khz = {1500000}, 95 .num_clk_values = 1, 96 }, 97 .dtbclk = { 98 .clk_values_khz = {600000}, 99 .num_clk_values = 1, 100 }, 101 .phyclk = { 102 .clk_values_khz = {810000}, 103 .num_clk_values = 1, 104 }, 105 .socclk = { 106 .clk_values_khz = {600000}, 107 .num_clk_values = 1, 108 }, 109 .dscclk = { 110 .clk_values_khz = {500000}, 111 .num_clk_values = 1, 112 }, 113 .phyclk_d18 = { 114 .clk_values_khz = {667000}, 115 .num_clk_values = 1, 116 }, 117 .phyclk_d32 = { 118 .clk_values_khz = {625000}, 119 .num_clk_values = 1, 120 }, 121 .dram_config = { 122 .channel_width_bytes = 4, 123 .channel_count = 4, 124 .alt_clock_bw_conversion = true, 125 }, 126 }, 127 128 .qos_parameters = { 129 .derate_table = { 130 .system_active_urgent = { 131 .dram_derate_percent_pixel = 65, 132 .dram_derate_percent_vm = 30, 133 .dram_derate_percent_pixel_and_vm = 60, 134 .fclk_derate_percent = 80, 135 .dcfclk_derate_percent = 80, 136 }, 137 .system_active_average = { 138 .dram_derate_percent_pixel = 30, 139 .dram_derate_percent_vm = 30, 140 .dram_derate_percent_pixel_and_vm = 30, 141 .fclk_derate_percent = 60, 142 .dcfclk_derate_percent = 60, 143 }, 144 .dcn_mall_prefetch_urgent = { 145 .dram_derate_percent_pixel = 65, 146 .dram_derate_percent_vm = 30, 147 .dram_derate_percent_pixel_and_vm = 60, 148 .fclk_derate_percent = 80, 149 .dcfclk_derate_percent = 80, 150 }, 151 .dcn_mall_prefetch_average = { 152 .dram_derate_percent_pixel = 30, 153 .dram_derate_percent_vm = 30, 154 .dram_derate_percent_pixel_and_vm = 30, 155 .fclk_derate_percent = 60, 156 .dcfclk_derate_percent = 60, 157 }, 158 .system_idle_average = { 159 .dram_derate_percent_pixel = 30, 160 .dram_derate_percent_vm = 30, 161 .dram_derate_percent_pixel_and_vm = 30, 162 .fclk_derate_percent = 60, 163 .dcfclk_derate_percent = 60, 164 }, 165 }, 166 .writeback = { 167 .base_latency_us = 12, 168 .scaling_factor_us = 0, 169 .scaling_factor_mhz = 0, 170 }, 171 .qos_params = { 172 .dcn32x = { 173 .loaded_round_trip_latency_fclk_cycles = 106, 174 .urgent_latency_us = { 175 .base_latency_us = 4, 176 .base_latency_pixel_vm_us = 4, 177 .base_latency_vm_us = 4, 178 .scaling_factor_fclk_us = 0, 179 .scaling_factor_mhz = 0, 180 }, 181 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 182 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 183 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 184 }, 185 }, 186 .qos_type = dml2_qos_param_type_dcn3, 187 }, 188 189 /* DCN42 params for LPDDR5/LPCAMM2 */ 190 .power_management_parameters = { 191 .dram_clk_change_blackout_us = 36, 192 .fclk_change_blackout_us = 0, 193 .g7_ppt_blackout_us = 0, 194 .stutter_enter_plus_exit_latency_us = 14, 195 .stutter_exit_latency_us = 12, 196 .z8_stutter_enter_plus_exit_latency_us = 300, 197 .z8_stutter_exit_latency_us = 200, 198 }, 199 200 .vmin_limit = { 201 .dispclk_khz = 632 * 1000, 202 }, 203 204 .dprefclk_mhz = 600, 205 .xtalclk_mhz = 24, 206 .pcie_refclk_mhz = 100, 207 .dchub_refclk_mhz = 50, 208 .mall_allocated_for_dcn_mbytes = 0, 209 .max_outstanding_reqs = 256, 210 .fabric_datapath_to_dcn_data_return_bytes = 32, 211 .return_bus_width_bytes = 64, 212 .hostvm_min_page_size_kbytes = 4, 213 .gpuvm_min_page_size_kbytes = 4, 214 .gpuvm_max_page_table_levels = 1, 215 .hostvm_max_non_cached_page_table_levels = 2, 216 .phy_downspread_percent = 0.38, 217 .dcn_downspread_percent = 0.38, 218 .dispclk_dppclk_vco_speed_mhz = 3000, 219 .do_urgent_latency_adjustment = 0, 220 .mem_word_bytes = 32, 221 .num_dcc_mcaches = 8, 222 .mcache_size_bytes = 2048, 223 .mcache_line_size_bytes = 32, 224 .max_fclk_for_uclk_dpm_khz = 2200 * 1000, 225 }; 226 227 /* DCN42 params for DDR5 */ 228 struct dml2_soc_power_management_parameters dcn42_ddr5_power_management_parameters = { 229 .dram_clk_change_blackout_us = 36, 230 .fclk_change_blackout_us = 0, 231 .g7_ppt_blackout_us = 0, 232 .stutter_enter_plus_exit_latency_us = 23.5, 233 .stutter_exit_latency_us = 21.5, 234 .z8_stutter_enter_plus_exit_latency_us = 300, 235 .z8_stutter_exit_latency_us = 200, 236 }; 237 238 static const struct dml2_ip_capabilities dml2_dcn42_max_ip_caps = { 239 .pipe_count = 4, 240 .otg_count = 4, 241 .num_dsc = 4, 242 .max_num_dp2p0_streams = 4, 243 .max_num_hdmi_frl_outputs = 1, 244 .max_num_dp2p0_outputs = 4, 245 .rob_buffer_size_kbytes = 64, 246 .config_return_buffer_size_in_kbytes = 1792, 247 .config_return_buffer_segment_size_in_kbytes = 64, 248 .meta_fifo_size_in_kentries = 32, 249 .compressed_buffer_segment_size_in_kbytes = 64, 250 .cursor_buffer_size = 42, 251 .max_flip_time_us = 110, 252 .max_flip_time_lines = 50, 253 .hostvm_mode = 0, 254 .subvp_drr_scheduling_margin_us = 100, 255 .subvp_prefetch_end_to_mall_start_us = 15, 256 .subvp_fw_processing_delay = 15, 257 .max_vactive_det_fill_delay_us = 400, 258 259 .fams2 = { 260 .max_allow_delay_us = 100 * 1000, 261 .scheduling_delay_us = 550, 262 .vertical_interrupt_ack_delay_us = 40, 263 .allow_programming_delay_us = 18, 264 .min_allow_width_us = 20, 265 .subvp_df_throttle_delay_us = 100, 266 .subvp_programming_delay_us = 200, 267 .subvp_prefetch_to_mall_delay_us = 18, 268 .drr_programming_delay_us = 35, 269 270 .lock_timeout_us = 5000, 271 .recovery_timeout_us = 5000, 272 .flip_programming_delay_us = 300, 273 }, 274 }; 275 276 #endif 277