1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2#include <dt-bindings/interrupt-controller/arm-gic.h> 3 4/ { 5 compatible = "brcm,bcm2712"; 6 7 #address-cells = <2>; 8 #size-cells = <2>; 9 10 interrupt-parent = <&gicv2>; 11 12 clocks { 13 /* The oscillator is the root of the clock tree. */ 14 clk_osc: clk-osc { 15 compatible = "fixed-clock"; 16 #clock-cells = <0>; 17 clock-output-names = "osc"; 18 clock-frequency = <54000000>; 19 }; 20 21 clk_vpu: clk-vpu { 22 compatible = "fixed-clock"; 23 #clock-cells = <0>; 24 clock-frequency = <750000000>; 25 clock-output-names = "vpu-clock"; 26 }; 27 28 clk_uart: clk-uart { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <9216000>; 32 clock-output-names = "uart-clock"; 33 }; 34 35 clk_emmc2: clk-emmc2 { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <200000000>; 39 clock-output-names = "emmc2-clock"; 40 }; 41 }; 42 43 cpus: cpus { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 47 /* Source for L1 d/i cache-line-size, cache-sets, cache-size 48 * https://developer.arm.com/documentation/100798/0401/L1-memory-system/About-the-L1-memory-system?lang=en 49 * Source for L2 cache-line-size and cache-sets: 50 * https://developer.arm.com/documentation/100798/0401/L2-memory-system/About-the-L2-memory-system?lang=en 51 * and for cache-size: 52 * https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712 53 */ 54 cpu0: cpu@0 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a76"; 57 reg = <0x000>; 58 enable-method = "psci"; 59 d-cache-size = <0x10000>; 60 d-cache-line-size = <64>; 61 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 62 i-cache-size = <0x10000>; 63 i-cache-line-size = <64>; 64 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 65 next-level-cache = <&l2_cache_l0>; 66 67 l2_cache_l0: l2-cache { 68 compatible = "cache"; 69 cache-size = <0x80000>; 70 cache-line-size = <64>; 71 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set 72 cache-level = <2>; 73 cache-unified; 74 next-level-cache = <&l3_cache>; 75 }; 76 }; 77 78 cpu1: cpu@1 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a76"; 81 reg = <0x100>; 82 enable-method = "psci"; 83 d-cache-size = <0x10000>; 84 d-cache-line-size = <64>; 85 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 86 i-cache-size = <0x10000>; 87 i-cache-line-size = <64>; 88 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 89 next-level-cache = <&l2_cache_l1>; 90 91 l2_cache_l1: l2-cache { 92 compatible = "cache"; 93 cache-size = <0x80000>; 94 cache-line-size = <64>; 95 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set 96 cache-level = <2>; 97 cache-unified; 98 next-level-cache = <&l3_cache>; 99 }; 100 }; 101 102 cpu2: cpu@2 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a76"; 105 reg = <0x200>; 106 enable-method = "psci"; 107 d-cache-size = <0x10000>; 108 d-cache-line-size = <64>; 109 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 110 i-cache-size = <0x10000>; 111 i-cache-line-size = <64>; 112 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 113 next-level-cache = <&l2_cache_l2>; 114 115 l2_cache_l2: l2-cache { 116 compatible = "cache"; 117 cache-size = <0x80000>; 118 cache-line-size = <64>; 119 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set 120 cache-level = <2>; 121 cache-unified; 122 next-level-cache = <&l3_cache>; 123 }; 124 }; 125 126 cpu3: cpu@3 { 127 device_type = "cpu"; 128 compatible = "arm,cortex-a76"; 129 reg = <0x300>; 130 enable-method = "psci"; 131 d-cache-size = <0x10000>; 132 d-cache-line-size = <64>; 133 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 134 i-cache-size = <0x10000>; 135 i-cache-line-size = <64>; 136 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set 137 next-level-cache = <&l2_cache_l3>; 138 139 l2_cache_l3: l2-cache { 140 compatible = "cache"; 141 cache-size = <0x80000>; 142 cache-line-size = <64>; 143 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set 144 cache-level = <2>; 145 cache-unified; 146 next-level-cache = <&l3_cache>; 147 }; 148 }; 149 150 /* Source for cache-line-size and cache-sets: 151 * https://developer.arm.com/documentation/100453/0401/L3-cache?lang=en 152 * Source for cache-size: 153 * https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712 154 */ 155 l3_cache: l3-cache { 156 compatible = "cache"; 157 cache-size = <0x200000>; 158 cache-line-size = <64>; 159 cache-sets = <2048>; // 2MiB(size)/64(line-size)=32768ways/16-way set 160 cache-level = <3>; 161 cache-unified; 162 }; 163 }; 164 165 psci { 166 method = "smc"; 167 compatible = "arm,psci-1.0", "arm,psci-0.2"; 168 }; 169 170 rmem: reserved-memory { 171 ranges; 172 #address-cells = <2>; 173 #size-cells = <2>; 174 175 atf@0 { 176 reg = <0x0 0x0 0x0 0x80000>; 177 no-map; 178 }; 179 180 cma: linux,cma { 181 compatible = "shared-dma-pool"; 182 size = <0x0 0x4000000>; /* 64MB */ 183 reusable; 184 linux,cma-default; 185 alloc-ranges = <0x0 0x00000000 0x0 0x40000000>; 186 }; 187 }; 188 189 soc: soc@107c000000 { 190 compatible = "simple-bus"; 191 ranges = <0x00000000 0x10 0x00000000 0x80000000>; 192 #address-cells = <1>; 193 #size-cells = <1>; 194 195 pcie_rescal: reset-controller@119500 { 196 compatible = "brcm,bcm7216-pcie-sata-rescal"; 197 reg = <0x00119500 0x10>; 198 #reset-cells = <0>; 199 }; 200 201 sdio1: mmc@fff000 { 202 compatible = "brcm,bcm2712-sdhci", 203 "brcm,sdhci-brcmstb"; 204 reg = <0x00fff000 0x260>, 205 <0x00fff400 0x200>; 206 reg-names = "host", "cfg"; 207 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>; 208 clocks = <&clk_emmc2>; 209 clock-names = "sw_sdio"; 210 mmc-ddr-3_3v; 211 }; 212 213 bcm_reset: reset-controller@1504318 { 214 compatible = "brcm,brcmstb-reset"; 215 reg = <0x01504318 0x30>; 216 #reset-cells = <1>; 217 }; 218 219 system_timer: timer@7c003000 { 220 compatible = "brcm,bcm2835-system-timer"; 221 reg = <0x7c003000 0x1000>; 222 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 226 clock-frequency = <1000000>; 227 }; 228 229 mailbox: mailbox@7c013880 { 230 compatible = "brcm,bcm2835-mbox"; 231 reg = <0x7c013880 0x40>; 232 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 233 #mbox-cells = <0>; 234 }; 235 236 uart10: serial@7d001000 { 237 compatible = "arm,pl011", "arm,primecell"; 238 reg = <0x7d001000 0x200>; 239 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 240 clocks = <&clk_uart>, <&clk_vpu>; 241 clock-names = "uartclk", "apb_pclk"; 242 arm,primecell-periphid = <0x00341011>; 243 status = "disabled"; 244 }; 245 246 interrupt-controller@7d517000 { 247 compatible = "brcm,bcm7271-l2-intc"; 248 reg = <0x7d517000 0x10>; 249 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 250 interrupt-controller; 251 #interrupt-cells = <1>; 252 }; 253 254 gio_aon: gpio@7d517c00 { 255 compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; 256 reg = <0x7d517c00 0x40>; 257 gpio-controller; 258 #gpio-cells = <2>; 259 brcm,gpio-bank-widths = <17 6>; 260 /* The lack of 'interrupt-controller' property here is intended: 261 * don't use GIO_AON as an interrupt controller because it will 262 * clash with the firmware monitoring the PMIC interrupt via the VPU. 263 */ 264 }; 265 266 gicv2: interrupt-controller@7fff9000 { 267 compatible = "arm,gic-400"; 268 reg = <0x7fff9000 0x1000>, 269 <0x7fffa000 0x2000>, 270 <0x7fffc000 0x2000>, 271 <0x7fffe000 0x2000>; 272 interrupt-controller; 273 #interrupt-cells = <3>; 274 }; 275 276 aon_intr: interrupt-controller@7d510600 { 277 compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc"; 278 reg = <0x7d510600 0x30>; 279 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 280 interrupt-controller; 281 #interrupt-cells = <1>; 282 }; 283 284 pixelvalve0: pixelvalve@7c410000 { 285 compatible = "brcm,bcm2712-pixelvalve0"; 286 reg = <0x7c410000 0x100>; 287 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 288 }; 289 290 pixelvalve1: pixelvalve@7c411000 { 291 compatible = "brcm,bcm2712-pixelvalve1"; 292 reg = <0x7c411000 0x100>; 293 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 294 }; 295 296 mop: mop@7c500000 { 297 compatible = "brcm,bcm2712-mop"; 298 reg = <0x7c500000 0x28>; 299 interrupt-parent = <&disp_intr>; 300 interrupts = <1>; 301 }; 302 303 moplet: moplet@7c501000 { 304 compatible = "brcm,bcm2712-moplet"; 305 reg = <0x7c501000 0x20>; 306 interrupt-parent = <&disp_intr>; 307 interrupts = <0>; 308 }; 309 310 disp_intr: interrupt-controller@7c502000 { 311 compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc"; 312 reg = <0x7c502000 0x30>; 313 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 314 interrupt-controller; 315 #interrupt-cells = <1>; 316 }; 317 318 dvp: clock@7c700000 { 319 compatible = "brcm,brcm2711-dvp"; 320 reg = <0x7c700000 0x10>; 321 clocks = <&clk_108MHz>; 322 #clock-cells = <1>; 323 #reset-cells = <1>; 324 }; 325 326 ddc0: i2c@7d508200 { 327 compatible = "brcm,brcmstb-i2c"; 328 reg = <0x7d508200 0x58>; 329 interrupt-parent = <&bsc_irq>; 330 interrupts = <1>; 331 clock-frequency = <97500>; 332 #address-cells = <1>; 333 #size-cells = <0>; 334 }; 335 336 ddc1: i2c@7d508280 { 337 compatible = "brcm,brcmstb-i2c"; 338 reg = <0x7d508280 0x58>; 339 interrupt-parent = <&bsc_irq>; 340 interrupts = <2>; 341 clock-frequency = <97500>; 342 #address-cells = <1>; 343 #size-cells = <0>; 344 }; 345 346 bsc_irq: interrupt-controller@7d508380 { 347 compatible = "brcm,bcm7271-l2-intc"; 348 reg = <0x7d508380 0x10>; 349 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 350 interrupt-controller; 351 #interrupt-cells = <1>; 352 }; 353 354 main_irq: interrupt-controller@7d508400 { 355 compatible = "brcm,bcm7271-l2-intc"; 356 reg = <0x7d508400 0x10>; 357 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 358 interrupt-controller; 359 #interrupt-cells = <1>; 360 }; 361 362 hdmi0: hdmi@7c701400 { 363 compatible = "brcm,bcm2712-hdmi0"; 364 reg = <0x7c701400 0x300>, 365 <0x7c701000 0x200>, 366 <0x7c701d00 0x300>, 367 <0x7c702000 0x80>, 368 <0x7c703800 0x200>, 369 <0x7c704000 0x800>, 370 <0x7c700100 0x80>, 371 <0x7d510800 0x100>, 372 <0x7c720000 0x100>; 373 reg-names = "hdmi", 374 "dvp", 375 "phy", 376 "rm", 377 "packet", 378 "metadata", 379 "csc", 380 "cec", 381 "hd"; 382 resets = <&dvp 1>; 383 interrupt-parent = <&aon_intr>; 384 interrupts = <1>, <2>, <3>, 385 <7>, <8>; 386 interrupt-names = "cec-tx", "cec-rx", "cec-low", 387 "hpd-connected", "hpd-removed"; 388 ddc = <&ddc0>; 389 }; 390 391 hdmi1: hdmi@7c706400 { 392 compatible = "brcm,bcm2712-hdmi1"; 393 reg = <0x7c706400 0x300>, 394 <0x7c706000 0x200>, 395 <0x7c706d00 0x300>, 396 <0x7c707000 0x80>, 397 <0x7c708800 0x200>, 398 <0x7c709000 0x800>, 399 <0x7c700180 0x80>, 400 <0x7d511000 0x100>, 401 <0x7c720000 0x100>; 402 reg-names = "hdmi", 403 "dvp", 404 "phy", 405 "rm", 406 "packet", 407 "metadata", 408 "csc", 409 "cec", 410 "hd"; 411 resets = <&dvp 2>; 412 interrupt-parent = <&aon_intr>; 413 interrupts = <11>, <12>, <13>, 414 <14>, <15>; 415 interrupt-names = "cec-tx", "cec-rx", "cec-low", 416 "hpd-connected", "hpd-removed"; 417 ddc = <&ddc1>; 418 }; 419 }; 420 421 axi: axi { 422 compatible = "simple-bus"; 423 #address-cells = <2>; 424 #size-cells = <2>; 425 426 ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>, 427 <0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>, 428 <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>, 429 <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>, 430 <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>; 431 432 dma-ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>, 433 <0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>, 434 <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>, 435 <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>, 436 <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>; 437 438 vc4: gpu { 439 compatible = "brcm,bcm2712-vc6"; 440 }; 441 442 pcie0: pcie@1000100000 { 443 compatible = "brcm,bcm2712-pcie"; 444 reg = <0x10 0x00100000 0x00 0x9310>; 445 device_type = "pci"; 446 linux,pci-domain = <0>; 447 max-link-speed = <2>; 448 num-lanes = <1>; 449 #address-cells = <3>; 450 #interrupt-cells = <1>; 451 #size-cells = <2>; 452 interrupt-parent = <&gicv2>; 453 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 455 interrupt-names = "pcie", "msi"; 456 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 457 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 458 <0 0 0 2 &gicv2 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 459 <0 0 0 3 &gicv2 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 460 <0 0 0 4 &gicv2 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 461 resets = <&pcie_rescal>, <&bcm_reset 42>; 462 reset-names = "rescal", "bridge"; 463 msi-controller; 464 msi-parent = <&pcie0>; 465 466 ranges = 467 /* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */ 468 <0x02000000 0x00 0x00000000 0x17 0x00000000 0x00 0xfffffffc>, 469 /* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */ 470 <0x43000000 0x04 0x00000000 0x14 0x00000000 0x03 0x00000000>; 471 472 dma-ranges = 473 /* 64GiB, 64-bit, prefetchable at PCIe 10_0000_0000 */ 474 <0x43000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>; 475 476 status = "disabled"; 477 }; 478 479 pcie1: pcie@1000110000 { 480 compatible = "brcm,bcm2712-pcie"; 481 reg = <0x10 0x00110000 0x00 0x9310>; 482 device_type = "pci"; 483 linux,pci-domain = <1>; 484 max-link-speed = <2>; 485 num-lanes = <1>; 486 #address-cells = <3>; 487 #interrupt-cells = <1>; 488 #size-cells = <2>; 489 interrupt-parent = <&gicv2>; 490 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 492 interrupt-names = "pcie", "msi"; 493 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 494 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 495 <0 0 0 2 &gicv2 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 496 <0 0 0 3 &gicv2 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 497 <0 0 0 4 &gicv2 GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 498 resets = <&pcie_rescal>, <&bcm_reset 43>; 499 reset-names = "rescal", "bridge"; 500 msi-controller; 501 msi-parent = <&mip1>; 502 503 ranges = 504 /* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */ 505 <0x02000000 0x00 0x00000000 0x1b 0x00000000 0x00 0xfffffffc>, 506 /* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */ 507 <0x43000000 0x04 0x00000000 0x18 0x00000000 0x03 0x00000000>; 508 509 dma-ranges = 510 /* 64GiB, 64-bit, non-prefetchable at PCIe 10_0000_0000 */ 511 <0x03000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>, 512 /* 4KiB, 64-bit, non-prefetchable at PCIe ff_ffff_f000 MIP1 */ 513 <0x03000000 0xff 0xfffff000 0x10 0x00131000 0x00 0x00001000>; 514 515 status = "disabled"; 516 }; 517 518 pcie2: pcie@1000120000 { 519 compatible = "brcm,bcm2712-pcie"; 520 reg = <0x10 0x00120000 0x00 0x9310>; 521 device_type = "pci"; 522 linux,pci-domain = <2>; 523 max-link-speed = <2>; 524 num-lanes = <4>; 525 #address-cells = <3>; 526 #interrupt-cells = <1>; 527 #size-cells = <2>; 528 interrupt-parent = <&gicv2>; 529 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 531 interrupt-names = "pcie", "msi"; 532 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 533 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 534 <0 0 0 2 &gicv2 GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 535 <0 0 0 3 &gicv2 GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 536 <0 0 0 4 &gicv2 GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 537 resets = <&pcie_rescal>, <&bcm_reset 44>; 538 reset-names = "rescal", "bridge"; 539 msi-controller; 540 msi-parent = <&mip0>; 541 542 ranges = 543 /* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */ 544 <0x02000000 0x00 0x00000000 0x1f 0x00000000 0x00 0xfffffffc>, 545 /* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */ 546 <0x43000000 0x04 0x00000000 0x1c 0x00000000 0x03 0x00000000>; 547 548 dma-ranges = 549 /* 4MiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */ 550 <0x02000000 0x00 0x00000000 0x1f 0x00000000 0x00 0x00400000>, 551 /* 64GiB, 64-bit, prefetchable at PCIe 10_0000_0000 */ 552 <0x43000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>, 553 /* 4KiB, 64-bit, non-prefetchable at PCIe ff_ffff_f000 MIP0 */ 554 <0x03000000 0xff 0xfffff000 0x10 0x00130000 0x00 0x00001000>; 555 556 status = "disabled"; 557 }; 558 559 mip0: msi-controller@1000130000 { 560 compatible = "brcm,bcm2712-mip"; 561 reg = <0x10 0x00130000 0x00 0xc0>, 562 <0xff 0xfffff000 0x00 0x1000>; 563 msi-controller; 564 msi-ranges = <&gicv2 GIC_SPI 128 IRQ_TYPE_EDGE_RISING 64>; 565 brcm,msi-offset = <0>; 566 }; 567 568 mip1: msi-controller@1000131000 { 569 compatible = "brcm,bcm2712-mip"; 570 reg = <0x10 0x00131000 0x00 0xc0>, 571 <0xff 0xfffff000 0x00 0x1000>; 572 msi-controller; 573 msi-ranges = <&gicv2 GIC_SPI 247 IRQ_TYPE_EDGE_RISING 8>; 574 brcm,msi-offset = <8>; 575 }; 576 }; 577 578 timer { 579 compatible = "arm,armv8-timer"; 580 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 581 IRQ_TYPE_LEVEL_LOW)>, 582 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 583 IRQ_TYPE_LEVEL_LOW)>, 584 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 585 IRQ_TYPE_LEVEL_LOW)>, 586 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 587 IRQ_TYPE_LEVEL_LOW)>, 588 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) | 589 IRQ_TYPE_LEVEL_LOW)>; 590 }; 591 592 clk_27MHz: clk-27M { 593 #clock-cells = <0>; 594 compatible = "fixed-clock"; 595 clock-frequency = <27000000>; 596 clock-output-names = "27MHz-clock"; 597 }; 598 599 clk_108MHz: clk-108M { 600 #clock-cells = <0>; 601 compatible = "fixed-clock"; 602 clock-frequency = <108000000>; 603 clock-output-names = "108MHz-clock"; 604 }; 605 606 hvs: hvs@107c580000 { 607 compatible = "brcm,bcm2712-hvs"; 608 reg = <0x10 0x7c580000 0x0 0x1a000>; 609 interrupt-parent = <&disp_intr>; 610 interrupts = <2>, <9>, <16>; 611 interrupt-names = "ch0-eof", "ch1-eof", "ch2-eof"; 612 }; 613}; 614