1/* 2 * B4860 Silicon/SoC Device Tree Source (pre include) 3 * 4 * Copyright 2012 - 2015 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/dts-v1/; 36 37/include/ "e6500_power_isa.dtsi" 38 39/ { 40 compatible = "fsl,B4860"; 41 #address-cells = <2>; 42 #size-cells = <2>; 43 interrupt-parent = <&mpic>; 44 45 aliases { 46 ccsr = &soc; 47 dcsr = &dcsr; 48 49 serial0 = &serial0; 50 serial1 = &serial1; 51 serial2 = &serial2; 52 serial3 = &serial3; 53 pci0 = &pci0; 54 usb0 = &usb0; 55 dma0 = &dma0; 56 dma1 = &dma1; 57 sdhc = &sdhc; 58 59 fman0 = &fman0; 60 ethernet0 = &enet0; 61 ethernet1 = &enet1; 62 ethernet2 = &enet2; 63 ethernet3 = &enet3; 64 ethernet4 = &enet4; 65 ethernet5 = &enet5; 66 ethernet6 = &enet6; 67 ethernet7 = &enet7; 68 }; 69 70 71 cpus { 72 #address-cells = <1>; 73 #size-cells = <0>; 74 75 cpu0: PowerPC,e6500@0 { 76 device_type = "cpu"; 77 reg = <0 1>; 78 clocks = <&clockgen 1 0>; 79 next-level-cache = <&L2_1>; 80 fsl,portid-mapping = <0x80000000>; 81 }; 82 cpu1: PowerPC,e6500@2 { 83 device_type = "cpu"; 84 reg = <2 3>; 85 clocks = <&clockgen 1 0>; 86 next-level-cache = <&L2_1>; 87 fsl,portid-mapping = <0x80000000>; 88 }; 89 cpu2: PowerPC,e6500@4 { 90 device_type = "cpu"; 91 reg = <4 5>; 92 clocks = <&clockgen 1 0>; 93 next-level-cache = <&L2_1>; 94 fsl,portid-mapping = <0x80000000>; 95 }; 96 cpu3: PowerPC,e6500@6 { 97 device_type = "cpu"; 98 reg = <6 7>; 99 clocks = <&clockgen 1 0>; 100 next-level-cache = <&L2_1>; 101 fsl,portid-mapping = <0x80000000>; 102 }; 103 }; 104}; 105