1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #ifndef __ARM64_KVM_ARM_H__ 8 #define __ARM64_KVM_ARM_H__ 9 10 #include <asm/esr.h> 11 #include <asm/memory.h> 12 #include <asm/sysreg.h> 13 #include <asm/types.h> 14 15 /* 16 * Because I'm terribly lazy and that repainting the whole of the KVM 17 * code with the proper names is a pain, use a helper to map the names 18 * inherited from AArch32 with the new fancy nomenclature. One day... 19 */ 20 #define __HCR(x) HCR_EL2_##x 21 22 #define HCR_TID5 __HCR(TID5) 23 #define HCR_DCT __HCR(DCT) 24 #define HCR_ATA_SHIFT __HCR(ATA_SHIFT) 25 #define HCR_ATA __HCR(ATA) 26 #define HCR_TTLBOS __HCR(TTLBOS) 27 #define HCR_TTLBIS __HCR(TTLBIS) 28 #define HCR_ENSCXT __HCR(EnSCXT) 29 #define HCR_TOCU __HCR(TOCU) 30 #define HCR_AMVOFFEN __HCR(AMVOFFEN) 31 #define HCR_TICAB __HCR(TICAB) 32 #define HCR_TID4 __HCR(TID4) 33 #define HCR_FIEN __HCR(FIEN) 34 #define HCR_FWB __HCR(FWB) 35 #define HCR_NV2 __HCR(NV2) 36 #define HCR_AT __HCR(AT) 37 #define HCR_NV1 __HCR(NV1) 38 #define HCR_NV __HCR(NV) 39 #define HCR_API __HCR(API) 40 #define HCR_APK __HCR(APK) 41 #define HCR_TEA __HCR(TEA) 42 #define HCR_TERR __HCR(TERR) 43 #define HCR_TLOR __HCR(TLOR) 44 #define HCR_E2H __HCR(E2H) 45 #define HCR_ID __HCR(ID) 46 #define HCR_CD __HCR(CD) 47 #define HCR_RW __HCR(RW) 48 #define HCR_TRVM __HCR(TRVM) 49 #define HCR_HCD __HCR(HCD) 50 #define HCR_TDZ __HCR(TDZ) 51 #define HCR_TGE __HCR(TGE) 52 #define HCR_TVM __HCR(TVM) 53 #define HCR_TTLB __HCR(TTLB) 54 #define HCR_TPU __HCR(TPU) 55 #define HCR_TPC __HCR(TPCP) 56 #define HCR_TSW __HCR(TSW) 57 #define HCR_TACR __HCR(TACR) 58 #define HCR_TIDCP __HCR(TIDCP) 59 #define HCR_TSC __HCR(TSC) 60 #define HCR_TID3 __HCR(TID3) 61 #define HCR_TID2 __HCR(TID2) 62 #define HCR_TID1 __HCR(TID1) 63 #define HCR_TID0 __HCR(TID0) 64 #define HCR_TWE __HCR(TWE) 65 #define HCR_TWI __HCR(TWI) 66 #define HCR_DC __HCR(DC) 67 #define HCR_BSU __HCR(BSU) 68 #define HCR_BSU_IS __HCR(BSU_IS) 69 #define HCR_FB __HCR(FB) 70 #define HCR_VSE __HCR(VSE) 71 #define HCR_VI __HCR(VI) 72 #define HCR_VF __HCR(VF) 73 #define HCR_AMO __HCR(AMO) 74 #define HCR_IMO __HCR(IMO) 75 #define HCR_FMO __HCR(FMO) 76 #define HCR_PTW __HCR(PTW) 77 #define HCR_SWIO __HCR(SWIO) 78 #define HCR_VM __HCR(VM) 79 80 /* 81 * The bits we set in HCR: 82 * TLOR: Trap LORegion register accesses 83 * RW: 64bit by default, can be overridden for 32bit VMs 84 * TACR: Trap ACTLR 85 * TSC: Trap SMC 86 * TSW: Trap cache operations by set/way 87 * TWE: Trap WFE 88 * TWI: Trap WFI 89 * TIDCP: Trap L2CTLR/L2ECTLR 90 * BSU_IS: Upgrade barriers to the inner shareable domain 91 * FB: Force broadcast of all maintenance operations 92 * AMO: Override CPSR.A and enable signaling with VA 93 * IMO: Override CPSR.I and enable signaling with VI 94 * FMO: Override CPSR.F and enable signaling with VF 95 * SWIO: Turn set/way invalidates into set/way clean+invalidate 96 * PTW: Take a stage2 fault if a stage1 walk steps in device memory 97 * TID3: Trap EL1 reads of group 3 ID registers 98 * TID1: Trap REVIDR_EL1, AIDR_EL1, and SMIDR_EL1 99 */ 100 #define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \ 101 HCR_BSU_IS | HCR_FB | HCR_TACR | \ 102 HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \ 103 HCR_FMO | HCR_IMO | HCR_PTW | HCR_TID3 | HCR_TID1) 104 #define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK | HCR_ATA) 105 #define HCR_HOST_NVHE_PROTECTED_FLAGS (HCR_HOST_NVHE_FLAGS | HCR_TSC) 106 #define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H | HCR_AMO | HCR_IMO | HCR_FMO) 107 108 #define MPAMHCR_HOST_FLAGS 0 109 110 /* TCR_EL2 Registers bits */ 111 #define TCR_EL2_DS (1UL << 32) 112 #define TCR_EL2_RES1 ((1U << 31) | (1 << 23)) 113 #define TCR_EL2_HPD (1 << 24) 114 #define TCR_EL2_TBI (1 << 20) 115 #define TCR_EL2_PS_SHIFT 16 116 #define TCR_EL2_PS_MASK (7 << TCR_EL2_PS_SHIFT) 117 #define TCR_EL2_PS_40B (2 << TCR_EL2_PS_SHIFT) 118 #define TCR_EL2_TG0_MASK TCR_TG0_MASK 119 #define TCR_EL2_SH0_MASK TCR_SH0_MASK 120 #define TCR_EL2_ORGN0_MASK TCR_ORGN0_MASK 121 #define TCR_EL2_IRGN0_MASK TCR_IRGN0_MASK 122 #define TCR_EL2_T0SZ_MASK 0x3f 123 #define TCR_EL2_MASK (TCR_EL2_TG0_MASK | TCR_EL2_SH0_MASK | \ 124 TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK) 125 126 /* VTCR_EL2 Registers bits */ 127 #define VTCR_EL2_DS TCR_EL2_DS 128 #define VTCR_EL2_RES1 (1U << 31) 129 #define VTCR_EL2_HD (1 << 22) 130 #define VTCR_EL2_HA (1 << 21) 131 #define VTCR_EL2_PS_SHIFT TCR_EL2_PS_SHIFT 132 #define VTCR_EL2_PS_MASK TCR_EL2_PS_MASK 133 #define VTCR_EL2_TG0_MASK TCR_TG0_MASK 134 #define VTCR_EL2_TG0_4K TCR_TG0_4K 135 #define VTCR_EL2_TG0_16K TCR_TG0_16K 136 #define VTCR_EL2_TG0_64K TCR_TG0_64K 137 #define VTCR_EL2_SH0_MASK TCR_SH0_MASK 138 #define VTCR_EL2_SH0_INNER TCR_SH0_INNER 139 #define VTCR_EL2_ORGN0_MASK TCR_ORGN0_MASK 140 #define VTCR_EL2_ORGN0_WBWA TCR_ORGN0_WBWA 141 #define VTCR_EL2_IRGN0_MASK TCR_IRGN0_MASK 142 #define VTCR_EL2_IRGN0_WBWA TCR_IRGN0_WBWA 143 #define VTCR_EL2_SL0_SHIFT 6 144 #define VTCR_EL2_SL0_MASK (3 << VTCR_EL2_SL0_SHIFT) 145 #define VTCR_EL2_T0SZ_MASK 0x3f 146 #define VTCR_EL2_VS_SHIFT 19 147 #define VTCR_EL2_VS_8BIT (0 << VTCR_EL2_VS_SHIFT) 148 #define VTCR_EL2_VS_16BIT (1 << VTCR_EL2_VS_SHIFT) 149 150 #define VTCR_EL2_T0SZ(x) TCR_T0SZ(x) 151 152 /* 153 * We configure the Stage-2 page tables to always restrict the IPA space to be 154 * 40 bits wide (T0SZ = 24). Systems with a PARange smaller than 40 bits are 155 * not known to exist and will break with this configuration. 156 * 157 * The VTCR_EL2 is configured per VM and is initialised in kvm_init_stage2_mmu. 158 * 159 * Note that when using 4K pages, we concatenate two first level page tables 160 * together. With 16K pages, we concatenate 16 first level page tables. 161 * 162 */ 163 164 #define VTCR_EL2_COMMON_BITS (VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \ 165 VTCR_EL2_IRGN0_WBWA | VTCR_EL2_RES1) 166 167 /* 168 * VTCR_EL2:SL0 indicates the entry level for Stage2 translation. 169 * Interestingly, it depends on the page size. 170 * See D.10.2.121, VTCR_EL2, in ARM DDI 0487C.a 171 * 172 * ----------------------------------------- 173 * | Entry level | 4K | 16K/64K | 174 * ------------------------------------------ 175 * | Level: 0 | 2 | - | 176 * ------------------------------------------ 177 * | Level: 1 | 1 | 2 | 178 * ------------------------------------------ 179 * | Level: 2 | 0 | 1 | 180 * ------------------------------------------ 181 * | Level: 3 | - | 0 | 182 * ------------------------------------------ 183 * 184 * The table roughly translates to : 185 * 186 * SL0(PAGE_SIZE, Entry_level) = TGRAN_SL0_BASE - Entry_Level 187 * 188 * Where TGRAN_SL0_BASE is a magic number depending on the page size: 189 * TGRAN_SL0_BASE(4K) = 2 190 * TGRAN_SL0_BASE(16K) = 3 191 * TGRAN_SL0_BASE(64K) = 3 192 * provided we take care of ruling out the unsupported cases and 193 * Entry_Level = 4 - Number_of_levels. 194 * 195 */ 196 #ifdef CONFIG_ARM64_64K_PAGES 197 198 #define VTCR_EL2_TGRAN VTCR_EL2_TG0_64K 199 #define VTCR_EL2_TGRAN_SL0_BASE 3UL 200 201 #elif defined(CONFIG_ARM64_16K_PAGES) 202 203 #define VTCR_EL2_TGRAN VTCR_EL2_TG0_16K 204 #define VTCR_EL2_TGRAN_SL0_BASE 3UL 205 206 #else /* 4K */ 207 208 #define VTCR_EL2_TGRAN VTCR_EL2_TG0_4K 209 #define VTCR_EL2_TGRAN_SL0_BASE 2UL 210 211 #endif 212 213 #define VTCR_EL2_LVLS_TO_SL0(levels) \ 214 ((VTCR_EL2_TGRAN_SL0_BASE - (4 - (levels))) << VTCR_EL2_SL0_SHIFT) 215 #define VTCR_EL2_SL0_TO_LVLS(sl0) \ 216 ((sl0) + 4 - VTCR_EL2_TGRAN_SL0_BASE) 217 #define VTCR_EL2_LVLS(vtcr) \ 218 VTCR_EL2_SL0_TO_LVLS(((vtcr) & VTCR_EL2_SL0_MASK) >> VTCR_EL2_SL0_SHIFT) 219 220 #define VTCR_EL2_FLAGS (VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN) 221 #define VTCR_EL2_IPA(vtcr) (64 - ((vtcr) & VTCR_EL2_T0SZ_MASK)) 222 223 /* 224 * ARM VMSAv8-64 defines an algorithm for finding the translation table 225 * descriptors in section D4.2.8 in ARM DDI 0487C.a. 226 * 227 * The algorithm defines the expectations on the translation table 228 * addresses for each level, based on PAGE_SIZE, entry level 229 * and the translation table size (T0SZ). The variable "x" in the 230 * algorithm determines the alignment of a table base address at a given 231 * level and thus determines the alignment of VTTBR:BADDR for stage2 232 * page table entry level. 233 * Since the number of bits resolved at the entry level could vary 234 * depending on the T0SZ, the value of "x" is defined based on a 235 * Magic constant for a given PAGE_SIZE and Entry Level. The 236 * intermediate levels must be always aligned to the PAGE_SIZE (i.e, 237 * x = PAGE_SHIFT). 238 * 239 * The value of "x" for entry level is calculated as : 240 * x = Magic_N - T0SZ 241 * 242 * where Magic_N is an integer depending on the page size and the entry 243 * level of the page table as below: 244 * 245 * -------------------------------------------- 246 * | Entry level | 4K 16K 64K | 247 * -------------------------------------------- 248 * | Level: 0 (4 levels) | 28 | - | - | 249 * -------------------------------------------- 250 * | Level: 1 (3 levels) | 37 | 31 | 25 | 251 * -------------------------------------------- 252 * | Level: 2 (2 levels) | 46 | 42 | 38 | 253 * -------------------------------------------- 254 * | Level: 3 (1 level) | - | 53 | 51 | 255 * -------------------------------------------- 256 * 257 * We have a magic formula for the Magic_N below: 258 * 259 * Magic_N(PAGE_SIZE, Level) = 64 - ((PAGE_SHIFT - 3) * Number_of_levels) 260 * 261 * where Number_of_levels = (4 - Level). We are only interested in the 262 * value for Entry_Level for the stage2 page table. 263 * 264 * So, given that T0SZ = (64 - IPA_SHIFT), we can compute 'x' as follows: 265 * 266 * x = (64 - ((PAGE_SHIFT - 3) * Number_of_levels)) - (64 - IPA_SHIFT) 267 * = IPA_SHIFT - ((PAGE_SHIFT - 3) * Number of levels) 268 * 269 * Here is one way to explain the Magic Formula: 270 * 271 * x = log2(Size_of_Entry_Level_Table) 272 * 273 * Since, we can resolve (PAGE_SHIFT - 3) bits at each level, and another 274 * PAGE_SHIFT bits in the PTE, we have : 275 * 276 * Bits_Entry_level = IPA_SHIFT - ((PAGE_SHIFT - 3) * (n - 1) + PAGE_SHIFT) 277 * = IPA_SHIFT - (PAGE_SHIFT - 3) * n - 3 278 * where n = number of levels, and since each pointer is 8bytes, we have: 279 * 280 * x = Bits_Entry_Level + 3 281 * = IPA_SHIFT - (PAGE_SHIFT - 3) * n 282 * 283 * The only constraint here is that, we have to find the number of page table 284 * levels for a given IPA size (which we do, see stage2_pt_levels()) 285 */ 286 #define ARM64_VTTBR_X(ipa, levels) ((ipa) - ((levels) * (PAGE_SHIFT - 3))) 287 288 #define VTTBR_CNP_BIT (UL(1)) 289 #define VTTBR_VMID_SHIFT (UL(48)) 290 #define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT) 291 292 /* Hyp System Trap Register */ 293 #define HSTR_EL2_T(x) (1 << x) 294 295 /* Hyp Coprocessor Trap Register Shifts */ 296 #define CPTR_EL2_TFP_SHIFT 10 297 298 /* Hyp Coprocessor Trap Register */ 299 #define CPTR_EL2_TCPAC (1U << 31) 300 #define CPTR_EL2_TAM (1 << 30) 301 #define CPTR_EL2_TTA (1 << 20) 302 #define CPTR_EL2_TSM (1 << 12) 303 #define CPTR_EL2_TFP (1 << CPTR_EL2_TFP_SHIFT) 304 #define CPTR_EL2_TZ (1 << 8) 305 #define CPTR_NVHE_EL2_RES1 (BIT(13) | BIT(9) | GENMASK(7, 0)) 306 #define CPTR_NVHE_EL2_RES0 (GENMASK(63, 32) | \ 307 GENMASK(29, 21) | \ 308 GENMASK(19, 14) | \ 309 BIT(11)) 310 311 #define CPTR_VHE_EL2_RES0 (GENMASK(63, 32) | \ 312 GENMASK(27, 26) | \ 313 GENMASK(23, 22) | \ 314 GENMASK(19, 18) | \ 315 GENMASK(15, 0)) 316 317 /* 318 * Polarity masks for HCRX_EL2, limited to the bits that we know about 319 * at this point in time. It doesn't mean that we actually *handle* 320 * them, but that at least those that are not advertised to a guest 321 * will be RES0 for that guest. 322 */ 323 #define __HCRX_EL2_MASK (BIT_ULL(6)) 324 #define __HCRX_EL2_nMASK (GENMASK_ULL(24, 14) | \ 325 GENMASK_ULL(11, 7) | \ 326 GENMASK_ULL(5, 0)) 327 #define __HCRX_EL2_RES0 ~(__HCRX_EL2_nMASK | __HCRX_EL2_MASK) 328 #define __HCRX_EL2_RES1 ~(__HCRX_EL2_nMASK | \ 329 __HCRX_EL2_MASK | \ 330 __HCRX_EL2_RES0) 331 332 /* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */ 333 #define HPFAR_MASK (~UL(0xf)) 334 /* 335 * We have 336 * PAR [PA_Shift - 1 : 12] = PA [PA_Shift - 1 : 12] 337 * HPFAR [PA_Shift - 9 : 4] = FIPA [PA_Shift - 1 : 12] 338 * 339 * Always assume 52 bit PA since at this point, we don't know how many PA bits 340 * the page table has been set up for. This should be safe since unused address 341 * bits in PAR are res0. 342 */ 343 #define PAR_TO_HPFAR(par) \ 344 (((par) & GENMASK_ULL(52 - 1, 12)) >> 8) 345 346 #define ECN(x) { ESR_ELx_EC_##x, #x } 347 348 #define kvm_arm_exception_class \ 349 ECN(UNKNOWN), ECN(WFx), ECN(CP15_32), ECN(CP15_64), ECN(CP14_MR), \ 350 ECN(CP14_LS), ECN(FP_ASIMD), ECN(CP10_ID), ECN(PAC), ECN(CP14_64), \ 351 ECN(SVC64), ECN(HVC64), ECN(SMC64), ECN(SYS64), ECN(SVE), \ 352 ECN(IMP_DEF), ECN(IABT_LOW), ECN(IABT_CUR), \ 353 ECN(PC_ALIGN), ECN(DABT_LOW), ECN(DABT_CUR), \ 354 ECN(SP_ALIGN), ECN(FP_EXC32), ECN(FP_EXC64), ECN(SERROR), \ 355 ECN(BREAKPT_LOW), ECN(BREAKPT_CUR), ECN(SOFTSTP_LOW), \ 356 ECN(SOFTSTP_CUR), ECN(WATCHPT_LOW), ECN(WATCHPT_CUR), \ 357 ECN(BKPT32), ECN(VECTOR32), ECN(BRK64), ECN(ERET) 358 359 #define kvm_mode_names \ 360 { PSR_MODE_EL0t, "EL0t" }, \ 361 { PSR_MODE_EL1t, "EL1t" }, \ 362 { PSR_MODE_EL1h, "EL1h" }, \ 363 { PSR_MODE_EL2t, "EL2t" }, \ 364 { PSR_MODE_EL2h, "EL2h" }, \ 365 { PSR_MODE_EL3t, "EL3t" }, \ 366 { PSR_MODE_EL3h, "EL3h" }, \ 367 { PSR_AA32_MODE_USR, "32-bit USR" }, \ 368 { PSR_AA32_MODE_FIQ, "32-bit FIQ" }, \ 369 { PSR_AA32_MODE_IRQ, "32-bit IRQ" }, \ 370 { PSR_AA32_MODE_SVC, "32-bit SVC" }, \ 371 { PSR_AA32_MODE_ABT, "32-bit ABT" }, \ 372 { PSR_AA32_MODE_HYP, "32-bit HYP" }, \ 373 { PSR_AA32_MODE_UND, "32-bit UND" }, \ 374 { PSR_AA32_MODE_SYS, "32-bit SYS" } 375 376 #endif /* __ARM64_KVM_ARM_H__ */ 377