1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree file for Marvell Armada AP807 Quad 4 * 5 * Copyright (C) 2019 Marvell Technology Group Ltd. 6 */ 7 8#include "armada-ap807.dtsi" 9 10/ { 11 cpus { 12 #address-cells = <1>; 13 #size-cells = <0>; 14 15 cpu0: cpu@0 { 16 device_type = "cpu"; 17 compatible = "arm,cortex-a72"; 18 reg = <0x000>; 19 enable-method = "psci"; 20 #cooling-cells = <2>; 21 clocks = <&cpu_clk 0>; 22 i-cache-size = <0xc000>; 23 i-cache-line-size = <64>; 24 i-cache-sets = <256>; 25 d-cache-size = <0x8000>; 26 d-cache-line-size = <64>; 27 d-cache-sets = <256>; 28 next-level-cache = <&l2_0>; 29 }; 30 cpu1: cpu@1 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a72"; 33 reg = <0x001>; 34 enable-method = "psci"; 35 #cooling-cells = <2>; 36 clocks = <&cpu_clk 0>; 37 i-cache-size = <0xc000>; 38 i-cache-line-size = <64>; 39 i-cache-sets = <256>; 40 d-cache-size = <0x8000>; 41 d-cache-line-size = <64>; 42 d-cache-sets = <256>; 43 next-level-cache = <&l2_0>; 44 }; 45 cpu2: cpu@100 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a72"; 48 reg = <0x100>; 49 enable-method = "psci"; 50 #cooling-cells = <2>; 51 clocks = <&cpu_clk 1>; 52 i-cache-size = <0xc000>; 53 i-cache-line-size = <64>; 54 i-cache-sets = <256>; 55 d-cache-size = <0x8000>; 56 d-cache-line-size = <64>; 57 d-cache-sets = <256>; 58 next-level-cache = <&l2_1>; 59 }; 60 cpu3: cpu@101 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a72"; 63 reg = <0x101>; 64 enable-method = "psci"; 65 #cooling-cells = <2>; 66 clocks = <&cpu_clk 1>; 67 i-cache-size = <0xc000>; 68 i-cache-line-size = <64>; 69 i-cache-sets = <256>; 70 d-cache-size = <0x8000>; 71 d-cache-line-size = <64>; 72 d-cache-sets = <256>; 73 next-level-cache = <&l2_1>; 74 }; 75 76 l2_0: l2-cache0 { 77 compatible = "cache"; 78 cache-size = <0x80000>; 79 cache-line-size = <64>; 80 cache-sets = <512>; 81 cache-level = <2>; 82 cache-unified; 83 }; 84 85 l2_1: l2-cache1 { 86 compatible = "cache"; 87 cache-size = <0x80000>; 88 cache-line-size = <64>; 89 cache-sets = <512>; 90 cache-level = <2>; 91 cache-unified; 92 }; 93 }; 94}; 95