xref: /linux/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi (revision 3fd6c59042dbba50391e30862beac979491145fe) 
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2UL SMARC SOM common parts
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
10#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
11
12/ {
13	aliases {
14		ethernet0 = &eth0;
15		ethernet1 = &eth1;
16	};
17
18	chosen {
19		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
20	};
21
22	memory@48000000 {
23		device_type = "memory";
24		/* first 128MB is reserved for secure area. */
25		reg = <0x0 0x48000000 0x0 0x38000000>;
26	};
27
28	reg_1p8v: regulator-1p8v {
29		compatible = "regulator-fixed";
30		regulator-name = "fixed-1.8V";
31		regulator-min-microvolt = <1800000>;
32		regulator-max-microvolt = <1800000>;
33		regulator-boot-on;
34		regulator-always-on;
35	};
36
37	reg_3p3v: regulator-3p3v {
38		compatible = "regulator-fixed";
39		regulator-name = "fixed-3.3V";
40		regulator-min-microvolt = <3300000>;
41		regulator-max-microvolt = <3300000>;
42		regulator-boot-on;
43		regulator-always-on;
44	};
45
46#if !(SW_SW0_DEV_SEL)
47	vccq_sdhi0: regulator-vccq-sdhi0 {
48		compatible = "regulator-gpio";
49
50		regulator-name = "SDHI0 VccQ";
51		regulator-min-microvolt = <1800000>;
52		regulator-max-microvolt = <3300000>;
53		states = <3300000 1>, <1800000 0>;
54		regulator-boot-on;
55		gpios = <&pinctrl RZG2L_GPIO(6, 2) GPIO_ACTIVE_HIGH>;
56		regulator-always-on;
57	};
58#endif
59};
60
61#if (SW_SW0_DEV_SEL)
62&adc {
63	pinctrl-0 = <&adc_pins>;
64	pinctrl-names = "default";
65	status = "okay";
66};
67#endif
68
69#if (!SW_ET0_EN_N)
70&eth0 {
71	pinctrl-0 = <&eth0_pins>;
72	pinctrl-names = "default";
73	phy-handle = <&phy0>;
74	phy-mode = "rgmii-id";
75	status = "okay";
76
77	phy0: ethernet-phy@7 {
78		compatible = "ethernet-phy-id0022.1640",
79			     "ethernet-phy-ieee802.3-c22";
80		reg = <7>;
81		interrupts-extended = <&irqc RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>;
82		rxc-skew-psec = <2400>;
83		txc-skew-psec = <2400>;
84		rxdv-skew-psec = <0>;
85		txen-skew-psec = <0>;
86		rxd0-skew-psec = <0>;
87		rxd1-skew-psec = <0>;
88		rxd2-skew-psec = <0>;
89		rxd3-skew-psec = <0>;
90		txd0-skew-psec = <0>;
91		txd1-skew-psec = <0>;
92		txd2-skew-psec = <0>;
93		txd3-skew-psec = <0>;
94	};
95};
96#endif
97
98&eth1 {
99	pinctrl-0 = <&eth1_pins>;
100	pinctrl-names = "default";
101	phy-handle = <&phy1>;
102	phy-mode = "rgmii-id";
103	status = "okay";
104
105	phy1: ethernet-phy@7 {
106		compatible = "ethernet-phy-id0022.1640",
107			     "ethernet-phy-ieee802.3-c22";
108		reg = <7>;
109		interrupts-extended = <&irqc RZG2L_IRQ7 IRQ_TYPE_LEVEL_LOW>;
110		rxc-skew-psec = <2400>;
111		txc-skew-psec = <2400>;
112		rxdv-skew-psec = <0>;
113		txen-skew-psec = <0>;
114		rxd0-skew-psec = <0>;
115		rxd1-skew-psec = <0>;
116		rxd2-skew-psec = <0>;
117		rxd3-skew-psec = <0>;
118		txd0-skew-psec = <0>;
119		txd1-skew-psec = <0>;
120		txd2-skew-psec = <0>;
121		txd3-skew-psec = <0>;
122	};
123};
124
125&extal_clk {
126	clock-frequency = <24000000>;
127};
128
129&ostm1 {
130	status = "okay";
131};
132
133&ostm2 {
134	status = "okay";
135};
136
137&pinctrl {
138	adc_pins: adc {
139		pinmux = <RZG2L_PORT_PINMUX(6, 2, 1)>; /* ADC_TRG */
140	};
141
142	eth0_pins: eth0 {
143		txc {
144			pinmux = <RZG2L_PORT_PINMUX(1, 0, 1)>; /* ET0_TXC */
145			power-source = <1800>;
146			output-enable;
147		};
148
149		mux {
150			pinmux = <RZG2L_PORT_PINMUX(4, 5, 1)>, /* ET0_LINKSTA */
151				 <RZG2L_PORT_PINMUX(4, 3, 1)>, /* ET0_MDC */
152				 <RZG2L_PORT_PINMUX(4, 4, 1)>, /* ET0_MDIO */
153				 <RZG2L_PORT_PINMUX(1, 1, 1)>, /* ET0_TX_CTL */
154				 <RZG2L_PORT_PINMUX(1, 2, 1)>, /* ET0_TXD0 */
155				 <RZG2L_PORT_PINMUX(1, 3, 1)>, /* ET0_TXD1 */
156				 <RZG2L_PORT_PINMUX(1, 4, 1)>, /* ET0_TXD2 */
157				 <RZG2L_PORT_PINMUX(2, 0, 1)>, /* ET0_TXD3 */
158				 <RZG2L_PORT_PINMUX(3, 0, 1)>, /* ET0_RXC */
159				 <RZG2L_PORT_PINMUX(3, 1, 1)>, /* ET0_RX_CTL */
160				 <RZG2L_PORT_PINMUX(3, 2, 1)>, /* ET0_RXD0 */
161				 <RZG2L_PORT_PINMUX(3, 3, 1)>, /* ET0_RXD1 */
162				 <RZG2L_PORT_PINMUX(4, 0, 1)>, /* ET0_RXD2 */
163				 <RZG2L_PORT_PINMUX(4, 1, 1)>; /* ET0_RXD3 */
164			power-source = <1800>;
165		};
166
167		irq {
168			pinmux = <RZG2L_PORT_PINMUX(5, 1, 7)>; /* IRQ2 */
169		};
170	};
171
172	eth1_pins: eth1 {
173		txc {
174			pinmux = <RZG2L_PORT_PINMUX(7, 0, 1)>; /* ET1_TXC */
175			power-source = <1800>;
176			output-enable;
177		};
178
179		mux {
180			pinmux = <RZG2L_PORT_PINMUX(10, 4, 1)>, /* ET1_LINKSTA */
181				 <RZG2L_PORT_PINMUX(10, 2, 1)>, /* ET1_MDC */
182				 <RZG2L_PORT_PINMUX(10, 3, 1)>, /* ET1_MDIO */
183				 <RZG2L_PORT_PINMUX(7, 1, 1)>, /* ET1_TX_CTL */
184				 <RZG2L_PORT_PINMUX(7, 2, 1)>, /* ET1_TXD0 */
185				 <RZG2L_PORT_PINMUX(7, 3, 1)>, /* ET1_TXD1 */
186				 <RZG2L_PORT_PINMUX(7, 4, 1)>, /* ET1_TXD2 */
187				 <RZG2L_PORT_PINMUX(8, 0, 1)>, /* ET1_TXD3 */
188				 <RZG2L_PORT_PINMUX(8, 4, 1)>, /* ET1_RXC */
189				 <RZG2L_PORT_PINMUX(9, 0, 1)>, /* ET1_RX_CTL */
190				 <RZG2L_PORT_PINMUX(9, 1, 1)>, /* ET1_RXD0 */
191				 <RZG2L_PORT_PINMUX(9, 2, 1)>, /* ET1_RXD1 */
192				 <RZG2L_PORT_PINMUX(9, 3, 1)>, /* ET1_RXD2 */
193				 <RZG2L_PORT_PINMUX(10, 0, 1)>; /* ET1_RXD3 */
194			power-source = <1800>;
195		};
196
197		irq {
198			pinmux = <RZG2L_PORT_PINMUX(18, 5, 1)>; /* IRQ7 */
199		};
200	};
201
202	qspi0_pins: qspi0 {
203		pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3",
204		       "QSPI0_SPCLK", "QSPI0_SSL";
205		power-source = <1800>;
206	};
207
208	sdhi0_emmc_pins: sd0emmc {
209		sd0_emmc_data {
210			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
211			       "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
212			power-source = <1800>;
213		};
214
215		sd0_emmc_ctrl {
216			pins = "SD0_CLK", "SD0_CMD";
217			power-source = <1800>;
218		};
219
220		sd0_emmc_rst {
221			pins = "SD0_RST#";
222			power-source = <1800>;
223		};
224	};
225
226	sdhi0_pins: sd0 {
227		sd0_data {
228			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
229			power-source = <3300>;
230		};
231
232		sd0_ctrl {
233			pins = "SD0_CLK", "SD0_CMD";
234			power-source = <3300>;
235		};
236
237		sd0_mux {
238			pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
239		};
240	};
241
242	sdhi0_pins_uhs: sd0_uhs {
243		sd0_data_uhs {
244			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
245			power-source = <1800>;
246		};
247
248		sd0_ctrl_uhs {
249			pins = "SD0_CLK", "SD0_CMD";
250			power-source = <1800>;
251		};
252
253		sd0_mux_uhs {
254			pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
255		};
256	};
257};
258
259&sbc {
260	pinctrl-0 = <&qspi0_pins>;
261	pinctrl-names = "default";
262	status = "okay";
263
264	flash@0 {
265		compatible = "jedec,spi-nor";
266		reg = <0>;
267		spi-max-frequency = <50000000>;
268		spi-tx-bus-width = <4>;
269		spi-rx-bus-width = <4>;
270
271		spi-cpol;
272		spi-cpha;
273		m25p,fast-read;
274
275		partitions {
276			compatible = "fixed-partitions";
277			#address-cells = <1>;
278			#size-cells = <1>;
279
280			partition@0 {
281				label = "bl2";
282				reg = <0x00000000 0x0001d000>;
283			};
284
285			partition@1d000 { /* fip is at offset 0x200 */
286				label = "fip";
287				reg = <0x0001d000 0x7e3000>;
288			};
289
290			partition@800000 {
291				label = "user";
292				reg = <0x800000 0x800000>;
293			};
294		};
295	};
296};
297
298#if (SW_SW0_DEV_SEL)
299&sdhi0 {
300	pinctrl-0 = <&sdhi0_emmc_pins>;
301	pinctrl-1 = <&sdhi0_emmc_pins>;
302	pinctrl-names = "default", "state_uhs";
303
304	vmmc-supply = <&reg_3p3v>;
305	vqmmc-supply = <&reg_1p8v>;
306	bus-width = <8>;
307	mmc-hs200-1_8v;
308	non-removable;
309	fixed-emmc-driver-type = <1>;
310	status = "okay";
311};
312#else
313&sdhi0 {
314	pinctrl-0 = <&sdhi0_pins>;
315	pinctrl-1 = <&sdhi0_pins_uhs>;
316	pinctrl-names = "default", "state_uhs";
317
318	vmmc-supply = <&reg_3p3v>;
319	vqmmc-supply = <&vccq_sdhi0>;
320	bus-width = <4>;
321	sd-uhs-sdr50;
322	sd-uhs-sdr104;
323	status = "okay";
324};
325#endif
326
327&wdt0 {
328	status = "okay";
329	timeout-sec = <60>;
330};
331