xref: /linux/arch/mips/kernel/asm-offsets.c (revision 6c7340a7a8d2b6ecad1ad108f6daa73ba1dc082f) 
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * asm-offsets.c: Calculate pt_regs and task_struct offsets.
4  *
5  * Copyright (C) 1996 David S. Miller
6  * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003 Ralf Baechle
7  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8  *
9  * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10  * Copyright (C) 2000 MIPS Technologies, Inc.
11  */
12 #define COMPILE_OFFSETS
13 
14 #include <linux/compat.h>
15 #include <linux/types.h>
16 #include <linux/sched.h>
17 #include <linux/mm.h>
18 #include <linux/kbuild.h>
19 #include <linux/suspend.h>
20 #include <asm/cpu-info.h>
21 #include <asm/pm.h>
22 #include <asm/ptrace.h>
23 #include <asm/processor.h>
24 #include <asm/smp-cps.h>
25 
26 #include <linux/kvm_host.h>
27 
28 void output_ptreg_defines(void);
output_ptreg_defines(void)29 void output_ptreg_defines(void)
30 {
31 	COMMENT("MIPS pt_regs offsets.");
32 #ifdef CONFIG_32BIT
33 	OFFSET(PT_ARG4, pt_regs, args[4]);
34 	OFFSET(PT_ARG5, pt_regs, args[5]);
35 	OFFSET(PT_ARG6, pt_regs, args[6]);
36 	OFFSET(PT_ARG7, pt_regs, args[7]);
37 #endif
38 	OFFSET(PT_R0, pt_regs, regs[0]);
39 	OFFSET(PT_R1, pt_regs, regs[1]);
40 	OFFSET(PT_R2, pt_regs, regs[2]);
41 	OFFSET(PT_R3, pt_regs, regs[3]);
42 	OFFSET(PT_R4, pt_regs, regs[4]);
43 	OFFSET(PT_R5, pt_regs, regs[5]);
44 	OFFSET(PT_R6, pt_regs, regs[6]);
45 	OFFSET(PT_R7, pt_regs, regs[7]);
46 	OFFSET(PT_R8, pt_regs, regs[8]);
47 	OFFSET(PT_R9, pt_regs, regs[9]);
48 	OFFSET(PT_R10, pt_regs, regs[10]);
49 	OFFSET(PT_R11, pt_regs, regs[11]);
50 	OFFSET(PT_R12, pt_regs, regs[12]);
51 	OFFSET(PT_R13, pt_regs, regs[13]);
52 	OFFSET(PT_R14, pt_regs, regs[14]);
53 	OFFSET(PT_R15, pt_regs, regs[15]);
54 	OFFSET(PT_R16, pt_regs, regs[16]);
55 	OFFSET(PT_R17, pt_regs, regs[17]);
56 	OFFSET(PT_R18, pt_regs, regs[18]);
57 	OFFSET(PT_R19, pt_regs, regs[19]);
58 	OFFSET(PT_R20, pt_regs, regs[20]);
59 	OFFSET(PT_R21, pt_regs, regs[21]);
60 	OFFSET(PT_R22, pt_regs, regs[22]);
61 	OFFSET(PT_R23, pt_regs, regs[23]);
62 	OFFSET(PT_R24, pt_regs, regs[24]);
63 	OFFSET(PT_R25, pt_regs, regs[25]);
64 	OFFSET(PT_R26, pt_regs, regs[26]);
65 	OFFSET(PT_R27, pt_regs, regs[27]);
66 	OFFSET(PT_R28, pt_regs, regs[28]);
67 	OFFSET(PT_R29, pt_regs, regs[29]);
68 	OFFSET(PT_R30, pt_regs, regs[30]);
69 	OFFSET(PT_R31, pt_regs, regs[31]);
70 	OFFSET(PT_LO, pt_regs, lo);
71 	OFFSET(PT_HI, pt_regs, hi);
72 #ifdef CONFIG_CPU_HAS_SMARTMIPS
73 	OFFSET(PT_ACX, pt_regs, acx);
74 #endif
75 	OFFSET(PT_EPC, pt_regs, cp0_epc);
76 	OFFSET(PT_BVADDR, pt_regs, cp0_badvaddr);
77 	OFFSET(PT_STATUS, pt_regs, cp0_status);
78 	OFFSET(PT_CAUSE, pt_regs, cp0_cause);
79 #ifdef CONFIG_CPU_CAVIUM_OCTEON
80 	OFFSET(PT_MPL, pt_regs, mpl);
81 	OFFSET(PT_MTP, pt_regs, mtp);
82 #endif /* CONFIG_CPU_CAVIUM_OCTEON */
83 	DEFINE(PT_SIZE, sizeof(struct pt_regs));
84 	BLANK();
85 }
86 
87 void output_task_defines(void);
output_task_defines(void)88 void output_task_defines(void)
89 {
90 	COMMENT("MIPS task_struct offsets.");
91 	OFFSET(TASK_THREAD_INFO, task_struct, stack);
92 	OFFSET(TASK_FLAGS, task_struct, flags);
93 	OFFSET(TASK_MM, task_struct, mm);
94 	OFFSET(TASK_PID, task_struct, pid);
95 #if defined(CONFIG_STACKPROTECTOR)
96 	OFFSET(TASK_STACK_CANARY, task_struct, stack_canary);
97 #endif
98 	DEFINE(TASK_STRUCT_SIZE, sizeof(struct task_struct));
99 	BLANK();
100 }
101 
102 void output_thread_info_defines(void);
output_thread_info_defines(void)103 void output_thread_info_defines(void)
104 {
105 	COMMENT("MIPS thread_info offsets.");
106 	OFFSET(TI_TASK, thread_info, task);
107 	OFFSET(TI_FLAGS, thread_info, flags);
108 	OFFSET(TI_TP_VALUE, thread_info, tp_value);
109 	OFFSET(TI_CPU, thread_info, cpu);
110 	OFFSET(TI_PRE_COUNT, thread_info, preempt_count);
111 	OFFSET(TI_REGS, thread_info, regs);
112 	OFFSET(TI_SYSCALL, thread_info, syscall);
113 	DEFINE(_THREAD_SIZE, THREAD_SIZE);
114 	DEFINE(_THREAD_MASK, THREAD_MASK);
115 	DEFINE(_IRQ_STACK_SIZE, IRQ_STACK_SIZE);
116 	DEFINE(_IRQ_STACK_START, IRQ_STACK_START);
117 	BLANK();
118 }
119 
120 void output_thread_defines(void);
output_thread_defines(void)121 void output_thread_defines(void)
122 {
123 	COMMENT("MIPS specific thread_struct offsets.");
124 	OFFSET(THREAD_REG16, task_struct, thread.reg16);
125 	OFFSET(THREAD_REG17, task_struct, thread.reg17);
126 	OFFSET(THREAD_REG18, task_struct, thread.reg18);
127 	OFFSET(THREAD_REG19, task_struct, thread.reg19);
128 	OFFSET(THREAD_REG20, task_struct, thread.reg20);
129 	OFFSET(THREAD_REG21, task_struct, thread.reg21);
130 	OFFSET(THREAD_REG22, task_struct, thread.reg22);
131 	OFFSET(THREAD_REG23, task_struct, thread.reg23);
132 	OFFSET(THREAD_REG29, task_struct, thread.reg29);
133 	OFFSET(THREAD_REG30, task_struct, thread.reg30);
134 	OFFSET(THREAD_REG31, task_struct, thread.reg31);
135 	OFFSET(THREAD_STATUS, task_struct,
136 	       thread.cp0_status);
137 
138 	OFFSET(THREAD_BVADDR, task_struct, \
139 	       thread.cp0_badvaddr);
140 	OFFSET(THREAD_BUADDR, task_struct, \
141 	       thread.cp0_baduaddr);
142 	OFFSET(THREAD_ECODE, task_struct, \
143 	       thread.error_code);
144 	OFFSET(THREAD_TRAPNO, task_struct, thread.trap_nr);
145 	BLANK();
146 }
147 
148 #ifdef CONFIG_MIPS_FP_SUPPORT
149 void output_thread_fpu_defines(void);
output_thread_fpu_defines(void)150 void output_thread_fpu_defines(void)
151 {
152 	OFFSET(THREAD_FPU, task_struct, thread.fpu);
153 
154 	OFFSET(THREAD_FPR0, task_struct, thread.fpu.fpr[0]);
155 	OFFSET(THREAD_FPR1, task_struct, thread.fpu.fpr[1]);
156 	OFFSET(THREAD_FPR2, task_struct, thread.fpu.fpr[2]);
157 	OFFSET(THREAD_FPR3, task_struct, thread.fpu.fpr[3]);
158 	OFFSET(THREAD_FPR4, task_struct, thread.fpu.fpr[4]);
159 	OFFSET(THREAD_FPR5, task_struct, thread.fpu.fpr[5]);
160 	OFFSET(THREAD_FPR6, task_struct, thread.fpu.fpr[6]);
161 	OFFSET(THREAD_FPR7, task_struct, thread.fpu.fpr[7]);
162 	OFFSET(THREAD_FPR8, task_struct, thread.fpu.fpr[8]);
163 	OFFSET(THREAD_FPR9, task_struct, thread.fpu.fpr[9]);
164 	OFFSET(THREAD_FPR10, task_struct, thread.fpu.fpr[10]);
165 	OFFSET(THREAD_FPR11, task_struct, thread.fpu.fpr[11]);
166 	OFFSET(THREAD_FPR12, task_struct, thread.fpu.fpr[12]);
167 	OFFSET(THREAD_FPR13, task_struct, thread.fpu.fpr[13]);
168 	OFFSET(THREAD_FPR14, task_struct, thread.fpu.fpr[14]);
169 	OFFSET(THREAD_FPR15, task_struct, thread.fpu.fpr[15]);
170 	OFFSET(THREAD_FPR16, task_struct, thread.fpu.fpr[16]);
171 	OFFSET(THREAD_FPR17, task_struct, thread.fpu.fpr[17]);
172 	OFFSET(THREAD_FPR18, task_struct, thread.fpu.fpr[18]);
173 	OFFSET(THREAD_FPR19, task_struct, thread.fpu.fpr[19]);
174 	OFFSET(THREAD_FPR20, task_struct, thread.fpu.fpr[20]);
175 	OFFSET(THREAD_FPR21, task_struct, thread.fpu.fpr[21]);
176 	OFFSET(THREAD_FPR22, task_struct, thread.fpu.fpr[22]);
177 	OFFSET(THREAD_FPR23, task_struct, thread.fpu.fpr[23]);
178 	OFFSET(THREAD_FPR24, task_struct, thread.fpu.fpr[24]);
179 	OFFSET(THREAD_FPR25, task_struct, thread.fpu.fpr[25]);
180 	OFFSET(THREAD_FPR26, task_struct, thread.fpu.fpr[26]);
181 	OFFSET(THREAD_FPR27, task_struct, thread.fpu.fpr[27]);
182 	OFFSET(THREAD_FPR28, task_struct, thread.fpu.fpr[28]);
183 	OFFSET(THREAD_FPR29, task_struct, thread.fpu.fpr[29]);
184 	OFFSET(THREAD_FPR30, task_struct, thread.fpu.fpr[30]);
185 	OFFSET(THREAD_FPR31, task_struct, thread.fpu.fpr[31]);
186 
187 	OFFSET(THREAD_FCR31, task_struct, thread.fpu.fcr31);
188 	OFFSET(THREAD_MSA_CSR, task_struct, thread.fpu.msacsr);
189 	BLANK();
190 }
191 #endif
192 
193 void output_mm_defines(void);
output_mm_defines(void)194 void output_mm_defines(void)
195 {
196 	COMMENT("Size of struct page");
197 	DEFINE(STRUCT_PAGE_SIZE, sizeof(struct page));
198 	BLANK();
199 	COMMENT("Linux mm_struct offsets.");
200 	OFFSET(MM_USERS, mm_struct, mm_users);
201 	OFFSET(MM_PGD, mm_struct, pgd);
202 	OFFSET(MM_CONTEXT, mm_struct, context);
203 	BLANK();
204 	DEFINE(_PGD_T_SIZE, sizeof(pgd_t));
205 	DEFINE(_PMD_T_SIZE, sizeof(pmd_t));
206 	DEFINE(_PTE_T_SIZE, sizeof(pte_t));
207 	BLANK();
208 	DEFINE(_PGD_T_LOG2, PGD_T_LOG2);
209 #ifndef __PAGETABLE_PMD_FOLDED
210 	DEFINE(_PMD_T_LOG2, PMD_T_LOG2);
211 #endif
212 	DEFINE(_PTE_T_LOG2, PTE_T_LOG2);
213 	BLANK();
214 	BLANK();
215 	DEFINE(_PMD_SHIFT, PMD_SHIFT);
216 	DEFINE(_PGDIR_SHIFT, PGDIR_SHIFT);
217 	BLANK();
218 	DEFINE(_PTRS_PER_PGD, PTRS_PER_PGD);
219 	DEFINE(_PTRS_PER_PMD, PTRS_PER_PMD);
220 	DEFINE(_PTRS_PER_PTE, PTRS_PER_PTE);
221 	BLANK();
222 	DEFINE(_PAGE_SHIFT, PAGE_SHIFT);
223 	DEFINE(_PAGE_SIZE, PAGE_SIZE);
224 	BLANK();
225 }
226 
227 #ifdef CONFIG_32BIT
228 void output_sc_defines(void);
output_sc_defines(void)229 void output_sc_defines(void)
230 {
231 	COMMENT("Linux sigcontext offsets.");
232 	OFFSET(SC_REGS, sigcontext, sc_regs);
233 	OFFSET(SC_FPREGS, sigcontext, sc_fpregs);
234 	OFFSET(SC_ACX, sigcontext, sc_acx);
235 	OFFSET(SC_MDHI, sigcontext, sc_mdhi);
236 	OFFSET(SC_MDLO, sigcontext, sc_mdlo);
237 	OFFSET(SC_PC, sigcontext, sc_pc);
238 	OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr);
239 	OFFSET(SC_FPC_EIR, sigcontext, sc_fpc_eir);
240 	OFFSET(SC_HI1, sigcontext, sc_hi1);
241 	OFFSET(SC_LO1, sigcontext, sc_lo1);
242 	OFFSET(SC_HI2, sigcontext, sc_hi2);
243 	OFFSET(SC_LO2, sigcontext, sc_lo2);
244 	OFFSET(SC_HI3, sigcontext, sc_hi3);
245 	OFFSET(SC_LO3, sigcontext, sc_lo3);
246 	BLANK();
247 }
248 #endif
249 
250 #ifdef CONFIG_64BIT
251 void output_sc_defines(void);
output_sc_defines(void)252 void output_sc_defines(void)
253 {
254 	COMMENT("Linux sigcontext offsets.");
255 	OFFSET(SC_REGS, sigcontext, sc_regs);
256 	OFFSET(SC_FPREGS, sigcontext, sc_fpregs);
257 	OFFSET(SC_MDHI, sigcontext, sc_mdhi);
258 	OFFSET(SC_MDLO, sigcontext, sc_mdlo);
259 	OFFSET(SC_PC, sigcontext, sc_pc);
260 	OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr);
261 	BLANK();
262 }
263 #endif
264 
265 void output_signal_defined(void);
output_signal_defined(void)266 void output_signal_defined(void)
267 {
268 	COMMENT("Linux signal numbers.");
269 	DEFINE(_SIGHUP, SIGHUP);
270 	DEFINE(_SIGINT, SIGINT);
271 	DEFINE(_SIGQUIT, SIGQUIT);
272 	DEFINE(_SIGILL, SIGILL);
273 	DEFINE(_SIGTRAP, SIGTRAP);
274 	DEFINE(_SIGIOT, SIGIOT);
275 	DEFINE(_SIGABRT, SIGABRT);
276 	DEFINE(_SIGEMT, SIGEMT);
277 	DEFINE(_SIGFPE, SIGFPE);
278 	DEFINE(_SIGKILL, SIGKILL);
279 	DEFINE(_SIGBUS, SIGBUS);
280 	DEFINE(_SIGSEGV, SIGSEGV);
281 	DEFINE(_SIGSYS, SIGSYS);
282 	DEFINE(_SIGPIPE, SIGPIPE);
283 	DEFINE(_SIGALRM, SIGALRM);
284 	DEFINE(_SIGTERM, SIGTERM);
285 	DEFINE(_SIGUSR1, SIGUSR1);
286 	DEFINE(_SIGUSR2, SIGUSR2);
287 	DEFINE(_SIGCHLD, SIGCHLD);
288 	DEFINE(_SIGPWR, SIGPWR);
289 	DEFINE(_SIGWINCH, SIGWINCH);
290 	DEFINE(_SIGURG, SIGURG);
291 	DEFINE(_SIGIO, SIGIO);
292 	DEFINE(_SIGSTOP, SIGSTOP);
293 	DEFINE(_SIGTSTP, SIGTSTP);
294 	DEFINE(_SIGCONT, SIGCONT);
295 	DEFINE(_SIGTTIN, SIGTTIN);
296 	DEFINE(_SIGTTOU, SIGTTOU);
297 	DEFINE(_SIGVTALRM, SIGVTALRM);
298 	DEFINE(_SIGPROF, SIGPROF);
299 	DEFINE(_SIGXCPU, SIGXCPU);
300 	DEFINE(_SIGXFSZ, SIGXFSZ);
301 	BLANK();
302 }
303 
304 #ifdef CONFIG_CPU_CAVIUM_OCTEON
305 void output_octeon_cop2_state_defines(void);
output_octeon_cop2_state_defines(void)306 void output_octeon_cop2_state_defines(void)
307 {
308 	COMMENT("Octeon specific octeon_cop2_state offsets.");
309 	OFFSET(OCTEON_CP2_CRC_IV,	octeon_cop2_state, cop2_crc_iv);
310 	OFFSET(OCTEON_CP2_CRC_LENGTH,	octeon_cop2_state, cop2_crc_length);
311 	OFFSET(OCTEON_CP2_CRC_POLY,	octeon_cop2_state, cop2_crc_poly);
312 	OFFSET(OCTEON_CP2_LLM_DAT,	octeon_cop2_state, cop2_llm_dat);
313 	OFFSET(OCTEON_CP2_3DES_IV,	octeon_cop2_state, cop2_3des_iv);
314 	OFFSET(OCTEON_CP2_3DES_KEY,	octeon_cop2_state, cop2_3des_key);
315 	OFFSET(OCTEON_CP2_3DES_RESULT,	octeon_cop2_state, cop2_3des_result);
316 	OFFSET(OCTEON_CP2_AES_INP0,	octeon_cop2_state, cop2_aes_inp0);
317 	OFFSET(OCTEON_CP2_AES_IV,	octeon_cop2_state, cop2_aes_iv);
318 	OFFSET(OCTEON_CP2_AES_KEY,	octeon_cop2_state, cop2_aes_key);
319 	OFFSET(OCTEON_CP2_AES_KEYLEN,	octeon_cop2_state, cop2_aes_keylen);
320 	OFFSET(OCTEON_CP2_AES_RESULT,	octeon_cop2_state, cop2_aes_result);
321 	OFFSET(OCTEON_CP2_GFM_MULT,	octeon_cop2_state, cop2_gfm_mult);
322 	OFFSET(OCTEON_CP2_GFM_POLY,	octeon_cop2_state, cop2_gfm_poly);
323 	OFFSET(OCTEON_CP2_GFM_RESULT,	octeon_cop2_state, cop2_gfm_result);
324 	OFFSET(OCTEON_CP2_HSH_DATW,	octeon_cop2_state, cop2_hsh_datw);
325 	OFFSET(OCTEON_CP2_HSH_IVW,	octeon_cop2_state, cop2_hsh_ivw);
326 	OFFSET(OCTEON_CP2_SHA3,		octeon_cop2_state, cop2_sha3);
327 	OFFSET(THREAD_CP2,	task_struct, thread.cp2);
328 #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \
329     CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
330 	OFFSET(THREAD_CVMSEG,	task_struct, thread.cvmseg.cvmseg);
331 #endif
332 	BLANK();
333 }
334 #endif
335 
336 #ifdef CONFIG_HIBERNATION
337 void output_pbe_defines(void);
output_pbe_defines(void)338 void output_pbe_defines(void)
339 {
340 	COMMENT(" Linux struct pbe offsets. ");
341 	OFFSET(PBE_ADDRESS, pbe, address);
342 	OFFSET(PBE_ORIG_ADDRESS, pbe, orig_address);
343 	OFFSET(PBE_NEXT, pbe, next);
344 	DEFINE(PBE_SIZE, sizeof(struct pbe));
345 	BLANK();
346 }
347 #endif
348 
349 #ifdef CONFIG_CPU_PM
350 void output_pm_defines(void);
output_pm_defines(void)351 void output_pm_defines(void)
352 {
353 	COMMENT(" PM offsets. ");
354 #ifdef CONFIG_EVA
355 	OFFSET(SSS_SEGCTL0,	mips_static_suspend_state, segctl[0]);
356 	OFFSET(SSS_SEGCTL1,	mips_static_suspend_state, segctl[1]);
357 	OFFSET(SSS_SEGCTL2,	mips_static_suspend_state, segctl[2]);
358 #endif
359 	OFFSET(SSS_SP,		mips_static_suspend_state, sp);
360 	BLANK();
361 }
362 #endif
363 
364 #ifdef CONFIG_MIPS_FP_SUPPORT
365 void output_kvm_defines(void);
output_kvm_defines(void)366 void output_kvm_defines(void)
367 {
368 	COMMENT(" KVM/MIPS Specific offsets. ");
369 
370 	OFFSET(VCPU_FPR0, kvm_vcpu_arch, fpu.fpr[0]);
371 	OFFSET(VCPU_FPR1, kvm_vcpu_arch, fpu.fpr[1]);
372 	OFFSET(VCPU_FPR2, kvm_vcpu_arch, fpu.fpr[2]);
373 	OFFSET(VCPU_FPR3, kvm_vcpu_arch, fpu.fpr[3]);
374 	OFFSET(VCPU_FPR4, kvm_vcpu_arch, fpu.fpr[4]);
375 	OFFSET(VCPU_FPR5, kvm_vcpu_arch, fpu.fpr[5]);
376 	OFFSET(VCPU_FPR6, kvm_vcpu_arch, fpu.fpr[6]);
377 	OFFSET(VCPU_FPR7, kvm_vcpu_arch, fpu.fpr[7]);
378 	OFFSET(VCPU_FPR8, kvm_vcpu_arch, fpu.fpr[8]);
379 	OFFSET(VCPU_FPR9, kvm_vcpu_arch, fpu.fpr[9]);
380 	OFFSET(VCPU_FPR10, kvm_vcpu_arch, fpu.fpr[10]);
381 	OFFSET(VCPU_FPR11, kvm_vcpu_arch, fpu.fpr[11]);
382 	OFFSET(VCPU_FPR12, kvm_vcpu_arch, fpu.fpr[12]);
383 	OFFSET(VCPU_FPR13, kvm_vcpu_arch, fpu.fpr[13]);
384 	OFFSET(VCPU_FPR14, kvm_vcpu_arch, fpu.fpr[14]);
385 	OFFSET(VCPU_FPR15, kvm_vcpu_arch, fpu.fpr[15]);
386 	OFFSET(VCPU_FPR16, kvm_vcpu_arch, fpu.fpr[16]);
387 	OFFSET(VCPU_FPR17, kvm_vcpu_arch, fpu.fpr[17]);
388 	OFFSET(VCPU_FPR18, kvm_vcpu_arch, fpu.fpr[18]);
389 	OFFSET(VCPU_FPR19, kvm_vcpu_arch, fpu.fpr[19]);
390 	OFFSET(VCPU_FPR20, kvm_vcpu_arch, fpu.fpr[20]);
391 	OFFSET(VCPU_FPR21, kvm_vcpu_arch, fpu.fpr[21]);
392 	OFFSET(VCPU_FPR22, kvm_vcpu_arch, fpu.fpr[22]);
393 	OFFSET(VCPU_FPR23, kvm_vcpu_arch, fpu.fpr[23]);
394 	OFFSET(VCPU_FPR24, kvm_vcpu_arch, fpu.fpr[24]);
395 	OFFSET(VCPU_FPR25, kvm_vcpu_arch, fpu.fpr[25]);
396 	OFFSET(VCPU_FPR26, kvm_vcpu_arch, fpu.fpr[26]);
397 	OFFSET(VCPU_FPR27, kvm_vcpu_arch, fpu.fpr[27]);
398 	OFFSET(VCPU_FPR28, kvm_vcpu_arch, fpu.fpr[28]);
399 	OFFSET(VCPU_FPR29, kvm_vcpu_arch, fpu.fpr[29]);
400 	OFFSET(VCPU_FPR30, kvm_vcpu_arch, fpu.fpr[30]);
401 	OFFSET(VCPU_FPR31, kvm_vcpu_arch, fpu.fpr[31]);
402 
403 	OFFSET(VCPU_FCR31, kvm_vcpu_arch, fpu.fcr31);
404 	OFFSET(VCPU_MSA_CSR, kvm_vcpu_arch, fpu.msacsr);
405 	BLANK();
406 }
407 #endif
408 
409 #ifdef CONFIG_MIPS_CPS
410 void output_cps_defines(void);
output_cps_defines(void)411 void output_cps_defines(void)
412 {
413 	COMMENT(" MIPS CPS offsets. ");
414 
415 	OFFSET(CLUSTERBOOTCFG_CORECONFIG, cluster_boot_config, core_config);
416 	DEFINE(CLUSTERBOOTCFG_SIZE, sizeof(struct cluster_boot_config));
417 
418 	OFFSET(COREBOOTCFG_VPEMASK, core_boot_config, vpe_mask);
419 	OFFSET(COREBOOTCFG_VPECONFIG, core_boot_config, vpe_config);
420 	DEFINE(COREBOOTCFG_SIZE, sizeof(struct core_boot_config));
421 
422 	OFFSET(VPEBOOTCFG_PC, vpe_boot_config, pc);
423 	OFFSET(VPEBOOTCFG_SP, vpe_boot_config, sp);
424 	OFFSET(VPEBOOTCFG_GP, vpe_boot_config, gp);
425 	DEFINE(VPEBOOTCFG_SIZE, sizeof(struct vpe_boot_config));
426 }
427 #endif
428