xref: /linux/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts (revision 0cac5ce06e524755b3dac1e0a060b05992076d93) 
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2022, Intel Corporation
4 */
5
6#include "socfpga_stratix10.dtsi"
7
8/ {
9	model = "SOCFPGA Stratix 10 SWVP";
10	compatible = "altr,socfpga-stratix10-swvp", "altr,socfpga-stratix10";
11
12	aliases {
13		serial0 = &uart0;
14		serial1 = &uart1;
15
16		timer0 = &timer0;
17		timer1 = &timer1;
18		timer2 = &timer2;
19		timer3 = &timer3;
20
21		ethernet0 = &gmac0;
22		ethernet1 = &gmac1;
23		ethernet2 = &gmac2;
24	};
25
26	chosen {
27		stdout-path = "serial1:115200n8";
28		linux,initrd-start = <0x10000000>;
29		linux,initrd-end = <0x125c8324>;
30	};
31
32	memory@80000000 {
33		device_type = "memory";
34		reg = <0x0 0x0 0x0 0x80000000>;
35	};
36};
37
38&cpu0 {
39	enable-method = "spin-table";
40	cpu-release-addr = <0x0 0x0000fff8>;
41};
42
43&cpu1 {
44	enable-method = "spin-table";
45	cpu-release-addr = <0x0 0x0000fff8>;
46};
47
48&cpu2 {
49	enable-method = "spin-table";
50	cpu-release-addr = <0x0 0x0000fff8>;
51};
52
53&cpu3 {
54	enable-method = "spin-table";
55	cpu-release-addr = <0x0 0x0000fff8>;
56};
57
58&osc1 {
59	clock-frequency = <25000000>;
60};
61
62&gmac0 {
63	status = "okay";
64	phy-mode = "rgmii";
65};
66
67&gmac1 {
68	status = "okay";
69	phy-mode = "rgmii";
70};
71
72&gmac2 {
73	status = "okay";
74	phy-mode = "rgmii";
75};
76
77&mmc {
78	status = "okay";
79	cap-sd-highspeed;
80	cap-mmc-highspeed;
81	broken-cd;
82	bus-width = <4>;
83};
84
85&uart0 {
86	status = "okay";
87};
88
89&uart1 {
90	status = "okay";
91};
92
93&usb0 {
94	clocks = <&clkmgr STRATIX10_L4_MP_CLK>;
95	status = "okay";
96};
97
98&usb1 {
99	clocks = <&clkmgr STRATIX10_L4_MP_CLK>;
100	status = "okay";
101};
102
103&sysmgr {
104	reg = <0xffd12000 0x1000>;
105};
106