1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #ifndef __AMDGPU_DM_PLANE_H__ 28 #define __AMDGPU_DM_PLANE_H__ 29 30 #include "dc.h" 31 32 int amdgpu_dm_plane_get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc, 33 struct dc_cursor_position *position); 34 35 void amdgpu_dm_plane_handle_cursor_update(struct drm_plane *plane, 36 struct drm_plane_state *old_plane_state); 37 38 int amdgpu_dm_plane_fill_dc_scaling_info(struct amdgpu_device *adev, 39 const struct drm_plane_state *state, 40 struct dc_scaling_info *scaling_info); 41 42 int amdgpu_dm_plane_helper_check_state(struct drm_plane_state *state, 43 struct drm_crtc_state *new_crtc_state); 44 45 int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev, 46 const struct amdgpu_framebuffer *afb, 47 const enum surface_pixel_format format, 48 const enum dc_rotation_angle rotation, 49 const uint64_t tiling_flags, 50 union dc_tiling_info *tiling_info, 51 struct plane_size *plane_size, 52 struct dc_plane_dcc_param *dcc, 53 struct dc_plane_address *address, 54 bool tmz_surface, 55 bool force_disable_dcc); 56 57 int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 58 struct drm_plane *plane, 59 unsigned long possible_crtcs, 60 const struct dc_plane_cap *plane_cap); 61 62 const struct drm_format_info *amdgpu_dm_plane_get_format_info(const struct drm_mode_fb_cmd2 *cmd); 63 64 void amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state *plane_state, 65 bool *per_pixel_alpha, bool *pre_multiplied_alpha, 66 bool *global_alpha, int *global_alpha_value); 67 68 bool amdgpu_dm_plane_is_video_format(uint32_t format); 69 #endif 70