1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2020 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #ifndef __AMDGPU_DM_IRQ_PARAMS_H__ 28 #define __AMDGPU_DM_IRQ_PARAMS_H__ 29 30 #include "amdgpu_dm_crc.h" 31 32 struct dm_irq_params { 33 u32 last_flip_vblank; 34 struct mod_vrr_params vrr_params; 35 struct dc_stream_state *stream; 36 int active_planes; 37 bool allow_sr_entry; 38 struct mod_freesync_config freesync_config; 39 40 #ifdef CONFIG_DEBUG_FS 41 enum amdgpu_dm_pipe_crc_source crc_src; 42 int crc_poly_mode; /* enum crc_poly_mode from timing_generator.h */ 43 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 44 struct crc_window_param window_param[MAX_CRC_WINDOW_NUM]; 45 /* At least one CRC window is activated or not*/ 46 bool crc_window_activated; 47 #endif 48 #endif 49 }; 50 51 #endif /* __AMDGPU_DM_IRQ_PARAMS_H__ */ 52