1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2015 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef __AMDGPU_DM_IRQ_H__ 26 #define __AMDGPU_DM_IRQ_H__ 27 28 #include "irq_types.h" /* DAL irq definitions */ 29 30 struct amdgpu_device; 31 struct amdgpu_crtc; 32 struct amdgpu_display_manager; 33 struct dc_sink; 34 struct hpd_rx_irq_offload_work_queue; 35 struct work_struct; 36 enum dmub_notification_type; 37 38 /* 39 * Display Manager IRQ-related interfaces (for use by DAL). 40 */ 41 42 /** 43 * amdgpu_dm_irq_init - Initialize internal structures of 'amdgpu_dm_irq'. 44 * 45 * This function should be called exactly once - during DM initialization. 46 * 47 * Returns: 48 * 0 - success 49 * non-zero - error 50 */ 51 int amdgpu_dm_irq_init(struct amdgpu_device *adev); 52 53 /** 54 * amdgpu_dm_irq_fini - deallocate internal structures of 'amdgpu_dm_irq'. 55 * 56 * This function should be called exactly once - during DM destruction. 57 * 58 */ 59 void amdgpu_dm_irq_fini(struct amdgpu_device *adev); 60 61 /** 62 * amdgpu_dm_irq_register_interrupt - register irq handler for Display block. 63 * 64 * @adev: AMD DRM device 65 * @int_params: parameters for the irq 66 * @ih: pointer to the irq hander function 67 * @handler_args: arguments which will be passed to ih 68 * 69 * Returns: 70 * IRQ Handler Index on success. 71 * NULL on failure. 72 * 73 * Cannot be called from an interrupt handler. 74 */ 75 void *amdgpu_dm_irq_register_interrupt(struct amdgpu_device *adev, 76 struct dc_interrupt_params *int_params, 77 void (*ih)(void *), 78 void *handler_args); 79 80 /** 81 * amdgpu_dm_irq_unregister_interrupt - unregister handler which was registered 82 * by amdgpu_dm_irq_register_interrupt(). 83 * 84 * @adev: AMD DRM device. 85 * @ih_index: irq handler index which was returned by 86 * amdgpu_dm_irq_register_interrupt 87 */ 88 void amdgpu_dm_irq_unregister_interrupt(struct amdgpu_device *adev, 89 enum dc_irq_source irq_source, 90 void *ih_index); 91 92 /** 93 * amdgpu_dm_irq_set - enable or disable a DC interrupt source. 94 * 95 * @adev: AMD DRM device 96 * @src: DC interrupt source to toggle 97 * @enable: true to enable the source, false to disable it 98 * 99 * DM-wide replacement for dc_interrupt_set(). As locking is DM's 100 * responsibility, this is a thin wrapper serializes the underlying 101 * read-modify-write against the other interrupt sources sharing HW control 102 * registers with @src, so DM must never call dc_interrupt_set() directly. 103 * 104 * Returns: true if the source was toggled. 105 */ 106 bool amdgpu_dm_irq_set(struct amdgpu_device *adev, enum dc_irq_source src, 107 bool enable); 108 109 /** 110 * amdgpu_dm_irq_ack - acknowledge a DC interrupt source. 111 * 112 * @adev: AMD DRM device 113 * @src: DC interrupt source to acknowledge 114 * 115 * DM-wide replacement for dc_interrupt_ack(), serialized the same way as 116 * amdgpu_dm_irq_set(). 117 */ 118 void amdgpu_dm_irq_ack(struct amdgpu_device *adev, enum dc_irq_source src); 119 120 void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev); 121 122 void amdgpu_dm_outbox_init(struct amdgpu_device *adev); 123 void amdgpu_dm_hpd_init(struct amdgpu_device *adev); 124 void amdgpu_dm_hpd_fini(struct amdgpu_device *adev); 125 126 /** 127 * amdgpu_dm_irq_suspend - disable ASIC interrupt during suspend. 128 * 129 */ 130 void amdgpu_dm_irq_suspend(struct amdgpu_device *adev); 131 132 /** 133 * amdgpu_dm_irq_resume_early - enable HPDRX ASIC interrupts during resume. 134 * amdgpu_dm_irq_resume - enable ASIC interrupt during resume. 135 * 136 */ 137 void amdgpu_dm_irq_resume_early(struct amdgpu_device *adev); 138 void amdgpu_dm_irq_resume_late(struct amdgpu_device *adev); 139 140 /* HPD handling */ 141 struct hpd_rx_irq_offload_work_queue *amdgpu_dm_hpd_rx_irq_create_workqueue(struct amdgpu_device *adev); 142 void amdgpu_dm_hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm); 143 int amdgpu_dm_register_hpd_handlers(struct amdgpu_device *adev); 144 void amdgpu_dm_hdmi_hpd_debounce_work(struct work_struct *work); 145 146 /* IRQ handlers */ 147 struct amdgpu_crtc *amdgpu_dm_get_crtc_by_otg_inst(struct amdgpu_device *adev, 148 int otg_inst); 149 int amdgpu_dm_dce110_register_irq_handlers(struct amdgpu_device *adev); 150 int amdgpu_dm_dcn10_register_irq_handlers(struct amdgpu_device *adev); 151 int amdgpu_dm_register_outbox_irq_handlers(struct amdgpu_device *adev); 152 153 #if IS_ENABLED(CONFIG_DRM_AMD_DC_KUNIT_TEST) 154 struct amdgpu_irq_src; 155 struct amdgpu_iv_entry; 156 enum amdgpu_interrupt_state; 157 158 enum dc_irq_source amdgpu_dm_hpd_to_dal_irq_source(unsigned int type); 159 bool are_sinks_equal(const struct dc_sink *sink1, const struct dc_sink *sink2); 160 const char *dmub_notification_type_str(enum dmub_notification_type e); 161 int amdgpu_dm_set_hpd_irq_state(struct amdgpu_device *adev, 162 struct amdgpu_irq_src *source, 163 unsigned int type, 164 enum amdgpu_interrupt_state state); 165 int amdgpu_dm_set_dmub_outbox_irq_state(struct amdgpu_device *adev, 166 struct amdgpu_irq_src *source, 167 unsigned int crtc_id, 168 enum amdgpu_interrupt_state state); 169 int amdgpu_dm_set_dmub_trace_irq_state(struct amdgpu_device *adev, 170 struct amdgpu_irq_src *source, 171 unsigned int type, 172 enum amdgpu_interrupt_state state); 173 int amdgpu_dm_set_pflip_irq_state(struct amdgpu_device *adev, 174 struct amdgpu_irq_src *source, 175 unsigned int crtc_id, 176 enum amdgpu_interrupt_state state); 177 int amdgpu_dm_set_crtc_irq_state(struct amdgpu_device *adev, 178 struct amdgpu_irq_src *source, 179 unsigned int crtc_id, 180 enum amdgpu_interrupt_state state); 181 int amdgpu_dm_set_vline0_irq_state(struct amdgpu_device *adev, 182 struct amdgpu_irq_src *source, 183 unsigned int crtc_id, 184 enum amdgpu_interrupt_state state); 185 int amdgpu_dm_set_vupdate_irq_state(struct amdgpu_device *adev, 186 struct amdgpu_irq_src *source, 187 unsigned int crtc_id, 188 enum amdgpu_interrupt_state state); 189 void amdgpu_dm_irq_schedule_work(struct amdgpu_device *adev, 190 enum dc_irq_source irq_source); 191 void amdgpu_dm_irq_immediate_work(struct amdgpu_device *adev, 192 enum dc_irq_source irq_source); 193 void dm_handle_hpd_rx_offload_work(struct work_struct *work); 194 void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector, 195 enum dc_detect_reason reason); 196 void handle_hpd_irq(void *param); 197 void schedule_hpd_rx_offload_work(struct amdgpu_device *adev, 198 struct hpd_rx_irq_offload_work_queue *offload_wq, 199 union hpd_irq_data hpd_irq_data); 200 void handle_hpd_rx_irq(void *param); 201 void dmub_hpd_callback(struct amdgpu_device *adev, 202 struct dmub_notification *notify); 203 void dmub_hpd_sense_callback(struct amdgpu_device *adev, 204 struct dmub_notification *notify); 205 void dm_pflip_high_irq(void *interrupt_params); 206 void dm_vupdate_high_irq(void *interrupt_params); 207 void dm_crtc_high_irq(void *interrupt_params); 208 void dm_handle_hpd_work(struct work_struct *work); 209 void dm_dmub_outbox1_low_irq(void *interrupt_params); 210 int amdgpu_dm_irq_handler(struct amdgpu_device *adev, 211 struct amdgpu_irq_src *source, 212 struct amdgpu_iv_entry *entry); 213 void dm_handle_vmin_vmax_update(struct work_struct *offload_work); 214 #endif 215 216 #endif /* __AMDGPU_DM_IRQ_H__ */ 217