1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26 #include <drm/drm_vblank.h>
27 #include <drm/drm_atomic_helper.h>
28
29 #include "dc.h"
30 #include "amdgpu.h"
31 #include "amdgpu_dm_psr.h"
32 #include "amdgpu_dm_replay.h"
33 #include "amdgpu_dm_crtc.h"
34 #include "amdgpu_dm_plane.h"
35 #include "amdgpu_dm_trace.h"
36 #include "amdgpu_dm_debugfs.h"
37 #include "modules/inc/mod_power.h"
38
39 #define HPD_DETECTION_PERIOD_uS 2000000
40 #define HPD_DETECTION_TIME_uS 100000
41
amdgpu_dm_crtc_handle_vblank(struct amdgpu_crtc * acrtc)42 void amdgpu_dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc)
43 {
44 struct drm_crtc *crtc = &acrtc->base;
45 struct drm_device *dev = crtc->dev;
46 unsigned long flags;
47
48 drm_crtc_handle_vblank(crtc);
49
50 spin_lock_irqsave(&dev->event_lock, flags);
51
52 /* Send completion event for cursor-only commits */
53 if (acrtc->event && acrtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
54 drm_crtc_send_vblank_event(crtc, acrtc->event);
55 drm_crtc_vblank_put(crtc);
56 acrtc->event = NULL;
57 }
58
59 spin_unlock_irqrestore(&dev->event_lock, flags);
60 }
61
amdgpu_dm_crtc_modeset_required(struct drm_crtc_state * crtc_state,struct dc_stream_state * new_stream,struct dc_stream_state * old_stream)62 bool amdgpu_dm_crtc_modeset_required(struct drm_crtc_state *crtc_state,
63 struct dc_stream_state *new_stream,
64 struct dc_stream_state *old_stream)
65 {
66 return crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
67 }
68
amdgpu_dm_crtc_vrr_active_irq(struct amdgpu_crtc * acrtc)69 bool amdgpu_dm_crtc_vrr_active_irq(struct amdgpu_crtc *acrtc)
70
71 {
72 return acrtc->dm_irq_params.freesync_config.state ==
73 VRR_STATE_ACTIVE_VARIABLE ||
74 acrtc->dm_irq_params.freesync_config.state ==
75 VRR_STATE_ACTIVE_FIXED;
76 }
77
amdgpu_dm_crtc_set_vupdate_irq(struct drm_crtc * crtc,bool enable)78 int amdgpu_dm_crtc_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
79 {
80 enum dc_irq_source irq_source;
81 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
82 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
83 int rc;
84
85 if (acrtc->otg_inst == -1)
86 return 0;
87
88 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
89
90 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
91
92 DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",
93 acrtc->crtc_id, enable ? "en" : "dis", rc);
94 return rc;
95 }
96
amdgpu_dm_crtc_vrr_active(const struct dm_crtc_state * dm_state)97 bool amdgpu_dm_crtc_vrr_active(const struct dm_crtc_state *dm_state)
98 {
99 return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
100 dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
101 }
102
103 /**
104 * amdgpu_dm_crtc_set_static_screen_optimze() - Toggle static screen optimizations.
105 *
106 * @dm: display manager
107 * @stream: DC stream state
108 * @sso_enable: desired static screen optimization state
109 * @allow_sr_entry: whether entry into self-refresh mode is allowed
110 *
111 * This function uses the static-screen optimization state as the trigger to
112 * set/clear the Replay and PSR vsync-related events.
113 */
amdgpu_dm_crtc_set_static_screen_optimze(struct amdgpu_display_manager * dm,struct dc_stream_state * stream,bool sso_enable,bool allow_sr_entry)114 void amdgpu_dm_crtc_set_static_screen_optimze(
115 struct amdgpu_display_manager *dm,
116 struct dc_stream_state *stream,
117 bool sso_enable, bool allow_sr_entry)
118 {
119 struct dc_link *link = stream->link;
120 bool set_vsync_event = !sso_enable;
121
122 /*
123 * allow_sr_entry gates only entry. A disable request must still set
124 * the vsync events to force Replay and PSR1 out and keep them blocked.
125 */
126 if (sso_enable && !allow_sr_entry)
127 return;
128
129 amdgpu_dm_replay_set_event(dm, stream,
130 set_vsync_event, replay_event_vsync, set_vsync_event);
131
132 if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1)
133 amdgpu_dm_psr_set_event(dm, stream,
134 set_vsync_event, psr_event_vsync, set_vsync_event);
135 }
136
amdgpu_dm_is_headless(struct amdgpu_device * adev)137 bool amdgpu_dm_is_headless(struct amdgpu_device *adev)
138 {
139 struct drm_connector *connector;
140 struct drm_connector_list_iter iter;
141 struct drm_device *dev;
142 bool is_headless = true;
143
144 if (adev == NULL)
145 return true;
146
147 dev = adev->dm.ddev;
148
149 drm_connector_list_iter_begin(dev, &iter);
150 drm_for_each_connector_iter(connector, &iter) {
151
152 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
153 continue;
154
155 if (connector->status == connector_status_connected) {
156 is_headless = false;
157 break;
158 }
159 }
160 drm_connector_list_iter_end(&iter);
161 return is_headless;
162 }
163
amdgpu_dm_idle_worker(struct work_struct * work)164 static void amdgpu_dm_idle_worker(struct work_struct *work)
165 {
166 struct idle_workqueue *idle_work;
167
168 idle_work = container_of(work, struct idle_workqueue, work);
169 idle_work->dm->idle_workqueue->running = true;
170
171 while (idle_work->enable) {
172 fsleep(HPD_DETECTION_PERIOD_uS);
173 mutex_lock(&idle_work->dm->dc_lock);
174 if (!idle_work->dm->dc->idle_optimizations_allowed) {
175 mutex_unlock(&idle_work->dm->dc_lock);
176 break;
177 }
178 dc_allow_idle_optimizations(idle_work->dm->dc, false);
179
180 mutex_unlock(&idle_work->dm->dc_lock);
181 fsleep(HPD_DETECTION_TIME_uS);
182 mutex_lock(&idle_work->dm->dc_lock);
183
184 if (!amdgpu_dm_is_headless(idle_work->dm->adev) &&
185 !amdgpu_dm_psr_is_active_allowed(idle_work->dm)) {
186 mutex_unlock(&idle_work->dm->dc_lock);
187 break;
188 }
189
190 if (idle_work->enable) {
191 dc_post_update_surfaces_to_stream(idle_work->dm->dc);
192 dc_allow_idle_optimizations(idle_work->dm->dc, true);
193 }
194 mutex_unlock(&idle_work->dm->dc_lock);
195 }
196 idle_work->dm->idle_workqueue->running = false;
197 }
198
idle_create_workqueue(struct amdgpu_device * adev)199 struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev)
200 {
201 struct idle_workqueue *idle_work;
202
203 idle_work = kzalloc_obj(*idle_work);
204 if (ZERO_OR_NULL_PTR(idle_work))
205 return NULL;
206
207 idle_work->dm = &adev->dm;
208 idle_work->enable = false;
209 idle_work->running = false;
210 INIT_WORK(&idle_work->work, amdgpu_dm_idle_worker);
211
212 return idle_work;
213 }
214
amdgpu_dm_crtc_vblank_control_worker(struct work_struct * work)215 static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work)
216 {
217 struct vblank_control_work *vblank_work =
218 container_of(work, struct vblank_control_work, work);
219 struct amdgpu_display_manager *dm = vblank_work->dm;
220
221 mutex_lock(&dm->dc_lock);
222
223 if (vblank_work->enable) {
224 dm->active_vblank_irq_count++;
225 amdgpu_dm_ism_commit_event(&vblank_work->acrtc->ism,
226 DM_ISM_EVENT_EXIT_IDLE_REQUESTED);
227 } else {
228 if (dm->active_vblank_irq_count > 0)
229 dm->active_vblank_irq_count--;
230 amdgpu_dm_ism_commit_event(&vblank_work->acrtc->ism,
231 DM_ISM_EVENT_ENTER_IDLE_REQUESTED);
232 }
233
234 mutex_unlock(&dm->dc_lock);
235
236 dc_stream_release(vblank_work->stream);
237
238 kfree(vblank_work);
239 }
240
amdgpu_dm_crtc_set_vblank(struct drm_crtc * crtc,bool enable)241 static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable)
242 {
243 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
244 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
245 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
246 struct amdgpu_display_manager *dm = &adev->dm;
247 struct vblank_control_work *work;
248 int irq_type;
249 int rc = 0;
250
251 if (enable && !acrtc->base.enabled) {
252 drm_dbg_vbl(crtc->dev,
253 "Reject vblank enable on unconfigured CRTC %d (enabled=%d)\n",
254 acrtc->crtc_id, acrtc->base.enabled);
255 return -EINVAL;
256 }
257
258 irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
259
260 if (enable && acrtc_state->stream) {
261 struct dc *dc = adev->dm.dc;
262 struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
263 struct psr_settings *psr = &acrtc_state->stream->link->psr_settings;
264 struct replay_settings *pr = &acrtc_state->stream->link->replay_settings;
265 bool sr_supported = (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED) ||
266 pr->config.replay_supported;
267
268 /*
269 * IPS & self-refresh feature can cause vblank counter resets between
270 * vblank disable and enable.
271 * It may cause system stuck due to waiting for the vblank counter.
272 * Call this function to estimate missed vblanks by using timestamps and
273 * update the vblank counter in DRM.
274 */
275 if (dc->caps.ips_support &&
276 dc->config.disable_ips != DMUB_IPS_DISABLE_ALL &&
277 sr_supported && vblank->config.disable_immediate)
278 drm_crtc_vblank_restore(crtc);
279 }
280
281 /*
282 * On DCN, VUPDATE_NO_LOCK is the single OTG interrupt used to deliver
283 * vblank and pageflip completion events, so enable it whenever vblank
284 * is enabled. On DCE, vupdate is only needed in VRR mode.
285 */
286 if (amdgpu_ip_version(adev, DCE_HWIP, 0) != 0) {
287 if (enable) {
288 rc = amdgpu_irq_get(adev, &adev->vupdate_irq, irq_type);
289 drm_dbg_vbl(crtc->dev, "Get vupdate_irq ret=%d\n", rc);
290 } else {
291 rc = amdgpu_irq_put(adev, &adev->vupdate_irq, irq_type);
292 drm_dbg_vbl(crtc->dev, "Put vupdate_irq ret=%d\n", rc);
293 }
294 } else if (dc_supports_vrr(dm->dc->ctx->dce_version)) {
295 if (enable) {
296 /* vblank irq on -> Only need vupdate irq in vrr mode
297 * Not ref-counted since we need explicit enable/disable
298 * for DCE VRR handling
299 */
300 if (amdgpu_dm_crtc_vrr_active(acrtc_state))
301 rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, true);
302 } else {
303 /* vblank irq off -> vupdate irq off */
304 rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, false);
305 }
306 }
307
308 if (rc)
309 return rc;
310
311 /*
312 * VLINE0 (crtc_irq) and GRPH_PFLIP (pageflip_irq) are only used on
313 * DCE. On DCN, vblank and pageflip completion are delivered from
314 * VUPDATE_NO_LOCK (enabled above), so don't touch them here.
315 */
316 if (amdgpu_ip_version(adev, DCE_HWIP, 0) == 0) {
317 /* crtc vblank or vstartup interrupt */
318 if (enable) {
319 rc = amdgpu_irq_get(adev, &adev->crtc_irq, irq_type);
320 drm_dbg_vbl(crtc->dev, "Get crtc_irq ret=%d\n", rc);
321 } else {
322 rc = amdgpu_irq_put(adev, &adev->crtc_irq, irq_type);
323 drm_dbg_vbl(crtc->dev, "Put crtc_irq ret=%d\n", rc);
324 }
325
326 if (rc)
327 return rc;
328
329 /*
330 * hubp surface flip interrupt
331 *
332 * We have no guarantee that the frontend index maps to the same
333 * backend index - some even map to more than one.
334 *
335 * TODO: Use a different interrupt or check DC itself for the mapping.
336 */
337 if (enable) {
338 rc = amdgpu_irq_get(adev, &adev->pageflip_irq, irq_type);
339 drm_dbg_vbl(crtc->dev, "Get pageflip_irq ret=%d\n", rc);
340 } else {
341 rc = amdgpu_irq_put(adev, &adev->pageflip_irq, irq_type);
342 drm_dbg_vbl(crtc->dev, "Put pageflip_irq ret=%d\n", rc);
343 }
344
345 if (rc)
346 return rc;
347 }
348
349 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
350 /* crtc vline0 interrupt, only available on DCN+ */
351 if (amdgpu_ip_version(adev, DCE_HWIP, 0) != 0) {
352 if (enable) {
353 rc = amdgpu_irq_get(adev, &adev->vline0_irq, irq_type);
354 drm_dbg_vbl(crtc->dev, "Get vline0_irq ret=%d\n", rc);
355 } else {
356 rc = amdgpu_irq_put(adev, &adev->vline0_irq, irq_type);
357 drm_dbg_vbl(crtc->dev, "Put vline0_irq ret=%d\n", rc);
358 }
359
360 if (rc)
361 return rc;
362 }
363 #endif
364
365 if (amdgpu_in_reset(adev))
366 return 0;
367
368 if (dm->vblank_control_workqueue) {
369 work = kzalloc_obj(*work, GFP_ATOMIC);
370 if (!work)
371 return -ENOMEM;
372
373 INIT_WORK(&work->work, amdgpu_dm_crtc_vblank_control_worker);
374 work->dm = dm;
375 work->acrtc = acrtc;
376 work->enable = enable;
377
378 if (acrtc_state->stream) {
379 dc_stream_retain(acrtc_state->stream);
380 work->stream = acrtc_state->stream;
381 }
382
383 queue_work(dm->vblank_control_workqueue, &work->work);
384 }
385
386 return 0;
387 }
388
amdgpu_dm_crtc_enable_vblank(struct drm_crtc * crtc)389 int amdgpu_dm_crtc_enable_vblank(struct drm_crtc *crtc)
390 {
391 return amdgpu_dm_crtc_set_vblank(crtc, true);
392 }
393
amdgpu_dm_crtc_disable_vblank(struct drm_crtc * crtc)394 void amdgpu_dm_crtc_disable_vblank(struct drm_crtc *crtc)
395 {
396 amdgpu_dm_crtc_set_vblank(crtc, false);
397 }
398
amdgpu_dm_crtc_destroy_state(struct drm_crtc * crtc,struct drm_crtc_state * state)399 static void amdgpu_dm_crtc_destroy_state(struct drm_crtc *crtc,
400 struct drm_crtc_state *state)
401 {
402 struct dm_crtc_state *cur = to_dm_crtc_state(state);
403
404 /* TODO Destroy dc_stream objects are stream object is flattened */
405 if (cur->stream)
406 dc_stream_release(cur->stream);
407
408
409 __drm_atomic_helper_crtc_destroy_state(state);
410
411
412 kfree(state);
413 }
414
amdgpu_dm_crtc_duplicate_state(struct drm_crtc * crtc)415 static struct drm_crtc_state *amdgpu_dm_crtc_duplicate_state(struct drm_crtc *crtc)
416 {
417 struct dm_crtc_state *state, *cur;
418
419 cur = to_dm_crtc_state(crtc->state);
420
421 if (WARN_ON(!crtc->state))
422 return NULL;
423
424 state = kzalloc_obj(*state);
425 if (!state)
426 return NULL;
427
428 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
429
430 if (cur->stream) {
431 state->stream = cur->stream;
432 dc_stream_retain(state->stream);
433 }
434
435 state->active_planes = cur->active_planes;
436 state->vrr_infopacket = cur->vrr_infopacket;
437 state->abm_level = cur->abm_level;
438 state->vrr_supported = cur->vrr_supported;
439 state->freesync_config = cur->freesync_config;
440 state->cm_has_degamma = cur->cm_has_degamma;
441 state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
442 state->regamma_tf = cur->regamma_tf;
443 state->crc_skip_count = cur->crc_skip_count;
444 state->mpo_requested = cur->mpo_requested;
445 state->cursor_mode = cur->cursor_mode;
446 /* TODO Duplicate dc_stream after objects are stream object is flattened */
447
448 return &state->base;
449 }
450
amdgpu_dm_crtc_destroy(struct drm_crtc * crtc)451 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
452 {
453 /*
454 * amdgpu_dm_ism_fini() is intentionally called in amdgpu_dm_fini().
455 * It must be called before dc_destroy() in amdgpu_dm_fini()
456 * to avoid ISM accessing an invalid dc handle once dc is released.
457 */
458
459 drm_crtc_cleanup(crtc);
460 kfree(crtc);
461 }
462
amdgpu_dm_crtc_reset_state(struct drm_crtc * crtc)463 static void amdgpu_dm_crtc_reset_state(struct drm_crtc *crtc)
464 {
465 struct dm_crtc_state *state;
466
467 if (crtc->state)
468 amdgpu_dm_crtc_destroy_state(crtc, crtc->state);
469
470 state = kzalloc_obj(*state);
471 if (WARN_ON(!state))
472 return;
473
474 __drm_atomic_helper_crtc_reset(crtc, &state->base);
475 }
476
477 #ifdef CONFIG_DEBUG_FS
amdgpu_dm_crtc_late_register(struct drm_crtc * crtc)478 static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc)
479 {
480 crtc_debugfs_init(crtc);
481
482 return 0;
483 }
484 #endif
485
486 #ifdef AMD_PRIVATE_COLOR
487 /**
488 * dm_crtc_additional_color_mgmt - enable additional color properties
489 * @crtc: DRM CRTC
490 *
491 * This function lets the driver enable post-blending CRTC regamma transfer
492 * function property in addition to DRM CRTC gamma LUT. Default value means
493 * linear transfer function, which is the default CRTC gamma LUT behaviour
494 * without this property.
495 */
496 static void
dm_crtc_additional_color_mgmt(struct drm_crtc * crtc)497 dm_crtc_additional_color_mgmt(struct drm_crtc *crtc)
498 {
499 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
500
501 if (adev->dm.dc->caps.color.mpc.ogam_ram)
502 drm_object_attach_property(&crtc->base,
503 adev->mode_info.regamma_tf_property,
504 AMDGPU_TRANSFER_FUNCTION_DEFAULT);
505 }
506
507 static int
amdgpu_dm_atomic_crtc_set_property(struct drm_crtc * crtc,struct drm_crtc_state * state,struct drm_property * property,uint64_t val)508 amdgpu_dm_atomic_crtc_set_property(struct drm_crtc *crtc,
509 struct drm_crtc_state *state,
510 struct drm_property *property,
511 uint64_t val)
512 {
513 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
514 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state);
515
516 if (property == adev->mode_info.regamma_tf_property) {
517 if (acrtc_state->regamma_tf != val) {
518 acrtc_state->regamma_tf = val;
519 acrtc_state->base.color_mgmt_changed |= 1;
520 }
521 } else {
522 drm_dbg_atomic(crtc->dev,
523 "[CRTC:%d:%s] unknown property [PROP:%d:%s]]\n",
524 crtc->base.id, crtc->name,
525 property->base.id, property->name);
526 return -EINVAL;
527 }
528
529 return 0;
530 }
531
532 static int
amdgpu_dm_atomic_crtc_get_property(struct drm_crtc * crtc,const struct drm_crtc_state * state,struct drm_property * property,uint64_t * val)533 amdgpu_dm_atomic_crtc_get_property(struct drm_crtc *crtc,
534 const struct drm_crtc_state *state,
535 struct drm_property *property,
536 uint64_t *val)
537 {
538 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
539 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state);
540
541 if (property == adev->mode_info.regamma_tf_property)
542 *val = acrtc_state->regamma_tf;
543 else
544 return -EINVAL;
545
546 return 0;
547 }
548 #endif
549
550 /* Implemented only the options currently available for the driver */
551 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
552 .reset = amdgpu_dm_crtc_reset_state,
553 .destroy = amdgpu_dm_crtc_destroy,
554 .set_config = drm_atomic_helper_set_config,
555 .page_flip = drm_atomic_helper_page_flip,
556 .atomic_duplicate_state = amdgpu_dm_crtc_duplicate_state,
557 .atomic_destroy_state = amdgpu_dm_crtc_destroy_state,
558 .set_crc_source = amdgpu_dm_crtc_set_crc_source,
559 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
560 .get_crc_sources = amdgpu_dm_crtc_get_crc_sources,
561 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
562 .enable_vblank = amdgpu_dm_crtc_enable_vblank,
563 .disable_vblank = amdgpu_dm_crtc_disable_vblank,
564 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
565 #if defined(CONFIG_DEBUG_FS)
566 .late_register = amdgpu_dm_crtc_late_register,
567 #endif
568 #ifdef AMD_PRIVATE_COLOR
569 .atomic_set_property = amdgpu_dm_atomic_crtc_set_property,
570 .atomic_get_property = amdgpu_dm_atomic_crtc_get_property,
571 #endif
572 };
573
amdgpu_dm_crtc_helper_disable(struct drm_crtc * crtc)574 static void amdgpu_dm_crtc_helper_disable(struct drm_crtc *crtc)
575 {
576 }
577
amdgpu_dm_crtc_count_crtc_active_planes(struct drm_crtc_state * new_crtc_state)578 static int amdgpu_dm_crtc_count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
579 {
580 struct drm_atomic_commit *state = new_crtc_state->state;
581 struct drm_plane *plane;
582 int num_active = 0;
583
584 drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) {
585 struct drm_plane_state *new_plane_state;
586
587 /* Cursor planes are "fake". */
588 if (plane->type == DRM_PLANE_TYPE_CURSOR)
589 continue;
590
591 new_plane_state = drm_atomic_get_new_plane_state(state, plane);
592
593 if (!new_plane_state) {
594 /*
595 * The plane is enable on the CRTC and hasn't changed
596 * state. This means that it previously passed
597 * validation and is therefore enabled.
598 */
599 num_active += 1;
600 continue;
601 }
602
603 /* We need a framebuffer to be considered enabled. */
604 num_active += (new_plane_state->fb != NULL);
605 }
606
607 return num_active;
608 }
609
amdgpu_dm_crtc_update_crtc_active_planes(struct drm_crtc * crtc,struct drm_crtc_state * new_crtc_state)610 static void amdgpu_dm_crtc_update_crtc_active_planes(struct drm_crtc *crtc,
611 struct drm_crtc_state *new_crtc_state)
612 {
613 struct dm_crtc_state *dm_new_crtc_state =
614 to_dm_crtc_state(new_crtc_state);
615
616 dm_new_crtc_state->active_planes = 0;
617
618 if (!dm_new_crtc_state->stream)
619 return;
620
621 dm_new_crtc_state->active_planes =
622 amdgpu_dm_crtc_count_crtc_active_planes(new_crtc_state);
623 }
624
amdgpu_dm_crtc_helper_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)625 static bool amdgpu_dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
626 const struct drm_display_mode *mode,
627 struct drm_display_mode *adjusted_mode)
628 {
629 return true;
630 }
631
amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc * crtc,struct drm_atomic_commit * state)632 static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
633 struct drm_atomic_commit *state)
634 {
635 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
636 crtc);
637 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
638 struct dc *dc = adev->dm.dc;
639 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
640 int ret = -EINVAL;
641
642 trace_amdgpu_dm_crtc_atomic_check(crtc_state);
643
644 amdgpu_dm_crtc_update_crtc_active_planes(crtc, crtc_state);
645
646 if (WARN_ON(unlikely(!dm_crtc_state->stream &&
647 amdgpu_dm_crtc_modeset_required(crtc_state, NULL, dm_crtc_state->stream)))) {
648 return ret;
649 }
650
651 /*
652 * We require the primary plane to be enabled whenever the CRTC is, otherwise
653 * drm_mode_cursor_universal may end up trying to enable the cursor plane while all other
654 * planes are disabled, which is not supported by the hardware. And there is legacy
655 * userspace which stops using the HW cursor altogether in response to the resulting EINVAL.
656 */
657 if (crtc_state->enable &&
658 !(crtc_state->plane_mask & drm_plane_mask(crtc->primary))) {
659 DRM_DEBUG_ATOMIC("Can't enable a CRTC without enabling the primary plane\n");
660 return -EINVAL;
661 }
662
663 /*
664 * Only allow async flips for fast updates that don't change the FB
665 * pitch, the DCC state, rotation, etc.
666 */
667 if (crtc_state->async_flip &&
668 dm_crtc_state->update_type != UPDATE_TYPE_FAST) {
669 drm_dbg_atomic(crtc->dev,
670 "[CRTC:%d:%s] async flips are only supported for fast updates\n",
671 crtc->base.id, crtc->name);
672 return -EINVAL;
673 }
674
675 if (!state->legacy_cursor_update && amdgpu_dm_crtc_vrr_active(dm_crtc_state)) {
676 struct drm_plane_state *primary_state;
677
678 /* Pull in primary plane for correct VRR handling */
679 primary_state = drm_atomic_get_plane_state(state, crtc->primary);
680 if (IS_ERR(primary_state))
681 return PTR_ERR(primary_state);
682 }
683
684 /* In some use cases, like reset, no stream is attached */
685 if (!dm_crtc_state->stream)
686 return 0;
687
688 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
689 return 0;
690
691 DRM_DEBUG_ATOMIC("Failed DC stream validation\n");
692 return ret;
693 }
694
695 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
696 .disable = amdgpu_dm_crtc_helper_disable,
697 .atomic_check = amdgpu_dm_crtc_helper_atomic_check,
698 .mode_fixup = amdgpu_dm_crtc_helper_mode_fixup,
699 .get_scanout_position = amdgpu_crtc_get_scanout_position,
700 };
701
702 /*
703 * This hysteresis filter as configured will:
704 *
705 * * Search through the latest 8[filter_history_size] entries in history,
706 * skipping entries that are older than [filter_old_history_threshold] frames
707 * (0 means ignore age)
708 * * Searches for short-idle-periods that lasted shorter than
709 * 4[filter_num_frames] frames-times
710 * * If there is at least 1[filter_entry_count] short-idle-period, then a delay
711 * of 4[activation_num_delay_frames] will applied before allowing idle
712 * optimizations again.
713 * * An additional delay of 11[sso_num_frames] is applied before enabling
714 * panel-specific optimizations.
715 *
716 * The values were determined empirically on another OS, optimizing for Z8
717 * residency on APUs when running a productivity + web browsing test.
718 *
719 * TODO: Run similar tests to determine if these values are also optimal for
720 * Linux, and if each APU generation benefits differently.
721 */
722 static struct amdgpu_dm_ism_config default_ism_config = {
723 .filter_num_frames = 4,
724 .filter_history_size = 8,
725 .filter_entry_count = 1,
726 .activation_num_delay_frames = 4,
727 .filter_old_history_threshold = 0,
728 .sso_num_frames = 11,
729 };
730
amdgpu_dm_crtc_init(struct amdgpu_display_manager * dm,struct drm_plane * plane,uint32_t crtc_index)731 int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
732 struct drm_plane *plane,
733 uint32_t crtc_index)
734 {
735 struct amdgpu_crtc *acrtc = NULL;
736 struct drm_plane *cursor_plane;
737 bool has_degamma;
738 int res = -ENOMEM;
739
740 cursor_plane = kzalloc_obj(*cursor_plane);
741 if (!cursor_plane)
742 goto fail;
743
744 cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
745 res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL);
746
747 acrtc = kzalloc_obj(struct amdgpu_crtc);
748 if (!acrtc)
749 goto fail;
750
751 res = drm_crtc_init_with_planes(
752 dm->ddev,
753 &acrtc->base,
754 plane,
755 cursor_plane,
756 &amdgpu_dm_crtc_funcs, NULL);
757
758 if (res)
759 goto fail;
760
761 amdgpu_dm_ism_init(&acrtc->ism, &default_ism_config);
762
763 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
764
765 /* Create (reset) the plane state */
766 if (acrtc->base.funcs->reset)
767 acrtc->base.funcs->reset(&acrtc->base);
768
769 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
770 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
771
772 acrtc->crtc_id = crtc_index;
773 acrtc->base.enabled = false;
774 acrtc->otg_inst = -1;
775
776 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
777
778 /* Don't enable DRM CRTC degamma property for
779 * 1. DCE since it doesn't support programmable degamma anywhere.
780 * 2. DCN401 since pre-blending degamma LUT doesn't apply to cursor.
781 * Note: DEGAMMA properties are created even if the primary plane has the
782 * COLOR_PIPELINE property. User space can use either the DEGAMMA properties
783 * or the COLOR_PIPELINE property. An atomic commit which attempts to enable
784 * both is rejected.
785 */
786 has_degamma = dm->adev->dm.dc->caps.color.dpp.dcn_arch &&
787 dm->adev->dm.dc->ctx->dce_version != DCN_VERSION_4_01;
788
789 drm_crtc_enable_color_mgmt(&acrtc->base, has_degamma ? MAX_COLOR_LUT_ENTRIES : 0,
790 true, MAX_COLOR_LUT_ENTRIES);
791
792 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
793
794 #ifdef AMD_PRIVATE_COLOR
795 dm_crtc_additional_color_mgmt(&acrtc->base);
796 #endif
797 return 0;
798
799 fail:
800 kfree(acrtc);
801 kfree(cursor_plane);
802 return res;
803 }
804
805