1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Author: Lorenzo Bianconi <lorenzo@kernel.org> 4 * Author: Benjamin Larsson <benjamin.larsson@genexis.eu> 5 * Author: Markus Gothe <markus.gothe@genexis.eu> 6 */ 7 8 #ifndef __AIROHA_COMMON_HEADER__ 9 #define __AIROHA_COMMON_HEADER__ 10 11 #include <dt-bindings/pinctrl/mt65xx.h> 12 #include <linux/bitfield.h> 13 #include <linux/bits.h> 14 #include <linux/cleanup.h> 15 #include <linux/gpio/driver.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/irq.h> 19 #include <linux/irqdomain.h> 20 #include <linux/mfd/syscon.h> 21 #include <linux/of.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_platform.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/pinctrl/pinctrl.h> 26 #include <linux/pinctrl/pinconf.h> 27 #include <linux/pinctrl/pinconf-generic.h> 28 #include <linux/pinctrl/pinmux.h> 29 #include <linux/platform_device.h> 30 #include <linux/regmap.h> 31 #include <linux/types.h> 32 33 #include "../core.h" 34 #include "../pinconf.h" 35 #include "../pinmux.h" 36 37 #define AIROHA_NUM_PINS 64 38 #define AIROHA_PIN_BANK_SIZE (AIROHA_NUM_PINS / 2) 39 #define AIROHA_REG_GPIOCTRL_NUM_PIN (AIROHA_NUM_PINS / 4) 40 41 #define PINCTRL_PIN_GROUP(id, table) \ 42 PINCTRL_PINGROUP(id, table##_pins, ARRAY_SIZE(table##_pins)) 43 44 #define PINCTRL_FUNC_DESC(id, table) \ 45 { \ 46 .desc = PINCTRL_PINFUNCTION(id, table##_groups, \ 47 ARRAY_SIZE(table##_groups)),\ 48 .groups = table##_func_group, \ 49 .group_size = ARRAY_SIZE(table##_func_group), \ 50 } 51 52 #define PINCTRL_CONF_DESC(p, offset, mask) \ 53 { \ 54 .pin = p, \ 55 .reg = { offset, mask }, \ 56 } 57 58 struct airoha_pinctrl_reg { 59 u32 offset; 60 u32 mask; 61 }; 62 63 enum airoha_pinctrl_mux_func { 64 AIROHA_FUNC_MUX, 65 AIROHA_FUNC_PWM_MUX, 66 AIROHA_FUNC_PWM_EXT_MUX, 67 }; 68 69 struct airoha_pinctrl_func_group { 70 const char *name; 71 struct { 72 enum airoha_pinctrl_mux_func mux; 73 u32 offset; 74 u32 mask; 75 u32 val; 76 } regmap[2]; 77 int regmap_size; 78 }; 79 80 struct airoha_pinctrl_func { 81 const struct pinfunction desc; 82 const struct airoha_pinctrl_func_group *groups; 83 u8 group_size; 84 }; 85 86 struct airoha_pinctrl_conf { 87 u32 pin; 88 struct airoha_pinctrl_reg reg; 89 }; 90 91 struct airoha_gpiochip_regs { 92 /* gpio */ 93 const u32 *data; 94 const u32 *dir; 95 const u32 *out; 96 /* irq */ 97 const u32 *status; 98 const u32 *level; 99 const u32 *edge; 100 }; 101 102 struct airoha_pinctrl_confs_info { 103 const struct airoha_pinctrl_conf *confs; 104 unsigned int num_confs; 105 }; 106 107 enum airoha_pinctrl_confs_type { 108 AIROHA_PINCTRL_CONFS_PULLUP, 109 AIROHA_PINCTRL_CONFS_PULLDOWN, 110 AIROHA_PINCTRL_CONFS_DRIVE_E2, 111 AIROHA_PINCTRL_CONFS_DRIVE_E4, 112 AIROHA_PINCTRL_CONFS_PCIE_RST_OD, 113 114 AIROHA_PINCTRL_CONFS_MAX, 115 }; 116 117 struct airoha_pinctrl { 118 struct pinctrl_dev *ctrl; 119 120 struct pinctrl_desc desc; 121 const struct pingroup *grps; 122 const struct airoha_pinctrl_func *funcs; 123 const struct airoha_pinctrl_confs_info *confs_info; 124 125 struct regmap *chip_scu; 126 struct regmap *regmap; 127 128 struct gpio_chip gpiochip; 129 struct airoha_gpiochip_regs *gpio_regs; 130 }; 131 132 struct airoha_pinctrl_match_data { 133 const char *chip_scu_compatible; 134 const char *pinctrl_name; 135 struct module *pinctrl_owner; 136 const struct pinctrl_pin_desc *pins; 137 const unsigned int num_pins; 138 const struct pingroup *grps; 139 const unsigned int num_grps; 140 const struct airoha_pinctrl_func *funcs; 141 const unsigned int num_funcs; 142 const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX]; 143 }; 144 145 int airoha_pinctrl_probe(struct platform_device *pdev); 146 147 #endif 148