1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * ADXL345 3-Axis Digital Accelerometer 4 * 5 * Copyright (c) 2017 Eva Rachel Retuya <eraretuya@gmail.com> 6 */ 7 8 #ifndef _ADXL345_H_ 9 #define _ADXL345_H_ 10 11 #define ADXL345_REG_DEVID 0x00 12 #define ADXL345_REG_THRESH_TAP 0x1D 13 #define ADXL345_REG_OFSX 0x1E 14 #define ADXL345_REG_OFSY 0x1F 15 #define ADXL345_REG_OFSZ 0x20 16 #define ADXL345_REG_OFS_AXIS(index) (ADXL345_REG_OFSX + (index)) 17 18 /* Tap duration */ 19 #define ADXL345_REG_DUR 0x21 20 /* Tap latency */ 21 #define ADXL345_REG_LATENT 0x22 22 /* Tap window */ 23 #define ADXL345_REG_WINDOW 0x23 24 /* Activity threshold */ 25 #define ADXL345_REG_THRESH_ACT 0x24 26 /* Inactivity threshold */ 27 #define ADXL345_REG_THRESH_INACT 0x25 28 /* Inactivity time */ 29 #define ADXL345_REG_TIME_INACT 0x26 30 /* Axis enable control for activity and inactivity detection */ 31 #define ADXL345_REG_ACT_INACT_CTRL 0x27 32 /* Free-fall threshold */ 33 #define ADXL345_REG_THRESH_FF 0x28 34 /* Free-fall time */ 35 #define ADXL345_REG_TIME_FF 0x29 36 /* Axis control for single tap or double tap */ 37 #define ADXL345_REG_TAP_AXIS 0x2A 38 /* Source of single tap or double tap */ 39 #define ADXL345_REG_ACT_TAP_STATUS 0x2B 40 /* Data rate and power mode control */ 41 #define ADXL345_REG_BW_RATE 0x2C 42 #define ADXL345_REG_POWER_CTL 0x2D 43 #define ADXL345_REG_INT_ENABLE 0x2E 44 #define ADXL345_REG_INT_MAP 0x2F 45 #define ADXL345_REG_INT_SOURCE 0x30 46 #define ADXL345_REG_DATA_FORMAT 0x31 47 #define ADXL345_REG_XYZ_BASE 0x32 48 #define ADXL345_REG_DATA_AXIS(index) \ 49 (ADXL345_REG_XYZ_BASE + (index) * sizeof(__le16)) 50 51 #define ADXL345_REG_FIFO_CTL 0x38 52 #define ADXL345_FIFO_CTL_SAMPLES_MSK GENMASK(4, 0) 53 /* 0: INT1, 1: INT2 */ 54 #define ADXL345_FIFO_CTL_TRIGGER_MSK BIT(5) 55 #define ADXL345_FIFO_CTL_MODE_MSK GENMASK(7, 6) 56 #define ADXL345_REG_FIFO_STATUS 0x39 57 #define ADXL345_REG_FIFO_STATUS_MSK 0x3F 58 59 #define ADXL345_INT_OVERRUN BIT(0) 60 #define ADXL345_INT_WATERMARK BIT(1) 61 #define ADXL345_INT_FREE_FALL BIT(2) 62 #define ADXL345_INT_INACTIVITY BIT(3) 63 #define ADXL345_INT_ACTIVITY BIT(4) 64 #define ADXL345_INT_DOUBLE_TAP BIT(5) 65 #define ADXL345_INT_SINGLE_TAP BIT(6) 66 #define ADXL345_INT_DATA_READY BIT(7) 67 68 /* 69 * BW_RATE bits - Bandwidth and output data rate. The default value is 70 * 0x0A, which translates to a 100 Hz output data rate 71 */ 72 #define ADXL345_BW_RATE GENMASK(3, 0) 73 #define ADXL345_BW_LOW_POWER BIT(4) 74 #define ADXL345_BASE_RATE_NANO_HZ 97656250LL 75 76 #define ADXL345_POWER_CTL_STANDBY 0x00 77 #define ADXL345_POWER_CTL_WAKEUP GENMASK(1, 0) 78 #define ADXL345_POWER_CTL_SLEEP BIT(2) 79 #define ADXL345_POWER_CTL_MEASURE BIT(3) 80 #define ADXL345_POWER_CTL_AUTO_SLEEP BIT(4) 81 #define ADXL345_POWER_CTL_LINK BIT(5) 82 83 /* Set the g range */ 84 #define ADXL345_DATA_FORMAT_RANGE GENMASK(1, 0) 85 /* Data is left justified */ 86 #define ADXL345_DATA_FORMAT_JUSTIFY BIT(2) 87 /* Up to 13-bits resolution */ 88 #define ADXL345_DATA_FORMAT_FULL_RES BIT(3) 89 #define ADXL345_DATA_FORMAT_SPI_3WIRE BIT(6) 90 #define ADXL345_DATA_FORMAT_SELF_TEST BIT(7) 91 #define ADXL345_DATA_FORMAT_2G 0 92 #define ADXL345_DATA_FORMAT_4G 1 93 #define ADXL345_DATA_FORMAT_8G 2 94 #define ADXL345_DATA_FORMAT_16G 3 95 96 #define ADXL345_DEVID 0xE5 97 #define ADXL345_FIFO_SIZE 32 98 99 /* 100 * In full-resolution mode, scale factor is maintained at ~4 mg/LSB 101 * in all g ranges. 102 * 103 * At +/- 16g with 13-bit resolution, scale is computed as: 104 * (16 + 16) * 9.81 / (2^13 - 1) = 0.0383 105 */ 106 #define ADXL345_USCALE 38300 107 108 /* 109 * The Datasheet lists a resolution of Resolution is ~49 mg per LSB. That's 110 * ~480mm/s**2 per LSB. 111 */ 112 #define ADXL375_USCALE 480000 113 114 struct regmap; 115 116 bool adxl345_is_volatile_reg(struct device *dev, unsigned int reg); 117 118 struct adxl345_chip_info { 119 const char *name; 120 int uscale; 121 }; 122 123 int adxl345_core_probe(struct device *dev, struct regmap *regmap, 124 bool fifo_delay_default, 125 int (*setup)(struct device*, struct regmap*)); 126 127 #endif /* _ADXL345_H_ */ 128