1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * adux1020.c - Support for Analog Devices ADUX1020 photometric sensor
4 *
5 * Copyright (C) 2019 Linaro Ltd.
6 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
7 *
8 * TODO: Triggered buffer support
9 */
10
11 #include <linux/bitfield.h>
12 #include <linux/delay.h>
13 #include <linux/err.h>
14 #include <linux/i2c.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18 #include <linux/module.h>
19 #include <linux/mutex.h>
20 #include <linux/regmap.h>
21
22 #include <linux/iio/iio.h>
23 #include <linux/iio/sysfs.h>
24 #include <linux/iio/events.h>
25
26 #define ADUX1020_REGMAP_NAME "adux1020_regmap"
27 #define ADUX1020_DRV_NAME "adux1020"
28
29 /* System registers */
30 #define ADUX1020_REG_CHIP_ID 0x08
31 #define ADUX1020_REG_SLAVE_ADDRESS 0x09
32
33 #define ADUX1020_REG_SW_RESET 0x0f
34 #define ADUX1020_REG_INT_ENABLE 0x1c
35 #define ADUX1020_REG_INT_POLARITY 0x1d
36 #define ADUX1020_REG_PROX_TH_ON1 0x2a
37 #define ADUX1020_REG_PROX_TH_OFF1 0x2b
38 #define ADUX1020_REG_PROX_TYPE 0x2f
39 #define ADUX1020_REG_TEST_MODES_3 0x32
40 #define ADUX1020_REG_FORCE_MODE 0x33
41 #define ADUX1020_REG_FREQUENCY 0x40
42 #define ADUX1020_REG_LED_CURRENT 0x41
43 #define ADUX1020_REG_OP_MODE 0x45
44 #define ADUX1020_REG_INT_MASK 0x48
45 #define ADUX1020_REG_INT_STATUS 0x49
46 #define ADUX1020_REG_DATA_BUFFER 0x60
47
48 /* Chip ID bits */
49 #define ADUX1020_CHIP_ID_MASK GENMASK(11, 0)
50 #define ADUX1020_CHIP_ID 0x03fc
51
52 #define ADUX1020_SW_RESET BIT(1)
53 #define ADUX1020_FIFO_FLUSH BIT(15)
54 #define ADUX1020_OP_MODE_MASK GENMASK(3, 0)
55 #define ADUX1020_DATA_OUT_MODE_MASK GENMASK(7, 4)
56 #define ADUX1020_DATA_OUT_PROX_I FIELD_PREP(ADUX1020_DATA_OUT_MODE_MASK, 1)
57
58 #define ADUX1020_MODE_INT_MASK GENMASK(7, 0)
59 #define ADUX1020_INT_ENABLE 0x2094
60 #define ADUX1020_INT_DISABLE 0x2090
61 #define ADUX1020_PROX_INT_ENABLE 0x00f0
62 #define ADUX1020_PROX_ON1_INT BIT(0)
63 #define ADUX1020_PROX_OFF1_INT BIT(1)
64 #define ADUX1020_FIFO_INT_ENABLE 0x7f
65 #define ADUX1020_MODE_INT_DISABLE 0xff
66 #define ADUX1020_MODE_INT_STATUS_MASK GENMASK(7, 0)
67 #define ADUX1020_FIFO_STATUS_MASK GENMASK(15, 8)
68 #define ADUX1020_INT_CLEAR 0xff
69 #define ADUX1020_PROX_TYPE BIT(15)
70
71 #define ADUX1020_INT_PROX_ON1 BIT(0)
72 #define ADUX1020_INT_PROX_OFF1 BIT(1)
73
74 #define ADUX1020_FORCE_CLOCK_ON 0x0f4f
75 #define ADUX1020_FORCE_CLOCK_RESET 0x0040
76 #define ADUX1020_ACTIVE_4_STATE 0x0008
77
78 #define ADUX1020_PROX_FREQ_MASK GENMASK(7, 4)
79 #define ADUX1020_PROX_FREQ(x) FIELD_PREP(ADUX1020_PROX_FREQ_MASK, x)
80
81 #define ADUX1020_LED_CURRENT_MASK GENMASK(3, 0)
82 #define ADUX1020_LED_PIREF_EN BIT(12)
83
84 /* Operating modes */
85 enum adux1020_op_modes {
86 ADUX1020_MODE_STANDBY,
87 ADUX1020_MODE_PROX_I,
88 ADUX1020_MODE_PROX_XY,
89 ADUX1020_MODE_GEST,
90 ADUX1020_MODE_SAMPLE,
91 ADUX1020_MODE_FORCE = 0x0e,
92 ADUX1020_MODE_IDLE = 0x0f,
93 };
94
95 struct adux1020_data {
96 struct i2c_client *client;
97 struct iio_dev *indio_dev;
98 struct mutex lock;
99 struct regmap *regmap;
100 };
101
102 struct adux1020_mode_data {
103 u8 bytes;
104 u8 buf_len;
105 u16 int_en;
106 };
107
108 static const struct adux1020_mode_data adux1020_modes[] = {
109 [ADUX1020_MODE_PROX_I] = {
110 .bytes = 2,
111 .buf_len = 1,
112 .int_en = ADUX1020_PROX_INT_ENABLE,
113 },
114 };
115
116 static const struct regmap_config adux1020_regmap_config = {
117 .name = ADUX1020_REGMAP_NAME,
118 .reg_bits = 8,
119 .val_bits = 16,
120 .max_register = 0x6F,
121 };
122
123 static const struct reg_sequence adux1020_def_conf[] = {
124 { 0x000c, 0x000f },
125 { 0x0010, 0x1010 },
126 { 0x0011, 0x004c },
127 { 0x0012, 0x5f0c },
128 { 0x0013, 0xada5 },
129 { 0x0014, 0x0080 },
130 { 0x0015, 0x0000 },
131 { 0x0016, 0x0600 },
132 { 0x0017, 0x0000 },
133 { 0x0018, 0x2693 },
134 { 0x0019, 0x0004 },
135 { 0x001a, 0x4280 },
136 { 0x001b, 0x0060 },
137 { 0x001c, 0x2094 },
138 { 0x001d, 0x0020 },
139 { 0x001e, 0x0001 },
140 { 0x001f, 0x0100 },
141 { 0x0020, 0x0320 },
142 { 0x0021, 0x0A13 },
143 { 0x0022, 0x0320 },
144 { 0x0023, 0x0113 },
145 { 0x0024, 0x0000 },
146 { 0x0025, 0x2412 },
147 { 0x0026, 0x2412 },
148 { 0x0027, 0x0022 },
149 { 0x0028, 0x0000 },
150 { 0x0029, 0x0300 },
151 { 0x002a, 0x0700 },
152 { 0x002b, 0x0600 },
153 { 0x002c, 0x6000 },
154 { 0x002d, 0x4000 },
155 { 0x002e, 0x0000 },
156 { 0x002f, 0x0000 },
157 { 0x0030, 0x0000 },
158 { 0x0031, 0x0000 },
159 { 0x0032, 0x0040 },
160 { 0x0033, 0x0008 },
161 { 0x0034, 0xE400 },
162 { 0x0038, 0x8080 },
163 { 0x0039, 0x8080 },
164 { 0x003a, 0x2000 },
165 { 0x003b, 0x1f00 },
166 { 0x003c, 0x2000 },
167 { 0x003d, 0x2000 },
168 { 0x003e, 0x0000 },
169 { 0x0040, 0x8069 },
170 { 0x0041, 0x1f2f },
171 { 0x0042, 0x4000 },
172 { 0x0043, 0x0000 },
173 { 0x0044, 0x0008 },
174 { 0x0046, 0x0000 },
175 { 0x0048, 0x00ef },
176 { 0x0049, 0x0000 },
177 { 0x0045, 0x0000 },
178 };
179
180 static const int adux1020_rates[][2] = {
181 { 0, 100000 },
182 { 0, 200000 },
183 { 0, 500000 },
184 { 1, 0 },
185 { 2, 0 },
186 { 5, 0 },
187 { 10, 0 },
188 { 20, 0 },
189 { 50, 0 },
190 { 100, 0 },
191 { 190, 0 },
192 { 450, 0 },
193 { 820, 0 },
194 { 1400, 0 },
195 };
196
197 static const int adux1020_led_currents[][2] = {
198 { 0, 25000 },
199 { 0, 40000 },
200 { 0, 55000 },
201 { 0, 70000 },
202 { 0, 85000 },
203 { 0, 100000 },
204 { 0, 115000 },
205 { 0, 130000 },
206 { 0, 145000 },
207 { 0, 160000 },
208 { 0, 175000 },
209 { 0, 190000 },
210 { 0, 205000 },
211 { 0, 220000 },
212 { 0, 235000 },
213 { 0, 250000 },
214 };
215
adux1020_flush_fifo(struct adux1020_data * data)216 static int adux1020_flush_fifo(struct adux1020_data *data)
217 {
218 int ret;
219
220 /* Force Idle mode */
221 ret = regmap_write(data->regmap, ADUX1020_REG_FORCE_MODE,
222 ADUX1020_ACTIVE_4_STATE);
223 if (ret < 0)
224 return ret;
225
226 ret = regmap_update_bits(data->regmap, ADUX1020_REG_OP_MODE,
227 ADUX1020_OP_MODE_MASK, ADUX1020_MODE_FORCE);
228 if (ret < 0)
229 return ret;
230
231 ret = regmap_update_bits(data->regmap, ADUX1020_REG_OP_MODE,
232 ADUX1020_OP_MODE_MASK, ADUX1020_MODE_IDLE);
233 if (ret < 0)
234 return ret;
235
236 /* Flush FIFO */
237 ret = regmap_write(data->regmap, ADUX1020_REG_TEST_MODES_3,
238 ADUX1020_FORCE_CLOCK_ON);
239 if (ret < 0)
240 return ret;
241
242 ret = regmap_write(data->regmap, ADUX1020_REG_INT_STATUS,
243 ADUX1020_FIFO_FLUSH);
244 if (ret < 0)
245 return ret;
246
247 return regmap_write(data->regmap, ADUX1020_REG_TEST_MODES_3,
248 ADUX1020_FORCE_CLOCK_RESET);
249 }
250
adux1020_read_fifo(struct adux1020_data * data,u16 * buf,u8 buf_len)251 static int adux1020_read_fifo(struct adux1020_data *data, u16 *buf, u8 buf_len)
252 {
253 unsigned int regval;
254 int i, ret;
255
256 /* Enable 32MHz clock */
257 ret = regmap_write(data->regmap, ADUX1020_REG_TEST_MODES_3,
258 ADUX1020_FORCE_CLOCK_ON);
259 if (ret < 0)
260 return ret;
261
262 for (i = 0; i < buf_len; i++) {
263 ret = regmap_read(data->regmap, ADUX1020_REG_DATA_BUFFER,
264 ®val);
265 if (ret < 0)
266 return ret;
267
268 buf[i] = regval;
269 }
270
271 /* Set 32MHz clock to be controlled by internal state machine */
272 return regmap_write(data->regmap, ADUX1020_REG_TEST_MODES_3,
273 ADUX1020_FORCE_CLOCK_RESET);
274 }
275
adux1020_set_mode(struct adux1020_data * data,enum adux1020_op_modes mode)276 static int adux1020_set_mode(struct adux1020_data *data,
277 enum adux1020_op_modes mode)
278 {
279 int ret;
280
281 /* Switch to standby mode before changing the mode */
282 ret = regmap_write(data->regmap, ADUX1020_REG_OP_MODE,
283 ADUX1020_MODE_STANDBY);
284 if (ret < 0)
285 return ret;
286
287 /* Set data out and switch to the desired mode */
288 switch (mode) {
289 case ADUX1020_MODE_PROX_I:
290 ret = regmap_update_bits(data->regmap, ADUX1020_REG_OP_MODE,
291 ADUX1020_DATA_OUT_MODE_MASK,
292 ADUX1020_DATA_OUT_PROX_I);
293 if (ret < 0)
294 return ret;
295
296 ret = regmap_update_bits(data->regmap, ADUX1020_REG_OP_MODE,
297 ADUX1020_OP_MODE_MASK,
298 ADUX1020_MODE_PROX_I);
299 if (ret < 0)
300 return ret;
301 break;
302 default:
303 return -EINVAL;
304 }
305
306 return 0;
307 }
308
adux1020_measure(struct adux1020_data * data,enum adux1020_op_modes mode,u16 * val)309 static int adux1020_measure(struct adux1020_data *data,
310 enum adux1020_op_modes mode,
311 u16 *val)
312 {
313 unsigned int status;
314 int ret, tries = 50;
315
316 /* Disable INT pin as polling is going to be used */
317 ret = regmap_write(data->regmap, ADUX1020_REG_INT_ENABLE,
318 ADUX1020_INT_DISABLE);
319 if (ret < 0)
320 return ret;
321
322 /* Enable mode interrupt */
323 ret = regmap_update_bits(data->regmap, ADUX1020_REG_INT_MASK,
324 ADUX1020_MODE_INT_MASK,
325 adux1020_modes[mode].int_en);
326 if (ret < 0)
327 return ret;
328
329 while (tries--) {
330 ret = regmap_read(data->regmap, ADUX1020_REG_INT_STATUS,
331 &status);
332 if (ret < 0)
333 return ret;
334
335 status &= ADUX1020_FIFO_STATUS_MASK;
336 if (status >= adux1020_modes[mode].bytes)
337 break;
338 msleep(20);
339 }
340
341 if (tries < 0)
342 return -EIO;
343
344 ret = adux1020_read_fifo(data, val, adux1020_modes[mode].buf_len);
345 if (ret < 0)
346 return ret;
347
348 /* Clear mode interrupt */
349 ret = regmap_write(data->regmap, ADUX1020_REG_INT_STATUS,
350 (~adux1020_modes[mode].int_en));
351 if (ret < 0)
352 return ret;
353
354 /* Disable mode interrupts */
355 return regmap_update_bits(data->regmap, ADUX1020_REG_INT_MASK,
356 ADUX1020_MODE_INT_MASK,
357 ADUX1020_MODE_INT_DISABLE);
358 }
359
adux1020_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)360 static int adux1020_read_raw(struct iio_dev *indio_dev,
361 struct iio_chan_spec const *chan,
362 int *val, int *val2, long mask)
363 {
364 struct adux1020_data *data = iio_priv(indio_dev);
365 u16 buf[3];
366 int ret = -EINVAL;
367 unsigned int regval;
368
369 mutex_lock(&data->lock);
370
371 switch (mask) {
372 case IIO_CHAN_INFO_RAW:
373 switch (chan->type) {
374 case IIO_PROXIMITY:
375 ret = adux1020_set_mode(data, ADUX1020_MODE_PROX_I);
376 if (ret < 0)
377 goto fail;
378
379 ret = adux1020_measure(data, ADUX1020_MODE_PROX_I, buf);
380 if (ret < 0)
381 goto fail;
382
383 *val = buf[0];
384 ret = IIO_VAL_INT;
385 break;
386 default:
387 break;
388 }
389 break;
390 case IIO_CHAN_INFO_PROCESSED:
391 switch (chan->type) {
392 case IIO_CURRENT:
393 ret = regmap_read(data->regmap,
394 ADUX1020_REG_LED_CURRENT, ®val);
395 if (ret < 0)
396 goto fail;
397
398 regval = regval & ADUX1020_LED_CURRENT_MASK;
399
400 *val = adux1020_led_currents[regval][0];
401 *val2 = adux1020_led_currents[regval][1];
402
403 ret = IIO_VAL_INT_PLUS_MICRO;
404 break;
405 default:
406 break;
407 }
408 break;
409 case IIO_CHAN_INFO_SAMP_FREQ:
410 switch (chan->type) {
411 case IIO_PROXIMITY:
412 ret = regmap_read(data->regmap, ADUX1020_REG_FREQUENCY,
413 ®val);
414 if (ret < 0)
415 goto fail;
416
417 regval = FIELD_GET(ADUX1020_PROX_FREQ_MASK, regval);
418
419 *val = adux1020_rates[regval][0];
420 *val2 = adux1020_rates[regval][1];
421
422 ret = IIO_VAL_INT_PLUS_MICRO;
423 break;
424 default:
425 break;
426 }
427 break;
428 default:
429 break;
430 }
431
432 fail:
433 mutex_unlock(&data->lock);
434
435 return ret;
436 };
437
adux1020_find_index(const int array[][2],int count,int val,int val2)438 static inline int adux1020_find_index(const int array[][2], int count, int val,
439 int val2)
440 {
441 int i;
442
443 for (i = 0; i < count; i++)
444 if (val == array[i][0] && val2 == array[i][1])
445 return i;
446
447 return -EINVAL;
448 }
449
adux1020_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)450 static int adux1020_write_raw(struct iio_dev *indio_dev,
451 struct iio_chan_spec const *chan,
452 int val, int val2, long mask)
453 {
454 struct adux1020_data *data = iio_priv(indio_dev);
455 int i, ret = -EINVAL;
456
457 mutex_lock(&data->lock);
458
459 switch (mask) {
460 case IIO_CHAN_INFO_SAMP_FREQ:
461 if (chan->type == IIO_PROXIMITY) {
462 i = adux1020_find_index(adux1020_rates,
463 ARRAY_SIZE(adux1020_rates),
464 val, val2);
465 if (i < 0) {
466 ret = i;
467 goto fail;
468 }
469
470 ret = regmap_update_bits(data->regmap,
471 ADUX1020_REG_FREQUENCY,
472 ADUX1020_PROX_FREQ_MASK,
473 ADUX1020_PROX_FREQ(i));
474 }
475 break;
476 case IIO_CHAN_INFO_PROCESSED:
477 if (chan->type == IIO_CURRENT) {
478 i = adux1020_find_index(adux1020_led_currents,
479 ARRAY_SIZE(adux1020_led_currents),
480 val, val2);
481 if (i < 0) {
482 ret = i;
483 goto fail;
484 }
485
486 ret = regmap_update_bits(data->regmap,
487 ADUX1020_REG_LED_CURRENT,
488 ADUX1020_LED_CURRENT_MASK, i);
489 }
490 break;
491 default:
492 break;
493 }
494
495 fail:
496 mutex_unlock(&data->lock);
497
498 return ret;
499 }
500
adux1020_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,bool state)501 static int adux1020_write_event_config(struct iio_dev *indio_dev,
502 const struct iio_chan_spec *chan,
503 enum iio_event_type type,
504 enum iio_event_direction dir,
505 bool state)
506 {
507 struct adux1020_data *data = iio_priv(indio_dev);
508 int ret, mask;
509
510 mutex_lock(&data->lock);
511
512 ret = regmap_write(data->regmap, ADUX1020_REG_INT_ENABLE,
513 ADUX1020_INT_ENABLE);
514 if (ret < 0)
515 goto fail;
516
517 ret = regmap_write(data->regmap, ADUX1020_REG_INT_POLARITY, 0);
518 if (ret < 0)
519 goto fail;
520
521 switch (chan->type) {
522 case IIO_PROXIMITY:
523 if (dir == IIO_EV_DIR_RISING)
524 mask = ADUX1020_PROX_ON1_INT;
525 else
526 mask = ADUX1020_PROX_OFF1_INT;
527
528 if (state)
529 ret = regmap_clear_bits(data->regmap,
530 ADUX1020_REG_INT_MASK, mask);
531 else
532 ret = regmap_set_bits(data->regmap,
533 ADUX1020_REG_INT_MASK, mask);
534 if (ret < 0)
535 goto fail;
536
537 /*
538 * Trigger proximity interrupt when the intensity is above
539 * or below threshold
540 */
541 ret = regmap_set_bits(data->regmap, ADUX1020_REG_PROX_TYPE,
542 ADUX1020_PROX_TYPE);
543 if (ret < 0)
544 goto fail;
545
546 /* Set proximity mode */
547 ret = adux1020_set_mode(data, ADUX1020_MODE_PROX_I);
548 break;
549 default:
550 ret = -EINVAL;
551 break;
552 }
553
554 fail:
555 mutex_unlock(&data->lock);
556
557 return ret;
558 }
559
adux1020_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)560 static int adux1020_read_event_config(struct iio_dev *indio_dev,
561 const struct iio_chan_spec *chan,
562 enum iio_event_type type,
563 enum iio_event_direction dir)
564 {
565 struct adux1020_data *data = iio_priv(indio_dev);
566 int ret, mask;
567 unsigned int regval;
568
569 switch (chan->type) {
570 case IIO_PROXIMITY:
571 if (dir == IIO_EV_DIR_RISING)
572 mask = ADUX1020_PROX_ON1_INT;
573 else
574 mask = ADUX1020_PROX_OFF1_INT;
575 break;
576 default:
577 return -EINVAL;
578 }
579
580 ret = regmap_read(data->regmap, ADUX1020_REG_INT_MASK, ®val);
581 if (ret < 0)
582 return ret;
583
584 return !(regval & mask);
585 }
586
adux1020_read_thresh(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)587 static int adux1020_read_thresh(struct iio_dev *indio_dev,
588 const struct iio_chan_spec *chan,
589 enum iio_event_type type,
590 enum iio_event_direction dir,
591 enum iio_event_info info, int *val, int *val2)
592 {
593 struct adux1020_data *data = iio_priv(indio_dev);
594 u8 reg;
595 int ret;
596 unsigned int regval;
597
598 switch (chan->type) {
599 case IIO_PROXIMITY:
600 if (dir == IIO_EV_DIR_RISING)
601 reg = ADUX1020_REG_PROX_TH_ON1;
602 else
603 reg = ADUX1020_REG_PROX_TH_OFF1;
604 break;
605 default:
606 return -EINVAL;
607 }
608
609 ret = regmap_read(data->regmap, reg, ®val);
610 if (ret < 0)
611 return ret;
612
613 *val = regval;
614
615 return IIO_VAL_INT;
616 }
617
adux1020_write_thresh(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)618 static int adux1020_write_thresh(struct iio_dev *indio_dev,
619 const struct iio_chan_spec *chan,
620 enum iio_event_type type,
621 enum iio_event_direction dir,
622 enum iio_event_info info, int val, int val2)
623 {
624 struct adux1020_data *data = iio_priv(indio_dev);
625 u8 reg;
626
627 switch (chan->type) {
628 case IIO_PROXIMITY:
629 if (dir == IIO_EV_DIR_RISING)
630 reg = ADUX1020_REG_PROX_TH_ON1;
631 else
632 reg = ADUX1020_REG_PROX_TH_OFF1;
633 break;
634 default:
635 return -EINVAL;
636 }
637
638 /* Full scale threshold value is 0-65535 */
639 if (val < 0 || val > 65535)
640 return -EINVAL;
641
642 return regmap_write(data->regmap, reg, val);
643 }
644
645 static const struct iio_event_spec adux1020_proximity_event[] = {
646 {
647 .type = IIO_EV_TYPE_THRESH,
648 .dir = IIO_EV_DIR_RISING,
649 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
650 BIT(IIO_EV_INFO_ENABLE),
651 },
652 {
653 .type = IIO_EV_TYPE_THRESH,
654 .dir = IIO_EV_DIR_FALLING,
655 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
656 BIT(IIO_EV_INFO_ENABLE),
657 },
658 };
659
660 static const struct iio_chan_spec adux1020_channels[] = {
661 {
662 .type = IIO_PROXIMITY,
663 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
664 BIT(IIO_CHAN_INFO_SAMP_FREQ),
665 .event_spec = adux1020_proximity_event,
666 .num_event_specs = ARRAY_SIZE(adux1020_proximity_event),
667 },
668 {
669 .type = IIO_CURRENT,
670 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
671 .extend_name = "led",
672 .output = 1,
673 },
674 };
675
676 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
677 "0.1 0.2 0.5 1 2 5 10 20 50 100 190 450 820 1400");
678
679 static struct attribute *adux1020_attributes[] = {
680 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
681 NULL
682 };
683
684 static const struct attribute_group adux1020_attribute_group = {
685 .attrs = adux1020_attributes,
686 };
687
688 static const struct iio_info adux1020_info = {
689 .attrs = &adux1020_attribute_group,
690 .read_raw = adux1020_read_raw,
691 .write_raw = adux1020_write_raw,
692 .read_event_config = adux1020_read_event_config,
693 .write_event_config = adux1020_write_event_config,
694 .read_event_value = adux1020_read_thresh,
695 .write_event_value = adux1020_write_thresh,
696 };
697
adux1020_interrupt_handler(int irq,void * private)698 static irqreturn_t adux1020_interrupt_handler(int irq, void *private)
699 {
700 struct iio_dev *indio_dev = private;
701 struct adux1020_data *data = iio_priv(indio_dev);
702 int ret, status;
703
704 ret = regmap_read(data->regmap, ADUX1020_REG_INT_STATUS, &status);
705 if (ret < 0)
706 return IRQ_HANDLED;
707
708 status &= ADUX1020_MODE_INT_STATUS_MASK;
709
710 if (status & ADUX1020_INT_PROX_ON1) {
711 iio_push_event(indio_dev,
712 IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, 0,
713 IIO_EV_TYPE_THRESH,
714 IIO_EV_DIR_RISING),
715 iio_get_time_ns(indio_dev));
716 }
717
718 if (status & ADUX1020_INT_PROX_OFF1) {
719 iio_push_event(indio_dev,
720 IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, 0,
721 IIO_EV_TYPE_THRESH,
722 IIO_EV_DIR_FALLING),
723 iio_get_time_ns(indio_dev));
724 }
725
726 regmap_update_bits(data->regmap, ADUX1020_REG_INT_STATUS,
727 ADUX1020_MODE_INT_MASK, ADUX1020_INT_CLEAR);
728
729 return IRQ_HANDLED;
730 }
731
adux1020_chip_init(struct adux1020_data * data)732 static int adux1020_chip_init(struct adux1020_data *data)
733 {
734 struct i2c_client *client = data->client;
735 int ret;
736 unsigned int val;
737
738 ret = regmap_read(data->regmap, ADUX1020_REG_CHIP_ID, &val);
739 if (ret < 0)
740 return ret;
741
742 if ((val & ADUX1020_CHIP_ID_MASK) != ADUX1020_CHIP_ID) {
743 dev_err(&client->dev, "invalid chip id 0x%04x\n", val);
744 return -ENODEV;
745 }
746
747 dev_dbg(&client->dev, "Detected ADUX1020 with chip id: 0x%04x\n", val);
748
749 ret = regmap_set_bits(data->regmap, ADUX1020_REG_SW_RESET,
750 ADUX1020_SW_RESET);
751 if (ret < 0)
752 return ret;
753
754 /* Load default configuration */
755 ret = regmap_multi_reg_write(data->regmap, adux1020_def_conf,
756 ARRAY_SIZE(adux1020_def_conf));
757 if (ret < 0)
758 return ret;
759
760 ret = adux1020_flush_fifo(data);
761 if (ret < 0)
762 return ret;
763
764 /* Use LED_IREF for proximity mode */
765 ret = regmap_clear_bits(data->regmap, ADUX1020_REG_LED_CURRENT,
766 ADUX1020_LED_PIREF_EN);
767 if (ret < 0)
768 return ret;
769
770 /* Mask all interrupts */
771 return regmap_update_bits(data->regmap, ADUX1020_REG_INT_MASK,
772 ADUX1020_MODE_INT_MASK, ADUX1020_MODE_INT_DISABLE);
773 }
774
adux1020_probe(struct i2c_client * client)775 static int adux1020_probe(struct i2c_client *client)
776 {
777 struct adux1020_data *data;
778 struct iio_dev *indio_dev;
779 int ret;
780
781 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
782 if (!indio_dev)
783 return -ENOMEM;
784
785 indio_dev->info = &adux1020_info;
786 indio_dev->name = ADUX1020_DRV_NAME;
787 indio_dev->channels = adux1020_channels;
788 indio_dev->num_channels = ARRAY_SIZE(adux1020_channels);
789 indio_dev->modes = INDIO_DIRECT_MODE;
790
791 data = iio_priv(indio_dev);
792
793 data->regmap = devm_regmap_init_i2c(client, &adux1020_regmap_config);
794 if (IS_ERR(data->regmap)) {
795 dev_err(&client->dev, "regmap initialization failed.\n");
796 return PTR_ERR(data->regmap);
797 }
798
799 data->client = client;
800 data->indio_dev = indio_dev;
801 mutex_init(&data->lock);
802
803 ret = adux1020_chip_init(data);
804 if (ret)
805 return ret;
806
807 if (client->irq) {
808 ret = devm_request_threaded_irq(&client->dev, client->irq,
809 NULL, adux1020_interrupt_handler,
810 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
811 ADUX1020_DRV_NAME, indio_dev);
812 if (ret) {
813 dev_err(&client->dev, "irq request error %d\n", -ret);
814 return ret;
815 }
816 }
817
818 return devm_iio_device_register(&client->dev, indio_dev);
819 }
820
821 static const struct i2c_device_id adux1020_id[] = {
822 { "adux1020" },
823 { }
824 };
825 MODULE_DEVICE_TABLE(i2c, adux1020_id);
826
827 static const struct of_device_id adux1020_of_match[] = {
828 { .compatible = "adi,adux1020" },
829 { }
830 };
831 MODULE_DEVICE_TABLE(of, adux1020_of_match);
832
833 static struct i2c_driver adux1020_driver = {
834 .driver = {
835 .name = ADUX1020_DRV_NAME,
836 .of_match_table = adux1020_of_match,
837 },
838 .probe = adux1020_probe,
839 .id_table = adux1020_id,
840 };
841 module_i2c_driver(adux1020_driver);
842
843 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
844 MODULE_DESCRIPTION("ADUX1020 photometric sensor");
845 MODULE_LICENSE("GPL");
846