1<?xml version="1.0" encoding="UTF-8"?> 2<database xmlns="http://nouveau.freedesktop.org/" 3xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" 4xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> 5<import file="freedreno_copyright.xml"/> 6 7<enum name="chip" bare="yes"> 8 <value name="A2XX" value="2"/> 9 <value name="A3XX" value="3"/> 10 <value name="A4XX" value="4"/> 11 <value name="A5XX" value="5"/> 12 <value name="A6XX" value="6"/> 13 <value name="A7XX" value="7"/> 14 <value name="A8XX" value="8"/> 15</enum> 16 17<enum name="adreno_pa_su_sc_draw"> 18 <value name="PC_DRAW_POINTS" value="0"/> 19 <value name="PC_DRAW_LINES" value="1"/> 20 <value name="PC_DRAW_TRIANGLES" value="2"/> 21</enum> 22 23<enum name="adreno_compare_func"> 24 <value name="FUNC_NEVER" value="0"/> 25 <value name="FUNC_LESS" value="1"/> 26 <value name="FUNC_EQUAL" value="2"/> 27 <value name="FUNC_LEQUAL" value="3"/> 28 <value name="FUNC_GREATER" value="4"/> 29 <value name="FUNC_NOTEQUAL" value="5"/> 30 <value name="FUNC_GEQUAL" value="6"/> 31 <value name="FUNC_ALWAYS" value="7"/> 32</enum> 33 34<enum name="adreno_stencil_op"> 35 <value name="STENCIL_KEEP" value="0"/> 36 <value name="STENCIL_ZERO" value="1"/> 37 <value name="STENCIL_REPLACE" value="2"/> 38 <value name="STENCIL_INCR_CLAMP" value="3"/> 39 <value name="STENCIL_DECR_CLAMP" value="4"/> 40 <value name="STENCIL_INVERT" value="5"/> 41 <value name="STENCIL_INCR_WRAP" value="6"/> 42 <value name="STENCIL_DECR_WRAP" value="7"/> 43</enum> 44 45<enum name="adreno_rb_blend_factor"> 46 <value name="FACTOR_ZERO" value="0"/> 47 <value name="FACTOR_ONE" value="1"/> 48 <value name="FACTOR_SRC_COLOR" value="4"/> 49 <value name="FACTOR_ONE_MINUS_SRC_COLOR" value="5"/> 50 <value name="FACTOR_SRC_ALPHA" value="6"/> 51 <value name="FACTOR_ONE_MINUS_SRC_ALPHA" value="7"/> 52 <value name="FACTOR_DST_COLOR" value="8"/> 53 <value name="FACTOR_ONE_MINUS_DST_COLOR" value="9"/> 54 <value name="FACTOR_DST_ALPHA" value="10"/> 55 <value name="FACTOR_ONE_MINUS_DST_ALPHA" value="11"/> 56 <value name="FACTOR_CONSTANT_COLOR" value="12"/> 57 <value name="FACTOR_ONE_MINUS_CONSTANT_COLOR" value="13"/> 58 <value name="FACTOR_CONSTANT_ALPHA" value="14"/> 59 <value name="FACTOR_ONE_MINUS_CONSTANT_ALPHA" value="15"/> 60 <value name="FACTOR_SRC_ALPHA_SATURATE" value="16"/> 61 <value name="FACTOR_SRC1_COLOR" value="20"/> 62 <value name="FACTOR_ONE_MINUS_SRC1_COLOR" value="21"/> 63 <value name="FACTOR_SRC1_ALPHA" value="22"/> 64 <value name="FACTOR_ONE_MINUS_SRC1_ALPHA" value="23"/> 65</enum> 66 67<bitset name="adreno_rb_stencilrefmask" inline="yes"> 68 <bitfield name="STENCILREF" low="0" high="7" type="hex"/> 69 <bitfield name="STENCILMASK" low="8" high="15" type="hex"/> 70 <bitfield name="STENCILWRITEMASK" low="16" high="23" type="hex"/> 71</bitset> 72 73<enum name="adreno_rb_surface_endian"> 74 <value name="ENDIAN_NONE" value="0"/> 75 <value name="ENDIAN_8IN16" value="1"/> 76 <value name="ENDIAN_8IN32" value="2"/> 77 <value name="ENDIAN_16IN32" value="3"/> 78 <value name="ENDIAN_8IN64" value="4"/> 79 <value name="ENDIAN_8IN128" value="5"/> 80</enum> 81 82<enum name="adreno_rb_dither_mode"> 83 <value name="DITHER_DISABLE" value="0"/> 84 <value name="DITHER_ALWAYS" value="1"/> 85 <value name="DITHER_IF_ALPHA_OFF" value="2"/> 86</enum> 87 88<enum name="adreno_rb_depth_format"> 89 <value name="DEPTHX_16" value="0"/> 90 <value name="DEPTHX_24_8" value="1"/> 91 <value name="DEPTHX_32" value="2"/> 92</enum> 93 94<enum name="adreno_rb_copy_control_mode"> 95 <value name="RB_COPY_RESOLVE" value="1"/> 96 <value name="RB_COPY_CLEAR" value="2"/> 97 <value name="RB_COPY_DEPTH_STENCIL" value="5"/> <!-- not sure if this is part of MODE or another bitfield?? --> 98</enum> 99 100<bitset name="adreno_reg_xy" inline="yes"> 101 <bitfield name="WINDOW_OFFSET_DISABLE" pos="31" type="boolean"/> 102 <bitfield name="X" low="0" high="14" type="uint"/> 103 <bitfield name="Y" low="16" high="30" type="uint"/> 104</bitset> 105 106<bitset name="adreno_cp_protect" inline="yes"> 107 <bitfield name="BASE_ADDR" low="0" high="16"/> 108 <bitfield name="MASK_LEN" low="24" high="28"/> 109 <bitfield name="TRAP_WRITE" pos="29"/> 110 <bitfield name="TRAP_READ" pos="30"/> 111</bitset> 112 113<domain name="AXXX" width="32"> 114 <brief>Registers in common between a2xx and a3xx</brief> 115 116 <reg32 offset="0x01c0" name="CP_RB_BASE"/> 117 <reg32 offset="0x01c1" name="CP_RB_CNTL"> 118 <bitfield name="BUFSZ" low="0" high="5"/> 119 <bitfield name="BLKSZ" low="8" high="13"/> 120 <bitfield name="BUF_SWAP" low="16" high="17"/> 121 <bitfield name="POLL_EN" pos="20" type="boolean"/> 122 <bitfield name="NO_UPDATE" pos="27" type="boolean"/> 123 <bitfield name="RPTR_WR_EN" pos="31" type="boolean"/> 124 </reg32> 125 <reg32 offset="0x01c3" name="CP_RB_RPTR_ADDR"> 126 <bitfield name="SWAP" low="0" high="1" type="uint"/> 127 <bitfield name="ADDR" low="2" high="31" shr="2"/> 128 </reg32> 129 <reg32 offset="0x01c4" name="CP_RB_RPTR" type="uint"/> 130 <reg32 offset="0x01c5" name="CP_RB_WPTR" type="uint"/> 131 <reg32 offset="0x01c6" name="CP_RB_WPTR_DELAY"/> 132 <reg32 offset="0x01c7" name="CP_RB_RPTR_WR"/> 133 <reg32 offset="0x01c8" name="CP_RB_WPTR_BASE"/> 134 <reg32 offset="0x01d5" name="CP_QUEUE_THRESHOLDS"> 135 <bitfield name="CSQ_IB1_START" low="0" high="3" type="uint"/> 136 <bitfield name="CSQ_IB2_START" low="8" high="11" type="uint"/> 137 <bitfield name="CSQ_ST_START" low="16" high="19" type="uint"/> 138 </reg32> 139 <reg32 offset="0x01d6" name="CP_MEQ_THRESHOLDS"> 140 <bitfield name="MEQ_END" low="16" high="20" type="uint"/> 141 <bitfield name="ROQ_END" low="24" high="28" type="uint"/> 142 </reg32> 143 <reg32 offset="0x01d7" name="CP_CSQ_AVAIL"> 144 <bitfield name="RING" low="0" high="6" type="uint"/> 145 <bitfield name="IB1" low="8" high="14" type="uint"/> 146 <bitfield name="IB2" low="16" high="22" type="uint"/> 147 </reg32> 148 <reg32 offset="0x01d8" name="CP_STQ_AVAIL"> 149 <bitfield name="ST" low="0" high="6" type="uint"/> 150 </reg32> 151 <reg32 offset="0x01d9" name="CP_MEQ_AVAIL"> 152 <bitfield name="MEQ" low="0" high="4" type="uint"/> 153 </reg32> 154 <reg32 offset="0x01dc" name="SCRATCH_UMSK"> 155 <bitfield name="UMSK" low="0" high="7" type="uint"/> 156 <bitfield name="SWAP" low="16" high="17" type="uint"/> 157 </reg32> 158 <reg32 offset="0x01dd" name="SCRATCH_ADDR"/> 159 <reg32 offset="0x01ea" name="CP_ME_RDADDR"/> 160 161 <reg32 offset="0x01ec" name="CP_STATE_DEBUG_INDEX"/> 162 <reg32 offset="0x01ed" name="CP_STATE_DEBUG_DATA"/> 163 <reg32 offset="0x01f2" name="CP_INT_CNTL"> 164 <bitfield name="SW_INT_MASK" pos="19" type="boolean"/> 165 <bitfield name="T0_PACKET_IN_IB_MASK" pos="23" type="boolean"/> 166 <bitfield name="OPCODE_ERROR_MASK" pos="24" type="boolean"/> 167 <bitfield name="PROTECTED_MODE_ERROR_MASK" pos="25" type="boolean"/> 168 <bitfield name="RESERVED_BIT_ERROR_MASK" pos="26" type="boolean"/> 169 <bitfield name="IB_ERROR_MASK" pos="27" type="boolean"/> 170 <bitfield name="IB2_INT_MASK" pos="29" type="boolean"/> 171 <bitfield name="IB1_INT_MASK" pos="30" type="boolean"/> 172 <bitfield name="RB_INT_MASK" pos="31" type="boolean"/> 173 </reg32> 174 <reg32 offset="0x01f3" name="CP_INT_STATUS"/> 175 <reg32 offset="0x01f4" name="CP_INT_ACK"/> 176 <reg32 offset="0x01f6" name="CP_ME_CNTL"> 177 <bitfield name="BUSY" pos="29" type="boolean"/> 178 <bitfield name="HALT" pos="28" type="boolean"/> 179 </reg32> 180 <reg32 offset="0x01f7" name="CP_ME_STATUS"/> 181 <reg32 offset="0x01f8" name="CP_ME_RAM_WADDR"/> 182 <reg32 offset="0x01f9" name="CP_ME_RAM_RADDR"/> 183 <reg32 offset="0x01fa" name="CP_ME_RAM_DATA"/> 184 <reg32 offset="0x01fc" name="CP_DEBUG"> 185 <bitfield name="PREDICATE_DISABLE" pos="23" type="boolean"/> 186 <bitfield name="PROG_END_PTR_ENABLE" pos="24" type="boolean"/> 187 <bitfield name="MIU_128BIT_WRITE_ENABLE" pos="25" type="boolean"/> 188 <bitfield name="PREFETCH_PASS_NOPS" pos="26" type="boolean"/> 189 <bitfield name="DYNAMIC_CLK_DISABLE" pos="27" type="boolean"/> 190 <bitfield name="PREFETCH_MATCH_DISABLE" pos="28" type="boolean"/> 191 <bitfield name="SIMPLE_ME_FLOW_CONTROL" pos="30" type="boolean"/> 192 <bitfield name="MIU_WRITE_PACK_DISABLE" pos="31" type="boolean"/> 193 </reg32> 194 <reg32 offset="0x01fd" name="CP_CSQ_RB_STAT"> 195 <bitfield name="RPTR" low="0" high="6" type="uint"/> 196 <bitfield name="WPTR" low="16" high="22" type="uint"/> 197 </reg32> 198 <reg32 offset="0x01fe" name="CP_CSQ_IB1_STAT"> 199 <bitfield name="RPTR" low="0" high="6" type="uint"/> 200 <bitfield name="WPTR" low="16" high="22" type="uint"/> 201 </reg32> 202 <reg32 offset="0x01ff" name="CP_CSQ_IB2_STAT"> 203 <bitfield name="RPTR" low="0" high="6" type="uint"/> 204 <bitfield name="WPTR" low="16" high="22" type="uint"/> 205 </reg32> 206 207 <reg32 offset="0x0440" name="CP_NON_PREFETCH_CNTRS"/> 208 <reg32 offset="0x0443" name="CP_STQ_ST_STAT"/> 209 <reg32 offset="0x044d" name="CP_ST_BASE"/> 210 <reg32 offset="0x044e" name="CP_ST_BUFSZ"/> 211 <reg32 offset="0x044f" name="CP_MEQ_STAT"/> 212 <reg32 offset="0x0452" name="CP_MIU_TAG_STAT"/> 213 <reg32 offset="0x0454" name="CP_BIN_MASK_LO"/> 214 <reg32 offset="0x0455" name="CP_BIN_MASK_HI"/> 215 <reg32 offset="0x0456" name="CP_BIN_SELECT_LO"/> 216 <reg32 offset="0x0457" name="CP_BIN_SELECT_HI"/> 217 <reg32 offset="0x0458" name="CP_IB1_BASE"/> 218 <reg32 offset="0x0459" name="CP_IB1_BUFSZ"/> 219 <reg32 offset="0x045a" name="CP_IB2_BASE"/> 220 <reg32 offset="0x045b" name="CP_IB2_BUFSZ"/> 221 <reg32 offset="0x047f" name="CP_STAT"> 222 <bitfield pos="31" name="CP_BUSY"/> 223 <bitfield pos="30" name="VS_EVENT_FIFO_BUSY"/> 224 <bitfield pos="29" name="PS_EVENT_FIFO_BUSY"/> 225 <bitfield pos="28" name="CF_EVENT_FIFO_BUSY"/> 226 <bitfield pos="27" name="RB_EVENT_FIFO_BUSY"/> 227 <bitfield pos="26" name="ME_BUSY"/> 228 <bitfield pos="25" name="MIU_WR_C_BUSY"/> 229 <bitfield pos="23" name="CP_3D_BUSY"/> 230 <bitfield pos="22" name="CP_NRT_BUSY"/> 231 <bitfield pos="21" name="RBIU_SCRATCH_BUSY"/> 232 <bitfield pos="20" name="RCIU_ME_BUSY"/> 233 <bitfield pos="19" name="RCIU_PFP_BUSY"/> 234 <bitfield pos="18" name="MEQ_RING_BUSY"/> 235 <bitfield pos="17" name="PFP_BUSY"/> 236 <bitfield pos="16" name="ST_QUEUE_BUSY"/> 237 <bitfield pos="13" name="INDIRECT2_QUEUE_BUSY"/> 238 <bitfield pos="12" name="INDIRECTS_QUEUE_BUSY"/> 239 <bitfield pos="11" name="RING_QUEUE_BUSY"/> 240 <bitfield pos="10" name="CSF_BUSY"/> 241 <bitfield pos="9" name="CSF_ST_BUSY"/> 242 <bitfield pos="8" name="EVENT_BUSY"/> 243 <bitfield pos="7" name="CSF_INDIRECT2_BUSY"/> 244 <bitfield pos="6" name="CSF_INDIRECTS_BUSY"/> 245 <bitfield pos="5" name="CSF_RING_BUSY"/> 246 <bitfield pos="4" name="RCIU_BUSY"/> 247 <bitfield pos="3" name="RBIU_BUSY"/> 248 <bitfield pos="2" name="MIU_RD_RETURN_BUSY"/> 249 <bitfield pos="1" name="MIU_RD_REQ_BUSY"/> 250 <bitfield pos="0" name="MIU_WR_BUSY"/> 251 </reg32> 252 <reg32 offset="0x0578" name="CP_SCRATCH_REG0" type="uint"/> 253 <reg32 offset="0x0579" name="CP_SCRATCH_REG1" type="uint"/> 254 <reg32 offset="0x057a" name="CP_SCRATCH_REG2" type="uint"/> 255 <reg32 offset="0x057b" name="CP_SCRATCH_REG3" type="uint"/> 256 <reg32 offset="0x057c" name="CP_SCRATCH_REG4" type="uint"/> 257 <reg32 offset="0x057d" name="CP_SCRATCH_REG5" type="uint"/> 258 <reg32 offset="0x057e" name="CP_SCRATCH_REG6" type="uint"/> 259 <reg32 offset="0x057f" name="CP_SCRATCH_REG7" type="uint"/> 260 261 <reg32 offset="0x0600" name="CP_ME_VS_EVENT_SRC"/> 262 <reg32 offset="0x0601" name="CP_ME_VS_EVENT_ADDR"/> 263 <reg32 offset="0x0602" name="CP_ME_VS_EVENT_DATA"/> 264 <reg32 offset="0x0603" name="CP_ME_VS_EVENT_ADDR_SWM"/> 265 <reg32 offset="0x0604" name="CP_ME_VS_EVENT_DATA_SWM"/> 266 <reg32 offset="0x0605" name="CP_ME_PS_EVENT_SRC"/> 267 <reg32 offset="0x0606" name="CP_ME_PS_EVENT_ADDR"/> 268 <reg32 offset="0x0607" name="CP_ME_PS_EVENT_DATA"/> 269 <reg32 offset="0x0608" name="CP_ME_PS_EVENT_ADDR_SWM"/> 270 <reg32 offset="0x0609" name="CP_ME_PS_EVENT_DATA_SWM"/> 271 <reg32 offset="0x060a" name="CP_ME_CF_EVENT_SRC"/> 272 <reg32 offset="0x060b" name="CP_ME_CF_EVENT_ADDR"/> 273 <reg32 offset="0x060c" name="CP_ME_CF_EVENT_DATA" type="uint"/> 274 <reg32 offset="0x060d" name="CP_ME_NRT_ADDR"/> 275 <reg32 offset="0x060e" name="CP_ME_NRT_DATA"/> 276 <reg32 offset="0x0612" name="CP_ME_VS_FETCH_DONE_SRC"/> 277 <reg32 offset="0x0613" name="CP_ME_VS_FETCH_DONE_ADDR"/> 278 <reg32 offset="0x0614" name="CP_ME_VS_FETCH_DONE_DATA"/> 279 280</domain> 281 282<!-- 283 Common between A3xx and A4xx: 284 --> 285 286<enum name="a3xx_rop_code"> 287 <value name="ROP_CLEAR" value="0"/> 288 <value name="ROP_NOR" value="1"/> 289 <value name="ROP_AND_INVERTED" value="2"/> 290 <value name="ROP_COPY_INVERTED" value="3"/> 291 <value name="ROP_AND_REVERSE" value="4"/> 292 <value name="ROP_INVERT" value="5"/> 293 <value name="ROP_XOR" value="6"/> 294 <value name="ROP_NAND" value="7"/> 295 <value name="ROP_AND" value="8"/> 296 <value name="ROP_EQUIV" value="9"/> 297 <value name="ROP_NOOP" value="10"/> 298 <value name="ROP_OR_INVERTED" value="11"/> 299 <value name="ROP_COPY" value="12"/> 300 <value name="ROP_OR_REVERSE" value="13"/> 301 <value name="ROP_OR" value="14"/> 302 <value name="ROP_SET" value="15"/> 303</enum> 304 305<enum name="a3xx_render_mode"> 306 <value name="RB_RENDERING_PASS" value="0"/> 307 <value name="RB_TILING_PASS" value="1"/> 308 <value name="RB_RESOLVE_PASS" value="2"/> 309 <value name="RB_COMPUTE_PASS" value="3"/> 310</enum> 311 312<enum name="a3xx_msaa_samples"> 313 <value name="MSAA_ONE" value="0"/> 314 <value name="MSAA_TWO" value="1"/> 315 <value name="MSAA_FOUR" value="2"/> 316 <value name="MSAA_EIGHT" value="3"/> 317</enum> 318 319<enum name="a3xx_threadmode"> 320 <value value="0" name="MULTI"/> 321 <value value="1" name="SINGLE"/> 322</enum> 323 324<enum name="a3xx_instrbuffermode"> 325 <!-- 326 When shader size goes above ~128 or so, blob switches to '0' 327 and doesn't emit shader in cmdstream. When either is '0' it 328 doesn't get emitted via CP_LOAD_STATE. When only one is 329 '0' the other gets size 256-others_size. So I think that: 330 BUFFER => execute out of state memory 331 CACHE => use available state memory as local cache 332 NOTE that when CACHE mode, also set CACHEINVALID flag! 333 334 TODO check if that 256 size is same for all a3xx 335 --> 336 <value value="0" name="CACHE"/> 337 <value value="1" name="BUFFER"/> 338</enum> 339 340<enum name="a3xx_threadsize"> 341 <value value="0" name="TWO_QUADS"/> 342 <value value="1" name="FOUR_QUADS"/> 343</enum> 344 345<enum name="a3xx_color_swap"> 346 <value name="WZYX" value="0"/> 347 <value name="WXYZ" value="1"/> 348 <value name="ZYXW" value="2"/> 349 <value name="XYZW" value="3"/> 350</enum> 351 352<enum name="a3xx_rb_blend_opcode"> 353 <value name="BLEND_DST_PLUS_SRC" value="0"/> 354 <value name="BLEND_SRC_MINUS_DST" value="1"/> 355 <value name="BLEND_DST_MINUS_SRC" value="2"/> 356 <value name="BLEND_MIN_DST_SRC" value="3"/> 357 <value name="BLEND_MAX_DST_SRC" value="4"/> 358</enum> 359 360<enum name="a4xx_tess_spacing"> 361 <value name="EQUAL_SPACING" value="0"/> 362 <value name="ODD_SPACING" value="2"/> 363 <value name="EVEN_SPACING" value="3"/> 364</enum> 365 366<doc>Address mode for a5xx+</doc> 367<enum name="a5xx_address_mode"> 368 <value name="ADDR_32B" value="0"/> 369 <value name="ADDR_64B" value="1"/> 370</enum> 371 372<doc> 373 Line mode for a5xx+ 374 Note that Bresenham lines are only supported with MSAA disabled. 375</doc> 376<enum name="a5xx_line_mode"> 377 <value value="0x0" name="BRESENHAM"/> 378 <value value="0x1" name="RECTANGULAR"/> 379</enum> 380 381<doc> 382 Blob (v615) seem to only use SAM and I wasn't able to coerce 383 it to produce any other command. 384 Probably valid for a4xx+ but not enabled or tested on anything 385 but a6xx. 386</doc> 387<enum name="a6xx_tex_prefetch_cmd"> 388 <doc> Produces garbage </doc> 389 <value value="0x0" name="TEX_PREFETCH_UNK0"/> 390 <value value="0x1" name="TEX_PREFETCH_SAM"/> 391 <value value="0x2" name="TEX_PREFETCH_GATHER4R"/> 392 <value value="0x3" name="TEX_PREFETCH_GATHER4G"/> 393 <value value="0x4" name="TEX_PREFETCH_GATHER4B"/> 394 <value value="0x5" name="TEX_PREFETCH_GATHER4A"/> 395 <doc> Causes reads from an invalid address </doc> 396 <value value="0x6" name="TEX_PREFETCH_UNK6"/> 397 <doc> Results in color being zero </doc> 398 <value value="0x7" name="TEX_PREFETCH_UNK7"/> 399</enum> 400 401<enum name="adreno_pipe"> 402 <value value="0" name="PIPE_NONE"/> 403 <value value="1" name="PIPE_BR"/> 404 <value value="2" name="PIPE_BV"/> 405 <value value="3" name="PIPE_LPAC"/> 406 <value value="4" name="PIPE_AQE0"/> 407 <value value="5" name="PIPE_AQE1"/> 408 <value value="6" name="PIPE_DDE_BR"/> 409 <value value="7" name="PIPE_DDE_BV"/> 410</enum> 411 412</database> 413